Device with fault diagnosis and positioning functions, design method, medium and equipment

Abstract

The invention discloses a device with fault diagnosis and positioning functions, a design method, a medium and equipment, and the design method comprises the steps: determining a function which needs to be realized by the device, and designing a function module; determining a fault diagnosis and positioning scheme for functional modules and selected devices of the device, and designing a fault diagnosis and positioning mechanism; designing a security assurance module; and packaging the device into a finished product. And carrying out white-box test, function test, acceleration test and type test test on the finished product of the device, feeding back the test result of each test under the condition that all the tests are not passed, and optimizing the next round of iteration until all the tests are passed. According to the method, the PFMEA analysis in the production process is introduced, the traditional method that fault diagnosis is only based on DFMEA analysis in the design stage is broken, the offering of the safety red line of the rail transit product is practiced, the safety of equipment is ensured, and the method has great practicability.

Description

Technical Field

[0001] The present invention relates to the technical field of rail transit system fault processing, and in particular to a device, a design method, a medium and equipment with fault diagnosis and positioning functions. Background Art

[0002] The internal structure of the rail transit signal system is very complex, mainly including on-board signal equipment and trackside signal equipment. On-board signal equipment is installed on the vehicle to control the daily safe operation of the vehicle, while trackside signal equipment is installed in the signal tower, machine room far from the track or in a place close to the track (for example, within 1 to 3 meters). Among them, the on-board equipment and trackside equipment will communicate in real time to jointly ensure the safety, reliability, punctuality and comfort of the train.

[0003] Nowadays, more and more signal equipment in rail transit needs to operate 24 hours a day, which places high demands on the uninterrupted operation of the signal equipment itself, as well as maintainability, fault detectability, and status monitorability. Therefore, designing a device with fault diagnosis and positioning functions is an urgent problem to be solved.

[0004] It should be understood that the above statements merely provide background technology related to the present invention and do not necessarily constitute prior art. Summary of the invention

[0005] The purpose of the present invention is to provide a device, design method, medium and equipment with fault diagnosis and positioning functions to ensure the maintainability, fault detectability, status monitorability, safety and reliability of the equipment during operation.

[0006] In order to achieve the above-mentioned purpose, the present invention provides a design method for a device with fault diagnosis and positioning functions, comprising the following steps: S1, determining the functions that the device needs to implement, and designing functional modules; S2, determining the fault diagnosis and positioning schemes for the functional modules of the device and the selected devices, and designing the fault diagnosis and positioning mechanisms; S3, designing a safety assurance module; S4, packaging the device into a finished product; S5, performing white box testing, functional testing, accelerated testing and type test testing on the finished product of the device. If all tests are not passed, the test results of each test are fed back to the S1 and S2 respectively, and the next round of iteration is optimized until all the white box tests, functional tests, accelerated tests and type test tests are passed.

[0007] Preferably, in S2, a fault diagnosis and location scheme is planned according to the specific functions of the device, including: hierarchical division of the diagnosed objects, independence of the diagnostic methods used, and failure of the diagnostic design should not affect the device function.

[0008] Preferably, the hierarchical division of the diagnosed object includes: functional module level and component level; wherein the functional module level is represented by the functional module in S1, and the component level is represented by the component required to be selected when implementing the functional module.

[0009] Preferably, the design of a fault diagnosis and location mechanism specifically includes the following steps: S21, using the methods in the fault diagnosis experience library to realize the fault diagnosis and location requirements of some functional modules and selected components in the device; S22, performing DFMEA analysis on the device; S23, performing PFMEA analysis on the device; S24, designing a corresponding fault diagnosis and location mechanism based on the analysis results of S22 and S23.

[0010] Preferably, in said S22, specific aspects of the DFMEA analysis of said device include: failure mode, component failure rate, failure occurrence, failure severity and failure detectability.

[0011] Preferably, a corresponding risk matrix is ​​established according to the fault occurrence and fault severity to obtain fault tolerance, including: unacceptable faults, unexpected faults, acceptable faults and negligible faults; wherein, for fault tolerances of unacceptable faults, unexpected faults and acceptable faults, a fault diagnosis and location mechanism is designed; for negligible faults, no fault diagnosis and location mechanism is used.

[0012] Preferably, the fault tolerance also needs to take safety factors into consideration. For negligible faults that affect safety functions, a fault diagnosis and location mechanism needs to be adopted to handle the fault in a timely manner.

[0013] Preferably, in said S23, specific aspects of the PFMEA analysis of the device include: failure mode, potential impact of failure, failure occurrence, failure severity and failure detectability.

[0014] Preferably, the risk priority number RPN = fault severity × fault occurrence × fault detectability; wherein, if the current RPN value is greater than the set RPN threshold, a fault diagnosis and location mechanism needs to be adopted to promptly handle the fault until the current RPN value is reduced to below the set RPN threshold.

[0015] Preferably, the RPN also needs to consider safety factors. For RPN values ​​below the RPN threshold that affect safety functions, a fault diagnosis and location mechanism needs to be adopted to handle the fault in a timely manner.

[0016] Preferably, in S5, the white box test will test the functional module level and the device level of the device, including: fault injection, hardware consistency, signal integrity, power integrity, and issue a test report after the test is completed.

[0017] Preferably, in S5, the functional test is a black box test, which applies stimulus or fault to the input end of the device and tests whether the result meets the expected value at the output end, so as to determine whether the device can correctly diagnose the fault at the functional module level.

[0018] Preferably, in S5, the accelerated test includes: a highly accelerated life test (HALT) test and a mean time between failures (MTBF) test.

[0019] Preferably, the HALT test accelerates the aging process through extreme environmental conditions, obtains the operating limit and the damage limit of the product, generates a factor λf1 affecting the failure rate of the device, and outputs a factor λs1 affecting the severity of the fault.

[0020] Preferably, the MTBF test evaluates the average working time of a product between two adjacent failures, and outputs a factor λf2 affecting the device failure rate and a factor λs2 affecting the fault severity; the calculation formula of λf2 is: MTBF=1 / λf2, where MTBF is the MTBF test result.

[0021] Preferably, in the accelerated test, the factor λf that ultimately affects the device failure rate and the factor λs that ultimately affects the fault severity are: λf=max{λf1,λf2}, λs=max{λs1,λs2} respectively.

[0022] The present invention also provides a device with fault diagnosis and positioning functions, which is designed using the above-mentioned design method of the device with fault diagnosis and positioning functions, and includes: a functional module, which realizes the required functions of the device; a fault diagnosis and positioning module, which is respectively connected to the functional module and the components constituting the functional module, to detect whether the functional module fails, and to determine the specific location of the functional module when the failure occurs; a safety assurance module, which is respectively connected to the functional module and the fault diagnosis and positioning module, to ensure the safety of the device.

[0023] The present invention also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the design method of the device with fault diagnosis and positioning functions is implemented.

[0024] The present invention also provides an electronic device, including a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the above-mentioned design method of the device with fault diagnosis and positioning functions is implemented.

[0025] In summary, compared with the prior art, the present invention provides a device, design method, medium and equipment with fault diagnosis and location functions, which have at least the following beneficial effects:

[0026] (1) The present invention innovatively introduces PFMEA analysis in the production process, breaking the traditional method of fault diagnosis based only on DFMEA analysis in the design stage, making the fault diagnosis more comprehensive, thereby discovering and solving potential risks that may cause production interruption or product quality problems in advance, greatly improving production efficiency and product quality;

[0027] (2) At the system level, the present invention comprehensively plans the design process of fault diagnosis, ensures that the verification link of the design is fully executed, and also focuses on the continuous optimization of the fault diagnosis design, striving to continuously improve the accuracy and efficiency of diagnosis in practical applications;

[0028] (3) The present invention can quickly and accurately locate the fault point, thereby shortening the maintenance time and improving the operating efficiency and reliability of the equipment;

[0029] (4) Priority is given to the safety functional attributes of the equipment, and the safety red lines of rail transit products are respected to ensure the safety of the equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A flow chart of a method for designing a device with fault diagnosis and positioning functions according to the present invention;

[0031] Figure 2 It is a schematic diagram of the risk matrix in the present invention;

[0032] Figure 3 It is a schematic diagram of the structure of an embodiment of a two-zone two-safety computing device of the present invention. DETAILED DESCRIPTION

[0033] The following is combined with Figure 1 ~Attached Figure 3 , the present invention is further explained by describing a preferred specific embodiment in detail.

[0034] It should be noted that the drawings are in a very simplified form and use non-precise proportions. They are only used to conveniently and clearly assist in explaining the embodiments of the present invention, and are not used to limit the conditions for the implementation of the present invention. Therefore, they have no substantive technical significance. Any structural modification, change in proportional relationship or adjustment of size, without affecting the effects and purposes that can be achieved by the present invention, should still fall within the scope of the technical content disclosed by the present invention.

[0035] It should be noted that, in the present invention, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only the elements explicitly listed, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0036] like Figure 1 As shown, the present invention provides a design method for a device with fault diagnosis and positioning functions, comprising the following steps:

[0037] S1. Determine the functions that the device needs to achieve and design functional modules;

[0038] S2. Determine a fault diagnosis and location scheme for the functional modules of the device and the selected components, and design a fault diagnosis and location mechanism;

[0039] S3, design safety assurance module;

[0040] S4, packaging the device into a finished product;

[0041] S5. Perform white box test, functional test, accelerated test and type test on the finished product of the device. If all tests are not passed, the test results of each test are fed back to S1 and S2 respectively to optimize the next round of iteration until all the white box test, functional test, accelerated test and type test are passed.

[0042] Furthermore, in S2, it is necessary to plan a fault diagnosis and location plan according to the specific functions of the device, and points that need to be considered include: the hierarchical division (functional module level, component level) of the diagnosed object, the independence of the diagnostic method used, and the fact that the device function should not be affected when the diagnostic design fails, etc.; it can be understood that the hierarchy of the diagnosed object includes the functional module level and the component level, the functional module level is represented by the functional module described in S1, and the component level is represented by the electronic components that need to be selected when implementing the functional module.

[0043] To be more specific, in planning fault diagnosis and positioning schemes, the determination of functional module-level fault diagnosis points and device-level fault diagnosis points is critical; the diagnosis and positioning of functional module-level faults requires starting from the module-level functions, fully understanding the impact of module-level functional failures and the expected values ​​of signals at different functional points of the functional module. If the actual value of the signal output at a certain functional point is inconsistent with the expected value of the output signal, it means that there is a fault at the functional point; and the diagnosis and positioning of device-level faults requires giving priority to functional chips with built-in fault alarms, fault feedback, fault status displays, and communication interfaces when selecting components, and it is necessary to combine circuit functions for fault discrimination design to implement the implantation of fault diagnosis points, and for the diagnostic point, it should have a linear or fixed expected output value. If the actual value output at the diagnostic point is inconsistent with the expected value of the output, it means that there is a fault at the diagnostic point, thereby achieving device-level fault diagnosis, so that the fault diagnosis and positioning capability of the device is more accurate.

[0044] Furthermore, in the above S2, when designing the fault diagnosis and location mechanism, the following steps are specifically included:

[0045] S21. Based on the existing experience, directly use the methods in the fault diagnosis experience library to realize the fault diagnosis and positioning requirements of some functional modules and selected components in the device;

[0046] S22, performing a Design Failure Mode and Effects Analysis (DFMEA) on the device;

[0047] S23, performing a Process Failure Mode and Effects Analysis (PFMEA) on the device;

[0048] S24. Design a corresponding fault diagnosis and location mechanism according to the analysis results of S22 and S23.

[0049] It can be understood that in the above S21, directly quoting the fault diagnosis and positioning methods in the fault diagnosis experience library can effectively improve the design efficiency and reduce the workload of subsequent testing and safety verification. However, since the methods in the fault diagnosis experience library cannot fully cover all functional modules of the newly designed device and the fault diagnosis and positioning requirements of the selected components, it can only realize the fault diagnosis and positioning of some functional modules and some selected components.

[0050] Furthermore, in S22, it is necessary to perform DFMEA analysis on the device at the functional module level and the device level from the aspects of failure mode, device failure rate, fault occurrence, fault severity, fault detectability, etc., and design a corresponding fault diagnosis and location mechanism.

[0051] Specifically, Figure 2 As shown in FIG. 1 , the risk matrix in the present invention is a schematic diagram, which establishes a corresponding risk matrix according to the fault occurrence and fault severity, and obtains the fault tolerance. Then, according to the acceptance degree of the fault tolerance, corresponding measures are taken. For the faults with unacceptable D, undesirable C, and acceptable B fault tolerance, the design of the fault diagnosis and location mechanism needs to be considered; and for the negligible fault A, the fault diagnosis and location mechanism does not need to be adopted.

[0052] However, it should be noted that for negligible faults, they generally do not affect normal functions, such as the indicator light display function of the panel, or the functions required by the device during research and development and debugging. If the diagnosis of such faults is forcibly increased, it will increase the cost of manpower and materials. However, for the field of rail transit, the severity of the fault also needs to consider the safety factor (Severity, S). Therefore, even if the occurrence of the fault is very low, the functional failure will affect the safety function, and the final result is intolerable. Measures need to be taken to eliminate such effects, that is, to adopt effective fault diagnosis and location mechanisms, accurately locate the fault point at the functional module level or device level, and then detect and handle the fault point in time when the function fails, so that such faults can lead to safety and do not cause safety hazards.

[0053] Furthermore, in the S23, it is necessary to perform PFMEA analysis on the device at the functional module level and the device level from the aspects of fault mode, potential impact of fault, fault occurrence, fault severity, and fault detectability, and design a corresponding fault diagnosis and location mechanism. Specifically, in the PFMEA analysis, under normal circumstances, the risk priority number (RiskPriorityNumber, RPN) = fault severity × fault occurrence × fault detectability, and then compare the current RPN value with the set RPN threshold Rth to determine which fault diagnosis and location mechanism should be used for the fault. In an embodiment of the present invention, the RPN threshold Rth can be set to 125. If the current RPN value is calculated to be greater than 125, corresponding measures need to be taken to reduce the current RPN value to below 125; wherein, the larger the RPN value, the greater the risk of failure. However, in the field of rail transit, we should not only look at the size of the RPN value, but also consider the safety factor S. Because even if the RPN value is very low, the failure will affect the safety function, which is ultimately intolerable. Measures need to be taken to eliminate this impact, that is, to adopt effective fault diagnosis and location mechanisms to accurately locate the fault point at the functional module level or device level, and then detect and handle the fault point in time when the function fails, so that such faults can lead to safety and do not cause safety hazards.

[0054] It should be noted that the reason for conducting PFMEA analysis is that the components in the production process may be damaged or fail, especially those related to safety functions. Specifically, such as incorrect placement of components, excessively high temperatures during welding, and damage to the pins during component pretreatment, etc., it is necessary to conduct a comprehensive PFMEA analysis and design a corresponding fault diagnosis and location mechanism to eliminate hidden dangers.

[0055] Furthermore, in S3, the safety assurance module is used to ensure that the device can operate safely and continuously while achieving its functions and fault diagnosis.

[0056] Furthermore, in the S5, when performing white box testing, the functional module level and device level of the device will be tested, including: fault injection, hardware consistency, signal integrity, power integrity and other tests, and a test report will be issued after the test is completed. The test report includes the missed diagnosis, inaccurate fault location, wrong diagnosis and other situations in the design of the fault diagnosis and positioning mechanism, and the test report will be fed back to the S1 and S2 to optimize the next round of iteration.

[0057] Furthermore, in S5, the functional test is a black box test, which applies stimulus or fault at the input end of the device and then tests whether the result meets the expected value at the output end, so as to determine whether the device can correctly diagnose the fault at the functional module level, and feed back the test result to S1 and S2 to optimize the next round of iteration.

[0058] Specifically, white box testing, also known as structural testing or transparent box testing, is a test in which the tester can view the internal structure and logic of the device being tested; while black box testing, also known as functional testing, is a test in which the tester treats the device as a black box that cannot be opened, without considering its internal structure and characteristics, and only focuses on the functionality of the device, and verifies the correctness of the device by inputting data and checking the output results.

[0059] Furthermore, in S5, the accelerated test includes: a Highly Accelerated Life Testing (HALT) test and a Mean Time Between Failure (MTBF) test.

[0060] Furthermore, the HALT test accelerates the aging process through extreme environmental conditions to obtain the working limit and damage limit of the product, thereby finding the weak points and design defects of the product. Through the HALT test, defects not found by the white box test and the black box test can be obtained, and the factor λf1 affecting the device failure rate is generated, and the factor λs1 affecting the fault severity is output.

[0061] The value of the factor λf1 affecting the failure rate of the device is related to the number of samples tested in the HALT test and the frequency of failures at the same fault point. In the HALT test of this embodiment, when the number of samples tested is ≥4 and the device function does not fail, λf1≤1, that is, the failure rate of the device is recognized or considered to be reduced; when the number of samples tested is <4 and a certain function of the device fails more than 2 times, λf1>1, that is, the failure rate of the faulty device is questioned and can be considered to be increased.

[0062] Among them, the value of the factor λs1 affecting the severity of the fault can be adjusted according to the result of the HALT test; among them, when the consequence of the device failure is less than the expected value, then λs1≤1, that is, the consequence of this fault is milder than expected, and the fault severity level can be considered to be reduced or kept unchanged; when the consequence of the device failure is greater than the expected value, λs1>1, that is, the consequence of this fault is more serious than expected, and it is necessary to consider increasing the fault severity level, so that when optimizing the next round of iterations, the risk matrix is ​​adjusted according to the factor λf1 and the factor λs1, and then the design of the fault diagnosis and location mechanism is adjusted. In other words, in this embodiment, when performing HALT test analysis, the fault severity of a certain fault of the device is an acceptable fault B, but after the test, it is found that the consequence caused by the fault is actually an unexpected C, then λs1>1; on the contrary, if after the test, B finds that the consequence caused by the fault is actually a negligible fault A, then λs1≤1.

[0063] Furthermore, the MTBF test is an important indicator for evaluating product reliability, so as to evaluate the average working time of a product between two adjacent failures, and output a factor λf2 affecting the device failure rate and a factor λs2 affecting the fault severity.

[0064] Among them, the MTBF value is strongly correlated with the device failure rate, and the specific formula is MTBF=1 / λf2 (where λf2 is the failure rate). Therefore, the factor λf2 can be determined according to the MTBF value; and the factor λs2 that affects the severity of the fault is determined in the same way as the λs1.

[0065] Further, after completing the HALT test and the MTBF test, the value of the factor λf that ultimately affects the device failure rate and the value of the factor λs that ultimately affects the fault severity can be determined based on the HALT test and the MTBF test results, where λf=max{λf1,λf2}, λs=max{λs1,λs2}; however, it should be noted that since the MTBF value is strongly correlated with the device failure rate, if λf1>λf2, the λf value needs to be determined based on the actual situation. Finally, the obtained factors λf and λs are fed back to the S1 and S2 to optimize the next round of iteration.

[0066] Furthermore, in S5, the type test is an industry standard test, that is, through third-party certification, to test whether the product meets the functional requirements to be achieved and whether it has the functions of fault diagnosis and location, and the test report is fed back to S1 and S2 to optimize the next round of iteration.

[0067] It can be understood that after completing the white box test, functional test, accelerated test and type test, if the device passes all of the above tests, the design of the device is completed and can be put into production; if the device fails any of the above tests, the test results are fed back to the S1 and S2 to optimize the next round of iteration and carry out a new round of design.

[0068] The present invention also provides a device with fault diagnosis and positioning functions, which is designed using the above-mentioned design method of the device with fault diagnosis and positioning functions, and includes: a functional module, which realizes the required functions of the device; a fault diagnosis and positioning module, which is respectively connected to the functional module and the devices constituting the functional module to detect whether the functional module fails and determine the specific location of the functional module when the failure occurs; a safety assurance module, which is respectively connected to the functional module and the fault diagnosis and positioning module to ensure the safety of the device.

[0069] In a preferred embodiment of the present invention, Figure 3 As shown, taking the design of a two-out-of-two safety computing device with fault diagnosis and positioning functions and performing chip temperature and voltage fault diagnosis as an example, the specific steps include:

[0070] First, it is determined that the device is a two-out-of-two safety operation device, and the function it implements is two-out-of-two safety operation. The functional modules of the device include two FPGA modules and two CPU modules, which are respectively arranged in the A channel system and the B channel system, and each channel system includes an FPGA module and a CPU module; wherein the A channel system includes FPGA1 and CPU1, and the B channel system includes FPGA2 and CPU2, and the CPU1 and the CPU2 are connected to each other for communication, and the FPGA1 and the FPGA2 are connected to each other for communication. In addition, the FPGA1 and the CPU1, and the FPGA2 and the CPU2 are also connected to each other for communication. In this embodiment, it can be realized by Localbus bus, PCIe bus, etc., but it is not limited to these two methods.

[0071] Secondly, based on the existing experience, the methods in the fault diagnosis experience library are used to match the circuit design and after the matching is completed, the independence of the fault diagnosis and location mechanisms is considered.

[0072] Furthermore, in the voltage diagnosis design, due to the possibility of sudden changes in voltage, if the voltage of each CPU is abnormal, the ability of the CPU to process the voltage detection value will be unreliable. Therefore, the voltage detection value of each CPU cannot be directly sent back to the CPU for processing, but needs to be detected by an independent detection device. Taking the A channel system as an example, a voltage diagnosis unit A1 and a voltage diagnosis unit A2 are designed accordingly; the voltage diagnosis unit A1 is connected to the CPU1 and the FPGA1 respectively, diagnoses the voltage of the CPU1 and feeds back the diagnosis information to the FPGA1; the voltage diagnosis unit A2 is connected to the CPU1 and the FPGA1 respectively, diagnoses the voltage of the FPGA1 and feeds back the diagnosis information to the CPU1; wherein, FPGA1 obtains the value fed back by the voltage diagnosis unit A1 to confirm whether the power supply voltage of CPU1 is normal. If the voltage is normal, FPGA1 does not perform abnormal processing and only transmits the status to the upper layer; if the voltage is abnormal, FPGA1 will promptly alarm the upper layer, and the upper layer will complete the abnormal processing to avoid security problems caused by the unreliable operation of CPU1 itself; similarly, the voltage detection of each FPGA is the same.

[0073] Furthermore, in the temperature diagnosis design, since the temperature change is a process, there will be no situation similar to voltage mutation, and the temperature of the CPU is higher than the temperature of the FPGA, it is only necessary to perform temperature detection on each of the CPUs; thus, a temperature diagnosis unit 1 and a temperature diagnosis unit 2 are designed in the A channel and the B channel respectively, the temperature diagnosis unit 1 diagnoses the temperature of the CPU 1 and feeds back the diagnosis information to the CPU 2, and the temperature diagnosis unit 2 diagnoses the temperature of the CPU 2 and feeds back the diagnosis information to the CPU 1;

[0074] Next, after completing the diagnostic design, the two-out-of-two safety computing device is subjected to DFMEA analysis and PFMEA analysis. Taking channel A as an example, the fault diagnosis priority is as follows: 1. voltage diagnosis, 2. temperature diagnosis, 3. fault diagnosis of the voltage diagnosis unit A1 itself, 4. fault diagnosis of the voltage diagnosis unit A2 itself, 5. fault diagnosis of the temperature diagnosis unit 1 itself; wherein, CPU1 and FPGA1 have internal self-check mechanisms that can diagnose their respective internal faults; voltage diagnosis units A1 and A2 have self-check interfaces, through which it is possible to diagnose whether the voltage diagnosis units A1 and A2 have faults; the temperature diagnosis unit 1 itself also has a self-check interface function that can diagnose whether the temperature diagnosis unit itself has faults; it can be understood that through this type of fault diagnosis design, when any chip fails, it can be directly discovered, thereby achieving accurate fault location.

[0075] Then, the design of channel B is completed with the same design as above, and after verifying that the design meets the safety standards, a product prototype of the two-out-of-two safety computing device is produced.

[0076] Finally, the product is subjected to white box testing, functional testing, accelerated testing and type test tests respectively, and the test results of each test are fed back to the next round of iteration to optimize the functional design of the two-out-of-two safety computing device, the fault diagnosis experience library data, the failure rate in the fault diagnosis design, the fault severity, and the fault detectability data, so as to re-evaluate the risk matrix and RPN value until the white box test, functional test, accelerated test and type test tests are all passed.

[0077] The present invention also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the design method of the device with fault diagnosis and positioning functions is implemented.

[0078] The present invention also provides an electronic device, including a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the design method of the device with fault diagnosis and positioning functions is implemented.

[0079] In summary, the present invention provides a device, design method, medium and equipment with fault diagnosis and positioning functions, which innovatively introduces PFMEA analysis of the production process, breaking the traditional method that fault diagnosis is only based on DFMEA analysis in the design stage. From the production level, it also considers the design scheme of fault diagnosis and positioning to avoid missed diagnosis and wrong diagnosis, and realizes that the equipment has a fault diagnosis scheme throughout its life cycle; not only learns the relevant experience of the fault diagnosis experience library, but also accelerates the realization of the fault diagnosis function through a variety of testing methods, which not only improves the research and development efficiency, but also improves the reliability, detectability and maintainability of the equipment; from the system level, it comprehensively plans the design of fault diagnosis, design verification, optimization of fault diagnosis design, and method of accurate fault positioning, which is extremely practical; gives priority to the safety function attributes of the equipment, practices the respect for the safety red line of rail transit products, and ensures the safety of the equipment.

[0080] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be appreciated that the above description should not be considered as a limitation of the present invention. After reading the above content, it will be apparent to those skilled in the art that various modifications and substitutions of the present invention will occur. Therefore, the protection scope of the present invention should be limited by the appended claims.

Claims

1. A method for designing a device with fault diagnosis and positioning functions, characterized in that: The following steps are involved: S1. Determine the functions that the device needs to achieve and design functional modules; S2. Determine a fault diagnosis and location scheme for the functional modules of the device and the selected components, and design a fault diagnosis and location mechanism; S3, design safety assurance module; S4, packaging the device into a finished product; S5. Perform white box test, functional test, accelerated test and type test on the finished product of the device. If all tests are not passed, the test results of each test are fed back to S1 and S2 respectively to optimize the next round of iteration until all the white box test, functional test, accelerated test and type test are passed.

2. The method for designing a device with fault diagnosis and positioning functions as claimed in claim 1, characterized in that: In S2, a fault diagnosis and location plan is planned according to the specific functions of the device, including: hierarchical division of the diagnosed objects, independence of the diagnostic methods used, and failure of the diagnostic design should not affect the device function.

3. The method for designing a device with fault diagnosis and positioning functions as claimed in claim 2, characterized in that: The hierarchical division of the diagnosed object includes: functional module level and component level; The functional module level refers to the functional modules in S1, and the device level refers to the devices required to be selected when implementing the functional modules.

4. The method for designing a device with fault diagnosis and positioning functions as claimed in claim 3, characterized in that: Design a fault diagnosis and location mechanism, which includes the following steps: S21, using the methods in the fault diagnosis experience library to realize the fault diagnosis and positioning requirements of some functional modules and selected components in the device; S22, performing DFMEA analysis on the device; S23, performing PFMEA analysis on the device; S24. Design a corresponding fault diagnosis and location mechanism according to the analysis results of S22 and S23.

5. The method for designing a device with fault diagnosis and positioning functions as claimed in claim 4, characterized in that: In the above S22, specific aspects of the DFMEA analysis of the device include: failure mode, device failure rate, failure occurrence, failure severity and failure detectability.

6. The method for designing a device with fault diagnosis and location functions as claimed in claim 5, characterized in that: According to the fault occurrence and fault severity, a corresponding risk matrix is ​​established to obtain fault tolerance, including: unacceptable faults, unexpected faults, acceptable faults and negligible faults; Among them, for faults with tolerance levels of unacceptable faults, unexpected faults, and acceptable faults, a fault diagnosis and location mechanism is designed; for negligible faults, no fault diagnosis and location mechanism is used.

7. The method for designing a device with fault diagnosis and positioning functions as claimed in claim 6, characterized in that: The fault tolerance also needs to take safety factors into consideration. For negligible faults that affect safety functions, a fault diagnosis and location mechanism needs to be adopted to handle the fault in a timely manner.

8. The method for designing a device with fault diagnosis and location functions as claimed in claim 5, characterized in that: In the above-mentioned S23, the specific aspects of the PFMEA analysis of the device include: failure mode, potential impact of failure, failure occurrence, failure severity and failure detectability.

9. The method for designing a device with fault diagnosis and positioning functions as claimed in claim 8, characterized in that: Risk priority number RPN = fault severity × fault occurrence × fault detectability; if the current RPN value is greater than the set RPN threshold, a fault diagnosis and location mechanism must be adopted to handle the fault in a timely manner until the current RPN value is reduced to below the set RPN threshold.

10. The method for designing a device with fault diagnosis and location functions as claimed in claim 9, characterized in that: The RPN also needs to consider safety factors. For RPN values ​​below the RPN threshold that affect safety functions, a fault diagnosis and location mechanism needs to be adopted to handle the fault in a timely manner.

11. The method for designing a device with fault diagnosis and positioning functions as claimed in claim 3, characterized in that: In the above S5, the white box test will test the functional module level and the device level of the device, including: fault injection, hardware consistency, signal integrity, power integrity, and issue a test report after the test is completed.

12. The method for designing a device with fault diagnosis and location functions as claimed in claim 1, characterized in that: In S5, the functional test is a black box test, which applies stimulus or fault to the input end of the device and tests whether the result meets the expected value at the output end, so as to determine whether the device can correctly diagnose the fault at the functional module level.

13. The method for designing a device with fault diagnosis and location functions as claimed in claim 1, characterized in that: In the above S5, the accelerated test includes: a highly accelerated life test (HALT) test and a mean time between failures (MTBF) test.

14. The method for designing a device with fault diagnosis and location functions as claimed in claim 13, characterized in that: The HALT test accelerates the aging process through extreme environmental conditions, obtains the working limit and the damage limit of the product, generates a factor λf1 that affects the failure rate of the device, and outputs a factor λs1 that affects the severity of the fault.

15. The method for designing a device with fault diagnosis and location functions as claimed in claim 14, characterized in that: The MTBF test evaluates the average working time of a product between two adjacent failures and outputs a factor λf2 that affects the failure rate of the device and a factor λs2 that affects the severity of the failure; The calculation formula of λf2 is: MTBF=1 / λf2, where MTBF is the MTBF test result.

16. The method for designing a device with fault diagnosis and location functions as claimed in claim 15, characterized in that: In the accelerated test, the factor λf that ultimately affects the device failure rate and the factor λs that ultimately affects the fault severity are: λf=max{λf1,λf2}, λs=max{λs1,λs2} respectively.

17. A device with fault diagnosis and positioning functions, designed by the design method of a device with fault diagnosis and positioning functions as claimed in any one of claims 1 to 16, comprising: Functional modules, realizing the required functions of the device; A fault diagnosis and positioning module, connected to the functional module and the components constituting the functional module, respectively, to detect whether the functional module fails and to determine the specific location of the functional module when the failure occurs; The safety assurance module is respectively connected to the functional module and the fault diagnosis and positioning module to ensure the safety of the device.

18. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method for designing a device with fault diagnosis and positioning functions according to any one of claims 1 to 16 is implemented.

19. An electronic device, characterized in that: The device comprises a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the method for designing a device with fault diagnosis and positioning functions as claimed in any one of claims 1 to 16 is implemented.

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