Method and device for evaluating conducted emission performance of chip, medium and electronic equipment

Abstract

The invention discloses a conducted emission performance evaluation method and device of a chip, a medium and electronic equipment. The method comprises the following steps: determining a first scattering parameter of a tested circuit in a chip; determining a second scattering parameter of a target circuit connected with the tested circuit in the circuit board for bearing the chip; determining a first change relation of a predetermined electrical parameter of the tested circuit relative to time; determining a first simulation parameter based on the first scattering parameter, the second scattering parameter and the first change relation; based on the first simulation parameter, simulating the chip and the circuit board to obtain a noise time domain waveform of a connection point of the tested circuit and the target circuit; converting the noise time domain waveform into a noise frequency domain waveform; and determining a conducted emission performance evaluation result of the tested circuit based on the noise frequency domain waveform. According to the embodiment of the invention, the conducted emission performance of the tested circuit in the chip can be effectively evaluated.

Description

Technical Field

[0001] The present disclosure relates to chip technology, and in particular to a method, device, medium and electronic equipment for evaluating the conducted emission performance of a chip. Background Art

[0002] Generally speaking, in the early stage of chip design, it is necessary to evaluate the conducted emission performance of some circuits in the chip. Based on the obtained conducted emission performance evaluation results, the chip design can be optimized. How to evaluate the conducted emission performance of these circuits in the chip is a problem worthy of attention for those skilled in the art. Summary of the invention

[0003] In order to solve the above technical problems, the present disclosure provides a method, device, medium and electronic device for evaluating the conducted emission performance of a chip.

[0004] According to one aspect of an embodiment of the present disclosure, a method for evaluating conducted emission performance of a chip is provided, comprising:

[0005] Determining a first scattering parameter of a circuit under test in a chip;

[0006] Determining a second scattering parameter of a target circuit connected to the circuit under test in a circuit board carrying the chip;

[0007] Determining a first variation relationship of a predetermined electrical parameter of the circuit under test with respect to time;

[0008] determining a first simulation parameter based on the first scattering parameter, the second scattering parameter, and the first variation relationship;

[0009] Based on the first simulation parameters, simulating the chip and the circuit board to obtain a noise time domain waveform of a connection point between the circuit under test and the target circuit;

[0010] Converting the noise time domain waveform into a noise frequency domain waveform;

[0011] Based on the noise frequency domain waveform, a conducted emission performance evaluation result of the circuit under test is determined.

[0012] According to another aspect of an embodiment of the present disclosure, a device for evaluating conducted emission performance of a chip is provided, comprising:

[0013] A first determination module, used to determine a first scattering parameter of a circuit under test in a chip;

[0014] A second determination module, used to determine a second scattering parameter of a target circuit connected to the circuit under test in a circuit board for carrying the chip;

[0015] A third determination module, used to determine a first variation relationship of a predetermined electrical parameter of the circuit under test with respect to time;

[0016] a fourth determining module, configured to determine a first simulation parameter based on the first scattering parameter determined by the first determining module, the second scattering parameter determined by the second determining module, and the first change relationship determined by the third determining module;

[0017] A simulation module, configured to simulate the chip and the circuit board based on the first simulation parameters determined by the fourth determination module, and obtain a noise time domain waveform of a connection point between the circuit under test and the target circuit;

[0018] A first conversion module, used for converting the noise time domain waveform obtained by the simulation module into a noise frequency domain waveform;

[0019] A fifth determination module is used to determine a conducted emission performance evaluation result of the circuit under test based on the noise frequency domain waveform obtained by the first conversion module.

[0020] According to another aspect of an embodiment of the present disclosure, a computer-readable storage medium is provided, wherein the storage medium stores a computer program, and the computer program is used to execute the method for evaluating the conducted emission performance of the above chip.

[0021] According to another aspect of the embodiments of the present disclosure, an electronic device is provided, the electronic device comprising:

[0022] processor;

[0023] a memory for storing instructions executable by the processor;

[0024] The processor is used to read the executable instructions from the memory and execute the instructions to implement the conducted emission performance evaluation method of the above chip.

[0025] According to another aspect of an embodiment of the present disclosure, a computer program product is provided. When instructions in the computer program product are executed by a processor, the method for evaluating the conducted emission performance of the above chip is executed.

[0026] Based on the conducted emission performance evaluation method, device, medium, electronic device and program product of the chip provided by the above embodiments of the present disclosure, the first scattering parameter of the circuit under test can be used to characterize the electrical characteristics of the circuit under test, the second scattering parameter of the target circuit connected to the circuit under test can be used to characterize the electrical characteristics of the target circuit, and the first change relationship of the predetermined electrical parameter of the circuit under test relative to time can be used to reflect the change law of the predetermined electrical parameter of the circuit under test in the time domain. Based on the first scattering parameter, the second scattering parameter and the first change relationship, the first simulation parameter is determined for the simulation of the chip and the circuit board, and the electrical characteristics of the circuit under test and the target circuit, as well as the change law of the predetermined electrical parameter of the circuit under test in the time domain can be effectively applied to the simulation process, so as to simulate the actual working state of the chip and the circuit board, and more reliably obtain the noise time domain waveform of the connection point between the circuit under test and the target circuit. Through the conversion between the frequency domain and the time domain, the noise frequency domain waveform can be obtained efficiently and quickly from the noise time domain waveform, so as to provide an effective reference for the conducted emission performance evaluation of the circuit under test, and ensure the accuracy and reliability of the conducted emission performance evaluation results obtained. Therefore, in the embodiments of the present disclosure, by using computer simulation technology, the conducted emission performance of the circuit under test in the chip can be effectively evaluated. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a flowchart of a method for evaluating the conducted emission performance of a chip provided by some exemplary embodiments of the present disclosure.

[0028] Figure 2 It is a flowchart of a method for determining a first simulation parameter provided by some exemplary embodiments of the present disclosure.

[0029] Figure 3 is a schematic diagram of a first variation relationship in some exemplary embodiments of the present disclosure.

[0030] Figure 4 is a schematic diagram of the second variation relationship in some exemplary embodiments of the present disclosure.

[0031] Figure 5 is a schematic diagram of the third variation relationship in some exemplary embodiments of the present disclosure.

[0032] Figure 6 It is a flowchart of an information verification method provided by some exemplary embodiments of the present disclosure.

[0033] Figure 7 is a schematic diagram of the fourth variation relationship in some exemplary embodiments of the present disclosure.

[0034] Figure 8 It is a flowchart of a method for determining a first scattering parameter of a circuit under test in a chip provided by some exemplary embodiments of the present disclosure.

[0035] Fig. 9 It is a flowchart of a method for determining a first variation relationship of a predetermined electrical parameter of a circuit under test with respect to time provided by some exemplary embodiments of the present disclosure.

[0036] Fig.10 It is a flowchart of a method for determining a conducted emission performance evaluation result of a circuit under test based on a noise frequency domain waveform provided by some exemplary embodiments of the present disclosure.

[0037] Figure 11-1 It is a flowchart of a method for evaluating the conducted emission performance of a chip provided by some other exemplary embodiments of the present disclosure.

[0038] Figure 11-2 is a schematic diagram of a conducted emission simulation link in some exemplary embodiments of the present disclosure.

[0039] Figure 11-3 is a schematic diagram of an impedance matching circuit in some exemplary embodiments of the present disclosure.

[0040] Figure 11-4 is a schematic diagram of a method for evaluating the conducted emission performance of a chip in some exemplary embodiments of the present disclosure.

[0041] Fig.12 It is a schematic diagram of the structure of a chip conduction emission performance evaluation device provided by some exemplary embodiments of the present disclosure.

[0042] Fig.13 is a structural diagram of the fourth determination module in some exemplary embodiments of the present disclosure.

[0043] Fig.14 is a schematic diagram of a module used for information verification in some exemplary embodiments of the present disclosure.

[0044] Fig.15 is a structural diagram of a first determination module in some exemplary embodiments of the present disclosure.

[0045] Fig.16 is a structural diagram of the third determination module in some exemplary embodiments of the present disclosure.

[0046] Fig.17 is a structural diagram of the fifth determination module in some exemplary embodiments of the present disclosure.

[0047] Fig.18 It is a schematic diagram of the structure of an electronic device provided by some exemplary embodiments of the present disclosure. DETAILED DESCRIPTION

[0048] To explain the present disclosure, example embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. It should be understood that the present disclosure is not limited to the example embodiments.

[0049] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

[0050] Application Overview

[0051] Currently, the application of chips is becoming more and more widespread. Optionally, the chip can be a system-on-chip (SOC) applied to a vehicle, for example, a SOC supporting an autonomous driving function.

[0052] Generally speaking, in the early design stage of a chip, it is necessary to evaluate the conducted emission performance of some circuits in the chip. The conducted emission performance of these circuits in the chip can be used to characterize the level of external conducted interference of these circuits. Based on the obtained conducted emission performance evaluation results, the design of the chip can be optimized. How to evaluate the conducted emission performance of these circuits in the chip is a problem worthy of attention for those skilled in the art.

[0053] Exemplary Systems

[0054] The exemplary method section below involves the use of computer simulation technology (Computer Simulation Technology, CST). In order to facilitate the understanding of the exemplary method section below, a brief introduction to computer simulation technology is first given here.

[0055] It can be understood that computer simulation technology is a comprehensive technology that uses the achievements of computer science and technology to build a model of the simulated system and conduct dynamic experiments on the model under certain experimental conditions. It has the advantages of high efficiency, safety, and less constraints from environmental conditions. It has become an important tool for analyzing, designing, operating, evaluating, and training systems (especially complex systems).

[0056] Exemplary Methods

[0057] Figure 1 It is a flowchart of a method for evaluating the conducted emission performance of a chip provided by some exemplary embodiments of the present disclosure. Figure 1 The method shown may include step 110, step 120, step 130, step 140, step 150, step 160 and step 170. Optionally, Figure 1 The method shown can be performed in the early design stage of a chip.

[0058] Step 110: determine a first scattering parameter of a circuit under test in a chip.

[0059] Optionally, the circuit under test in the chip can be any circuit in the chip for which conducted emission performance evaluation is to be performed. In one example, the circuit under test can be a central processing unit (CPU). In another example, the circuit under test can be a microcontroller (MCU). In another example, the circuit under test can be a neural processing unit (NPU), which can also be called a neural network accelerator.

[0060] Optionally, the first scattering parameter of the circuit under test may also be referred to as an S parameter of the circuit under test, and the first scattering parameter of the circuit under test may be used to characterize the electrical characteristics of the circuit under test. It is understood that S parameters are an important concept in microwave theory and technology, and S parameters can fully describe any linear, time-invariant component and comprehensively depict the characteristics of the component in the system to which it may be connected.

[0061] It should be noted that in the early stage of chip design, the chip entity usually does not exist, and it is impossible to obtain the first scattering parameter of the circuit under test by detecting the circuit under test in the chip. Therefore, the first scattering parameter of the circuit under test can be determined by using computer simulation technology.

[0062] Step 120: determine a second scattering parameter of a target circuit connected to the circuit under test in a circuit board for carrying the chip.

[0063] Optionally, the circuit board for carrying the chip may be a printed circuit board (PCB). The circuit board for carrying the chip may contain a circuit connected to the circuit under test, and the circuit may be used as a target circuit.

[0064] Optionally, the second scattering parameter of the target circuit may also be referred to as an S parameter of the target circuit, and the second scattering parameter of the target circuit may be used to characterize electrical characteristics of the target circuit.

[0065] It should be noted that in the early stage of chip design, the chip entity usually does not exist, and the circuit board used to carry the chip usually does not exist either, so it is impossible to obtain the second scattering parameter of the target circuit by detecting the target circuit in the circuit board. Therefore, the second scattering parameter of the target circuit can be determined by using computer simulation technology.

[0066] Step 130: Determine a first variation relationship of a predetermined electrical parameter of the circuit under test with respect to time.

[0067] Optionally, the predetermined electrical parameter of the circuit under test may include, but is not limited to, the voltage and current of the circuit under test. If the predetermined electrical parameter is the voltage of the circuit under test, the first change relationship may be characterized by a Dv / dt file. If the predetermined electrical parameter is the current of the circuit under test, the first change relationship may be characterized by a Di / dt file. As an example, the Dv / dt file may include a curve in which the horizontal axis represents time and the vertical axis represents the voltage of the circuit under test. The Di / dt file may include a curve in which the horizontal axis represents time and the vertical axis represents the current of the circuit under test.

[0068] Optionally, similar to the first scattering parameter and the second scattering parameter, the first variation relationship may also be determined using computer simulation technology.

[0069] Step 140: determining a first simulation parameter based on the first scattering parameter, the second scattering parameter and the first variation relationship.

[0070] Optionally, based on the first variation relationship, a variation relationship of the resistance of the circuit under test relative to time may be determined. The variation relationship of the resistance of the circuit under test relative to time may also be referred to as a variation relationship of the load of the circuit under test relative to time. The first simulation parameter may include a first scattering parameter, a second scattering parameter, and a variation relationship of the resistance of the circuit under test relative to time.

[0071] Step 150: Simulate the chip and the circuit board based on the first simulation parameter to obtain a noise time domain waveform of a connection point between the circuit under test and the target circuit.

[0072] Optionally, the drawings, dimensions, materials and other information of the circuit board, the layout file of the chip, the packaging form, the heat and power consumption distribution diagram and other information, and the first simulation parameter determined in step 140 can be input into the computer simulation software, and the computer simulation software can establish a model of the circuit board and the chip, and perform dynamic experiments on the established model to obtain the noise time domain waveform of the connection point between the tested circuit and the target circuit through simulation calculation. The noise time domain waveform can be a waveform in which the horizontal axis represents time and the vertical axis represents the simulated noise value.

[0073] Step 160: convert the noise time domain waveform into a noise frequency domain waveform.

[0074] Optionally, the noise time domain waveform may be subjected to Fourier transformation, such as Fast Fourier Transformation (FFT), to obtain the noise time domain waveform. The noise time domain waveform may be a waveform in which the horizontal axis represents the frequency value and the vertical axis represents the simulated noise value.

[0075] Step 170: Determine the conducted emission performance evaluation result of the circuit under test based on the noise frequency domain waveform.

[0076] Since the horizontal axis of the noise frequency domain waveform represents the frequency value and the vertical axis represents the simulated noise value, by analyzing the noise frequency domain waveform, it can be determined whether the level of external conducted interference of the circuit under test is within the allowable range. If the level of external conducted interference of the circuit under test is within the allowable range, the conducted emission performance evaluation result of the circuit under test can be used to characterize that the conducted emission performance of the circuit under test meets the requirements. If the level of external conducted interference of the circuit under test is outside the allowable range, the conducted emission performance evaluation result of the circuit under test can be used to characterize that the conducted emission performance of the circuit under test does not meet the requirements.

[0077] In the embodiment of the present disclosure, the first scattering parameter of the circuit under test can be used to characterize the electrical characteristics of the circuit under test, the second scattering parameter of the target circuit connected to the circuit under test can be used to characterize the electrical characteristics of the target circuit, and the first change relationship of the predetermined electrical parameter of the circuit under test relative to time can be used to reflect the change law of the predetermined electrical parameter of the circuit under test in the time domain. Based on the first scattering parameter, the second scattering parameter and the first change relationship, the first simulation parameter is determined for the simulation of the chip and the circuit board, and the electrical characteristics of the circuit under test and the target circuit, as well as the change law of the predetermined electrical parameter of the circuit under test in the time domain can be effectively applied to the simulation process, so as to simulate the actual working state of the chip and the circuit board, and more reliably obtain the noise time domain waveform of the connection point between the circuit under test and the target circuit. Through the conversion between the frequency domain and the time domain, the noise frequency domain waveform can be obtained efficiently and quickly from the noise time domain waveform, so as to provide an effective reference for the conducted emission performance evaluation of the circuit under test, and ensure the accuracy and reliability of the conducted emission performance evaluation result obtained. Therefore, in the embodiment of the present disclosure, through the use of computer simulation technology, the conducted emission performance of the circuit under test in the chip can be effectively evaluated.

[0078] In some optional examples, in response to the target circuit being used to transfer electrical energy to the circuit under test, the predetermined electrical parameter may be current.

[0079] In some other optional examples, in response to the target circuit being used to receive an operating signal from the circuit under test, the predetermined electrical parameter may be a voltage.

[0080] If the target circuit is used to transmit electric energy to the circuit under test, the target circuit can also be called the power supply circuit or power supply network of the circuit under test, and the circuit under test can be called the powered circuit. In this case, the chip power consumption module (CPM model) can be used to generate a Di / dt file of the circuit under test, and the generated Di / dt file can be used to characterize the first change relationship.

[0081] If the target circuit is used to receive the working signal from the circuit under test, and the target circuit is different from the power supply circuit of the circuit under test, the circuit under test can be used as the working signal sender, and the target circuit can be used as the working signal receiver. In this case, the input / output buffer information specification (IBIS) model can be used to generate a Dv / dt file of the circuit under test, and the generated Dv / dt file can be used to characterize the first change relationship.

[0082] In this way, if the conducted emission performance of the circuit under test is to be evaluated, the circuit in the circuit board used to transmit electric energy to the circuit under test can be used as the target circuit, or the circuit in the circuit board used to receive the working signal from the circuit under test can be used as the target circuit. The target circuit can be selected according to the actual situation, which is highly flexible.

[0083] Figure 2 It is a flowchart of a method for determining a first simulation parameter provided by some exemplary embodiments of the present disclosure. Figure 2 The method shown may include step 210, step 220 and step 230. Optionally, a combination of step 210 to step 230 may be used as an optional implementation of step 140 of the present disclosure.

[0084] Step 210 , in response to the predetermined electrical parameter being current, using a preset resistor, converting the first variation relationship into a second variation relationship of voltage of the circuit under test relative to time.

[0085] Optionally, the preset resistor may be a pre-set resistor used to assist in the conversion of the change relationship. As an example, the preset resistor may be 1 ohm, 2 ohms, 3 ohms, etc., which are not listed here one by one.

[0086] It can be understood that the voltage, current, and resistance satisfy the following first formula: voltage = current * resistance. Then, using the preset resistance, the first change relationship can be converted into a second change relationship of the voltage of the measured circuit relative to time according to the first formula. For example, the preset resistance can be a. The first change relationship can be expressed as Figure 3 The curve shown is used to characterize the Figure 3 As shown, at time t1, the current of the circuit under test can be b1, then according to the first formula, at time t1, the voltage of the circuit under test can be a*b1. Figure 3 As shown, at time t2, the current of the circuit under test can be b2, then according to the first formula, at time t2, the voltage of the circuit under test can be a*b2. In a similar way, it can be determined that at time t3 and time t5, the voltage of the circuit under test is a*b1; at time t4 and time t6, the voltage of the circuit under test is a*b2. On this basis, it can be obtained Figure 4 The horizontal axis shows time, and the vertical axis shows a curve of the voltage of the circuit under test. The obtained curve can be used to characterize the second variation relationship of the voltage of the circuit under test with respect to time.

[0087] Step 220: using a preset conversion relationship between voltage and resistance, convert the second change relationship into a third change relationship of the resistance of the measured circuit relative to time.

[0088] Optionally, the conversion relationship between the preset voltage and the resistance may be a pre-set conversion relationship for assisting the conversion of the change relationship. The conversion relationship between the preset voltage and the resistance may be used to indicate that the voltage and the resistance satisfy the following second formula: resistance / voltage=c.

[0089] In one example, if some physically manufactured chips contain a circuit of the same type as the circuit being tested, the circuit can be tested to determine the resistance and voltage of the circuit. By dividing the determined resistance and voltage, a ratio can be obtained, which can be used as c in the second formula.

[0090] Optionally, the second change relationship can be converted into a third change relationship of the resistance of the measured circuit relative to time using the second formula. Figure 4 As shown, at time t1, the voltage of the circuit under test is a*b1, then according to the second formula, at time t1, the resistance of the circuit under test can be a*b1*c. Figure 4 As shown in the figure, at time t2, the voltage of the circuit under test is a*b2. According to the second formula, at time t2, the resistance of the circuit under test can be a*b2*c. In a similar way, it can be determined that at time t3 and time t5, the resistance of the circuit under test is a*b1*c; at time t4 and time t6, the resistance of the circuit under test is a*b2*c. On this basis, it can be obtained Figure 5 The horizontal axis shows time, and the vertical axis shows a curve of the resistance of the circuit under test. The obtained curve can be used to characterize the third variation relationship of the resistance of the circuit under test with respect to time.

[0091] Step 230: determining a first simulation parameter based on the first scattering parameter, the second scattering parameter and the third variation relationship.

[0092] Optionally, the first simulation parameter may include a first scattering parameter, a second scattering parameter and a third variation relationship.

[0093] In some embodiments, the first simulation parameter may also include some conventional parameters, such as ambient temperature, ambient humidity, etc.

[0094] In the embodiments of the present disclosure, when the predetermined electrical parameter is current, based on the preset resistance and the conversion relationship between the preset voltage and resistance, the first change relationship can be first converted into the second change relationship, and then the second change relationship can be converted into the third change relationship, thereby providing an effective reference for determining the first simulation parameter, which is conducive to ensuring the rationality of the determined first simulation parameter.

[0095] Figure 6 It is a flowchart of an information verification method provided by some exemplary embodiments of the present disclosure. Figure 6 The method shown may include step 610, step 620, step 630, step 640 and step 650. Optionally, step 610 to step 650 may be performed after step 220 of the present disclosure. Figure 6 The method shown may be applicable to the case where the target circuit is used to transfer power to the circuit under test.

[0096] Step 610: using the voltage of the electric energy transmitted from the target circuit to the circuit under test, convert the third variation relationship into a fourth variation relationship of the current of the circuit under test relative to time.

[0097] Optionally, the third variation relationship can be converted into a fourth variation relationship of the current of the circuit under test relative to time according to the first formula by using the voltage of the electric energy transmitted from the target circuit to the circuit under test. For example, the voltage of the electric energy transmitted from the target circuit to the circuit under test can be d. Figure 5 As shown, at time t1, the resistance of the circuit under test is a*b1*c. Then, according to the first formula, at time t1, the current of the circuit under test can be d / (a*b1*c). Figure 5 As shown, at time t2, the resistance of the measured circuit is a*b2*c. According to the first formula, at time t2, the current of the measured circuit can be d / (a*b2*c). In a similar way, it can be determined that at time t3 and time t5, the resistance of the measured circuit is d / (a*b1*c); at time t4 and time t6, the resistance of the measured circuit is d / (a*b2*c). On this basis, it can be obtained Figure 7 The horizontal axis shows time, and the vertical axis shows a curve of the current of the circuit under test. The obtained curve can be used to characterize the fourth variation relationship of the current of the circuit under test with respect to time.

[0098] Step 620: compare the fourth change relationship with the first change relationship to obtain a first comparison result.

[0099] Optionally, the fourth variation relationship can be used Figure 7 The first change relationship can be represented by the curve in Figure 3If the curve in is used to represent the fourth change relationship, then a similarity algorithm can be used to calculate the similarity of the two curves, and the determined similarity can be used as a first comparison result between the fourth change relationship and the first change relationship.

[0100] Step 630, based on the first comparison result, verify the preset information; wherein the preset information includes at least one of the following: a preset resistance, a conversion relationship between a preset voltage and resistance.

[0101] Optionally, the first comparison result may be a similarity. If the similarity as the first comparison result is greater than a preset similarity, it may be determined that the verification of the preset information has passed. If the similarity as the first comparison result is less than or equal to the preset similarity, it may be determined that the verification of the preset information has failed. As an example, the preset similarity may be 0.8, 0.85, 0.9, etc., which are not listed here one by one.

[0102] Step 640 : in response to the verification of the preset information being passed, determining a first simulation parameter based on the first scattering parameter, the second scattering parameter and the third variation relationship.

[0103] Optionally, step 640 may be used as an optional implementation of step 230 of the present disclosure.

[0104] Step 650: In response to the verification of the preset information failing, adjusting the preset information.

[0105] If the verification of the preset information fails, only the preset resistance can be adjusted, for example, the preset resistance is adjusted from a to a'. Alternatively, only the conversion relationship between the preset voltage and resistance can be adjusted, for example, c in the second formula is adjusted to c. Alternatively, the preset resistance and the conversion relationship between the preset voltage and resistance can be adjusted at the same time. After the adjustment of the preset information is completed, steps 210 and 220 can be re-executed based on the adjusted preset information to obtain the third change relationship again, and then steps 610 to 650 are executed based on the re-obtained third change relationship, and the subsequent steps are analogous and will not be repeated here.

[0106] In the embodiment of the present disclosure, the voltage of the electric energy transmitted from the target circuit to the circuit under test can be used to efficiently and quickly convert the third change relationship into the fourth change relationship. Since the fourth change relationship and the first change relationship both reflect the change law of the current of the circuit under test in the time domain, if the preset information used in the conversion process from the first change relationship to the third change relationship is set reasonably, theoretically, the fourth change relationship and the first change relationship should have a high consistency. In view of this, the fourth change relationship and the first change relationship can be compared to determine whether the fourth change relationship and the first change relationship actually have a high consistency, and on this basis, it can be inferred whether the rationality of the preset information meets the requirements. If the rationality of the preset information meets the requirements, the third change relationship obtained based on the preset information can be used to determine the first simulation parameter, which is conducive to ensuring the rationality of the determined first simulation parameter. If the rationality of the preset information does not meet the requirements, the preset information can be adjusted until the preset information that meets the requirements is obtained, and the third change relationship is obtained on the basis of the preset information that meets the requirements, which is used to determine the first simulation parameter, which is conducive to ensuring the rationality of the determined first simulation parameter. In this way, the determined first simulation parameters are used for the simulation of the circuit board and the chip, which is conducive to ensuring the reliability of the final conducted emission performance evaluation result.

[0107] Figure 8 It is a flowchart of a method for determining a first scattering parameter of a circuit under test in a chip provided by some exemplary embodiments of the present disclosure. Figure 8 The method shown may include step 810 , step 820 , step 830 , and step 840 .

[0108] Step 810, determining a designated position of an input terminal of the circuit under test.

[0109] Optionally, a first input operation of a user may be received, and the first input operation may be used to specify the location of an input port of the circuit under test, and the location specified by the first input operation may be used as the designated location of the input end of the circuit under test. The first input operation may include but is not limited to a touch input operation, a voice input operation, a keyboard input operation, etc.

[0110] Step 820, determining a designated position of an output terminal of the circuit under test.

[0111] Optionally, a second input operation of the user may be received, and the second input operation may be used to specify the location of the output port of the circuit under test, and the location specified by the second input operation may be used as the output port designated location of the circuit under test. The second input operation may include but is not limited to a touch input operation, a voice input operation, a keyboard input operation, etc.

[0112] Step 830, determining a second simulation parameter based on the input end designated position and the output end designated position.

[0113] Optionally, first position information of the specified position of the input end may be determined. The first position information may be in the form of coordinates. Similarly, second position information of the specified position of the output end may also be determined. The second position information may be in the form of coordinates. The second simulation parameter may include the first position information and the second position information.

[0114] Step 840: Simulate the chip based on the second simulation parameter to obtain a first scattering parameter of the circuit under test.

[0115] Optionally, the layout file, packaging form, heat and power consumption distribution diagram and other information of the chip, as well as the second simulation parameters determined in step 830 can be input into the computer simulation software. The computer simulation software can build a model of the chip based on this, and conduct dynamic experiments on the built model to obtain the first scattering parameters of the circuit under test through simulation calculation.

[0116] In the embodiments of the present disclosure, the second simulation parameter can be determined efficiently and quickly based on the specified position of the input terminal and the specified position of the output terminal of the circuit under test for use in chip simulation, thereby enabling the first scattering parameter of the circuit under test to be determined efficiently and quickly through the use of computer simulation technology.

[0117] The above describes the method for determining the first scattering parameter of the circuit under test, and the second scattering parameter of the target circuit can be determined in a similar manner. For example, the input terminal designated position and the output terminal designated position of the target circuit can be determined, and based on the input terminal designated position and the output terminal designated position of the target circuit, corresponding simulation parameters can be determined for use in simulating the circuit board, thereby obtaining the second scattering parameter of the target circuit.

[0118] Fig. 9 It is a flowchart of a method for determining a first variation relationship of a predetermined electrical parameter of a circuit under test with respect to time provided by some exemplary embodiments of the present disclosure. Fig. 9 The method shown may include step 910 , step 920 , and step 930 .

[0119] Step 910, determining the operating mode of the circuit under test.

[0120] Optionally, the circuit under test can be configured to have multiple modes. For example, the circuit under test can be a neural network accelerator, and the neural network accelerator can be configured to include a first mode and a second mode; wherein, in the first mode, the neural network accelerator can be used to perform vector computing tasks; and in the second mode, the neural network accelerator can be used to perform tensor computing tasks. Vector computing can include point-to-point element-wise computing. Tensor computing can include convolution computing.

[0121] Optionally, a third input operation of the user may be received, and the third input operation may be used to select one of the multiple modes, which may be used as the working mode in step 910. The third input operation may include but is not limited to a touch input operation, a voice input operation, a keyboard input operation, and the like.

[0122] Step 920: Determine a third simulation parameter based on the working mode.

[0123] Optionally, the third simulation parameter may include an operating mode.

[0124] Step 930: Simulate the chip and the circuit board based on the third simulation parameter to obtain a first variation relationship of a predetermined electrical parameter of the circuit under test with respect to time.

[0125] Optionally, the drawings, dimensions, materials and other information of the circuit board, the layout files, packaging forms, heat and power consumption distribution diagrams and other information of the chip, as well as the third simulation parameters determined in step 930 can be input into the computer simulation software. The computer simulation software can establish a model of the circuit board and the chip based on this, and conduct dynamic experiments on the established model to obtain the first change relationship of the predetermined electrical parameters of the circuit under test with respect to time through simulation calculation.

[0126] It should be noted that, according to the working mode of the circuit under test, it is possible to clearly define how the circuit under test works. For example, the circuit under test may include multiple metal-oxide-semiconductor field-effect transistors (MOSFETs). According to the working mode of the circuit under test, it is possible to clearly define when each MOSFET is turned on and when it is turned off. It is understandable that the state of these MOSFETs will affect the voltage, current, etc. of the circuit under test. In the embodiments of the present disclosure, the third simulation parameter determined based on the working mode of the circuit under test is used for the simulation of the chip and the circuit board, which is conducive to effectively applying factors that may affect the voltage, current, etc. of the circuit under test to the simulation process, thereby being able to better ensure the reliability of the first change relationship obtained through simulation.

[0127] Fig.10It is a flowchart of a method for determining a conducted emission performance evaluation result of a circuit under test based on a noise frequency domain waveform provided by some exemplary embodiments of the present disclosure. Fig.10 The method shown may include step 1010 , step 1020 , step 1030 , and step 1040 .

[0128] Step 1010: Determine the simulated noise values ​​corresponding to the multiple frequency markers based on the noise frequency domain waveform.

[0129] Optionally, the noise frequency domain waveform can be a waveform in which the horizontal axis represents the frequency value and the vertical axis represents the simulated noise value. Then, the simulated noise values ​​corresponding to the multiple frequency identifiers can be extracted from the noise frequency domain waveform. The frequency identifier can be either a frequency value or a frequency range. The frequency range can also be called a frequency band. In an example, the frequency range of 0.15MHz to 3GMHz can be divided into multiple small frequency ranges, and each small frequency range obtained by the equal division can be used as a frequency identifier.

[0130] Step 1020: Determine the noise thresholds corresponding to the multiple frequency identifiers.

[0131] Optionally, noise thresholds corresponding to multiple frequency identifiers may be preset; wherein the noise threshold corresponding to any frequency identifier may be a maximum noise value set for the frequency identifier. The noise thresholds corresponding to the multiple frequency identifiers may be stored in a memory. In step 1020, the noise thresholds corresponding to the multiple frequency identifiers may be read from the memory.

[0132] Step 1030: Compare the simulated noise values ​​corresponding to the multiple frequency identifiers with the corresponding noise thresholds to obtain second comparison results corresponding to the multiple frequency identifiers.

[0133] Optionally, for each frequency identifier among the multiple frequency identifiers, the simulated noise value corresponding to the frequency identifier may be compared with the noise threshold corresponding to the frequency identifier, and the comparison result corresponding to the frequency identifier may be used as the second comparison result corresponding to the frequency identifier.

[0134] Step 1040: Determine a conducted emission performance evaluation result of the circuit under test based on the second comparison results corresponding to each of the multiple frequency identifiers.

[0135] Optionally, if the second comparison results corresponding to each of the multiple frequency identifiers are used to characterize that the corresponding simulated noise value is less than or equal to the corresponding noise threshold, it can be determined that the level of external conducted interference of the circuit under test is within the allowable range, and the conducted emission performance evaluation result of the circuit under test can be used to characterize that the conducted emission performance of the circuit under test meets the requirements. If the second comparison results corresponding to at least some of the frequency identifiers in the multiple frequency identifiers are used to characterize that the corresponding simulated noise value is greater than the corresponding noise threshold, it can be determined that the level of external conducted interference of the circuit under test is outside the allowable range, and the conducted emission performance evaluation result of the circuit under test can be used to characterize that the conducted emission performance of the circuit under test does not meet the requirements. In this way, the allowable range of external conducted interference of the circuit under test can be limited by the noise thresholds corresponding to each of the multiple frequency identifiers. For example, in the coordinate system where the noise frequency domain waveform is located, the area surrounded by the curve formed by the noise thresholds corresponding to each of the multiple frequency identifiers connected in sequence, the horizontal axis, and the vertical axis can be used to represent the allowable range.

[0136] In some embodiments, the multiple frequency identifiers may be multiple frequency bands, and if the simulated noise values ​​corresponding to some of the frequency bands are greater than the corresponding noise thresholds, these frequency bands may be optimized.

[0137] In the embodiments of the present disclosure, the simulated noise values ​​corresponding to the multiple frequency identifiers can be determined efficiently and quickly based on the noise frequency domain waveform. By comparing the simulated noise values ​​corresponding to the multiple frequency identifiers with the corresponding noise thresholds, it can be determined whether the level of external conducted interference of the circuit under test is within the allowable range, thereby efficiently and quickly determining the conducted emission performance evaluation result of the circuit under test.

[0138] In some optional examples, such as Figure 11-1 As shown, the S parameters of the circuit under test, the S parameters of the target circuit, and the Di / dt file of the circuit under test can be determined. Next, the Di / dt file of the circuit under test can be converted into the Dv / dt file of the circuit under test, and then the converted Dv / dt file is converted into the load-to-time variation relationship of the circuit under test (equivalent to the third variation relationship mentioned above). Optionally, the preset information mentioned above can be used in the conversion process from the Di / dt file of the circuit under test to the load-to-time variation relationship of the circuit under test. The preset information can be used. Figure 6 If the preset information is verified, the first simulation parameter can be determined based on the S parameter of the circuit under test, the S parameter of the target circuit, and the load of the circuit under test relative to time. Figure 11-2 The conducted emission simulation link shown. The conducted emission simulation link may include an impedance matching circuit, and the impedance matching circuit may refer to Figure 11-3The number of the circuits under test may be more than one, and accordingly, the number of the impedance matching circuits may also be more than one. Combining the first simulation parameter and the established conducted emission simulation link, the chip and the circuit board may be simulated to obtain the noise time domain waveform of the connection point between the circuit under test and the target circuit. Optionally, Figure 11-3 In the impedance matching circuit shown, position A can be used to contact the connection point, and the noise time domain waveform of the connection point can be obtained at position B. Through computer simulation software, the noise time domain waveform can be Fourier transformed to obtain the noise frequency waveform. Based on the noise frequency waveform, the conducted emission performance evaluation result of the circuit under test can be determined. Based on the obtained conducted emission performance evaluation result, the design scheme of the chip can be optimized.

[0139] In some optional examples, such as Figure 11-4 As shown, the circuit board can be powered by the power supply, and accordingly, the target circuit in the circuit board can power the circuit under test in the chip. In addition, the Di / dt file can be generated through the back-end model (such as the CPM model mentioned above). The connection point between the circuit under test and the target circuit mentioned above can also be called a test point.

[0140] In summary, by adopting the embodiments of the present disclosure, the conducted emission performance of the circuit under test in the chip can be effectively evaluated. Based on the obtained conducted emission performance evaluation results, the design scheme of the chip can be optimized to ensure that the electromagnetic interference (EMI) of the chip meets the prescribed requirements, which is conducive to shortening the chip development cycle and reducing the chip design cost and test optimization cost.

[0141] Exemplary Devices

[0142] Fig.12 It is a schematic diagram of the structure of a chip conduction emission performance evaluation device provided by some exemplary embodiments of the present disclosure. Fig.12 The apparatus shown may include:

[0143] A first determination module 1210 is used to determine a first scattering parameter of a circuit under test in a chip;

[0144] A second determination module 1220 is used to determine a second scattering parameter of a target circuit connected to the circuit under test in a circuit board for carrying a chip;

[0145] A third determination module 1230, configured to determine a first variation relationship of a predetermined electrical parameter of the circuit under test with respect to time;

[0146] A fourth determination module 1240, configured to determine a first simulation parameter based on the first scattering parameter determined by the first determination module 1210, the second scattering parameter determined by the second determination module 1220, and the first variation relationship determined by the third determination module 1230;

[0147] A simulation module 1250 is used to simulate the chip and the circuit board based on the first simulation parameter determined by the fourth determination module 1240 to obtain a noise time domain waveform of a connection point between the circuit under test and the target circuit;

[0148] A first conversion module 1260, configured to convert the noise time domain waveform obtained by the simulation module 1250 into a noise frequency domain waveform;

[0149] The fifth determination module 1270 is used to determine the conducted emission performance evaluation result of the circuit under test based on the noise frequency domain waveform converted by the first conversion module 1260.

[0150] In some optional examples,

[0151] In response to the target circuit being used to transfer electrical energy to the circuit under test, the predetermined electrical parameter is current;

[0152] or,

[0153] In response to the target circuit being used to receive an operating signal from the circuit under test, the predetermined electrical parameter is a voltage.

[0154] In some optional examples, such as Fig.13 As shown, the fourth determination module 1240 includes:

[0155] A first conversion submodule 1310 is used for converting the first change relationship determined by the third determination module 1230 into a second change relationship of voltage of the circuit under test relative to time using a preset resistance in response to the predetermined electrical parameter being current;

[0156] The second conversion submodule 1320 is used to convert the second change relationship determined by the first conversion submodule 1310 into a third change relationship of the resistance of the measured circuit relative to time by using a preset conversion relationship between voltage and resistance;

[0157] The first determination submodule 1330 is used to determine a first simulation parameter based on the first scattering parameter determined by the first determination module 1210 , the second scattering parameter determined by the second determination module 1220 , and the third change relationship converted by the second conversion submodule 1320 .

[0158] In some optional examples, such as Fig.14 As shown, the device provided by the embodiment of the present disclosure also includes:

[0159] A second conversion module 1410 is used to convert the third change relationship obtained by the second conversion submodule 1320 into a fourth change relationship of the current of the circuit under test relative to time by using the voltage of the electric energy transmitted from the target circuit to the circuit under test, after the second conversion submodule 1320 converts the second change relationship into a third change relationship of the resistance of the circuit under test relative to time by using the conversion relationship between the preset voltage and resistance;

[0160] A comparison module 1420, configured to compare the fourth change relationship obtained by the second conversion module 1410 with the first change relationship determined by the third determination module 1230 to obtain a first comparison result;

[0161] The verification module 1430 is used to verify the preset information based on the first comparison result obtained by the comparison module 1420; wherein the preset information includes at least one of the following: a preset resistance, a conversion relationship between a preset voltage and resistance;

[0162] A triggering module 1440, configured to trigger the fourth determining module 1240 in response to the verification module 1430 verifying the preset information successfully;

[0163] The adjustment module 1450 is configured to adjust the preset information in response to the verification module 1430 failing to verify the preset information.

[0164] In some optional examples, such as Fig.15 As shown, the first determination module 1210 includes:

[0165] The second determination submodule 1510 is used to determine the designated position of the input terminal of the circuit under test;

[0166] The third determination submodule 1520 is used to determine the designated position of the output terminal of the circuit under test;

[0167] A fourth determining submodule 1530, configured to determine a second simulation parameter based on the input terminal designated position determined by the second determining submodule 1510 and the output terminal designated position determined by the third determining submodule 1520;

[0168] The first simulation submodule 1540 is used to simulate the chip based on the second simulation parameter determined by the fourth determination submodule 1530 to obtain a first scattering parameter of the circuit under test.

[0169] In some optional examples, such as Fig.16 As shown, the third determination module 1230 includes:

[0170] A fifth determination submodule 1610 is used to determine the working mode of the circuit under test;

[0171] A sixth determining submodule 1620, configured to determine a third simulation parameter based on the working mode determined by the fifth determining submodule 1610;

[0172] The second simulation submodule 1630 is used to simulate the chip and the circuit board based on the third simulation parameter determined by the sixth determination submodule 1620 to obtain a first variation relationship of a predetermined electrical parameter of the circuit under test with respect to time.

[0173] In some optional examples, such as Fig.17 As shown, the fifth determination module 1270 includes:

[0174] A seventh determination submodule 1710 is configured to determine the simulated noise values ​​corresponding to the multiple frequency identifiers based on the noise frequency domain waveform converted by the first conversion module 1260;

[0175] An eighth determination submodule 1720 is configured to determine a noise threshold value corresponding to each of the plurality of frequency identifiers;

[0176] The comparison submodule 1730 is used to compare the simulated noise values ​​corresponding to the multiple frequency identifiers determined by the seventh determination submodule 1710 with the corresponding noise thresholds to obtain second comparison results corresponding to the multiple frequency identifiers;

[0177] The ninth determination submodule 1740 is used to determine the conducted emission performance evaluation result of the circuit under test based on the second comparison results corresponding to the multiple frequency identifiers obtained by the comparison submodule 1730.

[0178] In the device of the present disclosure, the various optional embodiments, optional implementation methods and optional examples disclosed above can be flexibly selected and combined as needed to achieve corresponding functions and effects, and the present disclosure does not list them one by one.

[0179] Exemplary Electronic Devices

[0180] Fig.18 The block diagram of an electronic device according to an embodiment of the present disclosure is illustrated. The electronic device 1800 includes one or more processors 1810 and a memory 1820 .

[0181] The processor 1810 may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 1800 to perform desired functions.

[0182] The memory 1820 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 1810 may execute one or more computer program instructions to implement the methods of the various embodiments of the present disclosure described above and / or other desired functions.

[0183] In one example, the electronic device 1800 may further include: an input device 1830 and an output device 1840 , and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0184] The input device 1830 may also include, for example, a keyboard, a mouse, etc.

[0185] The output device 1840 can output various information to the outside, and may include, for example, a display, a speaker, a printer, a communication network and its connected remote output device, etc.

[0186] Of course, to simplify, Fig.18 Only some of the components related to the present disclosure in the electronic device 1800 are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, according to specific application situations, the electronic device 1800 may also include any other appropriate components.

[0187] Exemplary computer program products and computer-readable storage media

[0188] In addition to the above-mentioned methods and devices, an embodiment of the present disclosure may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the method according to various embodiments of the present disclosure described in the above-mentioned "Exemplary Method" section of this specification.

[0189] The computer program product may be written in any combination of one or more programming languages ​​to write program code for performing the operations of the disclosed embodiments, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0190] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, enables the processor to execute the steps of the method according to various embodiments of the present disclosure described in the above “Exemplary Method” section of this specification.

[0191] The computer readable storage medium can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can include, for example, but is not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0192] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations. It cannot be considered that these advantages, strengths, effects, etc. must be possessed by each embodiment of the present disclosure. The specific details disclosed above are only for the purpose of illustration and ease of understanding, not limitation. The above details do not limit the present disclosure to being implemented by adopting the above specific details.

[0193] Those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the present disclosure claims and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A method for evaluating the conducted emission performance of a chip, comprising: Determining a first scattering parameter of a circuit under test in a chip; Determining a second scattering parameter of a target circuit connected to the circuit under test in a circuit board carrying the chip; Determining a first variation relationship of a predetermined electrical parameter of the circuit under test with respect to time; determining a first simulation parameter based on the first scattering parameter, the second scattering parameter, and the first variation relationship; Based on the first simulation parameters, simulating the chip and the circuit board to obtain a noise time domain waveform of a connection point between the circuit under test and the target circuit; Converting the noise time domain waveform into a noise frequency domain waveform; Based on the noise frequency domain waveform, a conducted emission performance evaluation result of the circuit under test is determined.

2. The method according to claim 1, wherein: In response to the target circuit being used to transfer electrical energy to the circuit under test, the predetermined electrical parameter is current; or, In response to the target circuit being used to receive an operating signal from the circuit under test, the predetermined electrical parameter is a voltage.

3. The method according to claim 2, wherein: The determining a first simulation parameter based on the first scattering parameter, the second scattering parameter and the first variation relationship includes: In response to the predetermined electrical parameter being current, using a preset resistor, converting the first variation relationship into a second variation relationship of voltage of the measured circuit relative to time; Using a preset conversion relationship between voltage and resistance, convert the second change relationship into a third change relationship of the resistance of the measured circuit relative to time; The first simulation parameter is determined based on the first scattering parameter, the second scattering parameter, and the third variation relationship.

4. The method according to claim 3, wherein: After converting the second change relationship into a third change relationship of the resistance of the measured circuit relative to time by using the preset conversion relationship between voltage and resistance, the method further includes: Using the voltage of the electric energy transmitted from the target circuit to the circuit under test, the third variation relationship is converted into a fourth variation relationship of the current of the circuit under test relative to time; Comparing the fourth change relationship with the first change relationship to obtain a first comparison result; Based on the first comparison result, the preset information is verified; wherein the preset information includes at least one of the following: the preset resistance, the conversion relationship between the preset voltage and the resistance; In response to the verification of the preset information being passed, executing the step of determining a first simulation parameter based on the first scattering parameter, the second scattering parameter and the third variation relationship; In response to the preset information being checked and failing, the preset information is adjusted.

5. The method according to any one of claims 1 to 4, wherein: The determining of a first scattering parameter of a circuit under test in a chip comprises: Determining a designated position of an input terminal of the circuit under test; Determining a designated position of an output terminal of the circuit under test; Determining a second simulation parameter based on the input end designated position and the output end designated position; The chip is simulated based on the second simulation parameter to obtain the first scattering parameter of the circuit under test.

6. The method according to any one of claims 1 to 4, wherein: Determining a first variation relationship of a predetermined electrical parameter of the circuit under test relative to time includes: Determining an operating mode of the circuit under test; Based on the working mode, determining a third simulation parameter; Based on the third simulation parameter, the chip and the circuit board are simulated to obtain a first variation relationship of a predetermined electrical parameter of the circuit under test with respect to time.

7. The method according to any one of claims 1 to 4, wherein: The step of determining a conducted emission performance evaluation result of the circuit under test based on the noise frequency domain waveform includes: Based on the noise frequency domain waveform, determining the simulated noise value corresponding to each of the plurality of frequency identifiers; Determine a noise threshold value corresponding to each of the plurality of frequency identifiers; Compare the simulated noise values ​​corresponding to each of the plurality of frequency identifiers with the corresponding noise threshold to obtain second comparison results corresponding to each of the plurality of frequency identifiers; Based on the second comparison results corresponding to each of the plurality of frequency identifiers, a conducted emission performance evaluation result of the circuit under test is determined.

8. A device for evaluating the conducted emission performance of a chip, comprising: A first determination module, used to determine a first scattering parameter of a circuit under test in a chip; A second determination module, used to determine a second scattering parameter of a target circuit connected to the circuit under test in a circuit board for carrying the chip; A third determination module, used to determine a first variation relationship of a predetermined electrical parameter of the circuit under test with respect to time; a fourth determining module, configured to determine a first simulation parameter based on the first scattering parameter determined by the first determining module, the second scattering parameter determined by the second determining module, and the first change relationship determined by the third determining module; A simulation module, configured to simulate the chip and the circuit board based on the first simulation parameters determined by the fourth determination module, and obtain a noise time domain waveform of a connection point between the circuit under test and the target circuit; A first conversion module, used for converting the noise time domain waveform obtained by the simulation module into a noise frequency domain waveform; A fifth determination module is used to determine a conducted emission performance evaluation result of the circuit under test based on the noise frequency domain waveform obtained by the first conversion module.

9. A computer-readable storage medium storing a computer program, wherein the computer program is used to execute the method for evaluating the conducted emission performance of a chip as claimed in any one of claims 1 to 7.

10. An electronic device, comprising: processor; a memory for storing instructions executable by the processor; The processor is used to read the executable instructions from the memory and execute the instructions to implement the conducted emission performance evaluation method of the chip described in any one of claims 1-7.

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