Fault injection evaluation method and system, and computer program product and medium

Abstract

A fault injection evaluation method and system, and a computer program product and a computer-readable storage medium. The fault injection evaluation method comprises: configuring a target number of cycles (301), wherein the target number of cycles is the number of cycles during which a circuit under test operates after being reset; at a configured fault injection moment, injecting a fault into said circuit (302); acquiring a fault output result that is output by said circuit after the fault is injected (303); and comparing the fault output result with a reference output result, so as to acquire a fault evaluation result (304).

Description

Fault injection evaluation method and system, computer program product, and medium

[0001] The present application claims priority to the Chinese patent application No. 202411038330.X, filed on July 30, 2024, and entitled "Fault injection evaluation method and system, computer program product, and medium", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of FPGA technology, and in particular to a fault injection evaluation method and device, a computer program, and a medium. BACKGROUND

[0003] A static random access memory (SRAM) type field programmable gate array (FPGA) chip is susceptible to radiation effects, especially single event upset (SEU) effects, in a space environment. The single event upset in the space environment is simulated by a fault injection method to evaluate the anti-radiation performance of the FPGA chip.

[0004] A conventional fault injection evaluation method randomly injects faults into a reference code stream configured to an FPGA chip. SUMMARY

[0005] The present application aims to provide a fault injection evaluation method and system, a computer program product, and a medium, which can achieve fault injection and fault evaluation at any time.

[0006] In a first aspect, the present application provides a fault injection evaluation method, comprising: configuring a target cycle number, the target cycle number being a cycle number of a to-be-tested circuit running after being reset; injecting a fault into the to-be-tested circuit at a configured fault injection time; obtaining a fault output result output by the to-be-tested circuit after the fault is injected; and comparing the fault output result with a reference output result to obtain a fault evaluation result.

[0007] The cycle number of the to-be-tested circuit running after being reset is configured, a fault is injected into the to-be-tested circuit at the configured fault injection time, and then the fault output result can be obtained. The fault evaluation result can be obtained by comparing the fault output result with the reference output result obtained in advance. The running state of the to-be-tested circuit can be accurately controlled by configuring the fault injection time, and fault injection and fault evaluation at any time are achieved.

[0008] Optionally, the reference output result is obtained in the following manner: the target number of cycles is configured for the circuit under test; a gated reset signal is output to the circuit under test to control the circuit under test to reset; and an output result of the circuit under test is taken as the reference output result; the output result of the circuit under test is an operation result obtained after the circuit under test runs the test data for the target number of cycles after the gated reset signal is released.

[0009] Optionally, the configured fault injection time is an initial time before the circuit under test is reset; and the fault output result output by the circuit under test after the fault is injected is obtained in the following manner: the target number of cycles is configured for the circuit under test; a gated reset signal is output to the circuit under test to control the circuit under test to reset; and the fault output result output by the circuit under test is obtained; the fault output result is an operation result obtained after the circuit under test runs the test data with the injected fault for the target number of cycles after the gated reset signal is released.

[0010] Optionally, the fault injection evaluation method further comprises: disconnecting a gated clock of the circuit under test when the target number of cycles is configured for the circuit under test; and restoring the gated clock of the circuit under test after the configuration of the target number of cycles is completed.

[0011] Optionally, the configured fault injection time is a time after the circuit under test runs for M cycles after being reset; and the fault output result output by the circuit under test after the fault is injected is obtained in the following manner: a remaining number of cycles is configured for the circuit under test, the remaining number of cycles being N-M; and the fault output result output by the circuit under test is obtained; the fault output result is an output result obtained after the circuit under test runs the test data with the injected fault for N-M cycles, N being the target number of cycles.

[0012] Optionally, the fault injection evaluation method further comprises: disconnecting a gated clock of the circuit under test when the remaining number of cycles is configured for the circuit under test; and restoring the gated clock of the circuit under test after the configuration of the remaining number of cycles for the circuit under test is completed.

[0013] Optionally, the fault injection into the circuit under test comprises: injecting a fault into the circuit under test by a fault injection module; and the fault comprises any one of the following: a single-bit error, a multi-bit error.

[0014] In a second aspect, the present application also provides a fault injection evaluation system, comprising: a host computer, a control circuit, and a circuit under test, wherein: the evaluation control module is adapted to configure a target number of cycles, the target number of cycles being a number of cycles that the circuit under test runs after being reset; at a configured fault injection time, injecting a fault into the circuit under test; obtaining a fault output result output by the circuit under test after the fault is injected; and the host computer is adapted to compare the fault output result with a reference output result, and obtain a fault evaluation result.

[0015] In a third aspect, the present application also provides a computer readable storage medium, which is a non-volatile storage medium or a non-transitory storage medium, and has stored thereon a computer program, which, when executed by a processor, performs the steps of any of the above-mentioned methods.

[0016] In a fourth aspect, the present application also provides a computer program product, comprising computer programs / instructions, which, when executed by a processor, implement the steps of any of the above-mentioned fault injection evaluation methods. BRIEF DESCRIPTION OF DRAWINGS

[0017] FIG. 1 is a structural schematic diagram of a fault injection evaluation system in an embodiment of the present application;

[0018] FIG. 2 is a flowchart of obtaining a reference output result in an embodiment of the present application;

[0019] FIG. 3 is a flowchart of a fault injection evaluation method in an embodiment of the present application. DETAILED DESCRIPTION

[0020] In the prior art, the traditional fault injection evaluation method can refer to the following steps:

[0021] 1) Analyzing the relationship between the reset initial value parameter and the reset polarity parameter of the target register, and finally obtaining the true value relationship table of them and the current value of the register;

[0022] 2) In the ISE development environment, artificially modifying the reset initial value parameter of the register, setting it to the opposite state of the original state, and then comparing the configuration code streams before and after the modification, to obtain the offset of the reset initial value parameter of the register in the code stream;

[0023] 3) Repeating step 2) to obtain the offset increment of the reset initial value parameter of the other registers relative to the reference register in the code stream, and then calculating the offset of the reset initial value parameters of all registers in the code stream;

[0024] 4) modifying the reset polarity parameter of the register manually in the ISE development environment, setting the parameter to the opposite state of the original state, comparing the configuration code stream before and after the modification, and thus obtaining the offset of the reset polarity parameter of the register in the code stream;

[0025] 5) repeating step 4) to obtain the offset increment of the reset polarity parameter of the other registers in the adjacent rows and columns relative to the reference register in the code stream, and then deducing the offset of the reset polarity parameter of all registers in the code stream;

[0026] 6) determining the X and Y coordinate information of the target register, obtaining the fault bit stream offset required for fault injection of the target register through the relationship between the coordinate information and the code stream offset of the reset initial value parameter and the reset polarity parameter of the register;

[0027] 7) using a fault injector to write the original configuration data and the fault configuration data to the FPGA through a fault injection interface (SelectMAP or JTAG), comparing the working states of the FPGA before and after the fault injection, and completing the fault injection evaluation.

[0028] However, the above-mentioned fault injection method needs to reacquire the relationship between the reset initial value parameter and the reset polarity parameter, the offset of the reset initial value parameter and the reset polarity parameter in the code stream, and the offset increment of the reset initial value parameter and the reset polarity parameter of the other registers in the adjacent rows and columns relative to the reference register in the code stream, etc. when transplanted to different models of FPGA, and the universality is poor. Moreover, the above-mentioned fault injection method can only inject faults to the initial value of the register, and cannot control the fault injection time.

[0029] In the embodiment of the present application, the number of cycles of the to-be-tested circuit running after being configured to reset is configured, and at the fault injection time, a fault is injected to the to-be-tested circuit, and thus the fault output result can be obtained. The fault evaluation result can be obtained by comparing the fault output result with the reference output result obtained in advance. By configuring the fault injection time, the running state of the to-be-tested circuit can be accurately controlled, and the fault injection and fault evaluation at any time are realized. Moreover, the present application can be applied to different models of FPGA, and the universality is strong.

[0030] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application are described in detail below with reference to the drawings.

[0031] Referring to FIG. 1, a fault injection evaluation system in an embodiment of the present application is given.

[0032] In the embodiment of the present application, the fault injection evaluation system can include a host computer 21, an evaluation control module 22, and a to-be-tested circuit 23.

[0033] In specific implementations, the evaluation control module 22 can communicate with the host computer 21 through a Joint Test Action Group (JTAG) interface. Alternatively, the evaluation control module 22 can communicate with the host computer 21 through a Universal Asynchronous Receiver Transmitter (UART) interface.

[0034] In specific implementations, the tester can pre-configure an execution file or program corresponding to the fault injection evaluation method, and input the execution file or program corresponding to the fault injection evaluation method into the host computer 21. The host computer 21 writes the execution file or program corresponding to the fault injection evaluation into the evaluation control module 22, so as to realize execution of the fault injection evaluation method by the evaluation control module 22. The tester can also trigger the evaluation control module 22 to start executing the fault injection evaluation method through the host computer 21.

[0035] In some embodiments, the tester can merge a design file corresponding to the evaluation control module 22 and a design file of the circuit under test 23, and input them into the host computer 21. An EDA tool (vivado) can be run in the host computer 21, and the tester can add part of the reconfiguration design function in the EDA tool to generate a total bit stream and a partial module bit stream. The total bit stream includes a bit stream corresponding to the evaluation control module 22 and a bit stream corresponding to the circuit under test 23, and the partial module bit stream includes a bit stream corresponding to the circuit under test 23. In the host computer 21, a register netlist location file corresponding to the circuit under test 23 can also be generated, and the register netlist location file is parsed to obtain the address of the register corresponding to the circuit under test 23 in the bit stream. A fault injection list file for storing fault injection addresses can also be generated to serve as an input file for subsequent fault injection.

[0036] In the embodiments of the present application, the input of the evaluation control module 22 can include a clock signal clk. The clock signal clk of the evaluation control module 22 can be provided by other clock generation circuits.

[0037] The evaluation control module 22 can output a gated clock gated_dut_clk and a gated reset signal gated_dut_rst based on the clock signal clk. Specifically, the evaluation control module 22 can perform gating processing on the clock signal clk and the reset signal rst to obtain the gated clock gated_dut_clk and the gated reset signal gated_dut_rst.

[0038] The evaluation control module 22 can control the working state of the DUT 23 through a gated clock gated_dut_clk. The evaluation control module 22 can enable a gated reset signal gated_dut_rst to control the reset of the DUT 23. The DUT 23 is reset after the gated reset signal gated_dut_rst is enabled, and starts to work after the gated reset signal gated_dut_rst is released, to perform operation on the input data.

[0039] In the embodiment of the present application, the evaluation control module 22 can configure the target period number N of the DUT 23. The target period number N is the period number of the DUT 23 after the gated reset signal gated_dut_rst is released.

[0040] When the period number of the DUT 23 after the reset is configured to reach the target period number, the evaluation control module 22 can first cut off the output of the gated clock gated_dut_clk, that is, stop outputting the gated clock gated_dut_clk to the DUT 23. In this case, the DUT 23 is in a non-working state.

[0041] In some embodiments, the evaluation control module 22 can include a counter register, and the value of the counter register can be configured by the host computer 21. The value of the counter register is the period number of the DUT 23 after the gated reset signal gated_dut_rst is released. The value of the counter register can be configured according to specific application scenarios.

[0042] In the embodiment of the present application, the tester can send an enable instruction to the evaluation control module 22 through the host computer 21. The enable instruction can be used to enable the evaluation control module 22, that is, control the evaluation control module 22 to start working. When the evaluation control module 22 starts working, the evaluation control module 22 outputs the gated clock gated_dut_clk to the DUT 23. The evaluation control module 22 outputs the gated reset signal gated_dut_rst to the DUT 23 after a first time period. The gated reset signal gated_dut_rst can last for a second time period. The evaluation control signal releases the gated reset signal gated_dut_rst after detecting that the time period of the gated reset signal gated_dut_rst reaches the second time period.

[0043] After the gated reset signal gated_dut_rst is released, the DUT 23 can perform operation on the input data, and the period number of the operation is the target period number configured above. The DUT 23 outputs the operation result after running for N periods.

[0044] When the evaluation control module 22 detects that the number of cycles in which the DUT 23 operates after the gated reset signal gated_dut_rst is released reaches N, the evaluation control module 22 stops outputting the gated clock gated_dut_clk to the DUT 23, thereby controlling the DUT 23 to stop operating. That is, the DUT 23 operates for N cycles after the gated reset signal gated_dut_rst is released, and then stops operating.

[0045] The evaluation control module 22 pulls the end indication signal (done) from low to high. The host computer 21 can continuously read the end indication signal. When the host computer 21 reads that the end indication signal is high, the host computer 21 can output a test end instruction to the evaluation control module 22.

[0046] In specific implementations, the evaluation control module 22 can obtain the operation result output by the DUT 23, and output the operation result to the host computer 21. Alternatively, the DUT 23 can directly output the operation result to the host computer 21.

[0047] In the embodiments of the present application, if the input test data in the DUT 23 is data without injected faults, the operation result output by the DUT 23 after operating for N cycles is the reference output result. In some embodiments, the reference output result can also be referred to as a golden output result.

[0048] If the input data in the DUT 23 is test data with injected faults, the operation result output by the DUT 23 after operating for N cycles is the fault output result.

[0049] The process of obtaining the reference output result is described below.

[0050] Referring to FIG. 2, a flowchart of obtaining the reference output result in the embodiments of the present application is given.

[0051] In step 201, the target number of cycles is configured.

[0052] In specific implementations, the target number of cycles is configured by the tester via the host computer 21. Specifically, the tester can send a configuration instruction to the evaluation control module 22 via the host computer 21 to configure the value of the count register in the evaluation control module 22.

[0053] Subsequently, the tester can send a test start instruction to the evaluation control module 22 via the host computer 21. The evaluation control module 22 enables the gated clock gated_dut_clk after receiving the test start instruction.

[0054] In step 202, the gated reset signal gated_dut_rst is enabled for a first time duration.

[0055] In specific implementation, the tester can configure the first time length through the host computer 21. The first time length can be represented by the number of running cycles of the evaluation control module 22. The evaluation control module 22 can enable the gated reset signal gated_dut_rst after the first time length.

[0056] In step 203, the gated reset signal gated_dut_rst is released after the second time length.

[0057] In specific implementation, the evaluation control module 22 releases the gated reset signal gated_dut_rst when the time length of enabling the gated reset signal gated_dut_rst reaches the second time length.

[0058] In step 204, the DUT circuit runs the test data for N cycles.

[0059] In specific implementation, the DUT circuit 23 runs the test data for N cycles after being reset.

[0060] In step 205, the evaluation control module controls the DUT circuit to stop working.

[0061] In specific implementation, the evaluation control module 22 can stop outputting the gated clock gated_dut_clk to the DUT circuit 23 after detecting that the DUT circuit 23 runs for N cycles. Alternatively, the evaluation control module 22 can stop enabling the gated clock gated_dut_clk. In this way, the evaluation control module 22 can control the DUT circuit 23 to stop working.

[0062] In step 206, the host computer sends a test end instruction to the evaluation control module to obtain the reference output result.

[0063] In specific implementation, after the gated reset signal gated_dut_rst is released, the DUT circuit 23 runs for N cycles for the test data and outputs the obtained operation result. The operation result output by the DUT circuit 23 is the reference output result. The host computer 21 can obtain the operation result output by the DUT circuit 23, that is, obtain the reference output result.

[0064] The fault injection evaluation method provided by the present application will be described in detail below. Referring to FIG. 3, a fault injection evaluation method in an embodiment of the present application is shown.

[0065] In step 301, the target cycle number is configured.

[0066] In the embodiment of the present application, before the fault injection evaluation is performed, the tester can send a configuration instruction to the evaluation control module 22 through the host computer 21 to configure the value of the count register in the evaluation control module 22.

[0067] In the embodiment of the present application, the target cycle number configured in step 301 can be equal to the target cycle number configured in step 201.

[0068] In step 302, a fault is injected into the circuit under test at the configured fault injection time.

[0069] In step 303, the fault output result of the circuit under test after the fault injection is obtained.

[0070] In the embodiment of the present application, the evaluation control module 22 can inject a fault into the circuit under test 23 through the fault injection module. The fault type can include single-bit error, multi-bit error, etc. The fault injection mode can include fixed-point injection, random injection, traversal injection, etc. The fault injection module can include an external fault injection module, an internal fault injection module, etc.

[0071] In the embodiment of the present application, according to the different injection time, the fault injection can include: initial time fault injection and running process fault injection.

[0072] In the specific implementation, for the initial time fault injection, it occurs before the host computer 21 sends the test start instruction to the evaluation control module 22. That is, before receiving the test start instruction, the evaluation control module 22 injects a fault into the test data through the fault injection module.

[0073] For the initial time fault injection, the following steps can be included:

[0074] Step 1.1), configure the target cycle number.

[0075] In the embodiment of the present application, the host computer 21 configures the value of the count register in the evaluation control module 22, that is, the target cycle number of the circuit under test 23 running after the gated_dut_rst reset signal is released. In this step, the target cycle number configured by the host computer 21 for the circuit under test 23 is equal to the target cycle number configured in step 201.

[0076] For example, when obtaining the reference output result, the configured target cycle number is 100. For the initial time fault injection, the configured target cycle number is also 100.

[0077] Step 1.2), inject a fault into the test data.

[0078] In the specific implementation, according to the address of a certain register in the code stream in the fault injection list file, the configuration data of a frame where the register is located is read back, the configuration data of the address is modified and written back to the code stream, thereby completing the fault injection operation of the register.

[0079] Step 1.3), the host computer sends a test start instruction.

[0080] The evaluation control module 22 receives the test start instruction sent by the host computer 21, and enables the gated clock gated_dut_clk.

[0081] Step 1.4), enable the gated reset signal gated_dut_rst for a first duration.

[0082] In a specific implementation, the first duration is configured by the host computer 21. The evaluation control module 22 can enable the gated reset signal gated_dut_rst after the first duration.

[0083] Step 1.5), release the gated reset signal gated_dut_rst for a second duration.

[0084] In a specific implementation, when the duration of the evaluation control module 22 enabling the gated reset signal gated_dut_rst reaches the second duration, the gated reset signal gated_dut_rst is released.

[0085] Step 1.6), the circuit under test runs the test data with injected faults, and the number of running cycles is N.

[0086] In a specific implementation, the circuit under test 23 runs the test data with injected faults for N cycles after being reset.

[0087] Step 1.7), the host computer sends a test end instruction, and the evaluation control module controls the circuit under test to stop working.

[0088] In a specific implementation, after the circuit under test 23 runs for N cycles, the evaluation control module 22 can stop outputting the gated clock gated_dut_clk to the circuit under test 23. Alternatively, the evaluation control module 22 can stop enabling the gated clock gated_dut_clk. In this way, the evaluation control module 22 can control the circuit under test 23 to stop working. The operation result output by the circuit under test 23 is the reference output result.

[0089] In a specific implementation, the fault injection during running can refer to: after the reset signal gated_dut_rst is released, the circuit under test 23 injects faults into the test data during running, and continues to run the test data with injected faults.

[0090] For fault injection during running, the following steps can be included:

[0091] Step 2.1), configure the number of cycles M.

[0092] In a specific implementation, the host computer 21 can configure the value of the count register in the evaluation control module 22 as M, where M < N.

[0093] Step 2.2), the host computer sends a test start instruction.

[0094] The evaluation control module 22 receives the test start instruction sent by the host computer 21 and enables the gated clock gated_dut_clk.

[0095] Step 2.3), enable the gated reset signal gated_dut_rst for a first duration.

[0096] In a specific implementation, the host computer 21 configures the first duration. The evaluation control module 22 can enable the gated reset signal gated_dut_rst after the first duration.

[0097] Step 2.4), release the gated reset signal gated_dut_rst for a second duration.

[0098] In a specific implementation, when the evaluation control module 22 enables the gated reset signal gated_dut_rst for a duration that reaches the second duration, the gated reset signal gated_dut_rst is released.

[0099] Step 2.5), the circuit under test runs the test data for M cycles.

[0100] In steps 2.1) to 2.5), the circuit under test 23 is controlled to run the test data that has not yet been injected with faults, and the circuit under test 23 runs the test data for M cycles.

[0101] In steps 2.1) to 2.4), the circuit under test 23 is in a non-working state. In step 2.5), the circuit under test 23 is working.

[0102] Step 2.6), control the fault injection module to inject faults into the test data.

[0103] Step 2.7), obtain N-M cycles.

[0104] In a specific implementation, the host computer 21 can configure the number of cycles that the circuit under test 23 needs to run after the faults are injected as N-M.

[0105] Step 2.8), the host computer sends a test start instruction.

[0106] The evaluation control module 22 receives the test start instruction sent by the host computer 21 and continues to enable the gated clock gated_dut_clk.

[0107] Step 2.9), the to-be-tested circuit runs the test data injected with the fault, and the running period is N.

[0108] In a specific implementation, after the to-be-tested circuit 23 is injected with the fault, the to-be-tested circuit 23 runs the test data injected with the fault for N-M periods.

[0109] Step 2.10), the host computer sends an end test instruction, and the evaluation control module controls the to-be-tested circuit to stop working.

[0110] Based on the steps 2.1) to 2.10) described above, the fault output result corresponding to the fault injection during the running can be obtained.

[0111] Step 304, compare the fault output result with the reference output result to obtain a fault evaluation result.

[0112] In the embodiment of the application, the fault output result can be obtained by the evaluation control module 22. The evaluation control module 22 compares the fault output result with the reference output result, and the comparison result is the fault evaluation result.

[0113] Alternatively, the host computer 21 can obtain the fault output result, and the host computer 21 compares the fault output result with the reference output result, and the comparison result is the fault evaluation result.

[0114] In the embodiment of the application, the fault evaluation result can include running normally and running error. The running normally described above means that the injected fault does not cause the running of the to-be-tested circuit 23 to be interrupted; and the running error described above means that the injected fault causes the running of the to-be-tested circuit 23 to be interrupted.

[0115] As can be seen from the above, the fault injection evaluation method provided in the above embodiment of the application can accurately control the running state of the to-be-tested circuit, and realizes fault injection and fault evaluation at any time.

[0116] In a specific implementation, each module / unit contained in each device / product described in the above embodiment can be a software module / unit, or a hardware module / unit, or part of a software module / unit and part of a hardware module / unit.

[0117] For example, for each device, product applied to or integrated into a chip, each module / unit contained therein can be implemented in the form of hardware such as a circuit, or at least part of the modules / units can be implemented in the form of a software program running on a processor integrated in the chip, and the remaining (if any) modules / units can be implemented in the form of hardware such as a circuit; for each device, product applied to or integrated into a chip module, each module / unit contained therein can be implemented in the form of hardware such as a circuit, and different modules / units can be located in the same component (for example, a chip, a circuit module, etc.) or different components of the chip module, or at least part of the modules / units can be implemented in the form of a software program running on a processor integrated in the chip module, and the remaining (if any) modules / units can be implemented in the form of hardware such as a circuit; for each device, product applied to or integrated into a terminal, each module / unit contained therein can be implemented in the form of hardware such as a circuit, and different modules / units can be located in the same component (for example, a chip, a circuit module, etc.) or different components of the terminal, or at least part of the modules / units can be implemented in the form of a software program running on a processor integrated in the terminal, and the remaining (if any) modules / units can be implemented in the form of hardware such as a circuit.

[0118] The embodiment of the present application further provides a computer readable storage medium, which is a nonvolatile storage medium or a non-transitory storage medium, and has a computer program stored thereon, and the computer program is run by a processor to perform the steps of the fault injection evaluation method provided in any of the above embodiments.

[0119] The embodiment of the present application further provides another fault injection evaluation device, which comprises a memory and a processor, and the memory has a computer program stored thereon, and the computer program is run by the processor to perform the steps of the fault injection evaluation method provided in any of the above embodiments.

[0120] The embodiment of the present application further provides a computer program product, which comprises computer programs / instructions, and the computer programs / instructions are run by a processor to perform the steps of the fault injection evaluation method provided in any of the above embodiments.

[0121] Those skilled in the art can understand that all or part of the steps of the above-mentioned embodiments can be completed by programs instructing related hardware, and the programs can be stored in a computer readable storage medium, and the storage medium can include ROM, RAM, magnetic or optical disk, etc.

[0122] Although the present application has been disclosed with reference to the above embodiments, the application is not limited to the above embodiments. It will be apparent to those skilled in the art that various modifications and changes can be made thereto without departing from the spirit and scope of the application. The scope of the application should be limited only by the appended claims.

Claims

1. A method of fault injection evaluation, the method comprising: The method comprises the following steps: configuring a target period number, the target period number being a period number of the to-be-tested circuit after being reset; injecting a fault into the to-be-tested circuit at a configured fault injection time; obtaining a fault output result output by the to-be-tested circuit after the fault is injected; comparing the fault output result with a reference output result to obtain a fault evaluation result.

2. The fault injection evaluation method of claim 1, wherein, The reference output result is obtained in the following manner: configuring the target period number for the to-be-tested circuit; outputting a gated reset signal to the to-be-tested circuit to control the to-be-tested circuit to be reset; obtaining an output result of the to-be-tested circuit as the reference output result, the output result of the to-be-tested circuit being an operation result obtained by the to-be-tested circuit after the to-be-tested circuit runs test data for a period number reaching the target period number after the gated reset signal is released.

3. The method of fault injection evaluation of claim 1, wherein, The configured fault injection time is an initial time before the to-be-tested circuit is released from the gated reset signal. The obtaining of the fault output result output by the to-be-tested circuit after the fault is injected comprises the following steps: configuring the target period number for the to-be-tested circuit; outputting a gated reset signal to the to-be-tested circuit to control the to-be-tested circuit to be reset; obtaining the fault output result output by the to-be-tested circuit, the fault output result being an operation result obtained by the to-be-tested circuit after the to-be-tested circuit runs the test data with the injected fault for a period number reaching the target period number after the gated reset signal is released.

4. The method of fault injection evaluation of claim 3, wherein, The method further comprises the following steps: when the target period number is configured for the to-be-tested circuit, disconnecting a gated clock of the to-be-tested circuit; and after the configuration of the target period number is completed, resuming the gated clock of the to-be-tested circuit.

5. The method of fault injection evaluation of claim 1, wherein, The configured fault injection time is a time after the to-be-tested circuit runs for M periods after being released from the gated reset signal. The obtaining of the fault output result output by the to-be-tested circuit after the fault is injected comprises the following steps: configuring a remaining period number for the to-be-tested circuit, the remaining period number being N-M; 6. The method of fault injection evaluation of claim 5, wherein, obtaining the fault output result output by the to-be-tested circuit, the fault output result being an output result obtained by the to-be-tested circuit after the to-be-tested circuit runs the test data with the injected fault for a period number reaching N-M, N being the target period number. The method further comprises the following steps: when the remaining period number is configured for the to-be-tested circuit, disconnecting a gated clock of the to-be-tested circuit; and 7. The method of fault injection evaluation according to any of claims 3 to 6, characterized in that, after the configuration of the remaining period number for the to-be-tested circuit is completed, resuming the gated clock of the to-be-tested circuit. The injecting of the fault into the to-be-tested circuit comprises the following steps:

8. A fault injection evaluation system, characterized by, injecting a fault into the to-be-tested circuit through a fault injection module, the fault including any one of the following: single-bit error, multi-bit error. The method comprises the following steps: a host computer, an evaluation control module, and a to-be-tested circuit, wherein: the evaluation control module is adapted to configure a target period number, the target period number being a period number of the to-be-tested circuit after being reset; inject a fault into the to-be-tested circuit at a configured fault injection time; and obtain a fault output result output by the to-be-tested circuit after the fault is injected; 9. A computer-readable storage medium, which is a non-volatile storage medium or a non-transitory storage medium, on which a computer program is stored, characterized by the host computer is adapted to compare the fault output result with a reference output result to obtain a fault evaluation result. The computer program is run by a processor to perform the steps of the fault injection evaluation method in any one of claims 1 to 7.

10. A computer program product comprising computer programs / instructions, characterized in that, The computer program / instructions, when executed by the processor, implement the steps of the fault injection evaluation method of any one of claims 1-7.

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