Addition module and operation method thereof, multiplier and operation method thereof, processor and equipment

Abstract

The embodiment of the invention provides an addition module and an operation method thereof, a multiplier and an operation method thereof, a processor and equipment, the addition module comprises an adder, a register and a control unit, the adder is configured to execute an addition operation of a first calculation precision to obtain a first operation result; the register is coupled with the adder and is configured to receive a first operation result obtained by the adder; the control unit is respectively coupled with the register and the summator, and is configured to control the register and the summator to carry out reconstruction operation so as to obtain a first multiplication module supporting second calculation precision. The number proportion of the addition modules and the multiplication modules in the multiplier can be dynamically adjusted by performing reconstruction operation on the addition modules, and the calculation precision of the multiplier-adder can be adjusted.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an addition module and an operation method thereof, a multiplier and an operation method thereof, a processor and a device. Background Art

[0002] With the development of artificial intelligence, in order to meet its ever-increasing computing power requirements, more and more computing structures targeting the characteristics of machine learning calculations have been proposed. In the calculation process of machine learning, vector multiplication and matrix multiplication account for the majority of the calculations, so how to improve the computing power and efficiency of these two types of operations is the focus of research. The basic operators of vector multiplication and matrix multiplication are multiplication and addition, so efficient multipliers and adders can greatly improve the efficiency of these two types of operations. Summary of the invention

[0003] At least one embodiment of the present disclosure provides an addition module, comprising: an adder, configured to perform an addition operation of a first calculation precision to obtain a first operation result; a register, coupled to the adder, and configured to receive the first operation result obtained by the adder; a control unit, coupled to the register and the adder, respectively, and configured to control the register and the adder to perform a reconstruction operation to obtain a first multiplication module supporting a second calculation precision; wherein the adder comprises a plurality of full adders, each of which comprises a first input terminal, a second input terminal, a carry input terminal, a sum output terminal, and a carry output terminal, and the plurality of full adders are connected in a first manner. The first stage is coupled in a cascade manner, the carry output terminal of the previous stage full adder is coupled to the carry input terminal of the next stage full adder, the first input terminals of the multiple full adders are configured to receive the first addend, the second input terminals of the multiple full adders are configured to receive the second addend, the sum output terminals of the multiple full adders are configured to output sum data, the carry output terminal of the previous stage full adder is configured to output carry data as input data of the carry input terminal of the next stage full adder, the carry output terminal of the last stage full adder of the multiple full adders is configured to output final carry data, and the first operation result includes multiple sum data and the final carry data.

[0004] At least one embodiment of the present disclosure also provides an operation method of the addition module according to the above-mentioned embodiment, comprising: performing a split operation or a merge operation on the adder and the register of the addition module respectively to obtain at least one first adder and at least one first register, wherein the first adder supports the second calculation precision; and reconstructing the connection mode of the at least one first adder and the at least one first register to obtain the first multiplication module.

[0005] For example, in the operation method of the adding module provided in at least one embodiment of the present disclosure, the adder and the register of the adding module are respectively split or merged to obtain at least one first adder and at least one first register, including: in response to the first calculation accuracy being higher than the second calculation accuracy, the multiple full adders in the adder of the adding module are split into at least two groups, each group of full adders is coupled in the first cascade manner to obtain the first adder, and the register of the adding module is split into at least two first registers; in response to the first calculation accuracy being lower than the second calculation accuracy, the adders of at least two adding modules are merged into the first adder, and the registers of the at least two adding modules are merged into the first register; in response to the first calculation accuracy being equal to the second calculation accuracy, the adder and the register of the adding module are used as the first adder and the first register, respectively.

[0006] For example, in the operation method of the adding module provided in at least one embodiment of the present disclosure, the at least two adding modules include a first adding module and a second adding module, and the method of merging the adders of the at least two adding modules into the first adder includes: coupling the carry output terminal of the last-stage full adder in the adder of the first adding module with the carry input terminal of the first-stage full adder in the adder of the second adding module to obtain the first adder.

[0007] For example, in the operation method of the addition module provided in at least one embodiment of the present disclosure, the second calculation precision is an N-bit integer, the first multiplication module includes N first adders and N first registers, each first adder includes N full adders coupled in the first cascade manner, N=2n, n is a positive integer, and the reconstructing the connection mode of the at least one first adder and the at least one first register to obtain the first multiplication module includes: coupling the N first adders to the N first registers respectively, so that the first register receives the second operation result obtained by the corresponding coupled first adder performing the addition operation of the second calculation precision; coupling the N first adders in a second cascade manner, wherein the sum output terminals of the 2nd to Nth full adders in the first adder of the previous stage are respectively coupled to the first input terminals of the 1st to (N-1)th full adders in the first adder of the next stage, and the carry output terminal of the Nth full adder in the first adder of the previous stage is coupled to the first input terminal of the Nth full adder in the first adder of the next stage.

[0008] For example, in the operation method of the addition module provided in at least one embodiment of the present disclosure, the first multiplication module performs a multiplication operation of the second calculation precision on the first multiplier and the second multiplier, and the first multiplier and the second multiplier respectively include N-bit data, and the operation method also includes: according to the 1st bit data of the second multiplier, using the shifted first multiplier or the shifted preset addend as the first addend of the first adder of the first level; according to the i-th bit data of the second multiplier, using the first multiplier or the preset addend as the second addend of the (i-1)th level first adder, where i=2,3,...,N.

[0009] For example, in the operation method of the addition module provided in at least one embodiment of the present disclosure, the method of using the shifted first multiplier or the shifted preset addend as the first addend of the first adder of the first stage according to the first bit data of the second multiplier includes: in response to the first bit data of the second multiplier being 1, using the shifted first multiplier as the first addend of the first adder of the first stage, and in response to the first bit data of the second multiplier being 0, using the shifted preset addend as the first addend of the first adder of the first stage.

[0010] For example, in the operating method of the addition module provided in at least one embodiment of the present disclosure, the method of using the first multiplier or the preset addend as the second addend of the first adder of the (i-1)th stage according to the i-th bit data of the second multiplier includes: in response to the i-th bit data of the second multiplier being 1, using the first multiplier as the second addend of the first adder of the (i-1)th stage; in response to the i-th bit data of the second multiplier being 0, using the preset addend as the second addend of the first adder of the (i-1)th stage.

[0011] At least one embodiment of the present disclosure also provides a multiplier-adder, comprising: multiple second multiplication modules, multiple first addition modules and multiple second addition modules, wherein the second addition module is the addition module according to claim 1, the first addition module comprises multiple full adders coupled in the first cascade manner, the second multiplication module is configured to perform multiplication operations of a third calculation precision, and the first addition module and the second addition module are configured to receive multiplication operation results output by the corresponding coupled second multiplication modules and perform addition operations of the first calculation precision.

[0012] At least one embodiment of the present disclosure also provides an operation method of the multiplier-adder according to the above-mentioned embodiment, comprising: reconstructing at least part of the second addition modules into the second multiplication modules and / or the first addition modules to adjust the ratio of the number of the second multiplication modules, the first addition modules and the second addition modules in the multiplier-adder; or in response to the multiplier-adder switching from the third calculation precision to the second calculation precision, reconstructing the multiple second multiplication modules into at least one first multiplication module, reconstructing the multiple first addition modules into at least one third addition module, and reconstructing at least part of the second addition modules into the at least one first multiplication module, wherein the third addition module supports a fourth calculation precision.

[0013] For example, in the operation method of the multiplier and adder provided in at least one embodiment of the present disclosure, the third calculation precision is int4, the first calculation precision and the second calculation precision are int8, and the fourth calculation precision is int16; the second multiplication module includes 4 second adders supporting the third calculation precision and 4 second registers, the bit width of the second register is 8 bits, and the second adder includes 4 full adders coupled in the first cascade manner; the first addition module includes 8 full adders coupled in the first cascade manner; the second addition module includes a third adder and a third register, the third adder includes the 8 full adders coupled in the first cascade manner, the bit width of the third register is 16 bits, and the third register is coupled to the third adder to receive the operation result obtained by the corresponding third adder performing the addition operation of the first calculation precision.

[0014] For example, in the operation method of the multiplier-adder provided in at least one embodiment of the present disclosure, the reconstructing the multiple second multiplication modules into at least one first multiplication module includes: merging the second adders and the second registers in every 4 second multiplication modules into 8 first adders and 8 first registers respectively, for reconstructing the first multiplication module, wherein the first adder supports the second calculation precision and the bit width of the first register is 16 bits; coupling the 8 first adders to the 8 first registers respectively, so that each first register receives the operation result obtained by the corresponding coupled first adder performing the addition operation of the second calculation precision; coupling the 8 first adders in a second cascade manner, wherein the sum output terminals of the 2nd to 8th full adders in the first adder of the previous stage are respectively coupled to the first input terminals of the 1st to 7th full adders in the first adder of the next stage, and the carry output terminal of the 8th full adder in the first adder of the previous stage is coupled to the first input terminal of the 8th full adder in the first adder of the next stage.

[0015] For example, in the operating method of the multiplier-adder provided in at least one embodiment of the present disclosure, the reconstructing the multiple first addition modules into at least one third addition module includes: merging every 2 first addition modules into the third addition module, wherein the third addition module includes the 8 full adders coupled in the first cascade manner.

[0016] For example, in the operating method of the multiplier-adder provided in at least one embodiment of the present disclosure, the reconstructing the at least part of the second addition modules into the at least one first multiplication module includes: coupling the third adders of every 8 second addition modules in the multiple second addition modules in the second cascade manner, wherein the sum output terminals of the 2nd to 8th full adders in the third adder of the previous stage are respectively coupled to the first input terminals of the 1st to 7th full adders in the first adder of the next stage, and the carry output terminal of the 8th full adder in the first adder of the previous stage is coupled to the first input terminal of the 8th full adder in the first adder of the next stage.

[0017] At least one embodiment of the present disclosure further provides a processor, which includes the multiplier-adder described in any of the above embodiments.

[0018] At least one embodiment of the present disclosure further provides an electronic device, which includes the processor described in any of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0020] Figure 1 A schematic diagram of the structure of a multiplier-adder is shown;

[0021] Figure 2 A schematic diagram of a convolution operation is shown;

[0022] Figure 3A A schematic diagram of the structure of an addition module provided by at least one embodiment of the present disclosure is shown;

[0023] Figure 3B Shows Figure 3A Schematic diagram of the connection between the adder and the register;

[0024] Figure 4 A schematic diagram showing an operation method of an addition module provided by at least one embodiment of the present disclosure;

[0025] Figure 5A A schematic diagram of the structure of a first multiplication module provided by at least one embodiment of the present disclosure is shown;

[0026] Figure 5B A schematic diagram showing a first adder provided by at least one embodiment of the present disclosure coupled in a second cascade manner;

[0027] Figure 6 A schematic diagram showing a multiplication operation performed on two binary data in at least one embodiment of the present disclosure is shown;

[0028] Figure 7 A schematic diagram showing setting parameters for multiplication operation in a first multiplication module is shown;

[0029] Figure 8 A schematic diagram of the structure of a multiplier-adder provided by at least one embodiment of the present disclosure is shown;

[0030] Fig. 9 A schematic structural diagram of an electronic device provided by at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0032] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0033] With the rapid development of machine learning technology, efficient data processing and computing power have become key factors in improving model performance. In hardware design, multipliers and adders are the core components for performing machine learning operations. Considering the characteristics of machine learning operations and the limitations of hardware design, multipliers and adders are generally combined into multipliers and adders in a fixed ratio.

[0034] For example, Figure 1 A schematic diagram of the structure of a multiplier-adder is shown. The multipliers and adders in the multiplier-adder are combined in a 1:1 ratio, and the multiplier-adder includes 16 multipliers and 16 adders. The calculation accuracy of the multiplier can be FP16, INT16, INT8, INT4, etc., and the calculation accuracy of the adder can be FP16, INT16, INT8, INT4, etc.

[0035] However, different machine learning algorithms and different calculation precisions have different resource requirements for multipliers and adders. For example, some algorithms may need to perform more multiplication operations, some algorithms may rely more on addition operations, and other algorithms may require higher calculation precision. Therefore, multipliers and adders designed with a fixed ratio have limitations. Since the ratio of multipliers to adders in the multiplier-adder is designed to be a fixed value, the utilization rate of the hardware resources in the multiplier-adder is low in some scenarios, so the maximum computing power of the hardware design cannot be exerted.

[0036] For example, taking the convolutional neural network (CNN) algorithm as an example, the CNN algorithm involves convolution operations, pooling operations, activation function operations, etc., among which the computing power required for convolution operations accounts for the vast majority of the computing power required for the CNN algorithm. Therefore, when designing CNN hardware acceleration, the focus is on the acceleration of convolution operations.

[0037] For example, Figure 2 A schematic diagram of a convolution operation is shown. Figure 2As shown, the convolution kernel is point-multiplied with the original feature map to realize the convolution operation. The size of the convolution kernel is 2×2 (4 elements in total). The convolution kernel is point-multiplied with the 2×2 feature data on the original feature map one by one. Each point multiplication generates a data. When the convolution kernel is point-multiplied with all 2×2 data sets on the original feature map, the generated data set constitutes a new feature map. For example, in a point multiplication operation, A0×k0+A1×k2+A8×k1+A9×k3=P9 is executed, and each point multiplication operation requires 4 2-input multiplications and 3 2-input additions. When a multiplier-adder can handle 4 multiplication operations and 3 addition operations at the same time (that is, the ratio of the number of multipliers to adders is 4:3), the multiplier-adder can achieve the highest computational efficiency when performing the convolution operation. However, as the algorithm changes (for example, the size of the convolution kernel changes), the number of multipliers and adders required to execute the algorithm will also change. At this time, the original multipliers and adders cannot achieve the highest computing efficiency, and some multipliers or adders will be idle.

[0038] One or more embodiments of the present disclosure provide an addition module and an operation method thereof, and a multiplier and an operation method thereof.

[0039] The addition module includes an adder, a register and a control unit, the adder is configured to perform an addition operation of a first calculation precision to obtain a first operation result; the register is coupled to the adder and is configured to receive the first operation result obtained by the adder; the control unit is coupled to the register and the adder respectively, and is configured to control the register and the adder to perform a reconstruction operation to obtain a first multiplication module supporting a second calculation precision. The addition module provided in the embodiment of the present disclosure can be used to reconstruct multiplication modules of different calculation precisions, so that the ratio of multiplication modules to addition modules in the multiplier can be dynamically adjusted, thereby adapting to the requirements of different machine learning algorithms for calculation precision and hardware resources, and improving the hardware resource utilization, calculation efficiency and flexibility of the multiplier.

[0040] The present disclosure is described below through several specific embodiments and in conjunction with the accompanying drawings. In order to keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components may be omitted. When any component of the embodiments of the present disclosure appears in more than one accompanying drawing, the component is represented by the same or similar reference numeral in each of the accompanying drawings.

[0041] Figure 3A A schematic diagram of the structure of an addition module provided by at least one embodiment of the present disclosure is shown.

[0042] like Figure 3AAs shown, the addition module 300 includes an adder 310, a register 320 and a control unit 330. The adder 310 is configured to perform an addition operation of a first calculation precision to obtain a first operation result. The register 320 is coupled to the adder 310 and is configured to receive the first operation result obtained by the adder 310. The control unit 330 is coupled to the adder 310 and the register 320 respectively, and is configured to control the adder 310 and the register 320 to perform a reconstruction operation to obtain a first multiplication module supporting a second calculation precision.

[0043] For example, the adder includes a plurality of full adders, each of which includes a first input terminal, a second input terminal, a carry input terminal, a sum output terminal and a carry output terminal. The plurality of full adders are coupled in a first cascade manner, specifically, the carry output terminal of the previous full adder is coupled to the carry input terminal of the next full adder. The first input terminal of the plurality of full adders is configured to receive a first addend, the second input terminal of the plurality of full adders is configured to receive a second addend, the sum output terminal of the plurality of full adders is configured to output sum data, the carry output terminal of the previous full adder is configured to output carry data as input data of the carry input terminal of the next full adder, and the carry output terminal of the last full adder in the plurality of full adders is configured to output final carry data. The first operation result includes a plurality of sum data and final carry data.

[0044] It should be noted that the calculation accuracy of the adder is related to the number of full adders coupled in the first cascade mode. For example, if the calculation accuracy of the adder is int4, the adder includes 4 full adders coupled in the first cascade mode. In addition, the full adder in the embodiment of the present disclosure is a 1-bit full adder by default, but other types of full adders, such as a 2-bit full adder, may also be used, and the present disclosure does not limit this.

[0045] For example, Figure 3B Shows Figure 3A Schematic diagram of the connection between the adder and the register.

[0046] like Figure 3B As shown, the calculation accuracy of the adder 310 (i.e., the first calculation accuracy) is int8, and the adder 310 includes 8 full adders 3100~3107 coupled in a first cascade manner. For example, the carry output terminal Cout0 of the first-stage full adder 3100 is coupled to the carry input terminal Cin1 of the second-stage full adder 3101, and the carry output terminal Cout1 of the second-stage full adder 3101 is coupled to the carry input terminal Cin2 of the third-stage full adder 3102.

[0047] For example, the full adders 3100-3107 are configured to perform an addition operation of a first calculation precision on a first addend A and a second addend B. The first addend A and the second addend B respectively include 8-bit data, for example, A = [a7, a6, a5, a4, a3, a2, a1, a0], B = [b7, b6, b5, b4, b3, b2, b1, b0]. For example, the carry data received by the carry input terminal Cin0 of the first-stage full adder 3100 can be set to 0.

[0048] like Figure 3B As shown, the first input terminals A0 to A7 of the full adders 3100 to 3107 are configured to receive the first addend A. For example, the first input terminal A0 of the full adder 3100 is configured to receive the first bit data a0 of the first addend A, the first input terminal A1 of the full adder 3101 is configured to receive the second bit data a1 of the first addend A, and so on.

[0049] like Figure 3B As shown, the second input terminals B0 to B7 of the full adders 3100 to 3107 are configured to receive the second addend B. For example, the second input terminal B0 of the full adder 3100 is configured to receive the first bit data b0 of the first addend B, the second input terminal B1 of the full adder 3101 is configured to receive the second bit data b1 of the first addend B, and so on.

[0050] like Figure 3B As shown, the sum output terminals S0 to S7 of the full adders 3100 to 3107 are configured to output sum data (e.g., Sum0 to Sum7). The carry output terminal of the previous full adder is configured to output carry data as input data of the carry input terminal of the next full adder. For example, the carry output terminal Cout0 of the first full adder 3100 outputs carry data (e.g., C0) as input data of the carry input terminal Cin1 of the second full adder 3101. The carry output terminal Cout7 of the last full adder 3107 is configured to output the final carry data (e.g., C7).

[0051] After the eight full adders 3100 to 3107 have all completed the addition operation with the first calculation accuracy, the eight sum data (e.g., Sum0 to Sum7) and the final carry data (e.g., C7) are stored in the register 320 as the first operation result, and then the first operation result is output through the register 320. Alternatively, after the eight full adders 3100 to 3107 have all completed the addition operation with the first calculation accuracy, the first operation result is directly output.

[0052] At least one embodiment of the present disclosure further provides an operation method of an addition module, wherein the addition module is the addition module provided by any of the above embodiments. Figure 4As shown, the operation method includes steps S401 and S402.

[0053] Step S401: performing a split operation or a merge operation on the adder and the register of the adding module respectively to obtain at least one first adder and at least one first register, wherein the first adder supports a second calculation precision.

[0054] Step S402: reconstructing the connection mode of at least one first adder and at least one first register to obtain a first multiplication module.

[0055] For example, after adjusting the calculation accuracy of the adder and the bit width of the register in the addition module (i.e., after obtaining the first adder and the first register), it is necessary to reconstruct (i.e., adjust or modify) the connection method of the first adder and the first register to obtain the first multiplication module.

[0056] For example, the above-mentioned step S401 may include: in response to the first calculation accuracy being higher than the second calculation accuracy, splitting multiple full adders in the adder of the addition module into at least two groups, coupling each group of full adders in a first cascade manner to obtain a first adder, and splitting the register of the addition module into at least two first registers.

[0057] For example, when the first calculation precision is int8 and the second calculation precision is int4, the bit width of the register of the addition module is 16 bits, and the adder of the addition module includes 8 adders in a first cascade manner (for example, see Figure 3B ) coupled full adders (referred to as "FullAdder_0 to FullAdder_7"), two first adders and two first registers can be obtained by splitting operation. The first adder includes four full adders coupled in a first cascade manner, and the bit width of the first register is 8 bits.

[0058] For example, the eight full adders FullAdder_0 to FullAdder_7 in the adder are divided into two groups, the first group includes full adders FullAdder_0 to FullAdder_3, and the second group includes full adders FullAdder_4 to FullAdder_7. Then, the connection between the carry output terminal of the fourth-stage full adder FullAdder_3 and the carry input terminal of the fifth-stage full adder FullAdder_4 can be disconnected, thereby obtaining two first adders. For example, the register in this example can be composed of 16 cascaded D flip-flops. When the register is split into two first registers, the first eight D flip-flops in the register can be cascaded to obtain a first register, and the last eight D flip-flops in the register can be cascaded to obtain another first register. Each first register is coupled to a first adder to receive and store the operation result obtained when the corresponding coupled first adder performs an addition operation of the second calculation precision.

[0059] For example, when the first calculation precision is int16 and the second calculation precision is int4, the bit width of the register of the addition module is 32 bits, and the adder of the addition module includes 16 adders in a first cascade manner (for example, see Figure 3B ) coupled full adder, at this time, the adder can be split into 4 first adders, and the register of the adding module can be split into four first registers. The specific splitting method can refer to the above example and will not be repeated here.

[0060] For example, the above step S401 may further include: in response to the first calculation accuracy being lower than the second calculation accuracy, merging adders of at least two adding modules into a first adder, and merging registers of at least two adding modules into a first register.

[0061] For example, at least two adding modules include a first adding module and a second adding module, and the step of merging the adders of the at least two adding modules into a first adder includes: coupling the carry output end of the last-stage full adder in the adder of the first adding module with the carry input end of the first-stage full adder in the adder of the second adding module to obtain the first adder.

[0062] For example, when the first calculation precision is int4 and the second calculation precision is int8, the bit width of the register of the addition module is 8 bits, and the adder of the addition module includes 4 full adders coupled in a first cascade manner (represented as "FullAdder_0~FullAdder_3" here). The first adder obtained by the merging operation needs to include 8 full adders coupled in a first cascade manner. The bit width of the first register is 16 bits. Therefore, it is necessary to perform merging operations on the adders and registers in the two addition modules respectively. For example, the carry output terminal of the last-stage full adder FullAdder_3 in the adder of the first addition module is coupled to the carry input terminal of the first-stage full adder FullAdder_0 in the adder of the second addition module. For example, the registers in the two addition modules can respectively include 8 D flip-flops, and a first register with a bit width of 16 bits can be obtained by cascading 16 D flip-flops.

[0063] For example, the above step S401 may also include: in response to the first calculation precision being equal to the second calculation precision, the adder and the register of the addition module are used as the first adder and the first register respectively. Since the first calculation precision is equal to the second calculation precision, there is no need to perform a split operation or a merge operation to adjust the calculation precision of the adder and the bit width of the register, and the adder and the register of the addition module can be directly used to reconstruct the first multiplication module supporting the second calculation precision.

[0064] For example, Figure 5A A schematic structural diagram of a first multiplication module provided by at least one embodiment of the present disclosure is shown.

[0065] like Figure 5A As shown, when the second calculation precision is an N-bit integer (intN), where N=2n, n is a positive integer, the first multiplication module 500 includes N first adders 510~5N0 and N first registers Reg1~RegN, and each first adder includes N full adders coupled in a first cascade manner.

[0066] For example, the first multiplication module may further include a control unit configured to control the first adders 510 ˜ 5N0 and the first registers Reg1 ˜RegN to jointly implement the multiplication operation of the second calculation precision performed by the first multiplication module.

[0067] For example, when executing the above step S402, the N first adders 510-5N0 are respectively coupled to the N first registers Reg1-RegN, so that the first register receives the second operation result obtained by the correspondingly coupled first adder performing the addition operation with the second calculation precision; the N first adders 510-5N0 are coupled in a second cascade manner, wherein the sum output terminals of the 2nd to Nth full adders in the first adder of the previous stage are respectively coupled to the first input terminals of the 1st to (N-1)th full adders in the first adder of the next stage, and the carry output terminal of the Nth full adder in the first adder of the previous stage is coupled to the first input terminal of the Nth full adder in the first adder of the next stage. It should be noted that in addition to the above second cascade manner, the first adders 510-5N0 can also be coupled in other cascade manners, and the present disclosure does not limit this.

[0068] Figure 5B Shows Figure 5A Schematic diagram of the first adder coupled in a second cascade manner.

[0069] For example, when N=4, Figure 5A The calculation precision supported by the first multiplication module 500 is int4. The first multiplication module 500 includes four first adders 510-540 and four first registers Reg1-Reg4 ( Figure 5B (not shown), each first adder includes four full adders coupled in a first cascade manner.

[0070] For example, Figure 5B As shown, the first adder 510 includes full adders 5100-5103, and the carry input terminals and carry output terminals of the full adders 5100-5103 are coupled in a first cascade manner. For details, please refer to the above description of Figure 3BThe description is not repeated here. The four first adders 510-540 are respectively coupled to the four first registers Reg1-Reg4, so that each first register receives the second operation result obtained by the correspondingly coupled first adder performing the addition operation of the second calculation accuracy. For example, the first register Reg1 is coupled to the first adder 510 to receive the sum data (for example, Sum1_0-Sum1_3) output by the sum output terminals S0-S3 of the full adders 5100-5103 in the first adder 510, and the carry data (for example, C1_3) output by the carry output terminal Cout3 of the full adder 5103, that is, the second operation result obtained by the first adder 510 is [C1_3, Sum1_3, Sum1_2, Sum1_1, Sum1_0]. By analogy, the first register Reg2 is coupled to the first adder 520 to receive the sum data (e.g., Sum2_0-Sum2_3) output by the sum output terminals S0-S3 of the full adders 5200-5203 in the first adder 520, and the carry data (e.g., C2_3) output by the carry output terminal Cout3 of the full adder 5203. The second operation result obtained by the first adder 520 is [C2_3, Sum2_3, Sum2_2, Sum2_1, Sum2_0].

[0071] In order to reconstruct the first multiplication module 500 with a calculation accuracy of int4, it is also necessary to couple the four first adders 510-540 in a second cascade manner. Figure 5BAs shown, the sum output terminals S1~S3 of the 2nd to 4th full adders 5101~5103 in the first-stage first adder 510 are respectively coupled to the first input terminals A0~A2 of the 1st to 3rd full adders 5200~5202 in the second-stage first adder 520, and the carry output terminal Cout3 of the 4th full adder 5103 in the first-stage first adder 510 is coupled to the first input terminal A3 of the 4th full adder 5203 in the second-stage first adder 520. The sum output terminals S1~S3 of the 2nd to 4th full adders 5201~5203 in the second-stage first adder 520 are respectively coupled to the first input terminals A0~A2 of the 1st to 3rd full adders 5300~5302 in the third-stage first adder 530, and the carry output terminal Cout3 of the 4th full adder 5203 in the second-stage first adder 520 is coupled to the first input terminal A3 of the 4th full adder 5303 in the third-stage first adder 530. The sum output terminals S1~S3 of the 2nd to 4th full adders 5301~5303 in the first adder 530 of the third stage are respectively coupled to the first input terminals A0~A2 of the 1st to 3rd full adders 5400~5402 in the first adder 540 of the fourth stage, and the carry output terminal Cout3 of the 4th full adder 5303 in the first adder 530 of the third stage is coupled to the first input terminal A3 of the 4th full adder 5403 in the first adder 540 of the fourth stage.

[0072] The principle of the first multiplication module performing multiplication operation on two binary data is: shift the multiplicand (hereinafter also referred to as the "first multiplier") successively, and then determine whether to accumulate the shifted multiplicand according to the value of each bit data of the multiplier (hereinafter also referred to as the "second multiplier"), so as to obtain the product of the two binary data.

[0073] For example, Figure 6 A schematic diagram of performing a multiplication operation on two binary data in at least one embodiment of the present disclosure is shown.

[0074] like Figure 6As shown, the first multiplier is 1011, the second multiplier is 1101, the calculation accuracy is int4, and the multiplication operation can be converted into 3 addition operations. Specifically, starting from the lowest bit of the second multiplier 1101, each bit of the second multiplier 1101 is multiplied by the first multiplier 1011 to obtain 4 multiplication results, of which [a3, a2, a1, a0] = [1, 0, 1, 1], [b3, b2, b1, b0] = [0, 0, 0, 0], [c3, c2, c1, c0] = [1, 0, 1, 1], [d3, d2, d1, d0] = [1, 0, 1, 1]. Then, the result of each multiplication is shifted left by one bit, and finally all the multiplication results are added to obtain the multiplication result [1, 0, 0, 0, 1, 1, 1, 1]. Since the multiplication operation is performed on two binary data, the second multiplier is composed of 0 and 1, and the result of multiplying each bit data of the second multiplier by the first multiplier is the first multiplier or 0, that is, the four addends participating in the addition operation can be determined according to the value of each bit data of the second multiplier.

[0075] It should be noted that in the above example, the multiplication operation with calculation precision of int4 is converted into 3 addition operations with calculation precision of int4, that is, Figure 5A The first multiplication module 500 shown actually uses three first adders (eg, adders 510-530) and three first registers Reg1-Reg3 when performing multiplication operations on the first multiplier 1011 and the second multiplier 1101. The remaining first adder 540 and first register Reg4 are temporarily idle.

[0076] For example, Figure 7 A schematic diagram of setting parameters for multiplication operation in the first multiplication module is shown.

[0077] For example, when the first multiplication module performs a multiplication operation of the second calculation precision (i.e., int4) on the first multiplier (e.g., 1011) and the second multiplier (e.g., 1101), the operation method of the addition module provided by at least one embodiment of the present disclosure further includes: according to the first bit data of the second multiplier, using the shifted first multiplier or the shifted preset addend as the first addend of the first adder of the first stage; according to the i-th bit data of the second multiplier, using the first multiplier or the preset addend as the second addend of the (i-1)th stage first adder, where i = 2, 3, 4. The preset addend here is 4-bit binary data, which can be set to 0000.

[0078] For example, when the first multiplication module performs a multiplication operation of the second calculation precision (i.e., int4) on the first multiplier (e.g., 1011) and the second multiplier (e.g., 1101), the carry data received by the carry input terminal Cin0 of the first full adder 5100~5300 in the first adder 510~530 can be set to 0, or can be set to other values ​​according to the requirements of the machine learning algorithm, and the present disclosure does not impose any restrictions on this.

[0079] like Figure 7 As shown, in response to the first bit data of the second multiplier being 1, the shifted first multiplier is used as the first addend [a3, a2, a1, a0] of the first adder 510 of the first stage, where the "shift operation" refers to arithmetic right shifting of the first multiplier 1011 by 1 bit, and the shifted first multiplier is 0101, at which time the first addend [a3, a2, a1, a0] of the first adder 510 of the first stage is [0, 1, 0, 1]. In response to the second bit data of the second multiplier being 0, the preset addend 0000 is used as the second addend [b3, b2, b1, b0] of the first adder 510 of the first stage, that is, [b3, b2, b1, b0] = [0, 0, 0, 0]. Afterwards, the first adder 510 of the first stage performs an addition operation on the first addend [a3, a2, a1, a0] and the second addend [b3, b2, b1, b0], and the first register Reg1 coupled to the first adder 510 of the first stage receives and stores the result of the addition operation and the lowest bit data of the first multiplier before shifting (i.e., the rightmost "1" in "1011"), that is, the data stored in the first register Reg1 is [C1_3, Sum1_3, Sum1_2, Sum1_1, Sum1_0, 1].

[0080] like Figure 7As shown, in response to the third bit data of the second multiplier being 1, the first multiplier 1011 is used as the second addend [c3, c2, c1, c0] of the second-stage first adder 520, that is, [c3, c2, c1, c0] = [1, 0, 1, 1], and the second-stage first adder 520 performs an addition operation on the second addend [c3, c2, c1, c0] and the data received from the first-stage first adder 510 (that is, [C1_3, Sum1_3, Sum1_2, Sum1_1]), and stores the obtained operation result [C2_3, Sum2_3, Sum2_2, Sum2_1, Sum2_0] in the first register Reg2 coupled to the second-stage first adder 520. Moreover, the first register Reg2 can also store the lowest bit data of the first multiplier before shifting (i.e., the rightmost "1" in "1011") and the sum data Sum1_0 output by the sum output terminal S1 of the full adder 5100. At this time, the data stored in the first register Reg2 is [C2_3, Sum2_3, Sum2_2, Sum2_1, Sum2_0, Sum1_0, 1].

[0081] like Figure 7 As shown, in response to the 4th bit data of the second multiplier being 1, the first multiplier 1011 is used as the second addend [d3, d2, d1, d0] of the third-level first adder 530, that is, [d3, d2, d1, d0] = [1, 0, 1, 1], and the third-level first adder 530 performs an addition operation on the second addend [d3, d2, d1, d0] and the data received from the second-level first adder 520 (that is, [C2_3, Sum2_3, Sum2_2, Sum2_1]), and stores the obtained operation result [C3_3, Sum3_3, Sum3_2, Sum3_1, Sum3_0] in the first register Reg3 coupled to the third-level first adder 530. Moreover, the first register Reg3 can also store the lowest bit data of the first multiplier before shifting (i.e., the rightmost "1" in "1011"), the sum data Sum1_0 output by the sum output terminal S1 of the full adder 5100, and the sum data Sum2_0 output by the sum output terminal S1 of the full adder 5200. At this time, the data stored in the first register Reg3 is [C3_3, Sum3_3, Sum3_2, Sum3_1, Sum3_0, Sum2_0, Sum1_0, 1]. Therefore, the first multiplication module performs a multiplication operation of the second calculation precision (i.e., int4) on the first multiplier 1011 and the second multiplier 1101, and the obtained multiplication result [M7, M6, M5, M4, M3, M2, M1, M0] is [C3_3, Sum3_3, Sum3_2, Sum3_1, Sum3_0, Sum2_0, Sum1_0, 1] = [1, 0, 0, 0, 1, 1, 1, 1].

[0082] At least one embodiment of the present disclosure further provides a multiplier-adder, which includes an addition module (hereinafter referred to as a "second addition module") provided in any of the above embodiments.

[0083] For example, Figure 8 A schematic diagram of the structure of a multiplier-accumulator provided by at least one embodiment of the present disclosure is shown.

[0084] like Figure 8 As shown, the multiplier 800 includes a plurality of multiplication modules 810 (i.e., "second multiplication modules"), a plurality of addition modules 820 (i.e., "first addition modules"), and a plurality of addition modules 830 (i.e., "second addition modules", see for example Figure 3A Each adding module 820 includes a plurality of adding modules in a first cascade manner (see, for example, Figure 3B ) coupled full adders. Each adding module 830 includes an adder, a register and a control unit, and the adder includes a plurality of first cascaded full adders (see, for example, Figure 3B Each multiplication module 810 is configured to perform a multiplication operation of the third calculation precision, and each addition module 820 and each addition module 830 are configured to receive a multiplication operation result output by a corresponding coupled multiplication module 810 and perform an addition operation of the first calculation precision.

[0085] For example, the ratio of the number of multiplication modules 810, addition modules 820, and addition modules 830 in the multiplier-adder 800 may be 2:1:1, which is not limited in the present disclosure.

[0086] It should be noted that Figure 8 The connection manner between the multiple multiplication modules 810, the multiple addition modules 820 and the multiple addition modules 830 shown in the figure is exemplary, and the connection manner can be modified according to actual needs, and the present disclosure does not limit this.

[0087] At least one embodiment of the present disclosure further provides an operation method of a multiplier-adder, wherein the multiplier-adder is as follows: Figure 8 The multiplier 800 shown, the operation method includes: reconstructing at least part of the second addition modules into second multiplication modules and / or first addition modules to adjust the ratio of the number of second multiplication modules, first addition modules and second addition modules in the multiplier; and in response to the multiplier switching from the third calculation precision to the second calculation precision, reconstructing multiple second multiplication modules into at least one first multiplication module, reconstructing multiple first addition modules into at least one third addition module, and reconstructing at least part of the second addition modules into at least one first multiplication module, wherein the third addition module supports the fourth calculation precision.

[0088] The operating method of the above-mentioned multiplier and adder can switch and adjust the calculation accuracy of the multiplier and adder and dynamically adjust the ratio of the number of multiplication modules and addition modules in the multiplier and adder through reconstruction operations on the first multiplication module, the first addition module and the second addition module, so as to adapt to the requirements of different machine learning algorithms for calculation accuracy and hardware resources (i.e., multiplication modules and addition modules), and improve the hardware resource utilization, calculation efficiency and flexibility of the multiplier and adder.

[0089] The following example takes the third calculation precision as int4, the first and second calculation precisions as int8, and the fourth calculation precision as int16, and combines Figure 8 The multiplier-adder 800 shown further introduces the operation method of the above-mentioned multiplier-adder.

[0090] In this example, the calculation precision of the second multiplication module (i.e., "multiplication module 810") is int4, and each second multiplication module includes 4 second adders supporting the third calculation precision (i.e., int4) and 4 second registers, the bit width of each second register is 8 bits (i.e., 8 bits of data can be stored), and each second adder includes 4 full adders coupled in a first cascade manner. The calculation precision of the first addition module (i.e., "addition module 820") is int8, and includes 8 full adders coupled in a first cascade manner. The calculation precision of the second addition module (i.e., "addition module 830") is int8, and includes a third adder and a third register, the third adder includes 8 full adders coupled in a first cascade manner, the bit width of the third register is 16 bits (i.e., 16 bits of data can be stored), and the third register is coupled to the third adder to receive the operation result obtained by the corresponding third adder performing the addition operation of the first calculation precision (i.e., int8). For example, the structure of the second multiplication module (ie, "multiplication module 810") can refer to Figure 5A The structure of the first adding module (i.e., “adding module 820”) can be referred to Figure 3B The adder 310 shown in FIG. 1 and the second adding module (i.e., the adding module 830) can refer to Figure 3A .

[0091] For example, when reconstructing multiple second multiplication modules (i.e., "multiplication modules 810", with a calculation accuracy of int4) in the multiplier 800 into at least one first multiplication module (with a calculation accuracy of int8), every 4 second multiplication modules (e.g., the 4 multiplication modules 810 in the dotted box G1) can be reconstructed into 1 first multiplication module. Specifically, the 4 multiplication modules 810 include a total of 16 second adders with a calculation accuracy of int4 and 16 second registers with a bit width of 8 bits. The 16 second adders are merged into 8 first adders with a calculation accuracy of int8, and the 16 second registers are merged into 8 first registers with a bit width of 16 bits. Then, the obtained 8 first adders are coupled to the 8 first registers respectively, so that each first register receives the operation result obtained by the corresponding coupled first adder performing the addition operation with the second calculation accuracy. Finally, the eight first adders are coupled in a second cascade manner, wherein the sum outputs of the second to eighth full adders in the first adder of the previous stage are coupled to the first inputs of the first to seventh full adders in the first adder of the next stage, respectively, and the carry output of the eighth full adder in the first adder of the previous stage is coupled to the first input of the eighth full adder in the first adder of the next stage. Specifically, the connection method of the eight first adders and the eight first registers can refer to the above description of Figure 5B The description is not repeated here.

[0092] For example, when the plurality of first adding modules (i.e., "adding modules 820", with a calculation accuracy of int8) in the multiplier 800 are reconstructed into at least one third adding module (with a calculation accuracy of int16), every two first adding modules in the plurality of first adding modules (e.g., the two adding modules 820 in the dashed box G2) can be combined into one third adding module. The third adding module includes eight full adders coupled in a first cascade manner, for example, see Figure 3B Adder 310 in .

[0093] For example, when at least part of the second addition modules (i.e., "addition modules 830", with a calculation accuracy of int8) are reconstructed into at least one first multiplication module (with a calculation accuracy of int8), every 8 second addition modules in the plurality of second addition modules (e.g., the 8 addition modules 830 in the dashed box G3_1) can be merged into one first multiplication module. Specifically, the 8 addition modules 830 in the dashed box G3_1 include 8 third adders with a calculation accuracy of int8 and 8 third registers with a bit width of 16 bits, wherein the 8 third registers are respectively coupled to the 8 third adders. Therefore, it is also necessary to couple the eight third adders in a second cascade manner, that is, the sum output terminals of the second to eighth full adders in the third adder of the previous stage are respectively coupled to the first input terminals of the first to seventh full adders in the first adder of the next stage, and the carry output terminal of the eighth full adder in the first adder of the previous stage is coupled to the first input terminal of the eighth full adder in the first adder of the next stage. Here, the connection method of the eight third adders and the eight third registers can refer to the above-mentioned connection method of the eight third adders and the eight third registers. Figure 5B The description is not repeated here.

[0094] In addition, every two second addition modules in the multiple second addition modules (for example, the two addition modules 830 in the dotted box G4) can be merged into one third addition module. The merging method can refer to the above-mentioned method of merging the two addition modules 820 in the dotted box G2 into one third addition module, which will not be repeated here.

[0095] For example, Figure 8 As shown, the multiplier 800 includes 48 multiplication modules 810, 24 first addition modules 820 and 24 second addition modules 830, and the ratio of the number of multiplication modules to the number of addition modules is 2:1. In response to the calculation accuracy of the multiplier 800 switching from int4 to int8, according to the above-mentioned operation method of the multiplier, the 48 multiplication modules 810 with a calculation accuracy of int4 can be reconstructed into 12 first multiplication modules with a calculation accuracy of int8, the 24 first addition modules 820 with a calculation accuracy of int8 can be reconstructed into 12 third addition modules with a calculation accuracy of int16, and the 24 second addition modules 830 with a calculation accuracy of int8 can be reconstructed into 3 first multiplication modules with a calculation accuracy of int8 (corresponding to the dotted boxes G3_1 to G3_3). At this time, the multiplier obtained based on the reconstruction operation includes 15 first multiplication modules and 12 third addition modules, and the ratio of the number of multiplication modules to the number of addition modules is 5:4.

[0096] In another example, the 24 second addition modules 830 with a calculation accuracy of int8 can also be reconstructed into 2 first multiplication modules with a calculation accuracy of int8 and 2 third addition modules with a calculation accuracy of int16. At this time, the multiplier-adder obtained based on the reconstruction operation includes 14 first multiplication modules and 14 third addition modules, and the ratio of the number of multiplication modules to the number of addition modules is 1:1.

[0097] In addition, when configuring the multiplier-adder provided in at least one embodiment of the present disclosure, the first adding module (eg Figure 8 The "addition module 820" of FIG. 8 is replaced by a second addition module (eg Figure 8 The “second addition module”) is a dynamic adjustment range of the ratio of the number of multiplication modules to the number of addition modules in the multiplier-adder, and the present disclosure does not impose any restrictions on this.

[0098] In at least one embodiment of the present disclosure, if the machine learning algorithm has a large demand for addition modules, for example, a second multiplication module with a calculation accuracy of int4 in one multiplier 800 (i.e., "multiplication module 810") can be first split into four addition modules with a calculation accuracy of int4, and then these four addition modules with a calculation accuracy of int4 can be reconstructed into two second addition modules with a calculation accuracy of int8 (i.e., "addition module 830").

[0099] It should be noted that the specific calculation precisions mentioned in the embodiments of the present disclosure, such as the first calculation precision and the second calculation precision are int8, the third calculation precision is int4, and the fourth calculation precision is int16, are only for illustration. These calculation precisions can also be int4, int8, int16, int32, etc. Users can set them according to actual needs, and the present disclosure does not impose any restrictions on this.

[0100] Based on the addition module provided in the embodiment of the present disclosure, by reconstructing multiple addition modules into multiplication modules and / or addition modules, the ratio of the number of multiplication modules and addition modules in the multiplier-adder and their respective calculation accuracy can be flexibly changed, so as to better adapt to various machine learning algorithm requirements and calculation accuracy requirements, and maximize the utilization of the multiplier-adder hardware resources.

[0101] At least one embodiment of the present disclosure further provides a processor, which includes the multiplier and adder provided by any of the above embodiments. The processor may be, for example, a central processing unit (CPU) or a coprocessor, and the coprocessor may be, for example, a graphics processing unit (GPU), a general-purpose graphics processing unit (GPGPU), an AI accelerator (such as a tensor processor, etc.), etc., and the embodiments of the present disclosure do not limit this; and the embodiments of the present disclosure do not limit the specific architecture of the processor, the applicable instruction set, etc.

[0102] One or more embodiments of the present disclosure also provide an electronic device, which includes the processor provided by any of the above embodiments.

[0103] For example, Fig. 9 A schematic structural diagram of an electronic device provided by at least one embodiment of the present disclosure is shown.

[0104] The electronic devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc., and may also be used to implement various types of servers.

[0105] For example, Fig. 9 As shown, in some examples, the electronic device 900 includes a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 901, which may include a multiplier and adder provided by at least one embodiment of the present disclosure, and the processing device 901 may perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 902 or a program loaded from a storage device 908 to a random access memory (RAM) 903. Various programs and data required for the operation of the computer system are also stored in the RAM 903. The processing device 901, the ROM 902, and the RAM 903 are connected to each other via a bus 904. An input / output (I / O) interface 905 is also connected to the bus 904.

[0106] For example, the following components may be connected to the I / O interface 905: an input device 906 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 907 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 908 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 909 which may also include, for example, a network interface card such as a LAN card, a modem, etc. The communication device 909 may allow the electronic device 900 to communicate with other devices wirelessly or by wire to exchange data, and perform communication processing via a network such as the Internet. A drive 910 is also connected to the I / O interface 905 as needed. Removable media 911, such as magnetic disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on the drive 910 as needed, so that the computer programs read therefrom are installed into the storage device 908 as needed. Although Fig. 9 The electronic device 900 is shown to include various devices, but it should be understood that it is not required to implement or include all the devices shown. More or fewer devices may be implemented or included instead.

[0107] For example, the electronic device 900 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 909 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular phone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communication may use any of a variety of communication standards, protocols, and techniques, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging and / or Short Message Service (SMS), or any other suitable communication protocol.

[0108] In addition to the above exemplary descriptions, there are a few points that need to be explained:

[0109] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0110] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0111] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. An addition module, comprising: an adder, configured to perform an addition operation of a first calculation precision to obtain a first operation result; a register, coupled to the adder and configured to receive the first operation result obtained by the adder; a control unit, coupled to the register and the adder respectively, and configured to control the register and the adder to perform a reconstruction operation to obtain a first multiplication module supporting a second calculation precision; The adder includes a plurality of full adders, each of which includes a first input terminal, a second input terminal, a carry input terminal, a sum output terminal and a carry output terminal. The multiple full adders are coupled in a first cascade manner, the carry output terminal of the previous full adder is coupled to the carry input terminal of the next full adder, the first input terminals of the multiple full adders are configured to receive a first addend, the second input terminals of the multiple full adders are configured to receive a second addend, the sum output terminals of the multiple full adders are configured to output sum data, the carry output terminal of the previous full adder is configured to output carry data as input data of the carry input terminal of the next full adder, the carry output terminal of the last full adder of the multiple full adders is configured to output final carry data, and the first operation result includes multiple sum data and the final carry data.

2. A method for operating the adding module according to claim 1, comprising: Performing a split operation or a merge operation on the adder and the register of the adding module respectively to obtain at least one first adder and at least one first register, wherein the first adder supports the second calculation precision; The connection mode of the at least one first adder and the at least one first register is reconstructed to obtain the first multiplication module.

3. The operating method according to claim 2, wherein: The step of performing a split operation or a merge operation on the adder and the register of the adding module to obtain at least one first adder and at least one first register comprises: In response to the first calculation accuracy being higher than the second calculation accuracy, splitting a plurality of full adders in the adder of the adding module into at least two groups, coupling each group of full adders in the first cascade manner to obtain the first adder, and splitting the register of the adding module into at least two of the first registers; In response to the first calculation precision being lower than the second calculation precision, merging adders of at least two adding modules into the first adder, and merging registers of the at least two adding modules into the first register; In response to the first calculation precision being equal to the second calculation precision, the adder and the register of the adding module are used as the first adder and the first register, respectively.

4. The operating method according to claim 3, wherein: The at least two adding modules include a first adding module and a second adding module, and the step of merging the adders of the at least two adding modules into the first adder includes: The carry output terminal of the last-stage full adder in the adder of the first adding module is coupled to the carry input terminal of the first-stage full adder in the adder of the second adding module to obtain the first adder.

5. The operating method according to claim 3, wherein: The second calculation precision is an N-bit integer, the first multiplication module includes N first adders and N first registers, each first adder includes N full adders coupled in the first cascade manner, N=2 n , n is a positive integer, The reconstructing the connection mode between the at least one first adder and the at least one first register to obtain the first multiplication module includes: respectively coupling the N first adders to the N first registers, so that the first registers receive second operation results obtained by the correspondingly coupled first adders performing addition operations with the second calculation precision; N of the first adders are coupled in a second cascade manner, wherein the sum output terminals of the 2nd to Nth full adders in the first adder of the previous stage are respectively coupled to the first input terminals of the 1st to (N-1)th full adders in the first adder of the next stage, and the carry output terminal of the Nth full adder in the first adder of the previous stage is coupled to the first input terminal of the Nth full adder in the first adder of the next stage.

6. The operating method according to claim 5, wherein: The first multiplication module performs a multiplication operation of the second calculation precision on a first multiplier and a second multiplier, the first multiplier and the second multiplier respectively including N-bit data, and the operation method further includes: According to the first bit data of the second multiplier, using the shifted first multiplier or the shifted preset addend as the first addend of the first adder of the first stage; According to the i-th bit data of the second multiplier, the first multiplier or the preset addend is used as the second addend of the (i-1)-th stage first adder, where i=2, 3, ..., N.

7. The operating method according to claim 6, wherein: The method of using the shifted first multiplier or the shifted preset addend as the first addend of the first adder of the first stage according to the first bit data of the second multiplier includes: In response to the first bit data of the second multiplier being 1, using the shifted first multiplier as the first addend of the first adder of the first stage, and In response to the first bit data of the second multiplier being 0, the shifted preset addend is used as the first addend of the first adder of the first stage.

8. The operating method according to claim 6, wherein: The method of using the first multiplier or the preset addend as the second addend of the (i-1)th stage first adder according to the i-th bit data of the second multiplier comprises: In response to the i-th bit data of the second multiplier being 1, the first multiplier is used as the second addend of the (i-1)-th stage first adder, In response to the i-th bit data of the second multiplier being 0, the preset addend is used as the second addend of the (i-1)th stage first adder.

9. A multiplier-accumulator, comprising: A plurality of second multiplication modules, a plurality of first addition modules and a plurality of second addition modules, wherein, The second adding module is the adding module according to claim 1, The first adding module includes a plurality of full adders coupled in the first cascade manner, The second multiplication module is configured to perform a multiplication operation of a third calculation precision, The first adding module and the second adding module are configured to receive the multiplication operation results output by the correspondingly coupled second multiplication modules and perform the addition operation of the first calculation precision.

10. A method for operating a multiplier-accumulator according to claim 9, comprising: Reconstructing at least part of the second adding modules into the second multiplying modules and / or the first adding modules to adjust the ratio of the number of the second multiplying modules, the first adding modules and the second adding modules in the multiplier-adder; or In response to the multiplier and adder switching from the third computing precision to the second computing precision, the multiple second multiplication modules are reconstructed into at least one first multiplication module, the multiple first addition modules are reconstructed into at least one third addition module, and at least part of the second addition modules are reconstructed into the at least one first multiplication module, wherein the third addition module supports a fourth computing precision.

11. The operating method according to claim 10, wherein: The third calculation precision is int4, the first calculation precision and the second calculation precision are int8, and the fourth calculation precision is int16; The second multiplication module includes 4 second adders supporting the third calculation precision and 4 second registers, the bit width of the second register is 8 bits, and the second adder includes 4 full adders coupled in the first cascade manner; the first addition module includes 8 full adders coupled in the first cascade manner; the second addition module includes a third adder and a third register, the third adder includes the 8 full adders coupled in the first cascade manner, the bit width of the third register is 16 bits, and the third register is coupled to the third adder to receive the operation result obtained by the corresponding third adder performing the addition operation of the first calculation precision.

12. The operating method according to claim 11, wherein: The reconstructing the plurality of second multiplication modules into at least one first multiplication module comprises: Merging the second adders and the second registers in every four second multiplication modules into eight first adders and eight first registers, respectively, for reconstructing the first multiplication module, wherein the first adders support the second calculation precision, and the bit width of the first register is 16 bits; The eight first adders are coupled to the eight first registers respectively, so that each first register receives a calculation result obtained by the corresponding coupled first adder performing the addition operation of the second calculation precision; The eight first adders are coupled in a second cascade manner, wherein the sum output terminals of the second to eighth full adders in the first adder of the previous stage are respectively coupled to the first input terminals of the first to seventh full adders in the first adder of the next stage, and the carry output terminal of the eighth full adder in the first adder of the previous stage is coupled to the first input terminal of the eighth full adder in the first adder of the next stage.

13. The operating method according to claim 11, wherein: The step of reconstructing the plurality of first adding modules into at least one third adding module comprises: Every two of the first adding modules are combined into the third adding module, wherein the third adding module includes the eight full adders coupled in the first cascade manner.

14. The operating method according to claim 11, wherein: The reconstructing the at least part of the second addition module into the at least one first multiplication module comprises: coupling the third adders of every eight of the second adding modules in the plurality of second adding modules in the second cascade manner, Among them, the sum output terminals of the 2nd to 8th full adders in the third adder of the previous stage are respectively coupled to the first input terminals of the 1st to 7th full adders in the first adder of the next stage, and the carry output terminal of the 8th full adder in the first adder of the previous stage is coupled to the first input terminal of the 8th full adder in the first adder of the next stage.

15. A processor, comprising: The multiplier-accumulator as claimed in claim 9.

16. An electronic device comprising the processor according to claim 15.

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