Multiplication device

Abstract

A multiplication apparatus includes: a sign calculator adapted to determine a sign bit of a target product based on a sign bit of a first value and a sign bit of a second value; the first value and the second value are floating-point numbers; the compensator is suitable for determining an index flag bit and a first compensation value based on the mantissa bit of the first value and the mantissa bit of the second value; an exponent calculator adapted to determine a first exponent bit based on the exponent bit of the first value and the exponent bit of the second value; determining an index bit of the target product based on the first index bit and the index flag bit; a mantissa calculator adapted to determine a first mantissa bit based on the mantissa bit of the first value and the mantissa bit of the second value; and based on the first mantissa digit and the first compensation value, determining the mantissa digit of the target product, and finally obtaining the target product. According to the scheme, floating-point number multiplication can be converted into floating-point number addition, good approximation precision is achieved, and the area and power consumption of a calculation unit can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of artificial intelligence technology, and in particular to a multiplication operation device. Background Art

[0002] In the field of artificial intelligence (AI) accelerators, due to the computationally intensive nature of neural networks, it is often necessary to design computing units with huge area and power consumption to process data. Since there are a large number of convolution operations in neural networks, and the results of convolution operations are basically generated by computing units composed of multipliers and adders, a large amount of area and power consumption resources in AI accelerators are allocated to computing units composed of multipliers and adders.

[0003] In the current AI accelerator field, multipliers consume a lot of resources. Therefore, an approximate multiplier with less resource consumption is usually used to replace the multiplier, which can greatly reduce power consumption without significantly affecting the accuracy of the neural network. Summary of the invention

[0004] The object of the present invention is to provide a multiplication operation device, which converts floating-point multiplication into floating-point addition and has good approximate accuracy, and can significantly reduce the area and power consumption of a calculation unit.

[0005] To solve the above technical problems, the present invention provides a multiplication operation device, including: a sign calculator, an exponent calculator, a mantissa calculator, and a compensator, wherein: the sign calculator is suitable for determining the sign bit of the target product based on the sign bit of a first value and the sign bit of a second value; the first value and the second value are both floating point numbers; the compensator is suitable for determining the exponent flag and the first compensation value based on the mantissa bit of the first value and the mantissa bit of the second value; the exponent calculator is suitable for determining the first exponent bit based on the exponent bit of the first value and the exponent bit of the second value; based on the first exponent bit and the exponent flag bit, the exponent bit of the target product is determined; the mantissa calculator is suitable for determining the first mantissa bit based on the mantissa bit of the first value and the mantissa bit of the second value; based on the first mantissa bit and the first compensation value, the mantissa bit of the target product is determined; the target product is obtained by splicing the sign bit of the target product, the exponent bit of the target product, and the mantissa bit of the target product.

[0006] Optionally, the sign calculator includes an XOR operation unit; the XOR operation unit has a first input terminal that inputs the sign bit of the first value, a second terminal that inputs the sign bit of the second value, and an output terminal that outputs an XOR operation result of the sign bit of the first value and the sign bit of the second value, and the XOR operation result is the sign bit of the target product.

[0007] Optionally, the exponential calculator includes a first adder, a first subtractor and a selector, wherein: the first adder has a first input terminal that inputs the exponent bit of the first value, a second input terminal that inputs the exponent bit of the second value, and an output terminal that is coupled to the first input terminal of the output subtractor to output the first exponent bit; the selector has an input terminal that inputs the exponent flag bit, and an output terminal that outputs the exponent correction value corresponding to the exponent flag bit; the first subtractor has a second input terminal that is coupled to the output terminal of the selector to output the exponent bit of the target product.

[0008] Optionally, the mantissa calculator comprises: a second adder, a third adder and a shift splicer, wherein: the second adder has a first input terminal that inputs the mantissa bits of the first value, a second input terminal that inputs the mantissa bits of the second value, an output terminal that is coupled to the first input terminal of the shift splicer and the first input terminal of the third adder, and outputs the first mantissa bits; the third adder has a second input terminal that inputs the first compensation value, an output terminal that is coupled to the second input terminal of the shift splicer, and outputs a second sum of the first mantissa bits and the first compensation value; the shift splicer has a first output terminal that outputs the exponent flag bit, and a second output terminal that outputs the mantissa bits of the target product.

[0009] Optionally, the shift splicer determines that the exponent flag is a first value when the upper 2 bits of the second sum value are 00; determines that the exponent flag is a second value when the upper 2 bits of the second sum value are 01 or 10; and the first value is not equal to the second value.

[0010] Optionally, when the exponent flag is the first value, the mantissa of the target product is: the concatenation of the lower 2N bits of the second sum and the lower X bits of the first mantissa; the length of the first mantissa is X+2N-1 bits; when the exponent flag is the second value and the upper 2 bits of the second sum are 01, the mantissa of the target product is: the highest bit is 0, the 2nd to 2N+1st bits are the lower 2N bits of the second sum, and the 2N+2nd to Xth bits are: the X-1th bit of the first mantissa to the second to last bit of the first mantissa; when the exponent flag is the second value and the upper 2 bits of the second sum are 10, the mantissa of the target product is: the highest bit is 1, the 2nd to 2N+1st bits are the lower 2N bits of the second sum, and the 2N+2nd to Xth bits are: the X-1th bit of the first mantissa to the second to last bit of the first mantissa.

[0011] Optionally, the compensator is suitable for determining a first product based on the high N bits of the mantissa of the first value and the high N bits of the mantissa of the second value; determining a compensation amount based on the N+1th to N+Mth bits of the mantissa of the first value and the N+1th to N+Mth bits of the mantissa of the second value; and determining the first compensation value based on the first product and the compensation amount.

[0012] Optionally, the compensator comprises: a multiplier, a compensation amount determination module and a fourth adder, wherein: the multiplier, whose first input terminal inputs the high N bits of the mantissa of the first value, whose second input terminal inputs the high N bits of the mantissa of the second value, and whose output terminal is coupled to the first input terminal of the fourth adder; the compensation amount determination module, whose first input terminal inputs the N+1th to N+Mth bits of the mantissa of the first value, whose second input terminal inputs the N+1th to N+Mth bits of the mantissa of the second value, and whose output terminal is coupled to the second input terminal of the fourth adder to output the compensation amount; the fourth adder, whose output terminal outputs the first compensation value.

[0013] Optionally, the multiplication operation device also includes: a data splitting module, whose first input end inputs the first value, and whose first output end outputs the sign bit of the first value, the exponent bit of the first value, and the mantissa bit of the first value; whose second input end inputs the second value, and whose second output end outputs the sign bit of the second value, the exponent bit of the second value, and the mantissa bit of the second value.

[0014] Optionally, the multiplication operation device further includes: a data splicing module, adapted to splice the sign bit of the target product, the exponent bit of the target product and the mantissa bit of the target product.

[0015] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0016] The multiplication operation of the first value and the second value of the floating-point number is converted into an addition operation through the sign calculator, the exponent calculator, and the mantissa calculator. The first exponent bit and the first mantissa bit in the addition operation are adjusted through the compensator, so that the error distribution can be uniformized, which can reduce the area and power consumption of the calculation unit and improve the calculation accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a structural schematic diagram of a multiplication operation device in an embodiment of the present invention;

[0018] Figure 2 is a schematic diagram of the structure of an exponential calculator in an embodiment of the present invention;

[0019] Figure 3is a schematic structural diagram of a mantissa calculator in an embodiment of the present invention;

[0020] Figure 4 is a schematic structural diagram of a compensator in an embodiment of the present invention;

[0021] Figure 5 It is a flowchart of a multiplication calculation in an embodiment of the present invention. DETAILED DESCRIPTION

[0022] In the prior art, there are some design schemes for the computing unit of AI accelerators using approximate multipliers. One scheme is to modify the encoder part in the booth multiplier and simplify the encoder's Karnaugh map to save the area and power consumption of the computing unit. Another scheme is to simplify the compression process of the partial product in the multiplier. However, the above two schemes will result in a large loss of accuracy of the neural network.

[0023] In the present invention, the multiplication operation of the first value and the second value of the floating point number is converted into an addition operation through a sign calculator, an exponent calculator, and a mantissa calculator. The first exponent bit and the first mantissa bit in the addition operation are adjusted through a compensator, so that the error distribution that occurs can be uniformized, and the area and power consumption of the calculation unit can be reduced while the calculation accuracy can be improved.

[0024] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0025] The calculation principle of the multiplication operation device provided in the following embodiments of the present invention is based on the Mitchell algorithm. The principle of the Mitchell algorithm is briefly described below.

[0026] It is known in the prior art that for a decimal number A, its corresponding floating point representation method can be expressed by the following formula (1):

[0027] A=(-1) S *2 (e-bias )*(1+0.m) (1)

[0028] Where S is the sign bit, e constitutes the exponent bit, 0.m represents a real number greater than 0 and less than 1; bias is the bias calculated based on the exponent bit. If the exponent bit is set to n, then bias = 2 (n-1) -1.

[0029] The multiplication operation device provided in the following embodiments of the present invention can be based on the Mitchell algorithm to approximately complete the multiplication of two numbers by two binary additions, with a maximum error of no more than 1 / 9. The principle of the Mitchell algorithm is as follows:

[0030] If two positive real numbers A and B are multiplied, P = A × B, then log2P = log2A + log2B.

[0031] Express A in floating point format, and we get A = 2 (e1-bias) *(1+0.m1), then log2A=(e1-bias)+log2(1+0.m1). Express B in floating point format, and we get B=2 (e2-bias )*(1+0.m2).

[0032] Therefore, log2P=(e1-bias+e2-bias)+log2(1+0.m1)+log2(1+0.m2).

[0033] Since 0.m is between 0 and 1, log2(1+0.m)≈0.m, we can get the following simplified formula:

[0034] P≈2 (e1+e2-2bias )*(1+0.m1+0.m2), 0.m1+0.m2<1;

[0035] P≈2 (e1+e2-2bias) *(0.m1+0.m2-1), 0.m1+0.m2≥1.

[0036] Thus, an approximate multiplication result is obtained through the Mitchell algorithm. The hardware of the Mitchell algorithm can use two adders and a part of the logic structure to form a multiplier, thereby eliminating the multiplication operation in the multiplier.

[0037] The embodiment of the present invention provides a multiplication operation device for performing approximate multiplication operation, referring to Figure 1 , the multiplication operation device is described in detail below.

[0038] In the embodiment of the present invention, the multiplication operation device may include a sign calculator 11 , an exponent calculator 12 , a mantissa calculator 13 and a compensator 14 .

[0039] In a specific implementation, the multiplication operation device can be used to calculate the product between the first value and the second value. It should be noted that the target product calculated by the multiplication operation device provided in the embodiment of the present invention is essentially an approximate product between the first value and the second value, because: the multiplication operation device described below converts the multiplication operation between the first value and the second value into an addition operation based on the Mitchell algorithm.

[0040] In the embodiment of the present invention, the first value and the second value can be floating point numbers in the IEEE-754 floating point format, or floating point numbers in a variant format corresponding to the IEEE-754 floating point format. The first value and the second value in the floating point format are composed of three parts: a sign bit, an exponent bit, and a mantissa bit.

[0041] In specific applications, it can be known that for a single-precision floating-point number, its length is 32 bits, of which: the first bit is the sign bit, the length of the sign bit is 1 bit; the second to ninth bits are the exponent bits, the length of the exponent bits is 8 bits, the tenth to 32nd bits are the mantissa bits, the length of the mantissa bits is 23 bits.

[0042] For double-precision floating-point numbers, the length is 64 bits, of which: the first bit is the sign bit, the length of the sign bit is 1 bit; the second to 11th bits are the exponent bits, the length of the exponent bits is 11 bits; the 12th to 64th bits are the mantissa bits, the length of the mantissa bits is 52 bits.

[0043] In an embodiment of the present invention, the multiplication operation device can split the first value and the second value, the split first value includes a sign bit, an exponent bit and a mantissa bit, and the split second value also includes a sign bit, an exponent bit and a mantissa bit.

[0044] In some embodiments, the multiplication operation device may also include a data splitting module 10, which is used to split the first value and the second value to obtain the sign bit of the first value, the exponent bit of the first value, and the mantissa bit of the first value, and the sign bit of the second value, the exponent bit of the second value, and the mantissa bit of the second value, respectively.

[0045] In a specific implementation, the sign bit of the target product may be determined based on the sign bit of the first value and the sign bit of the second value.

[0046] Specifically, the sign bit of the first value and the sign bit of the second value may be respectively input to the sign calculator 11 , and the sign calculator 11 calculates and outputs the sign bit of the target product.

[0047] In some embodiments, the first bit of the first value may be obtained, that is, the sign bit of the first value; the first bit of the second value may be obtained, that is, the sign bit of the second value. The sign calculator 11 may be an XOR operator, which performs an XOR operation on the sign bit of the first value and the sign bit of the second value, and uses the result of the XOR operation as the sign bit of the target product.

[0048] For example, if the sign bit of the first value is 1 and the sign bit of the second value is 0, the sign calculator 11 performs an XOR operation on the sign bit of the first value and the sign bit of the second value, and the XOR operation result is 1, then the sign bit of the target product is determined to be 1.

[0049] In a specific implementation, the exponent bit of the first value and the exponent bit of the second value may be respectively input into the exponent calculator 12 , and the exponent calculator 12 operates on the exponent bit of the first value and the exponent bit of the second value to obtain the first exponent bit.

[0050] Specifically, the exponent calculator 12 may perform an addition operation on the exponent bit of the first value and the exponent bit of the second value to obtain the first exponent bit.

[0051] In a specific implementation, the mantissa of the first value and the mantissa of the second value may be respectively input into the mantissa calculator 13, and the mantissa calculator 13 operates the mantissa of the first value and the mantissa of the second value to obtain the first mantissa.

[0052] Specifically, the mantissa calculator 13 may perform an addition operation on the mantissa bits of the first value and the mantissa bits of the second value to obtain the first mantissa bits.

[0053] In a specific implementation, the compensator 14 can obtain the high N bits of the mantissa of the first value and the high N bits of the mantissa of the second value, multiply the high N bits of the mantissa of the first value with the high N bits of the mantissa of the second value, and obtain a first product of length 2N.

[0054] The compensator 14 can also obtain the N+1th to N+Mth bits of the mantissa of the first value and the N+1th to N+Mth bits of the mantissa of the second value, and determine the compensation amount based on the N+1th to N+Mth bits of the mantissa of the first value and the N+1th to N+Mth bits of the mantissa of the second value.

[0055] The values ​​of N and M are related to the precision requirements of the multiplication device. Specifically, when M is the same, the larger the value of N, the higher the precision of the multiplication device. Correspondingly, when N is the same, the larger the value of M, the higher the precision of the multiplication device.

[0056] The corresponding compensation amounts may be different for different values ​​of the N+1th to N+Mth digits of the mantissa of the first value and the N+1th to N+Mth digits of the mantissa of the second value.

[0057] Specifically, compensation amounts corresponding to different values ​​of the N+1th to N+Mth digits of the mantissa of the first value and the N+1th to N+Mth digits of the mantissa of the second value may be set.

[0058] For example, N=3, M=1. When the 4th digit of the mantissa of the first value and the 4th digit of the mantissa of the second value are both 1, the preset compensation amount is 000010; when the 4th digit of the mantissa of the first value and the 4th digit of the mantissa of the second value are both 0, the preset compensation amount is 000000; when either the 4th digit of the mantissa of the first value or the 4th digit of the mantissa of the second value is 1, the preset compensation amount is 000001.

[0059] The compensator 14 performs an addition operation on the first product and the compensation amount, and uses the obtained first sum as the first compensation value. The number of bits of the compensation amount is the same as the number of bits of the first product.

[0060] In some embodiments, N=3 and M=1 may be used. Thus, the compensator 14 may obtain the upper 3 bits of the mantissa of the first value and the upper 3 bits of the mantissa of the second value, and perform a multiplication operation on the two to obtain a first product of length 6 bits. The compensator 14 determines the compensation amount based on the 4th bit of the mantissa of the first value and the 4th bit of the mantissa of the mantissa of the second value.

[0061] In some other embodiments, N=4 and M=2 may be used. Thus, the compensator 14 may obtain the upper 4 bits of the mantissa of the first value and the upper 4 bits of the mantissa of the second value, and perform a multiplication operation on the two to obtain a first product of length 8 bits. The compensator 14 determines the compensation amount based on the 5th to 6th bits of the mantissa of the first value and the 5th to 6th bits of the mantissa of the second value.

[0062] In a specific implementation, the mantissa calculator 13 may determine the exponent flag and the mantissa of the target product according to the first compensation value and the first mantissa.

[0063] Specifically, the mantissa calculator 13 may take the upper 2N+1 bits of the first mantissa and perform addition operation with the upper 2N+1 bits of the first compensation value to obtain the second sum. The mantissa calculator 13 may obtain the upper 2 bits of the second sum.

[0064] If the upper 2 bits of the second sum are 00, the exponent flag is determined to be 0; the mantissa of the target product is determined to be: the concatenation of the lower 2N bits of the second sum and the lower X bits of the first mantissa, and the length of the first mantissa is X+2N+1bit.

[0065] For example, if the first value is a single-precision floating point number, the length of the sum of the mantissa of the first value and the mantissa of the second value is 24 bits. If N=3, the lower 6 bits of the second sum value are taken and concatenated with the lower 17 bits of the first mantissa (ie, X=17), and the concatenated result is the mantissa of the target product.

[0066] The "splicing" described in the embodiment of the present invention may refer to directly splicing different binary numbers. Specifically, as in the above example, the lower 6 bits of the second sum value are used as the upper 6 bits of the mantissa of the target product, and the lower 17 bits of the first mantissa are used as the lower 17 bits of the mantissa of the target product. Thus, the mantissa of the target product with a length of 23 bits is obtained.

[0067] If the upper 2 bits of the second sum are 01, the exponent flag is determined to be 1; the mantissa bits of the target product are determined as follows: the highest bit is 0, the 2nd to 2N+1st bits are the lower 2N bits of the second sum, and the 2N+2nd to Xth bits are: the X-1th bit of the first mantissa bit to the second to last bit of the first mantissa bit.

[0068] For example, if the first value is a single-precision floating point number, the length of the first mantissa is 23 bits. If N=3, the highest bit is 0, and the lower 6 bits of the second sum are concatenated with the 16th to the second to last bits of the first mantissa, and the concatenated result is the mantissa of the target product.

[0069] If the values ​​of the upper 2 bits of the second sum are 10, the exponent flag is determined to be 1; the mantissa bits of the target product are determined as follows: the highest bit is 1, the 2nd to 2N+1st bits are the lower 2N bits of the second sum, and the 2N+2nd to Xth bits are: the X-1th bit of the first mantissa bit to the second to last bit of the first mantissa bit.

[0070] For example, if the first value is a single-precision floating point number, the length of the first mantissa is 23 bits. If N=3, the highest bit is 1, and the lower 6 bits of the second sum are concatenated with the 16th to the second to last bits of the first mantissa, and the concatenated result is the mantissa of the target product.

[0071] In a specific implementation, the exponent calculator 12 may determine the exponent bits of the target product based on the first exponent bits and the exponent flag bits.

[0072] In some embodiments, the exponent calculator 12 may determine the corresponding exponent correction value based on the value of the exponent flag bit. Further, the exponent calculator 12 calculates the difference between the first exponent bit and the exponent correction value as the exponent bit of the target product.

[0073] Specifically, if the value of the exponent flag is the first value, the corresponding first exponent correction value can be determined, and the first exponent bit is subtracted from the first exponent correction value, and the obtained difference is used as the exponent bit of the target product.

[0074] If the value of the exponent flag is the second value, the corresponding second exponent correction value can be determined, and the first exponent bit is subtracted from the second exponent correction value, and the obtained difference is used as the exponent bit of the target product.

[0075] The first exponent correction value is not equal to the second exponent correction value. In other words, different values ​​of the exponent flag bit correspond to different exponent correction values.

[0076] In some embodiments, if the first value and the second value are both single-precision floating point numbers and the value of the exponent flag is 1, the value of the first exponent correction value can be 011111111; if the value of the exponent flag is 0, the value of the first exponent correction value can be 011111110.

[0077] The specific structures of the sign calculator 11, the exponent calculator 12, the mantissa calculator 13 and the compensator 14 are described in detail below.

[0078] Reference Figure 2 , a schematic diagram of the structure of an exponential calculator in an embodiment of the present invention is given.

[0079] Figure 2 In the embodiment, the exponential calculator includes a first adder 21, a first subtractor 22 and a selector 23, and the selector 23 stores the exponential correction value.

[0080] The first input terminal of the first adder 21 can input the exponent bit of the first value, the second input terminal of the first adder 21 can input the exponent bit of the second value, the first adder 21 sums the exponent bit of the first value and the exponent bit of the second value, and the output terminal of the first adder 21 outputs the first exponent bit.

[0081] The selector 23 can receive the exponent flag bit, determine the exponent correction value to be the first exponent correction value or the second exponent correction value based on the value of the exponent flag bit, and output the determined exponent correction value to the first subtractor 22. It can be understood that the above-mentioned selector 23 is only an example, and substantially other devices or circuits capable of realizing the following functions can be understood as the above-mentioned selector 23: receiving the exponent flag bit, determining the exponent correction value and outputting it to the first subtractor 22.

[0082] The first input terminal of the first subtractor 22 can input the first exponent bit, and the second input terminal of the first subtractor 22 can input the exponent correction value. The first subtractor 22 performs a subtraction operation on the first exponent bit and the exponent correction value, and the difference outputted by the output terminal of the first subtractor 22 is the exponent bit of the target product.

[0083] Reference Figure 3 , a schematic diagram of the structure of a mantissa calculator in an embodiment of the present invention is given.

[0084] Figure 3 In the embodiment, the mantissa calculator may include a second adder 31, a third adder 32 and a shift splicer 33, wherein:

[0085] The first input terminal of the second adder 31 inputs the mantissa of the first value, and the second input terminal of the second adder 31 inputs the mantissa of the second value. The second adder 31 adds the mantissa of the first value and the mantissa of the second value, and the output terminal of the second adder 31 outputs the first mantissa.

[0086] The first input terminal of the third adder 32 is coupled to the output terminal of the second adder 31, that is, the first input terminal of the third adder 32 inputs the first mantissa. The second input terminal of the third adder 32 is coupled to the output terminal of the compensator and inputs the first compensation value.

[0087] The output end of the third adder 32 is also coupled to the first input end of the shift splicer 33, and the output end of the second adder 31 is coupled to the second input end of the shift splicer 33. The shift splicer 33 can output the exponent flag and the mantissa of the target product.

[0088] Specifically, the output terminal of the third adder 32 outputs the sum of the first mantissa and the first compensation value (second sum). The shift splicer 33 receives the second sum, selects the upper 2 bits of the second sum, and determines the value of the exponent flag based on the upper 2 bits of the second sum.

[0089] Specifically, if the upper 2 bits of the second sum are 00, the shift splicer 33 can determine that the exponent flag is 0; and the shift splicer 33 splices the lower 2N bits of the second sum with the lower X bits of the first mantissa, and the splicing result is the mantissa of the target product.

[0090] If the upper 2 bits of the second sum are 01, the exponent flag is determined to be 1; the mantissa bits of the target product are determined as follows: the highest bit is 0, the 2nd to 2N+1st bits are the lower 2N bits of the second sum, and the 2N+2nd to Xth bits are: the X-1th bit of the first mantissa bit to the second to last bit of the first mantissa bit.

[0091] If the values ​​of the upper 2 bits of the second sum are 10, the exponent flag is determined to be 1; the mantissa bits of the target product are determined as follows: the highest bit is 1, the 2nd to 2N+1st bits are the lower 2N bits of the second sum, and the 2N+2nd to Xth bits are: the X-1th bit of the first mantissa bit to the second to last bit of the first mantissa bit.

[0092] Reference Figure 4 , a schematic structural diagram of a compensator in an embodiment of the present invention is given.

[0093] Figure 4 In the embodiment, the compensator may include a multiplier 41, a compensation amount determination module 42 and a fourth adder 43.

[0094] The first input terminal of the multiplier 41 can input the high N bits of the mantissa of the first value, and the second input terminal of the multiplier 41 can input the high N bits of the mantissa of the second value. The multiplier 41 multiplies the high N bits of the mantissa of the first value with the high N bits of the mantissa of the second value to obtain a first product of length 2N. The output terminal of the multiplier 41 can output the first product.

[0095] The compensation amount determination module 42 may input the N+1th to N+Mth digits of the mantissa of the first value and the N+1th to N+Mth digits of the mantissa of the second value. The compensation amount determination module 42 may determine the compensation amount based on the N+1th to N+Mth digits of the mantissa of the first value and the N+1th to N+Mth digits of the mantissa of the second value.

[0096] A first input terminal of the fourth adder 43 is coupled to the output terminal of the multiplier 41 , and a second input terminal of the fourth adder 43 is coupled to the output terminal of the compensation amount determination module 42 . The first product and the compensation amount are added to obtain a first compensation value.

[0097] In the embodiment of the present invention, the multiplication operation device may further include a data splicing module 15, which is suitable for splicing the sign bit of the target product, the exponent bit of the target product, and the exponent bit of the target product to obtain the target product.

[0098] The specific operation process of the multiplication operation device provided in the above embodiment of the present invention is described below through specific examples. Figure 5 , a flowchart of a multiplication calculation in an embodiment of the present invention is given.

[0099] Set the first value to A and the second value to B. Both the first value and the second value are single-precision floating-point numbers. The sign bit of the first value is represented by A_S, and the sign bit of the second value is represented by B_S; the exponent bit of the first value is represented by A_E, and the exponent bit of the second value is represented by B_E; the mantissa bit of the first value is represented by A_M, and the mantissa bit of the second value is represented by B_M.

[0100] Step 501, obtaining the sign bit of the target product.

[0101] In a specific implementation, A_S and B_S are respectively input into a sign calculator, which performs an XOR operation on A_S and B_S to obtain a sign bit P_S of the target product.

[0102] Step 502, obtaining the first exponent bit.

[0103] In a specific implementation, A_E and B_E are respectively input into an exponential calculator, and the exponential calculator performs an addition operation on A_E and B_E to obtain a first exponent position E_1.

[0104] Step 503, obtaining the first mantissa.

[0105] In a specific implementation, A_M and B_M are respectively input into a mantissa calculator, and the mantissa calculator performs an addition operation on A_M and B_M to obtain a first mantissa digit M_1, where the length of M_1 is 24 bits.

[0106] Step 504: Obtain a first compensation value.

[0107] In a specific implementation, the upper 3 bits of A_M and the upper 3 bits of B_M are obtained, and the upper 3 bits of A_M and the upper 3 bits of B_M are multiplied to obtain a first product M_2, and the length of M_2 is 6 bits.

[0108] The 4th bit of A_M and the 4th bit of B_M are obtained. Based on the values ​​of the 4th bit of A_M and the 4th bit of B_M, the compensation amount is determined.

[0109] Specifically, if the 4th bit of A_M and the 4th bit of B_M are both 1, the first compensation value is M_3=M_2+000010; if only one of the 4th bit of A_M and the 4th bit of B_M is 1, the first compensation value is M_3=M_2+000001; if the 4th bit of A_M and the 4th bit of B_M are both 0, the first compensation value is M_3=M_2.

[0110] In a specific implementation, the length of the above compensation amount (000010, 000001) is equal to the length of M_2.

[0111] It should be noted that in the above step 504, the upper 4 bits of A_M and the upper 4 bits of B_M can also be obtained for multiplication, and the length of the obtained product M_2 is 8 bits. Accordingly, the 5th bit of A_M and the 5th bit of B_M can be obtained. In this scenario, if the 5th bit of A_M and the 5th bit of B_M are both 1, the first compensation value is M_3=M_2+00000010; if only one of the 4th bit of A_M and the 4th bit of B_M is 1, the first compensation value M_3=M_2+000001; if the 4th bit of A_M and the 4th bit of B_M are both 0, the first compensation value M_3=M_2.

[0112] Step 505, obtaining the mantissa of the target product.

[0113] In a specific implementation, the upper 7 bits of M_3 and the upper 7 bits of M_1 may be added to obtain an 8-bit second sum value M_4.

[0114] Get the upper 2 bits of M_4. If the upper 2 bits of M_4 are 00, determine that the exponent flag is 0, and the mantissa of the target product output by the mantissa calculator is: P_M = M_4[5:0] to M_1[16:0];

[0115] The above M_4[5:0] is: the lower 6 bits of M_4. The above M_1[16:0] is: the lower 17 bits of M_1. M_4[5:0]~M_1[16:0] may mean: concatenating M_4[5:0] and M_1[16:0]. Specifically, in P_M, the upper 6 bits are M_4[5:0], and the lower 17 bits are M_1[16:0].

[0116] For example, if M_4 is 00111001, then M_4[5:0] is 111001. If M_1 is 01101010101010101010101011, then M_1[16:0] is 0101010101010101011, and the concatenated P_M is 1110010101010101010101011.

[0117] If the values ​​of the upper 2 bits of M_4 are 01, the exponent flag is determined to be 1, and the mantissa of the target product output by the mantissa calculator is: P_M=0~M_4[5:0]~M_1[16:1];

[0118] The above-mentioned M_4[5:0] is: the lower 6 bits of M_4. The above-mentioned M_1[16:1] is: the second to last bit to the seventeenth to last bit of M_1.

[0119] For example, if M_4 is 00111001, then M_4[5:0] is 111001. If M_1 is 01101010101010101010101011, then M_1[16:1] is 010101010101010101, and the concatenated P_M is 011100101010101010101010101.

[0120] If the values ​​of the upper 2 bits of M_4 are 10, the exponent flag is determined to be 1, and the mantissa bits of the target product output by the mantissa calculator are: P_M=1~M_4[5:0]~M_1[16:1].

[0121] For example, if M_4 is 00111001, then M_4[5:0] is 111001. If M_1 is 01101010101010101010101011, then M_1[16:1] is 010101010101010101, and the concatenated P_M is 111100101010101010101010101.

[0122] Step 506, obtaining the exponent bits of the target product.

[0123] In a specific implementation, the exponent bit of the target product is determined according to the exponent flag bit obtained in the above step 505 and the first exponent bit obtained in the above step 503.

[0124] Specifically, if the value of the exponent flag is 0, subtract E_1 from 011111111 to obtain the exponent of the target product P_E=E_1-011111111;

[0125] If the value of the exponent flag is 1, E_1 is subtracted from 011111111 to obtain the exponent of the target product P_E=E_1-011111110.

[0126] Step 507, obtaining the target product.

[0127] In a specific implementation, the target product can be obtained by splicing the sign bit of the target product, the exponent bit of the target product, and the mantissa bit of the target product through a data splicing module.

[0128] That is, the target product may be P=P_S~P_E~P_M.

[0129] For example, the sign bit of the target product is 1, the exponent bit of the target product is 01101100, and the mantissa bit of the target product is 0110101010101010101010101. Thus, the target product obtained by concatenation is 1011011000110101010101010101010101.

[0130] In summary, in the embodiment of the present invention, the multiplication operation of the first value and the second value of the floating point number is converted into an addition operation through the sign calculator, the exponent calculator, and the mantissa calculator. The first exponent bit and the first mantissa bit in the addition operation are adjusted through the compensator, so that the error distribution that occurs can be uniformized, and the area and power consumption of the calculation unit can be reduced while the calculation accuracy can be improved.

[0131] A person skilled in the art may understand that all or part of the steps in the various methods of the above embodiments may be completed by instructing the relevant hardware through a program, and the program may be stored in a computer-readable storage medium, which may include: ROM, RAM, disk or CD, etc.

[0132] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A multiplication device, characterized in that: include: Sign calculator, exponent calculator, mantissa calculator, compensator, among which: The sign calculator is adapted to determine a sign bit of a target product based on a sign bit of a first value and a sign bit of a second value, wherein the first value and the second value are both floating point numbers; The compensator is adapted to determine an exponent flag and a first compensation value based on the mantissa bits of the first value and the mantissa bits of the second value; The exponent calculator is adapted to determine a first exponent bit based on the exponent bit of the first value and the exponent bit of the second value; and determine an exponent bit of the target product based on the first exponent bit and the exponent flag bit; The mantissa calculator is adapted to determine a first mantissa bit based on the mantissa bit of the first value and the mantissa bit of the second value; and determine a mantissa bit of the target product based on the first mantissa bit and the first compensation value; The target product is obtained by concatenating the sign bit of the target product, the exponent bit of the target product, and the mantissa bit of the target product.

2. The multiplication device according to claim 1, wherein: The symbolic calculator comprises an XOR operation unit; The XOR operation unit has a first input terminal that inputs the sign bit of the first value, a second terminal that inputs the sign bit of the second value, and an output terminal that outputs an XOR operation result of the sign bit of the first value and the sign bit of the second value, wherein the XOR operation result is the sign bit of the target product.

3. The multiplication device according to claim 1, wherein: The exponential calculator comprises a first adder, a first subtractor and a selector, wherein: The first adder has a first input terminal inputting the exponent bit of the first value, a second input terminal inputting the exponent bit of the second value, and an output terminal coupled to the first input terminal of the output first subtractor to output the first exponent bit; The selector has an input terminal that inputs the exponent flag bit, and an output terminal that outputs an exponent correction value corresponding to the exponent flag bit; The first subtractor has a second input terminal coupled to the output terminal of the selector, and outputs the exponent bit of the target product.

4. The multiplication device according to claim 1, wherein: The mantissa calculator comprises: a second adder, a third adder and a shift splicer, wherein: The second adder has a first input terminal inputting the mantissa bits of the first value, a second input terminal inputting the mantissa bits of the second value, an output terminal coupled to the first input terminal of the shift splicer and the first input terminal of the third adder, and outputting the first mantissa bits; The third adder has a second input terminal inputting the first compensation value, an output terminal coupled to the second input terminal of the shift splicer, and outputting a second sum of the first mantissa and the first compensation value; The shift splicer has a first output terminal that outputs the exponent flag bit, and a second output terminal that outputs the mantissa bit of the target product.

5. The multiplication device according to claim 4, characterized in that: The shift splicer determines that the exponent flag is a first value when the upper 2 bits of the second sum value are 00; determines that the exponent flag is a second value when the upper 2 bits of the second sum value are 01 or 10; and the first value is not equal to the second value.

6. The multiplication device according to claim 5, characterized in that: When the exponent flag is the first value, the mantissa of the target product is: the concatenation of the lower 2N bits of the second sum value and the lower X bits of the first mantissa; the length of the first mantissa is X+2N-1 bits; When the exponent flag is the second value and the high 2 bits of the second sum are 01, the mantissa of the target product is as follows: the highest bit is 0, the 2nd to 2N+1st bits are the low 2N bits of the second sum, and the 2N+2nd to Xth bits are: the X-1th bit of the first mantissa to the second to last bit of the first mantissa; When the exponent flag is the second value and the upper 2 bits of the second sum are 10, the mantissa bits of the target product are: the highest bit is 1, the 2nd to 2N+1st bits are the lower 2N bits of the second sum, and the 2N+2nd to Xth bits are: the X-1th bit of the first mantissa bit to the second to last bit of the first mantissa bit.

7. The multiplication device according to claim 1, wherein: The compensator is suitable for determining a first product based on the upper N bits of the mantissa of the first value and the upper N bits of the mantissa of the second value; determining a compensation amount based on the N+1th to N+Mth bits of the mantissa of the first value and the N+1th to N+Mth bits of the mantissa of the second value; and determining the first compensation value based on the first product and the compensation amount.

8. The multiplication device according to claim 7, wherein: The compensator comprises: a multiplier, a compensation amount determination module and a fourth adder, wherein: The multiplier has a first input terminal inputting high N bits of the mantissa of the first value, a second input terminal inputting high N bits of the mantissa of the second value, and an output terminal coupled to a first input terminal of the fourth adder; The compensation amount determination module has a first input terminal inputting the N+1th to N+Mth bits of the mantissa of the first value, a second input terminal inputting the N+1th to N+Mth bits of the mantissa of the second value, an output terminal coupled to the second input terminal of the fourth adder, and outputting the compensation amount; The fourth adder outputs the first compensation value at its output terminal.

9. The multiplication device according to claim 1, wherein: Also includes: a data splitting module, wherein a first input terminal thereof inputs the first value, and a first output terminal thereof outputs a sign bit of the first value, an exponent bit of the first value, and a mantissa bit of the first value; The second input terminal thereof inputs the second value, and the second output terminal thereof outputs the sign bit of the second value, the exponent bit of the second value, and the mantissa bit of the second value.

10. The multiplication device according to claim 1, wherein: Also includes: The data splicing module is adapted to splice the sign bit of the target product, the exponent bit of the target product and the mantissa bit of the target product.

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