Program updating method and system for Nor Flash chip containing code protection area

Abstract

The invention discloses a program updating method for a Nor Flash chip containing a code protection area, which comprises the following steps: when a program updating instruction is received, acquiring a program updating file, erasing configuration information of the updating, storage information of the Nor Flash chip and configuration information of a first storage area; setting an erasing mode of a second storage area according to the erasing configuration information, the storage information of the Nor Flash chip and the configuration information of the first storage area, and executing erasing operation in the second storage area according to the erasing mode; and after the erasing operation is completed, writing the program updating file into the erased row of the second storage area by row. According to the erasing configuration information, the storage information of the Nor Flash chip and the configuration information of the first storage area, a line-by-line erasing mode or a block-by-block erasing mode is automatically selected for erasing, so that the use efficiency of the second storage area and the updating time and frequency of the program are optimized, interference to the program of the first storage area is reduced, and the user experience is improved. And the risk of the program in the first storage area is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of Nor Flash storage chips, and in particular to a program updating method, system, device and computer-readable storage medium for a Nor Flash chip including a code protection area. Background Art

[0002] In chip products containing Nor Flash, Nor Flash is used to store the customer's executable program. Customers usually have confidentiality requirements for the program and do not want the developed code to be read by others. Some chip users are software and solution developers (hereinafter referred to as Customer A), not end customers. They develop part of the software library and then perform secondary software development for end customers (hereinafter referred to as Customer B). The software developed by Customer A hopes to support the use of Customer B, that is, to support Customer B to execute Customer A's software code, but does not want Customer B to be able to directly see (read) the code content developed by Customer A. This is usually called a Nor Flash chip with a code protection area.

[0003] For Nor Flash chips that contain code protection areas, usually after customer A develops the software library program, the chip and customer A's software library program are packaged together and given to customer B for secondary development. At this time, customer A's program will not change, but when customer B develops his own program, he will frequently erase and write the Nor Flash in B's program area.

[0004] According to the characteristics of Nor Flash, if customer B needs to modify and update the program, it is generally necessary to first erase the original data line by line and then write the new data. In the case of a large Nor Flash capacity and a large program area of ​​customer B, the update time will be very long. At the same time, according to the characteristics of Nor Flash, if customer B frequently erases and writes the program area, it will cause slight disturbance to the program of customer A stored in the code protection area. If the number of erases and writes is too many, the software library program of customer A stored in the code protection area will be destroyed.

[0005] Based on this, a new solution is needed. Summary of the invention

[0006] The main purpose of the present invention is to provide a program update method and system for a Nor Flash chip including a code protection zone, in order to address the problems of long update time and risk of damaging the program in the code protection zone in the existing program update method for a Nor Flash chip including a code protection zone.

[0007] To achieve the above object, the present invention provides a program update method for a Nor Flash chip including a code protection area, wherein the Nor Flash chip includes a first storage area and a second storage area, wherein the first storage area is used to store code to be protected, and the method includes the following steps: Upon receiving a program update instruction, obtaining a program update file, erase configuration information for this update, storage information of the Nor Flash chip, and configuration information of the first storage area, wherein the configuration information includes a start storage address and an end storage address of the first storage area; According to the erasure configuration information, the storage information of the Nor Flash chip and the configuration information of the first storage area, setting an erasure mode of the second storage area and performing an erasure operation in the second storage area according to the erasure mode; and After the erasing operation is completed, the program update file is written row by row into the erased rows of the second storage area.

[0008] In the program update method for a Nor Flash chip including a code protection area provided by the present invention, setting an erasure mode of the second storage area according to the erase configuration information, the storage information of the Nor Flash chip and the configuration information of the first storage area and performing an erase operation in the second storage area according to the erase mode includes: According to the storage information of the Nor Flash chip and the configuration information of the first storage area, determining the positional relationship between the first storage area and the second storage area, wherein when the starting storage address of the first storage area is 0, determining that the first storage area is located above the second storage area, and when the ending storage address of the first storage area is the maximum storage address of the Nor Flash chip, determining that the second storage area is located above the first storage area, otherwise, determining that the first storage area is located in the middle of the second storage area; Dividing the Nor Flash chip into N erase blocks according to the erase configuration information; According to the positional relationship, an erasing mode of the second storage area is set and an erasing operation is performed in the second storage area according to the erasing mode.

[0009] In the program update method for a Nor Flash chip including a code protection area provided by the present invention, when the first storage area is located above the second storage area, the steps of setting an erasing mode for the second storage area according to the positional relationship and performing an erasing operation in the second storage area according to the erasing mode include: Searching the N erase blocks for an erase block to which the end storage address of the first storage area belongs; An erase operation is started in the second storage area, wherein a row-by-row erase operation is performed on storage rows belonging to the second storage area in the erase block to which the end storage address of the first storage area belongs, and a block-by-block erase operation is performed on the remaining erase blocks of the second storage area.

[0010] In the program update method for a Nor Flash chip including a code protection area provided by the present invention, when the first storage area is located below the second storage area, the steps of setting an erasing mode for the second storage area according to the positional relationship and performing an erasing operation in the second storage area according to the erasing mode include: Searching the N erase blocks for an erase block to which the start storage address of the first storage area belongs; The block-by-block erasing operation starts in the second storage area. When the erase block to which the starting storage address of the first storage area belongs is executed, the row-by-row erasing operation is performed on the storage rows belonging to the second storage area in the erase block to which the starting storage address of the first storage area belongs.

[0011] In the program update method for a Nor Flash chip including a code protection area provided by the present invention, when the first storage area is located in the middle of the second storage area, the steps of setting an erasing mode of the second storage area according to the positional relationship and performing an erasing operation in the second storage area according to the erasing mode include: Searching the N erase blocks for an erase block to which a start storage address of the first storage area belongs and an erase block to which an end storage address of the first storage area belongs; A block-by-block erasing operation is started in the second storage area, wherein, when the execution reaches the erase block to which the starting storage address of the first storage area belongs, a row-by-row erasing operation is performed on the storage rows belonging to the second storage area in the erase block to which the starting storage address of the first storage area belongs, and when the execution reaches the erase block to which the ending storage address of the first storage area belongs, a row-by-row erasing operation is performed on the storage rows belonging to the second storage area in the erase block to which the ending storage address of the first storage area belongs, and a block-by-block erasing operation is performed on the remaining erase blocks of the second storage area.

[0012] According to another aspect of the present invention, there is also provided a program update system for a Nor Flash chip including a code protection area, wherein the Nor Flash chip includes a first storage area and a second storage area, wherein the first storage area is used to store code to be protected, including: an acquisition module, configured to acquire, upon receiving a program update instruction, a program update file, erase configuration information for this update, storage information of the Nor Flash chip, and configuration information of the first storage area, wherein the configuration information includes a start storage address and an end storage address of the first storage area; an erasing module, configured to set an erasing mode of the second storage area according to the erasing configuration information, the storage information of the Nor Flash chip and the configuration information of the first storage area, and perform an erasing operation in the second storage area according to the erasing mode; and The updating module is used to write the program updating file into the erased row of the second storage area row by row after the erasing operation is completed.

[0013] In the program update system for a Nor Flash chip including a code protection zone provided by the present invention, the erasing module includes: a position relationship determination unit, configured to determine the position relationship between the first storage area and the second storage area according to the storage information of the Nor Flash chip and the configuration information of the first storage area, wherein when the starting storage address of the first storage area is 0, it is determined that the first storage area is located above the second storage area, and when the ending storage address of the first storage area is the maximum storage address of the Nor Flash chip, it is determined that the second storage area is located above the first storage area; otherwise, it is determined that the first storage area is located in the middle of the second storage area; A division unit, used for dividing the Nor Flash chip into N erase blocks according to the erase configuration information; An execution unit is used to set an erasing mode of the second storage area according to the position relationship and perform an erasing operation in the second storage area according to the erasing mode.

[0014] In the program update system for a Nor Flash chip including a code protection zone provided by the present invention, when the first storage area is located above the second storage area, the execution unit is used to search the erase block to which the end storage address of the first storage area belongs in the N erase blocks, and start to perform an erase operation in the second storage area, wherein a row-by-row erase operation is performed on storage rows belonging to the second storage area in the erase block to which the end storage address of the first storage area belongs, and a block-by-block erase operation is performed on the remaining erase blocks in the second storage area; When the first storage area is located below the second storage area, the execution unit is used to search the erase block to which the start storage address of the first storage area belongs in the N erase blocks, start to perform a block-by-block erase operation in the second storage area, and when the erase block to which the start storage address of the first storage area belongs is executed, perform a row-by-row erase operation on the storage rows belonging to the second storage area in the erase block to which the start storage address of the first storage area belongs; When the first storage area is located in the middle of the second storage area, the execution unit is used to search the erase block to which the start storage address of the first storage area belongs and the erase block to which the end storage address of the first storage area belongs in the N erase blocks, and start to perform a block-by-block erasing operation in the second storage area, wherein, when executing to the erase block to which the start storage address of the first storage area belongs, a row-by-row erasing operation is performed on the storage rows belonging to the second storage area in the erase block to which the start storage address of the first storage area belongs, and when executing to the erase block to which the end storage address of the first storage area belongs, a row-by-row erasing operation is performed on the storage rows belonging to the second storage area in the erase block to which the end storage address of the first storage area belongs, and a block-by-block erasing operation is performed on the remaining erase blocks in the second storage area.

[0015] The present invention also provides a program update device for a Nor Flash chip including a code protection zone, comprising a processor and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, the steps of the program update method for a Nor Flash chip including a code protection zone are implemented as described above.

[0016] The program update system and method for a Nor Flash chip including a code protection area provided by the present invention have the following beneficial effects: the present invention automatically selects a row-by-row erasing or a block-by-block erasing mode for erasing according to the erase configuration information, the storage information of the Nor Flash chip and the configuration information of the first storage area, which not only optimizes the use efficiency of the second storage area, the update time and number of programs, but also reduces the interference with the program in the first storage area, and reduces the risk of the program in the first storage area. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below. Obviously, the drawings in the following description are only embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on the provided drawings without creative work: Figure 1 The figure shows a partition diagram of a Nor Flash chip including a code protection zone used in the present invention; Figure 2 FIG. 1 is a flow chart of a program update method for a Nor Flash chip including a code protection zone provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0018] In order to facilitate understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Typical embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0020] Figure 1 FIG. 1 is a schematic diagram showing the partitioning of a Nor Flash chip including a code protection zone used in the present invention. Figure 1 As shown, the Nor Flash chip includes a first storage area for storing a client A program and a second storage area for storing a client B program. The client A program is the code that needs to be protected when executing a program update.

[0021] Figure 2 FIG. 1 is a flow chart of a method for updating a program in a Nor Flash chip including a code protection zone provided by an embodiment of the present invention. Figure 2 As shown, the program update method for a Nor Flash chip including a code protection zone includes the following steps: Step S1, when receiving a program update instruction, obtaining a program update file, erase configuration information of this update, storage information of the Nor Flash chip and configuration information of the first storage area, wherein the configuration information includes a start storage address and an end storage address of the first storage area; Specifically, in one embodiment of the present invention, when a program update instruction is received from a processor, the program update file, the erase configuration information of this update, the storage information of the Nor Flash chip, and the configuration information of the first storage area are obtained. Among them, the program update file refers to a file containing new program code, which is usually a binary file. The erase configuration information of this update refers to the size of the erase block during this update, that is, the number of rows included in each erase block. For example, 8 means that 8 rows of data are erased at a time when performing block erasure. The storage information of the Nor Flash chip refers to the maximum storage address of the Nor Flash chip. For example, Figure 1 The Nor Flash chip in the NVMe SSD includes n rows of storage areas, and its maximum storage address is n. The configuration information of the first storage area refers to the starting storage address and the ending storage address of the first storage area. For example, Figure 1 The starting storage address of the first storage area of ​​the Nor Flash chip in is 0, and the ending storage address is x, that is, the second storage area starts from the x+1th row.

[0022] Step S2: according to the erasure configuration information, the storage information of the Nor Flash chip and the configuration information of the first storage area, setting an erasure mode of the second storage area and performing an erasure operation in the second storage area according to the erasure mode.

[0023] Specifically, in one embodiment of the present invention, in the block-by-block erasing method, it is necessary to divide n rows of Nor Flash chips into multiple erase blocks from the beginning, that is, 1 erase block = a number of rows, such as m. Therefore, the start position and / or end position of the first storage area and some storage rows of the second storage area will be divided into the same erase block. Since the first storage area is the area where the protection code is located, it cannot be erased, so a part of the Nor Flash space will be wasted, and the maximum possible waste is (m-1) rows of space. For example, in Figure 1 In the example shown, the client B program can only use the space starting from block2, and part of the space in block1 cannot be used. Therefore, step S2 includes: Step S21: Determine the positional relationship between the first storage area and the second storage area according to the storage information of the Nor Flash chip and the configuration information of the first storage area.

[0024] Specifically, in one embodiment of the present invention, the positional relationship between the first storage area and the second storage area is determined by the maximum storage address of the Nor Flash chip, the starting storage address and the ending storage address of the first storage area. That is, when the starting storage address of the first storage area is 0, it is determined that the first storage area is located above the second storage area, and when the ending storage address of the first storage area is the maximum storage address of the Nor Flash chip, it is determined that the second storage area is located above the first storage area, otherwise, it is determined that the first storage area is located in the middle of the second storage area.

[0025] Step S22: dividing the Nor Flash chip into N erase blocks according to the erase configuration information; Step S23: according to the position relationship, setting an erasing mode of the second storage area and performing an erasing operation in the second storage area according to the erasing mode.

[0026] Further, in one embodiment of the present invention, when the first storage area is located above the second storage area, only the erase block where the end position of the first storage area is located may intersect with the erase block where the start position of the second storage area is located. Figure 1 In the example shown, the last row of the first storage area where the client A program is located and the first m-1 rows of the second storage area where the client B program is located are divided into block 1 together, and a row-by-row erasing operation is performed on the first m-1 rows of the second storage area where the client B program is located, and a block-by-block erasing operation is performed on the remaining erase blocks of the second storage area. Therefore, step S23 includes: Searching the N erase blocks for an erase block to which the end storage address of the first storage area belongs; An erase operation is started in the second storage area, wherein a row-by-row erase operation is performed on storage rows belonging to the second storage area in the erase block to which the end storage address of the first storage area belongs, and a block-by-block erase operation is performed on the remaining erase blocks of the second storage area.

[0027] Further, in one embodiment of the present invention, when the first storage area is located below the second storage area, only the erase block where the start position of the first storage area is located may have an intersection with the erase block where the end position of the second storage area is located, that is, the first few rows of the first storage area where the client A program is located and the last few rows of the second storage area where the client B program is located are divided into the same erase block. For example, for erase block block i, a block-by-block erase operation is performed for the first i-1 erase blocks, and a row-by-row erase operation is performed for several rows belonging to the second storage area in the i-th erase block. Therefore, step S23 includes: Searching the N erase blocks for an erase block to which the start storage address of the first storage area belongs; The block-by-block erasing operation starts in the second storage area. When the erase block to which the starting storage address of the first storage area belongs is executed, the row-by-row erasing operation is performed on the storage rows belonging to the second storage area in the erase block to which the starting storage address of the first storage area belongs.

[0028] Further, in one embodiment of the present invention, when the first storage area is located in the middle of the second storage area, the erase block at the start position of the first storage area may intersect with the erase block at the end position of the second storage area, and the erase block at the end position of the first storage area may intersect with the erase block at the start position of the second storage area, that is, the first few rows of the first storage area where the client A program is located and the last few rows of the first part of the second storage area where the client B program is located are divided into the same erase block (for example, erase block block i), the last few rows of the first storage area where the client A program is located and the first few rows of the second part of the second storage area where the client B program is located are divided into the same erase block (for example, erase block block j), and a block-by-block erase operation is performed for the first i-1 erase blocks, a row-by-row erase operation is performed for several rows belonging to the second storage area in the i-th erase block and several rows belonging to the second storage area in the j-th erase block, and a block-by-block erase operation is performed for the j+1-th to N-th erase blocks. Step S23 includes: Searching the N erase blocks for an erase block to which a start storage address of the first storage area belongs and an erase block to which an end storage address of the first storage area belongs; A block-by-block erasing operation is started in the second storage area, wherein, when the execution reaches the erase block to which the starting storage address of the first storage area belongs, a row-by-row erasing operation is performed on the storage rows belonging to the second storage area in the erase block to which the starting storage address of the first storage area belongs, and when the execution reaches the erase block to which the ending storage address of the first storage area belongs, a row-by-row erasing operation is performed on the storage rows belonging to the second storage area in the erase block to which the ending storage address of the first storage area belongs, and a block-by-block erasing operation is performed on the remaining erase blocks of the second storage area.

[0029] In this embodiment, through the starting storage address and / or the ending storage address of the first storage area, it can be known in which erase block the address is located; when updating the client B program in the second storage area, it is necessary to erase the client B program first, and the block-by-block erasing method is used by default. When the starting storage address and / or the ending storage address are encountered, it is automatically changed to the row-by-row erasing method. After the erasing of the erase block containing the starting storage address and / or the ending storage address of the client A program is completed, it is automatically changed to the block-by-block erasing until the end.

[0030] For example, suppose each block of Nor Flash has 8 rows, and the program of customer B has 300 rows in total. If row-by-row erasure is used, and the erasing time of each row and each block is 2ms (Nor Flash characteristic, the erasing time of row and block is the same), then 300x2=600ms of erasing time is required. If the erasing method of automatically selecting row or block is used, the erasing time can be optimized as follows: 300 = 37 blocks x 8 + 4 rows 37 x 2ms + 4 x 2ms = 82ms It only takes 82ms to complete the erase, which is much shorter than 600ms.

[0031] At the same time, the number of flash erases is also reduced a lot, from 300 times to 4+37=41 times. The reduction in the number of erases increases the chip's service life and data reliability.

[0032] Step S3: After the erasing operation is completed, the program update file is written row by row into the erased row of the second storage area.

[0033] The present invention adopts an automatic switching method of block-by-block erasing and row-by-row erasing. By mixing block-by-block erasing and row-by-row erasing, the erasing time can be significantly shortened compared to completely erasing all rows row by row, and the number of erasing times can also be greatly reduced. By reducing the erasing time and number of times, not only the update efficiency is improved, but also the service life of the Flash chip is effectively extended, thereby improving the durability of the chip and the data reliability. According to the positional relationship of the storage area and the division of the erase blocks, the erasing mode (row by row or block by block) is flexibly selected to maximize the use of the storage space of the Nor Flash chip and optimize the performance. By finely controlling the erasing operation, unnecessary erasing operations are reduced, and the security and stability of the data are improved.

[0034] Correspondingly, the present invention also provides a program update system for a Nor Flash chip including a code protection area, the Nor Flash chip including a first storage area and a second storage area, the first storage area being used to store code to be protected, including: an acquisition module, used to acquire a program update file, erase configuration information for this update, storage information of the Nor Flash chip and configuration information of the first storage area when receiving a program update instruction, the configuration information including a starting storage address and an ending storage address of the first storage area; an erasing module, used to set an erasing mode of the second storage area according to the erase configuration information, the storage information of the Nor Flash chip and the configuration information of the first storage area, and perform an erasing operation in the second storage area according to the erasing mode; and an update module, used to write the program update file to the erased rows of the second storage area row by row after the erase operation is completed.

[0035] Further, in one embodiment of the present invention, the erasing module includes: a position relationship determination unit, used to determine the position relationship between the first storage area and the second storage area according to the storage information of the Nor Flash chip and the configuration information of the first storage area, wherein when the starting storage address of the first storage area is 0, it is determined that the first storage area is located above the second storage area, and when the ending storage address of the first storage area is the maximum storage address of the Nor Flash chip, it is determined that the second storage area is located above the first storage area, otherwise, it is determined that the first storage area is located in the middle of the second storage area; a division unit, used to divide the NorFlash chip into N erase blocks according to the erase configuration information; an execution unit, used to set the erase mode of the second storage area according to the position relationship and perform an erase operation in the second storage area according to the erase mode.

[0036] Further, in one embodiment of the present invention, when the first storage area is located above the second storage area, the execution unit is used to search the erase block to which the end storage address of the first storage area belongs in the N erase blocks, and start to perform an erase operation in the second storage area, wherein a row-by-row erase operation is performed on the storage rows belonging to the second storage area in the erase block to which the end storage address of the first storage area belongs, and a block-by-block erase operation is performed on the remaining erase blocks of the second storage area. When the first storage area is located below the second storage area, the execution unit is used to search the erase block to which the start storage address of the first storage area belongs in the N erase blocks, and start to perform a block-by-block erase operation in the second storage area, and when the erase block to which the start storage address of the first storage area belongs is executed, a row-by-row erase operation is performed on the storage rows belonging to the second storage area in the erase block to which the start storage address of the first storage area belongs. When the first storage area is located in the middle of the second storage area, the execution unit is used to search the erase block to which the start storage address of the first storage area belongs and the erase block to which the end storage address of the first storage area belongs in the N erase blocks, and start to perform a block-by-block erasing operation in the second storage area, wherein, when executing to the erase block to which the start storage address of the first storage area belongs, a row-by-row erasing operation is performed on the storage rows belonging to the second storage area in the erase block to which the start storage address of the first storage area belongs, and when executing to the erase block to which the end storage address of the first storage area belongs, a row-by-row erasing operation is performed on the storage rows belonging to the second storage area in the erase block to which the end storage address of the first storage area belongs, and a block-by-block erasing operation is performed on the remaining erase blocks in the second storage area.

[0037] The embodiment of the present invention further provides a program update device for a Nor Flash chip including a code protection zone, which may include: Memory for storing computer programs; The processor can implement the following steps when executing the computer program stored in the above memory: When a program update instruction is received, a program update file, erase configuration information of this update, storage information of the Nor Flash chip, and configuration information of the first storage area are obtained, wherein the configuration information includes a starting storage address and an ending storage address of the first storage area; according to the erase configuration information, the storage information of the Nor Flash chip, and the configuration information of the first storage area, an erase mode of the second storage area is set and an erase operation is performed in the second storage area according to the erase mode; and after the erase operation is completed, the program update file is written to the erased rows of the second storage area row by row.

[0038] The embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the following steps can be implemented; When a program update instruction is received, a program update file, erase configuration information of this update, storage information of the Nor Flash chip, and configuration information of the first storage area are obtained, wherein the configuration information includes a starting storage address and an ending storage address of the first storage area; according to the erase configuration information, the storage information of the Nor Flash chip, and the configuration information of the first storage area, an erase mode of the second storage area is set and an erase operation is performed in the second storage area according to the erase mode; and after the erase operation is completed, the program update file is written to the erased rows of the second storage area row by row.

[0039] The computer-readable storage medium may include: a USB flash drive, a mobile hard disk, a read-only memory (ROM) > a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program codes.

[0040] In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0041] Similarly, it should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed method should not be interpreted as reflecting the intention that the claimed invention requires more features than those explicitly recited in each claim. More specifically, as reflected in the claims below, inventive aspects lie in less than all the features of the individual embodiments disclosed above. Therefore, the claims that follow the specific embodiment are hereby expressly incorporated into the specific embodiment, with each claim itself serving as a separate embodiment of the present invention.

[0042] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and further may be divided into a plurality of submodules or subunits or subcomponents. All features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device so disclosed may be combined in any combination, except that at least some of such features and / or processes or units are mutually exclusive. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature that provides the same, equivalent or similar purpose.

[0043] In addition, those skilled in the art will appreciate that, although some embodiments herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present invention and form different embodiments. For example, in the claims below, any one of the claimed embodiments may be used in any combination.

[0044] The various component embodiments of the present invention may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. It should be understood by those skilled in the art that a microprocessor or a digital signal processor (DSP) may be used in practice to implement some or all of the functions of some or all of the components in the embodiments of the present invention. The present invention may also be implemented as a device or apparatus program (e.g., a computer program and a computer program product) for executing part or all of the methods described herein. Such a program implementing the present invention may be stored on a computer-readable medium, or may be in the form of one or more signals. Such a signal may be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.

[0045] It should be noted that the above embodiments illustrate the present invention rather than limit it, and that those skilled in the art may devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets shall not be construed as a limitation on the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "one" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present invention may be implemented by means of hardware comprising a number of different elements and by means of a suitably programmed computer. In a unit claim enumerating a number of devices, several of these devices may be embodied by the same hardware item. The use of the words first, second, and third, etc., does not indicate any order. These words may be interpreted as names.

Claims

1. A program update method for a Nor Flash chip including a code protection area, wherein the Nor Flash chip includes a first storage area and a second storage area, wherein the first storage area is used to store code to be protected, characterized in that: The following steps are involved: Upon receiving a program update instruction, obtaining a program update file, erase configuration information for this update, storage information of the NorFlash chip, and configuration information of the first storage area, wherein the configuration information includes a start storage address and an end storage address of the first storage area; According to the erase configuration information, the storage information of the Nor Flash chip and the configuration information of the first storage area, setting an erase mode of the second storage area and performing an erase operation in the second storage area according to the erase mode; as well as After the erasing operation is completed, the program update file is written row by row into the erased rows of the second storage area.

2. The program update method for a Nor Flash chip including a code protection zone according to claim 1, characterized in that: According to the erase configuration information, the storage information of the Nor Flash chip and the configuration information of the first storage area, setting an erase mode of the second storage area and performing an erase operation in the second storage area according to the erase mode includes: According to the storage information of the Nor Flash chip and the configuration information of the first storage area, determining the positional relationship between the first storage area and the second storage area, wherein when the starting storage address of the first storage area is 0, determining that the first storage area is located above the second storage area, and when the ending storage address of the first storage area is the maximum storage address of the NorFlash chip, determining that the second storage area is located above the first storage area, otherwise, determining that the first storage area is located in the middle of the second storage area; Dividing the Nor Flash chip into N erase blocks according to the erase configuration information; According to the positional relationship, an erasing mode of the second storage area is set and an erasing operation is performed in the second storage area according to the erasing mode.

3. The program update method for a Nor Flash chip including a code protection zone as claimed in claim 2, characterized in that: When the first storage area is located above the second storage area, the steps of setting an erasing mode for the second storage area according to the positional relationship and performing an erasing operation in the second storage area according to the erasing mode include: Searching the N erase blocks for an erase block to which the end storage address of the first storage area belongs; An erase operation is started in the second storage area, wherein a row-by-row erase operation is performed on storage rows belonging to the second storage area in the erase block to which the end storage address of the first storage area belongs, and a block-by-block erase operation is performed on the remaining erase blocks of the second storage area.

4. The program update method for a Nor Flash chip including a code protection zone according to claim 2, characterized in that: When the first storage area is located below the second storage area, the steps of setting an erasing mode for the second storage area according to the positional relationship and performing an erasing operation in the second storage area according to the erasing mode include: Searching the N erase blocks for an erase block to which the start storage address of the first storage area belongs; The block-by-block erasing operation starts in the second storage area. When the erase block to which the starting storage address of the first storage area belongs is executed, the row-by-row erasing operation is performed on the storage rows belonging to the second storage area in the erase block to which the starting storage address of the first storage area belongs.

5. The program update method for a Nor Flash chip including a code protection area according to claim 2, characterized in that: When the first storage area is located in the middle of the second storage area, the steps of setting an erasing mode for the second storage area according to the positional relationship and performing an erasing operation in the second storage area according to the erasing mode include: Searching the N erase blocks for an erase block to which a start storage address of the first storage area belongs and an erase block to which an end storage address of the first storage area belongs; A block-by-block erasing operation is started in the second storage area, wherein, when the execution reaches the erase block to which the starting storage address of the first storage area belongs, a row-by-row erasing operation is performed on the storage rows belonging to the second storage area in the erase block to which the starting storage address of the first storage area belongs, and when the execution reaches the erase block to which the ending storage address of the first storage area belongs, a row-by-row erasing operation is performed on the storage rows belonging to the second storage area in the erase block to which the ending storage address of the first storage area belongs, and a block-by-block erasing operation is performed on the remaining erase blocks of the second storage area.

6. A program update system for a Nor Flash chip including a code protection area, the Nor Flash chip comprising a first storage area and a second storage area, the first storage area being used to store code to be protected, characterized in that: include: an acquisition module, configured to acquire, upon receiving a program update instruction, a program update file, erase configuration information for this update, storage information of the Nor Flash chip, and configuration information of the first storage area, wherein the configuration information includes a start storage address and an end storage address of the first storage area; An erasing module, configured to set an erasing mode of the second storage area according to the erasing configuration information, the storage information of the Nor Flash chip and the configuration information of the first storage area, and perform an erasing operation in the second storage area according to the erasing mode; as well as The updating module is used to write the program updating file into the erased row of the second storage area row by row after the erasing operation is completed.

7. The program update system for a Nor Flash chip including a code protection zone as claimed in claim 6, characterized in that: The erasing module comprises: a position relationship determination unit, configured to determine the position relationship between the first storage area and the second storage area according to the storage information of the Nor Flash chip and the configuration information of the first storage area, wherein when the starting storage address of the first storage area is 0, it is determined that the first storage area is located above the second storage area, and when the ending storage address of the first storage area is the maximum storage address of the Nor Flash chip, it is determined that the second storage area is located above the first storage area; otherwise, it is determined that the first storage area is located in the middle of the second storage area; A division unit, used for dividing the Nor Flash chip into N erase blocks according to the erase configuration information; An execution unit is used to set an erasing mode of the second storage area according to the position relationship and perform an erasing operation in the second storage area according to the erasing mode.

8. The program update system for a Nor Flash chip including a code protection zone as claimed in claim 7, characterized in that: When the first storage area is located above the second storage area, the execution unit is used to search the erase block to which the end storage address of the first storage area belongs in the N erase blocks, and start to perform an erase operation in the second storage area, wherein a row-by-row erase operation is performed on the storage rows belonging to the second storage area in the erase block to which the end storage address of the first storage area belongs, and a block-by-block erase operation is performed on the remaining erase blocks in the second storage area; When the first storage area is located below the second storage area, the execution unit is used to search the erase block to which the start storage address of the first storage area belongs in the N erase blocks, start to perform a block-by-block erase operation in the second storage area, and when the erase block to which the start storage address of the first storage area belongs is executed, perform a row-by-row erase operation on the storage rows belonging to the second storage area in the erase block to which the start storage address of the first storage area belongs; When the first storage area is located in the middle of the second storage area, the execution unit is used to search the erase block to which the start storage address of the first storage area belongs and the erase block to which the end storage address of the first storage area belongs in the N erase blocks, and start to perform a block-by-block erasing operation in the second storage area, wherein, when executing to the erase block to which the start storage address of the first storage area belongs, a row-by-row erasing operation is performed on the storage rows belonging to the second storage area in the erase block to which the start storage address of the first storage area belongs, and when executing to the erase block to which the end storage address of the first storage area belongs, a row-by-row erasing operation is performed on the storage rows belonging to the second storage area in the erase block to which the end storage address of the first storage area belongs, and a block-by-block erasing operation is performed on the remaining erase blocks in the second storage area.

9. A program update device for a Nor Flash chip including a code protection area, characterized in that: The invention comprises a processor and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, the steps of the program update method for a Nor Flash chip containing a code protection zone as claimed in any one of claims 1 to 4 are implemented.

10. A computer-readable storage medium, wherein a computer program is stored in the computer-readable storage medium, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 4 is implemented.

Images