Register data overflow processing method and device, computer equipment and storage medium

Abstract

The invention relates to a register data overflow processing method and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the steps that the working state of a current virtual register is obtained, and under the condition that the current virtual register is in a to-be-overflowed state, a data overflow site corresponding to the current virtual register is determined; action instructions corresponding to the current virtual register are sequentially extracted, a target virtual register is constructed according to the action instructions, and the action types of the action instructions are determined; selecting a target insertion instruction according to the action type; wherein the target insertion instruction is an internal register carrying instruction; the target virtual register is used for replacing the current virtual register to serve as an operation object, and data of the data overflow site is stored or taken out according to the target insertion instruction. By adopting the method, the time cost caused by the register data overflow instruction can be reduced.

Description

Technical Field

[0001] The present application relates to the technical field of electronic digital data processing, and in particular to a register data overflow processing method, device, computer equipment, storage medium and computer program product. Background Art

[0002] Physical register allocation is required during the compilation process. There are many ways to solve the problem of insufficient physical registers in conventional allocation schemes, such as evict / split, etc. In some states, data needs to be temporarily stored in an external cache and loaded back before the next use. This scheme is called register allocation overflow.

[0003] At present, in the relevant register allocation strategy, when overflow (Spill) is required, a "STORE" instruction is generally inserted after the variable definition point to temporarily store the data in the external cache; before the subsequent variable use point, a "RELOAD" instruction is inserted to retrieve the data from the external cache and put it into the register for use.

[0004] Once register overflow occurs, it will overflow to the STORE / RELOAD instructions used in the external cache. Register overflow will cause the adverse effect of large instruction time overhead, which will ultimately have a significant impact on program performance. Summary of the invention

[0005] Based on this, it is necessary to provide a register data overflow processing method, apparatus, computer device, computer-readable storage medium and computer program product that can reduce the time cost caused by register data overflow instructions in response to the above technical problems.

[0006] In a first aspect, the present application provides a register data overflow processing method, comprising:

[0007] Acquire the working state of the current virtual register, and when the current virtual register is in a pending overflow state, determine the data overflow position corresponding to the current virtual register;

[0008] Extracting action instructions corresponding to the current virtual register in sequence, constructing a target virtual register according to the action instructions, and determining an action type of the action instructions;

[0009] Selecting a target insertion instruction according to the action type; wherein the target insertion instruction is an internal register transfer instruction;

[0010] The target virtual register is used to replace the current virtual register as an operation object, and the data at the data overflow site is stored or retrieved according to the target insertion instruction.

[0011] In one embodiment, the method is applied to predicate register data; the action type includes a definition type and a use type; and selecting a target insertion instruction according to the action type includes:

[0012] In case the action type is a definition type, selecting a predicate register store instruction as a target insertion instruction;

[0013] In case the action type is a use type, a predicate register load instruction is selected as a target insertion instruction.

[0014] In one embodiment, the storing or retrieving operation of the data at the data overflow site according to the target insertion instruction includes:

[0015] In the case where the action type is a use type, detecting whether the current action instruction is the first action instruction in the current target continuous sequence; wherein the current target continuous sequence refers to a continuous instruction sequence constituted by the action instructions whose action type is a use type;

[0016] In the case that the current action instruction is the first action instruction in the current target continuous sequence, the data at the data overflow site is fetched according to the target insertion instruction.

[0017] In one embodiment, obtaining the working status of the current virtual register includes:

[0018] Acquire a queue of virtual registers to be processed; wherein the queue of virtual registers to be processed includes at least one virtual register;

[0019] Traversing the virtual registers in the queue of virtual registers to be processed one by one to obtain the working status of the current virtual registers;

[0020] Correspondingly, after performing the operation of storing or retrieving the data at the data overflow site according to the target insertion instruction, the method further includes:

[0021] Deleting the current virtual register;

[0022] The target virtual register is added to the queue of virtual registers to be processed.

[0023] In one embodiment, after traversing the virtual registers in the queue of virtual registers to be processed one by one to obtain the working status of the current virtual register, the method further includes:

[0024] When the current virtual register is in a to-be-allocated state, the current virtual register is allocated to a target physical register.

[0025] In one embodiment, after traversing the virtual registers in the queue of virtual registers to be processed one by one to obtain the working status of the current virtual register, the method further includes:

[0026] In the case that the current virtual register is in the allocation state to be evicted, releasing the allocation relationship of the existing virtual register in the target physical register;

[0027] Adding the existing virtual register to the queue of virtual registers to be processed;

[0028] The current virtual register is allocated to the target physical register.

[0029] In a second aspect, the present application further provides a register data overflow processing device, comprising:

[0030] An overflow point positioning module, used for obtaining the working state of the current virtual register, and determining the data overflow position corresponding to the current virtual register when the current virtual register is in a pending overflow state;

[0031] An instruction traversal module, used to sequentially extract action instructions corresponding to the current virtual register, construct a target virtual register according to the action instructions, and determine an action type of the action instructions;

[0032] An instruction selection module, used for selecting a target insertion instruction according to the action type; wherein the target insertion instruction is an internal register transfer instruction;

[0033] The overflow processing module is used to store or retrieve the data at the data overflow site according to the target insertion instruction.

[0034] In a third aspect, the present application further provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0035] Acquire the working state of the current virtual register, and when the current virtual register is in a pending overflow state, determine the data overflow position corresponding to the current virtual register;

[0036] Extracting action instructions corresponding to the current virtual register in sequence, constructing a target virtual register according to the action instructions, and determining an action type of the action instructions;

[0037] Selecting a target insertion instruction according to the action type; wherein the target insertion instruction is an internal register transfer instruction;

[0038] The target virtual register is used to replace the current virtual register as an operation object, and the data at the data overflow site is stored or retrieved according to the target insertion instruction.

[0039] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the following steps are implemented:

[0040] Acquire the working state of the current virtual register, and when the current virtual register is in a pending overflow state, determine the data overflow position corresponding to the current virtual register;

[0041] Extracting action instructions corresponding to the current virtual register in sequence, constructing a target virtual register according to the action instructions, and determining an action type of the action instructions;

[0042] Selecting a target insertion instruction according to the action type; wherein the target insertion instruction is an internal register transfer instruction;

[0043] The target virtual register is used to replace the current virtual register as an operation object, and the data at the data overflow site is stored or retrieved according to the target insertion instruction.

[0044] In a fifth aspect, the present application further provides a computer program product, including a computer program, which implements the following steps when executed by a processor:

[0045] Acquire the working state of the current virtual register, and when the current virtual register is in a pending overflow state, determine the data overflow position corresponding to the current virtual register;

[0046] Extracting action instructions corresponding to the current virtual register in sequence, constructing a target virtual register according to the action instructions, and determining an action type of the action instructions;

[0047] Selecting a target insertion instruction according to the action type; wherein the target insertion instruction is an internal register transfer instruction;

[0048] The target virtual register is used to replace the current virtual register as an operation object, and the data at the data overflow site is stored or retrieved according to the target insertion instruction.

[0049] The above register data overflow processing method, device, computer equipment, storage medium and computer program product, by obtaining the working state of the current virtual register, when the current virtual register is in the state to be overflowed, determine the data overflow site corresponding to the current virtual register, record the data overflow site when the data overflows, and provide a target for subsequent data storage and loading, so that the data storage and loading actions after the subsequent update of the register can be accurately located to the same register position. Next, extract the action instructions corresponding to the current virtual register in turn, construct the target virtual register according to the action instructions, and determine the action type of the action instruction, and then select the internal register transfer instruction as the target insertion instruction according to the action type. Since the internal register transfer instruction only performs data transmission between different registers inside the processor, it has the advantage of a short execution cycle and does not require data transfer between the register and the memory. Therefore, the target virtual register is used instead of the current virtual register as the operation object, and the data at the data overflow site is stored or retrieved according to the target insertion instruction. The internal register transfer instruction can be used to replace the storage and loading instructions in the related technology, thereby reducing the time cost brought by the register data overflow instruction and improving the program performance stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0051] Figure 1 An application environment diagram of a register data overflow processing method in an embodiment;

[0052] Figure 2 A schematic flow chart of a register data overflow processing method in one embodiment;

[0053] Figure 3 This is a flow chart of step S202 of a register data overflow processing method in one embodiment;

[0054] Figure 4 is a structural block diagram of a register data overflow processing device in one embodiment;

[0055] Figure 5 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0056] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0057] The register data overflow processing method provided in the embodiment of the present application can be applied to Figure 1 In the application environment shown. Among them, the data storage system 102 can be used to store program running data and intermediate data generated during the program running process. The server 104 can be used to control the instructions of data storage, data loading and other actions, so as to allocate the data to be allocated to the target location of the data storage system. The data storage system may include a physical register PhysReg, which may include a conventional register file (CRF) and a predicate register file (PRF). Among them, the server 104 can be implemented by an independent server or a server cluster composed of multiple servers.

[0058] In an exemplary embodiment, Figure 2 As shown, a register data overflow processing method is provided, which is applied to Figure 1 The server 104 in the example is used as an example to illustrate the method, which includes the following steps S202 to S208. Among them:

[0059] Step S202, obtaining the working state of the current virtual register, and when the current virtual register is in a pending overflow state, determining the data overflow position corresponding to the current virtual register.

[0060] Among them, the current virtual register is in a pending overflow state, which means that the current virtual register cannot be directly allocated to the target physical register, resulting in data overflow. In related technologies, external cache is usually used as a data temporary storage point, and STORE / RELOAD instructions are inserted to perform life cycle segmentation to solve the virtual register overflow problem.

[0061] Exemplarily, the server 104 can sequentially obtain the working states of multiple virtual registers during the allocation and mapping of virtual registers, thereby mapping the current virtual register to the physical register according to its working state, and determining that the current virtual register is in a pending overflow state when there is no available physical register. Further, taking the current virtual register mapped to the common register CRF as an example, when it is determined that the current virtual register is in a pending overflow state, the current CRF site is recorded as the data overflow site corresponding to the current virtual register.

[0062] Step S204 , extracting the action instructions corresponding to the current virtual register in sequence, constructing the target virtual register according to the action instructions, and determining the action type of the action instructions.

[0063] Among them, both the current virtual register and the target virtual register can be virtual registers of PRF (predicate register). The server 104 can insert the required instructions to perform life cycle segmentation according to the action instruction by using the ordinary register CRF instead of the external cache as a data temporary storage point, and build the target virtual register, thereby updating the current virtual register to the target virtual register.

[0064] Among them, the action type can include definition type (DEF) and use type (USE). The DEF instruction of the virtual register VReg is used to assign a value to the virtual register for the first time. At this action instruction point, VReg obtains a specific value, which can mark the state of VReg and trigger related storage operations; the USE instruction of the virtual register VReg is used to use the previously defined value of VReg. When each instruction needs to read the value of VReg, it will be marked as USE. The current value of VReg is required when executing the USE operation, for example, calculation or comparison can be performed.

[0065] Exemplarily, the server 104 may collect the DEF instructions or USE instructions of VReg and organize these instructions into an instruction queue, and then perform traversal processing on the instruction queue. Subsequently, the server 104 may take the instruction Inst from the instruction queue, generate a new PRF (predicate register) virtual register for the update of the current instruction, for use when updating the instruction, and record the new PRF virtual register as NewVReg. And push NewVReg into NewVReg-List. Specifically, Inst may be the DEF point or USE point of the virtual register VReg.

[0066] Step S206, selecting a target insertion instruction according to the action type.

[0067] Wherein, the target insertion instruction is an internal register transfer instruction, and the method can be applied to predicate register data.

[0068] Exemplarily, the server 104 may select a predicate register store instruction as the target insertion instruction when the action type is a definition type; and select a predicate register load instruction as the target insertion instruction when the action type is a use type.

[0069] Furthermore, the predicate register store instruction may be the PRF2CRF instruction; the predicate register load instruction may be the PRFFromCRF instruction. That is, CRF can be used as a temporary storage object, and the STORE action caused by the overflow is borne by the PRF2CRF instruction, and the RELOAD action caused by the overflow is borne by the PRFFromCRF instruction. Among them, the PRF2CRF instruction and the PRFFromCRF instruction belong to the internal register transfer instructions (Internal Register Transfer Instructions). Their function is to transfer data between registers (physical registers and ordinary registers) inside the processor, which is similar to moving data and does not involve operations on memory.

[0070] The STORE / RELOAD instructions in the related art belong to memory interaction instructions, which are used to interact with the memory and emphasize the data transfer process from registers to memory or from memory to registers. Therefore, since the internal register transfer instruction only transfers data between different registers within the processor, it has the advantage of a short execution cycle and does not require data transfer between registers and memory.

[0071] Step S208, using the target virtual register to replace the current virtual register as the operation object, and performing a storage or fetch operation on the data at the data overflow site according to the target insertion instruction.

[0072] Among them, for USE points, the total overflow operation of the related technology is to insert a RELOAD action before each USE point. However, due to the particularity of the predicate register, a series of continuous use type (USE) instructions often appear to form a PRF USE sequence, that is, there is no definition type instruction in this continuous PRF USE sequence, that is, there is no DEF point, and the PRF used is the same value. Therefore, in this case, it is only necessary to insert the corresponding instruction before the first USE point, and the subsequent USE points can reuse the loaded data.

[0073] Exemplarily, server 104 may detect whether the current action instruction is the first action instruction in the current target continuous sequence when the action type is a usage type; wherein the current target continuous sequence refers to a continuous instruction sequence constituted by action instructions whose action type is a usage type; when the current action instruction is the first action instruction in the current target continuous sequence, the data at the data overflow site is retrieved according to the target insertion instruction.

[0074] Furthermore, when the currently processed Inst is the DEF point of VReg, the server 104 can update Inst to make it DEF NewVReg, and then use NewVReg as the operation object to insert the PRF2CRF instruction into the CRF site determined in step S202, that is, the data overflow site; in view of the above-mentioned characteristics of PRF guard, when the server 104 detects such a continuous PRF USE sequence, it can only judge the first USE point in the PRF USE sequence as requiring the insertion of the PRFFromCRF action, and the subsequent USE instructions are judged as not requiring the insertion of the PRFFromCRF instruction, thereby performing storage or retrieval operations on the data at the data overflow site according to the target insertion instruction.

[0075] In the above register data overflow processing method, by obtaining the working state of the current virtual register, when the current virtual register is in the state to be overflowed, the data overflow site corresponding to the current virtual register is determined, and the data overflow site is recorded when the data overflows, which can provide a target for subsequent data storage and loading, so that the data storage and loading actions after the subsequent update of the register can be accurately located to the same register position. Next, the action instructions corresponding to the current virtual register are extracted in sequence, the target virtual register is constructed according to the action instructions, and the action type of the action instruction is determined, and then the internal register transfer instruction is selected as the target insertion instruction according to the action type. Since the internal register transfer instruction only performs data transmission between different registers inside the processor, it has the advantage of a short execution cycle and does not require data transfer between the register and the memory.

[0076] It optimizes the predicate register in the overflow scenario. When the virtual register to be overflowed is a predicate register, a common register (CRF) is used to replace the external memory as the data temporary storage point, and correspondingly, the common ALU instructions with short execution cycles (PRF2CRF instructions and PRFFromCRF instructions) are used to replace the STORE instructions and RELOAD instructions in the relevant overflow scheme to perform overflow operations. CRF is used instead of external memory to do PRF RA Spilling, and arithmetic operation instructions with short execution cycles are used to replace the Memory STORE / RELOAD instructions used in conventional RA Spilling, thereby reducing the RASpilling cost and improving the program running speed.

[0077] Therefore, the target virtual register is used instead of the current virtual register as the operation object, and the data at the data overflow site is stored or retrieved according to the target insertion instruction. The internal register transfer instruction can be used to replace the storage and loading instructions in the related technology, thereby reducing the time cost brought by the register data overflow instruction and improving the program performance stability.

[0078] In an exemplary embodiment, Figure 3 As shown, step S202 includes steps S302 to S304, and accordingly, step S208 may further include step S306. Among them:

[0079] Step S302, obtaining a queue of virtual registers to be processed.

[0080] The queue of virtual registers to be processed includes at least one virtual register. The queue of virtual registers to be processed may be a priority queue.

[0081] Exemplarily, the server 104 may sequentially dequeue a virtual register VReg according to the priority, and then perform a hierarchical attempt to allocate registers to the virtual register VReg in sequence.

[0082] Step S304, traverse the virtual registers in the queue of virtual registers to be processed one by one to obtain the working status of the current virtual registers.

[0083] Exemplarily, when the current virtual register is in a pending allocation state, the server 104 may allocate the current virtual register to the target physical register. The current virtual register being in a pending allocation state means that an available physical register PhysReg can be directly found at present, and it is recorded as allocating VReg to PhysReg, and this round of allocation ends, and VReg is successfully dequeued.

[0084] Exemplarily, if there is no available physical register, an attempt can be made to release the allocation relationship of a certain allocated PyhsReg, and the generated VReg-s can be re-queued to wait for the next round of allocation. In the case where the current virtual register is in the state of allocation to be evicted, the server 104 can release the allocation relationship of the existing virtual register in the target physical register; add the existing virtual register to the queue of virtual registers to be processed; and allocate the current virtual register to the target physical register.

[0085] Step S306, deleting the current virtual register and adding the target virtual register to a queue of virtual registers to be processed.

[0086] Exemplarily, when the instruction in the current virtual register has not been processed yet, the next instruction processing is entered. When the instructions in the current virtual register have been processed, it means that the DEF / USE of VReg has been updated to the DEF / USE of NewVReg generated in each round of traversal. At this time, VReg is an "unreferenced" virtual register and needs to be eliminated. Then the NewReg-List generated during the traversal process is re-entered into the priority queue, waiting for the next round of dequeueing and register allocation.

[0087] In another exemplary embodiment, the server 104 first obtains the queue of virtual registers to be processed, and traverses the virtual registers in the queue of virtual registers to be processed one by one to obtain the working status of the current virtual register. When the current virtual register is in the state to be allocated, the current virtual register is allocated to the target physical register; when the current virtual register is in the state to be allocated after eviction, the allocation relationship of the existing virtual register in the target physical register is released, the existing virtual register is added to the queue of virtual registers to be processed, and the current virtual register is allocated to the target physical register.

[0088] Next, when the current virtual register is in a pending overflow state, the server 104 determines the data overflow site corresponding to the current virtual register, extracts the action instructions corresponding to the current virtual register in sequence, constructs the target virtual register according to the action instructions, and determines the action type of the action instruction. When the action type is a definition type, the predicate register storage instruction is selected as the target insertion instruction; when the action type is a use type, the predicate register load instruction is selected as the target insertion instruction.

[0089] Subsequently, when the action type is a use type, detect whether the current action instruction is the first action instruction in the current target continuous sequence; wherein, the current target continuous sequence refers to a continuous instruction sequence constituted by action instructions whose action type is a use type, and when the current action instruction is the first action instruction in the current target continuous sequence, perform a fetch operation on the data at the data overflow site according to the target insertion instruction, and finally delete the current virtual register and re-add the target virtual register to be processed queue.

[0090] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0091] Based on the same inventive concept, the embodiment of the present application also provides a register data overflow processing device for implementing the register data overflow processing method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in the one or more register data overflow processing device embodiments provided below can refer to the limitations of the register data overflow processing method above, and will not be repeated here.

[0092] In an exemplary embodiment, Figure 4 As shown, a register data overflow processing device is provided, including: an overflow point positioning module 402, an instruction traversal module 404, an instruction selection module 406 and an overflow processing module 408, wherein:

[0093] The overflow point positioning module 402 is used to obtain the working state of the current virtual register, and when the current virtual register is in a pending overflow state, determine the data overflow point corresponding to the current virtual register;

[0094] The instruction traversal module 404 is used to sequentially extract the action instructions corresponding to the current virtual register, construct the target virtual register according to the action instructions, and determine the action type of the action instructions;

[0095] The instruction selection module 406 is used to select a target insertion instruction according to the action type; wherein the target insertion instruction is an internal register transfer instruction;

[0096] The overflow processing module 408 is used to store or retrieve data at the data overflow site according to the target insertion instruction.

[0097] In one embodiment, the method is applied to predicate register data; the action type includes a definition type and a use type; the instruction selection module 406 includes:

[0098] A first selection unit is used to select a predicate register store instruction as a target insertion instruction when the action type is a definition type;

[0099] The second selection unit is used to select a predicate register load instruction as a target insertion instruction when the action type is a use type.

[0100] In one embodiment, the overflow processing module 408 includes:

[0101] An instruction detection unit, used for detecting whether the current action instruction is the first action instruction in the current target continuous sequence when the action type is the use type; wherein the current target continuous sequence refers to a continuous instruction sequence composed of action instructions whose action type is the use type;

[0102] The instruction operation unit is used to fetch the data at the data overflow site according to the target insertion instruction when the current action instruction is the first action instruction in the current target continuous sequence.

[0103] In one embodiment, the overflow point location module 402 includes:

[0104] A queue acquisition unit, used for acquiring a queue of virtual registers to be processed; wherein the queue of virtual registers to be processed includes at least one virtual register;

[0105] A queue traversal unit, used for traversing the virtual registers in the queue of virtual registers to be processed one by one to obtain the working status of the current virtual registers;

[0106] Correspondingly, the device is also used to: delete the current virtual register; and add the target virtual register to the queue of virtual registers to be processed.

[0107] In one embodiment, the device further comprises:

[0108] The first processing unit is used to allocate the current virtual register to the target physical register when the current virtual register is in a to-be-allocated state.

[0109] In one embodiment, the device further comprises:

[0110] A second processing unit is used to release the allocation relationship of the existing virtual register in the target physical register when the current virtual register is in the allocation state to be evicted;

[0111] The queue updating unit is used to add the existing virtual register to the queue of virtual registers to be processed; and to allocate the current virtual register to the target physical register.

[0112] Each module in the register data overflow processing device can be implemented in whole or in part by software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module.

[0113] In an exemplary embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as shown in FIG. Figure 5As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. Among them, the processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a register data overflow processing method is implemented.

[0114] In an exemplary embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the following steps when executing the computer program: obtaining the working state of a current virtual register, and determining a data overflow site corresponding to the current virtual register when the current virtual register is in a pending overflow state; extracting action instructions corresponding to the current virtual register in sequence, constructing a target virtual register according to the action instructions, and determining an action type of the action instruction; selecting a target insertion instruction according to the action type; wherein the target insertion instruction is an internal register transfer instruction; using the target virtual register as an operation object instead of the current virtual register, and performing a storage or retrieval operation on the data overflow site according to the target insertion instruction.

[0115] In one embodiment, when the processor executes the computer program, the following steps are further implemented: when the action type is a definition type, a predicate register store instruction is selected as a target insertion instruction; when the action type is a use type, a predicate register load instruction is selected as a target insertion instruction.

[0116] In one embodiment, the processor also implements the following steps when executing a computer program: when the action type is a usage type, detecting whether the current action instruction is the first action instruction in the current target continuous sequence; wherein the current target continuous sequence refers to a continuous instruction sequence constituted by action instructions whose action type is the usage type; when the current action instruction is the first action instruction in the current target continuous sequence, performing a fetch operation on the data at the data overflow site according to the target insertion instruction.

[0117] In one embodiment, when the processor executes the computer program, the following steps are also implemented: obtaining a queue of virtual registers to be processed; wherein the queue of virtual registers to be processed includes at least one virtual register; traversing the virtual registers in the queue of virtual registers to be processed one by one to obtain the working status of the current virtual register; deleting the current virtual register; and adding the target virtual register to the queue of virtual registers to be processed.

[0118] In one embodiment, when the processor executes the computer program, the following steps are further implemented: when the current virtual register is in a to-be-allocated state, the current virtual register is allocated to the target physical register.

[0119] In one embodiment, when the processor executes the computer program, the following steps are also implemented: when the current virtual register is in the allocation state to be evicted, the allocation relationship of the existing virtual register in the target physical register is released; the existing virtual register is added to the queue of virtual registers to be processed; and the current virtual register is allocated to the target physical register.

[0120] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented: obtaining the working state of the current virtual register, and when the current virtual register is in a pending overflow state, determining the data overflow site corresponding to the current virtual register; extracting the action instructions corresponding to the current virtual register in sequence, constructing a target virtual register according to the action instructions, and determining the action type of the action instruction; selecting a target insertion instruction according to the action type; wherein the target insertion instruction is an internal register transfer instruction; using the target virtual register instead of the current virtual register as an operation object, and performing a storage or retrieval operation on the data at the data overflow site according to the target insertion instruction.

[0121] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: when the action type is a definition type, a predicate register store instruction is selected as a target insertion instruction; when the action type is a use type, a predicate register load instruction is selected as a target insertion instruction.

[0122] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: when the action type is a usage type, detecting whether the current action instruction is the first action instruction in the current target continuous sequence; wherein the current target continuous sequence refers to a continuous instruction sequence composed of action instructions whose action type is the usage type; when the current action instruction is the first action instruction in the current target continuous sequence, performing a fetch operation on the data at the data overflow site according to the target insertion instruction.

[0123] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: obtaining a queue of virtual registers to be processed; wherein the queue of virtual registers to be processed includes at least one virtual register; traversing the virtual registers in the queue of virtual registers to be processed one by one to obtain the working status of the current virtual register; deleting the current virtual register; and adding the target virtual register to the queue of virtual registers to be processed.

[0124] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: when the current virtual register is in a to-be-allocated state, the current virtual register is allocated to the target physical register.

[0125] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: when the current virtual register is in the allocation state to be evicted, the allocation relationship of the existing virtual register in the target physical register is released; the existing virtual register is added to the queue of virtual registers to be processed; and the current virtual register is allocated to the target physical register.

[0126] In one embodiment, a computer program product is provided, including a computer program, which implements the following steps when executed by a processor: obtaining the working state of a current virtual register, and determining a data overflow site corresponding to the current virtual register when the current virtual register is in a pending overflow state; extracting action instructions corresponding to the current virtual register in sequence, constructing a target virtual register according to the action instructions, and determining an action type of the action instruction; selecting a target insertion instruction according to the action type; wherein the target insertion instruction is an internal register transfer instruction; using the target virtual register instead of the current virtual register as an operation object, and performing a storage or retrieval operation on the data at the data overflow site according to the target insertion instruction.

[0127] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: when the action type is a definition type, a predicate register store instruction is selected as a target insertion instruction; when the action type is a use type, a predicate register load instruction is selected as a target insertion instruction.

[0128] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: when the action type is a usage type, detecting whether the current action instruction is the first action instruction in the current target continuous sequence; wherein the current target continuous sequence refers to a continuous instruction sequence composed of action instructions whose action type is the usage type; when the current action instruction is the first action instruction in the current target continuous sequence, performing a fetch operation on the data at the data overflow site according to the target insertion instruction.

[0129] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: obtaining a queue of virtual registers to be processed; wherein the queue of virtual registers to be processed includes at least one virtual register; traversing the virtual registers in the queue of virtual registers to be processed one by one to obtain the working status of the current virtual register; deleting the current virtual register; and adding the target virtual register to the queue of virtual registers to be processed.

[0130] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: when the current virtual register is in a to-be-allocated state, the current virtual register is allocated to the target physical register.

[0131] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: when the current virtual register is in the allocation state to be evicted, the allocation relationship of the existing virtual register in the target physical register is released; the existing virtual register is added to the queue of virtual registers to be processed; and the current virtual register is allocated to the target physical register.

[0132] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0133] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0134] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A register data overflow processing method, characterized in that: The method comprises: Acquire the working state of the current virtual register, and when the current virtual register is in a pending overflow state, determine the data overflow position corresponding to the current virtual register; Extracting action instructions corresponding to the current virtual register in sequence, constructing a target virtual register according to the action instructions, and determining an action type of the action instructions; Selecting a target insertion instruction according to the action type; wherein the target insertion instruction is an internal register transfer instruction; The target virtual register is used to replace the current virtual register as an operation object, and the data at the data overflow site is stored or retrieved according to the target insertion instruction.

2. The method according to claim 1, characterized in that The method is applied to predicate register data; the action type includes a definition type and a use type; and the step of selecting a target insertion instruction according to the action type includes: In case the action type is a definition type, selecting a predicate register store instruction as a target insertion instruction; In case the action type is a use type, a predicate register load instruction is selected as a target insertion instruction.

3. The method according to claim 2, characterized in that The storing or retrieving operation of the data at the data overflow site according to the target insertion instruction includes: In the case where the action type is a use type, detecting whether the current action instruction is the first action instruction in the current target continuous sequence; wherein the current target continuous sequence refers to a continuous instruction sequence constituted by the action instructions whose action type is a use type; In the case that the current action instruction is the first action instruction in the current target continuous sequence, the data at the data overflow site is fetched according to the target insertion instruction.

4. The method according to claim 1, characterized in that: The obtaining of the working status of the current virtual register comprises: Acquire a queue of virtual registers to be processed; wherein the queue of virtual registers to be processed includes at least one virtual register; Traversing the virtual registers in the queue of virtual registers to be processed one by one to obtain the working status of the current virtual registers; Correspondingly, after performing the operation of storing or retrieving the data at the data overflow site according to the target insertion instruction, the method further includes: Deleting the current virtual register; The target virtual register is added to the queue of virtual registers to be processed.

5. The method according to claim 4, characterized in that After traversing the virtual registers in the queue of virtual registers to be processed one by one to obtain the working status of the current virtual registers, the method further includes: When the current virtual register is in a to-be-allocated state, the current virtual register is allocated to a target physical register.

6. The method according to claim 4, characterized in that After traversing the virtual registers in the queue of virtual registers to be processed one by one to obtain the working status of the current virtual registers, the method further includes: In the case that the current virtual register is in the allocation state to be evicted, releasing the allocation relationship of the existing virtual register in the target physical register; Adding the existing virtual register to the queue of virtual registers to be processed; The current virtual register is allocated to the target physical register.

7. A register data overflow processing device, characterized in that: The device comprises: An overflow point positioning module, used for obtaining the working state of the current virtual register, and determining the data overflow position corresponding to the current virtual register when the current virtual register is in a pending overflow state; An instruction traversal module, used to sequentially extract action instructions corresponding to the current virtual register, construct a target virtual register according to the action instructions, and determine an action type of the action instructions; An instruction selection module, used for selecting a target insertion instruction according to the action type; wherein the target insertion instruction is an internal register transfer instruction; The overflow processing module is used to store or retrieve the data at the data overflow site according to the target insertion instruction.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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