Multi-core processor

Abstract

The invention discloses a multi-core processor, which is used for improving the accuracy degree of data prefetching and further improving the data access efficiency of the multi-core processor. The processor comprises a plurality of processing units, a prediction unit, a prefetching unit and a memory unit, any processing unit comprises a first data collector, and the first data collector is used for collecting first historical data of the processing unit; the first historical data comprises an instruction executed by the processing unit, a memory address accessed by the instruction and whether data of the memory address is hit in a cache; the prediction unit is used for analyzing first historical data of any processing unit in a past period of time to obtain a predicted access sequence of the processing unit to the memory unit in a future period of time; and the prefetching unit is used for prefetching data from the memory unit according to the predicted access sequence and transmitting the prefetched data to the processing unit.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a multi-core processor. Background Art

[0002] Multi-core processors are widely used in modern computing systems to enable parallel processing and improved performance. In particular, applications such as scientific computing, gaming, real-time data processing, and artificial intelligence benefit greatly from multi-core systems. Efficient data access and management are critical to maximizing the performance of multi-core systems, especially when dealing with high-performance computing tasks and AI workloads.

[0003] Data prefetching technology reduces data access latency and improves system response speed by loading data into the cache in advance. The existing hardware-based data prefetching method only pre-loads the memory access units that may be accessed in the future into the cache based on the current running data access information. The accuracy of data prefetching is not high. Hardware prefetching will retrieve a large amount of useless data, occupying memory access bandwidth and causing cache pollution problems.

[0004] Therefore, there is an urgent need for a solution to improve the accuracy of data prefetching, thereby improving the data access efficiency of multi-core processors. Summary of the invention

[0005] The present application provides a multi-core processor for improving the accuracy of data pre-fetching, thereby improving the data access efficiency of the multi-core processor.

[0006] The present application provides a multi-core processor, comprising a plurality of processing units, a prediction unit, a pre-fetch unit and a memory unit;

[0007] Any processing unit includes a first data collector, the first data collector is used to collect first historical data of the processing unit; the first historical data includes instructions executed by the processing unit, memory addresses accessed by the instructions, and whether the data at the memory address hits in the cache;

[0008] The prediction unit is used to analyze the first historical data of any processing unit in the past period of time to obtain a predicted access sequence of the processing unit to the memory unit in the future period of time;

[0009] The pre-fetch unit is used to pre-fetch data from the memory unit according to the predicted access sequence, and transmit the pre-fetched data to the processing unit.

[0010] In the above technical scheme, the prediction unit analyzes the execution instructions and data access rules of the processing unit, establishes the correlation between instructions and the correlation between the executed instructions and the memory addresses accessed by the instructions, and then can relatively accurately predict the predicted access sequence of the processing unit to the memory unit in the future. The prefetch unit prefetches the corresponding data to the processing unit according to the predicted access sequence, so that the processing unit can directly obtain the corresponding data from the cache of the processing unit when using the data, which can save the time of the processing unit to obtain data from the memory unit and improve the data access efficiency of the multi-core processor.

[0011] In one possible design, the prediction unit is specifically used to analyze the execution order between executed instructions in the first historical data of the processing unit over a period of time in the past, and the spatial locality and temporal locality of the memory addresses accessed by the executed instructions through a machine learning model.

[0012] In the above technical solution, the execution order between executed instructions, the spatial locality and temporal locality of the memory addresses accessed by the executed instructions are analyzed through a machine learning model to establish the correlation between instructions and the correlation between the executed instructions and the memory addresses accessed by the instructions. The machine learning model can fully explore the spatial and temporal connections and regularities between the instructions and the memory addresses accessed by the instructions in the executed access sequence, making the predicted access sequence of the processing unit to the memory unit in the future more accurate and reliable, and the machine learning model can quickly analyze and process a large number of historical access sequences, greatly improving the efficiency of data analysis and prediction.

[0013] In one possible design, the multi-core processor further includes a performance feedback unit;

[0014] The performance feedback unit is used to analyze the difference between the predicted access sequence and the actual access sequence, obtain a first analysis result and feed it back to the prediction unit;

[0015] The prediction unit is also used to optimize the machine learning model based on the first analysis result.

[0016] In the above technical solution, the performance feedback unit can obtain the accuracy of the current machine learning model prediction by analyzing the difference between the predicted access sequence and the actual access sequence. The machine learning model is optimized based on the analysis results of the performance feedback unit to improve the accuracy of the machine learning model prediction. The optimized and updated machine model is continuously iterated through the feedback loop to ensure the continuous enhancement of the data prefetching system performance.

[0017] In a possible design, the first data collector is further used to collect a first performance indicator of the processing unit;

[0018] The memory unit comprises a second data collector for collecting a second performance indicator of the memory unit;

[0019] The performance feedback unit is further configured to analyze a preset number of first performance indicators and / or second performance indicators, obtain a second analysis result, and feed it back to the prediction unit;

[0020] The prediction unit is also used to optimize the machine learning model based on the second analysis result.

[0021] In the above technical solution, the machine learning model is optimized based on the analysis results of the first performance indicator and / or the second performance indicator by the performance feedback unit, so as to improve the accuracy of the prediction of the machine learning model. The machine model after optimization and update is continuously iterated through the feedback loop, so as to continuously improve the accuracy of the prediction and the efficiency of the pre-fetching mechanism, and ensure the continuous enhancement of the performance of the data pre-fetching system.

[0022] In a possible design, the performance feedback unit is specifically used to set the priority of each processing unit according to the improvement degree of the preset number of first performance indicators and / or the improvement degree of the second performance indicator;

[0023] The pre-fetch unit is specifically used to pre-fetch data corresponding to the respective predicted access sequences from the memory unit for each processing unit in turn according to the priority of each processing unit.

[0024] In the above technical solution, the priorities of different processing units are set according to the degree of improvement of the performance indicators of the processing units and / or memory units. For the processing units with high priorities, the prediction unit prioritizes predicting their predicted access sequences, and the prefetch unit prioritizes prefetching the corresponding data according to the predicted access sequences, so as to reduce the bandwidth load and delay caused by the intensive access of the memory unit by multiple processing units.

[0025] In one possible design, the first historical data also includes a memory access mode indicated by the instruction.

[0026] In one possible design, the performance feedback unit is also used to replace the machine learning model suitable for the current memory access mode according to the degree of improvement of the first performance indicator and / or the degree of improvement of the second performance indicator and the current memory access mode.

[0027] In the above technical solution, the access rules of memory addresses in different types of memory access modes are different, and the applicable machine learning models are also different. In the embodiment of the present application, the machine learning model used can be adjusted according to the data access mode of the processing unit to improve the accuracy of predicting the access sequence and ensure the continuous enhancement of the performance of the data prefetching system.

[0028] In a possible design, the first performance indicator includes cache hit rate, branch prediction accuracy, instruction throughput, and prefetch success rate; the second performance indicator includes memory address access frequency, access latency, and bandwidth utilization.

[0029] In one possible design, the processing unit includes a central processing unit (CPU) and one or more of a graphics processing unit (GPU), a tensor processor, or an AI accelerator.

[0030] In one possible design, the prediction unit reuses the hardware structure of a graphics processor GPU or an AI accelerator to perform training and reasoning on a machine learning model.

[0031] In the above technical solution, the hardware structure used for training and reasoning of the machine learning model of the prediction unit is similar to the hardware structure of the image processor GPU or AI accelerator. Therefore, reusing the hardware structure of the graphics processor GPU or AI accelerator for training and reasoning of the machine learning model can save the hardware cost of the multi-core processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1 A schematic diagram of a multi-core processor provided in an embodiment of the present application Figure 1 ;

[0034] Figure 2 A schematic diagram of a multi-core processor provided in an embodiment of the present application Figure 2 ;

[0035] Figure 3 A schematic diagram of a multi-core processor provided in an embodiment of the present application Figure 3 . DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0037] In the embodiments of the present application, a plurality refers to two or more than two. The words "first", "second" and the like are only used for the purpose of distinguishing descriptions and cannot be understood as indicating or implying relative importance or order.

[0038] Figure 1 A schematic diagram of the structure of a multi-core processor provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the multi-core processor 100 includes a plurality of processing units 110, a prediction unit 120, a pre-fetch unit 130 and a memory unit 140. The processing unit 110 is connected to the prediction unit 120, the data pre-fetch unit 130 and the memory unit 140 respectively.

[0039] The processing unit 110 may include a central processing unit CPU and a graphics processing unit GPU, a tensor processing unit TPU or one or more of an AI accelerator. Any processing unit 110 includes a first data collector 111, and the first data collector 111 is used to collect the first historical data of the processing unit 110. The first historical data includes the instructions executed by the processing unit 110, the memory address accessed by the instruction, and whether the data of the memory address hits in the cache. Among them, in the embodiment of the present application, the data of the memory address is mainly counted whether it hits in the L1 cache inside the processing unit 110. It can also be counted according to specific needs. Whether the data of the memory address hits in the L1 cache inside the processing unit 110, and whether the data of the memory address hits in the L2 / L3 shared cache outside the processing unit 110. This application does not make specific limitations. The following takes the counting of whether the L1 cache hits as an example to describe the method of the embodiment of the present application.

[0040] The prediction unit 120 is connected to the processing unit 110 and the pre-fetch unit 130 respectively, and is used to analyze the first historical data of any processing unit 110 in the past period of time to obtain the predicted access sequence of the processing unit 110 to the memory unit 140 in the future period of time.

[0041] The pre-fetch unit 130 is connected to the prediction unit 120 and the memory unit 140 respectively, and is used to pre-fetch data from the memory unit 140 according to the predicted access sequence, and transmit the pre-fetched data to the processing unit 110 .

[0042] Specifically, after obtaining the predicted access sequence, the prediction unit 120 sends a control signal to the pre-fetch unit 130, the control signal including the memory address and the size of the address block, and the pre-fetch unit 130 obtains the corresponding data from the memory unit 140 according to the memory address and the size of the address block and transmits it to the corresponding processing unit 110. Specifically, the pre-fetch unit 120 transmits the pre-fetched data to the cache of the corresponding processing unit 110, so that the processing unit 110 can directly obtain the corresponding data from the cache when using the data.

[0043] In the above technical solution, the processing unit 110 usually repeatedly executes some fixed program segments when executing tasks, and the instructions included in these program segments, the order of instructions, and the memory addresses accessed by the instructions are relatively fixed. Based on this, the prediction unit 120 analyzes the execution instructions and data access rules of the processing unit 110, establishes the correlation between instructions, and the correlation between the executed instructions and the memory addresses accessed by the instructions, and then can relatively accurately predict the predicted access sequence of the processing unit 110 to the memory unit 140 in the future. The pre-fetch unit 130 pre-fetches the corresponding data to the processing unit 110 according to the predicted access sequence, so that the processing unit 110 can directly obtain the corresponding data from the cache of the processing unit 110 when using the data, which can save the time of the processing unit 110 obtaining data from the memory unit and improve the data access efficiency of the multi-core processor. For example, the processing unit often executes a certain program segment, and the program segment needs to use the data in the memory addresses 0x1000, 0x1004 and 0x1008. Then, this program segment is associated with the memory addresses 0x1000, 0x1004 and 0x1008 it accesses. When the processing unit executes to the entrance of this program segment again, it can be predicted that the memory addresses that the processing unit will access next are 0x1000, 0x1004 and 0x1008. The pre-fetch unit pre-fetches the data of the memory addresses 0x1000, 0x1004 and 0x1008 to the processing unit, so that the processing unit can directly obtain the corresponding data from the cache of the processing unit when executing the program segment. In a possible implementation, the prediction unit 120 analyzes the first historical data of any processing unit 110 in the past period of time, and is specifically used to analyze the execution order between the executed instructions in the first historical data of the processing unit 110 in the past period of time, and the spatial locality and temporal locality of the memory addresses accessed by the executed instructions, through a machine learning model.

[0044] Exemplarily, the analysis of the temporal locality of the accessed memory address may specifically analyze the time interval of the repeatedly accessed memory address. For example, the loop iteration algorithm accesses the same variable multiple times in a short period of time. For example, the access sequence of a certain processing unit 110 to the memory unit 140 within a period of time is A, B, C, D, X, Y, Z, A, B, C, D, X, Y, Z (quasi-loop structure). Then, the prediction unit 120 performs temporal locality analysis on the access sequence and can predict that the processing unit 110 will continue to access the memory units X, Y, Z after accessing the memory units A, B, C, D. Then, when the processing unit 110 accesses the memory units A, B, C, D, the prefetch unit 130 can prefetch the data of the memory units X, Y, Z into the cache of the processing unit 110, so as to save the time for the processing unit 110 to obtain the data of X, Y, Z from the memory unit 140 when the processing unit 110 needs to use the data of X, Y, Z next, thereby improving the cache hit rate and improving the data access efficiency.

[0045] Analyzing the spatial locality of the accessed memory addresses can specifically analyze the positional relationship between the accessed memory addresses and whether certain memory areas are accessed intensively. For example, in the memory sequential access mode, for example, the processing unit 110 accesses consecutive array elements X[0], X[1], X[2], X[3]..., then the prefetch unit 130 can prefetch data of adjacent modules (blocks that are not in the same cache line) into the cache of the processing unit; for another example, the processing unit 110 accesses elements in matrix operations such as X[0], X[8], X

[16] , X

[24] ..., the address span is large but regular and is very likely to be in different cache lines, then the prefetch unit 130 can prefetch the corresponding data into the cache of the processing unit 110 according to the interval regularity between the accessed elements, thereby improving data access efficiency.

[0046] In the embodiment of the present application, the execution order between the executed instructions of the processor unit 110 and the spatial locality and temporal locality of the memory addresses accessed by the executed instructions are analyzed by a machine learning model, so that the spatial and temporal connections and rules between the instructions and the memory addresses accessed by the instructions in the executed access sequence can be fully excavated, so that the predicted access sequence of the processing unit to the memory unit in the future is more accurate and reliable, and the machine learning model can quickly analyze and process a large number of historical access sequences, greatly improving the efficiency of data analysis and prediction. The machine learning model may include but is not limited to a recurrent neural network (RNN), a long short-term memory network (LSTM), a decision tree (Decision Tree) or a random forest (randomforest), etc., and different machine learning models can be adapted according to the complexity of the processor workload and system requirements. For example, the recurrent neural network RNN ​​can capture the time dependency in sequential data, and is suitable for predicting the predicted access sequence to the memory unit in the future based on the access sequence to the memory unit in the past period of time. The long short-term memory network LSTM can better learn the long-term dependency in the data. If the access sequence to the memory unit shows dependence over a long time interval, the long short-term memory network LSTM is suitable. Decision trees or random forests can handle categorical data and continuous data. When there is a nonlinear interaction between features such as cache hit / miss rate, access frequency and locality, the random forest algorithm can be selected. When training the machine learning model, first clean and organize the historical data of the processing unit (including the instructions executed by the processing unit, the memory address accessed by the instruction, and whether the data at the memory address hits in the cache) to make it suitable for the machine learning model. Depending on the selected machine learning model, the machine learning model is trained using supervised or reinforcement learning methods. For example, supervised learning labels based on whether prefetching a specific memory block will result in a cache hit (prefetch success) or a cache miss (prefetch failure) to maintain the effectiveness of the training results. Apply the trained machine model to real-time data to predict future data access sequences.

[0047] Figure 2 A schematic diagram of the structure of another multi-core processor provided in an embodiment of the present application is shown in FIG. Figure 2 As shown, the multi-core processor 100 further includes a performance feedback unit 150. The performance feedback unit 150 is connected to the data processing unit 110 and the prediction unit 120 respectively, and is used to analyze the difference between the predicted access sequence and the actual access sequence, obtain a first analysis result and feed it back to the prediction unit 120. The prediction unit 120 is also used to optimize the machine learning model based on the first analysis result.

[0048] The performance feedback unit 150 can obtain the accuracy of the current machine learning model prediction by analyzing the difference between the predicted access sequence and the actual access sequence. The machine learning model can be optimized based on the analysis results of the performance feedback unit, such as adjusting the parameters of the machine learning model, introducing additional performance indicators as features, or using more advanced algorithm models, which can improve the accuracy of the machine learning model prediction. The machine model after optimization and update is continuously iterated through the feedback loop, which can continuously improve the accuracy of the prediction and the efficiency of the prefetch mechanism, ensuring the continuous enhancement of the performance of the data prefetch system.

[0049] In a possible implementation, the first data collector 111 is also used to collect the first performance indicator of the processing unit 110; the first performance indicator may include cache hit rate, branch prediction accuracy, instruction throughput, and prefetch success rate, and the first performance indicator may be collected by the performance monitoring unit of the processing unit 110 itself. The cache hit rate represents the ratio of the number of successful data reads from the cache to the total number of reads; the branch prediction accuracy represents the accuracy of the branch path predicted by the machine learning model; the instruction throughput refers to the number of operations that the processing unit can complete in a unit of time; and the prefetch success rate represents the accuracy of the prefetch. Figure 3 The memory unit 140 includes a second data collector 141 for collecting a second performance indicator of the memory unit; the second performance indicator may include an access frequency, an access delay, and a bandwidth utilization rate of a memory address. The access frequency of a memory address represents the access frequency of a memory address within a certain period of time; the access delay represents the time required to obtain data from different memory levels; and the bandwidth utilization rate represents the amount of data transmitted between different memory levels and each processing unit.

[0050] The performance feedback unit 150 is also used to analyze a preset number of first performance indicators and / or second performance indicators, obtain a second analysis result and feed it back to the prediction unit 120; the prediction unit 120 is also used to optimize the machine learning model based on the second analysis result.

[0051] Specifically, the performance indicators that the multi-core processor pays more attention to during actual work can be collected, and the collected performance indicators are sent to the performance feedback unit at intervals. The performance feedback unit analyzes the changes in the pre-fetching of performance indicator data and feeds back the analysis results to the prediction unit, so that the prediction unit can optimize the machine learning model according to the analysis results to improve the accuracy of the prediction of the machine learning model. For example, the data collector of the memory unit collects the bandwidth usage of the multi-core processor during actual work, and the performance unit analyzes the bandwidth usage. If the bandwidth usage has a decreasing trend, the current data pre-fetching strategy may not be particularly matched with the currently executed program or processing scenario. Therefore, the machine learning model can be optimized based on the analysis results. Specifically, the machine learning model can be re-trained based on the historical data of the recent period of time, so that the data pre-fetching strategy obtained by the re-trained machine learning model is more suitable for the currently executed program or processing scenario. The machine model after the optimization and update is continuously iterated through the feedback loop, which can continuously improve the accuracy of the prediction and the efficiency of the pre-fetching mechanism, ensuring the continuous enhancement of the performance of the data pre-fetching system.

[0052] In a possible implementation, the performance feedback unit 150 is specifically used to set the priority of each processing unit 110 according to the degree of improvement of a preset number of first performance indicators and / or the degree of improvement of the second performance indicator; the prefetch unit 130 is specifically used to prefetch data corresponding to each predicted access sequence from the memory unit for each processing unit 110 in turn according to the priority of each processing unit 110. Among them, the first performance indicator may include cache hit rate, branch prediction accuracy, instruction throughput, prefetch success rate, etc.; the second performance indicator may include memory address access frequency, access delay, bandwidth utilization, etc. The degree of improvement can be the degree of improvement of the performance indicator using the current data prefetch strategy compared with not using the data prefetch strategy, or it can be the degree of improvement of the performance indicator using the current data prefetch strategy compared with using the data prefetch strategy in the previous time period. This application does not make specific limitations on this.

[0053] When multi-core multi-channel data needs to be pre-fetched at the same time, there may be a phenomenon that the predicted access sequence is correct but the pre-fetching of data lags behind the real-time task, resulting in a still low cache hit rate, and the effect of improving data access efficiency is not achieved. Therefore, the priority of different processing units can be set according to the degree of improvement of the performance indicators of the processing unit 110 and / or the memory unit 140. Exemplarily, the processing unit 110 is sorted according to the degree of improvement of the performance indicators of the processing unit and / or the memory unit after the pre-fetch strategy is used, for example, the processing units are sorted according to the degree of improvement of the processor cache hit rate, and / or the degree of improvement of the branch prediction accuracy, and / or the degree of improvement of the instruction throughput, and / or the degree of improvement of the pre-fetch success rate, and the processor with a higher degree of improvement is set to a higher priority. Or the processing units are sorted according to the degree of improvement of the access frequency of the memory address after the pre-fetch strategy is used, the degree of reduction of the access delay, and the degree of improvement of the bandwidth utilization rate. For the processing units with high priority, the prediction unit 120 preferentially predicts their predicted access sequences, and the pre-fetch unit 120 preferentially pre-fetches corresponding data according to the predicted access sequences, so as to reduce the bandwidth load and delay caused by the intensive access of the memory unit by multiple processing units 110.

[0054] Taking cache hit rate as an indicator for priority setting as an example, assuming that a multi-core processor has four processing units A, B, C and D, and the cache hit rates of the four processing units are collected respectively, if the performance feedback unit analyzes that the improvement of the cache hit rate of the four processing units after using the current data prefetching strategy is in the order of processing unit B>processing unit A>processing unit D>processing unit C, then it can be inferred that after using the current data prediction strategy, the performance improvement order of the four processing units is processing unit B>processing unit A>processing unit D>processing unit C, then the priority of processing unit B is set to be the highest, the prediction unit gives priority to predicting the predicted access sequence of processing unit B, and the prefetch unit also gives priority to prefetching the corresponding data according to the predicted access sequence of processing unit B, followed by processing unit A, processing unit D and processing unit C. Alternatively, the priority of the processing unit can also be determined by the comprehensive improvement of multiple performance indicators, for example, the priority of the processing unit can be determined by the comprehensive improvement of cache hit rate, instruction throughput and access delay. Specifically, the indicator for priority setting can be set according to actual needs.

[0055] In a possible implementation, the first historical data also includes a memory access mode indicated by the instruction. The memory access mode refers to the behavior and order of a program when accessing memory, and the memory access mode includes a sequential access mode, a span access mode, a random access mode, a linked list access mode, and the like.

[0056] The performance feedback unit is also used to replace the machine learning model suitable for the current memory access mode according to the degree of improvement of the first performance indicator and / or the degree of improvement of the second performance indicator and the current memory access mode.

[0057] Different types of memory access modes have different access rules for memory addresses, and different machine learning is applicable to different data characteristics, so different types of memory access modes are applicable to different machine learning models. In the embodiment of the present application, the machine learning model used can be adjusted according to the data access mode of the processing unit to improve the accuracy of the predicted access sequence and ensure the continuous enhancement of the performance of the data prefetching system. For example, the prediction effect is better when using the long short-term memory network LSTM in the sequential access mode or the span access mode. Alternatively, when the amount of data is small, the recurrent neural network RNN ​​can also be used for prediction. If the memory access mode is in the random access mode, the instability of spatial locality will make it difficult to predict the access sequence. Or the memory access mode is in the linked list access mode, such as traversing the linked list, the next memory access address depends only on the value stored in the current memory location such as Node->Node.next->Node.next, and the change of the dynamic address will also make it difficult to predict the access sequence. Then when the access mode is a random access mode or a linked list access mode, the machine learning model applicable to the current memory access mode can be replaced, such as a random forest algorithm model.

[0058] In a possible implementation, the prediction unit 120 may reuse the hardware structure of a graphics processor GPU or an AI accelerator to perform training and reasoning of a machine learning model.

[0059] The hardware structure used for training and reasoning of the machine learning model of the prediction unit 120 is similar to the hardware structure of the image processor GPU or AI accelerator, for example, both include structural units for data preprocessing and feature value extraction, structural units for model training, and parallel operation matrix structural units for model reasoning. Therefore, reusing the hardware structure of the graphics processor GPU or AI accelerator for training and reasoning of machine learning models can save the hardware cost of multi-core processors.

[0060] The present application provides a multi-core processor, wherein a prediction unit analyzes the execution instructions and data access rules of a processing unit, predicts the predicted access sequence of the processing unit to a memory unit in the future, and a pre-fetch unit pre-fetches corresponding data to the processing unit according to the predicted access sequence, so that the processing unit can directly obtain the corresponding data from the cache of the processing unit when using the data, which can save the time for the processing unit to obtain data from the memory unit and improve the data access efficiency of the multi-core processor. The feedback unit analyzes the performance indicators of the processing unit and the memory unit, optimizes the machine learning model, and can continuously improve the accuracy of the prediction and the efficiency of the pre-fetch mechanism, ensuring the continuous enhancement of the performance of the data pre-fetching system.

[0061] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0062] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A multi-core processor, characterized in that: including a plurality of processing units, a prediction unit, a pre-fetch unit and a memory unit; Any processing unit includes a first data collector, the first data collector is used to collect first historical data of the processing unit; the first historical data includes instructions executed by the processing unit, memory addresses accessed by the instructions, and whether the data at the memory address hits in the cache; The prediction unit is used to analyze the first historical data of any processing unit in the past period of time to obtain a predicted access sequence of the processing unit to the memory unit in the future period of time; The pre-fetch unit is used to pre-fetch data from the memory unit according to the predicted access sequence, and transmit the pre-fetched data to the processing unit.

2. The multi-core processor according to claim 1, characterized in that: The prediction unit is specifically used to analyze the execution order between executed instructions in the first historical data of the processing unit over a period of time in the past, and the spatial locality and temporal locality of the memory addresses accessed by the executed instructions through a machine learning model.

3. The multi-core processor according to claim 2, characterized in that: The multi-core processor also includes a performance feedback unit; The performance feedback unit is used to analyze the difference between the predicted access sequence and the actual access sequence, obtain a first analysis result and feed it back to the prediction unit; The prediction unit is also used to optimize the machine learning model based on the first analysis result.

4. The multi-core processor according to claim 2, characterized in that: The first data collector is also used to collect a first performance indicator of the processing unit; The memory unit comprises a second data collector for collecting a second performance indicator of the memory unit; The performance feedback unit is further configured to analyze a preset number of first performance indicators and / or second performance indicators, obtain a second analysis result, and feed it back to the prediction unit; The prediction unit is also used to optimize the machine learning model based on the second analysis result.

5. The multi-core processor according to claim 4, characterized in that: The performance feedback unit is specifically used to set the priority of each processing unit according to the improvement degree of the preset number of first performance indicators and / or the improvement degree of the second performance indicators; The pre-fetch unit is specifically used to pre-fetch data corresponding to the respective predicted access sequences from the memory unit for each processing unit in turn according to the priority of each processing unit.

6. The multi-core processor according to claim 1, characterized in that: The first historical data also includes a memory access mode indicated by the instruction.

7. The multi-core processor according to claim 6, characterized in that: The performance feedback unit is also used to replace the machine learning model suitable for the current memory access mode according to the degree of improvement of the first performance indicator and / or the degree of improvement of the second performance indicator and the current memory access mode.

8. The multi-core processor according to claim 4, characterized in that: The first performance indicators include cache hit rate, branch prediction accuracy, instruction throughput, and prefetch success rate; The second performance indicator includes memory address access frequency, access delay, and bandwidth usage.

9. The multi-core processor according to any one of claims 1 to 7, characterized in that: The processing unit includes a central processing unit (CPU) and a graphics processing unit (GPU), a tensor processor or an AI accelerator.

10. The multi-core processor according to claim 9, characterized in that: The prediction unit reuses the hardware structure of a graphics processing unit GPU or an AI accelerator to perform training and reasoning on a machine learning model.

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