Instruction operation method, electronic equipment and readable medium

Abstract

The invention provides an instruction running method, electronic equipment and a readable medium. The method comprises the steps that a processor detects a first instruction; the processor determines that a first entry exists in the branch prediction structure, a value bundle corresponding to the first entry is a first value bundle to which the first instruction belongs, a position field of the first entry is matched with a first position value in an instruction pointer of the first instruction, and the first position value indicates the position of the first instruction in the first value bundle to which the first instruction belongs; and skipping to a first address, wherein the first address is a target address corresponding to the first position value in the target address field of the first entry. In the embodiment of the invention, the branch prediction structure can record the position information of the branch instruction in the value beam to which the branch instruction belongs, and the branch prediction structure is used for carrying out independent jump information prediction on different branch instructions, so that the prediction precision can be improved.

Description

Technical Field

[0001] The present application relates to the field of computers, and in particular to an instruction execution method, an electronic device and a readable medium. Background Art

[0002] In modern computer architecture, branch instruction predictors are crucial to improving processor performance. Since the processor processes instructions sequentially, when encountering a branch instruction, the processor needs to predict the execution status of the branch (i.e., whether the branch instruction jumps, and which new address the program will jump to to continue execution) based on the branch instruction predictor in order to continue executing the next instruction in the pipeline. However, if the branch instruction predictor predicts incorrectly, the processor may need to flush the pipeline and reload the instruction, which will result in performance loss. Summary of the invention

[0003] The present application provides an instruction execution method, an electronic device and a readable medium.

[0004] In a first aspect, an embodiment of the present application provides an instruction execution method, which is applied to an electronic device, wherein a branch prediction structure is stored in a processor of the electronic device, wherein the branch prediction structure includes multiple entries, each entry corresponds to at least part of the branch instructions in a value bundle, and each entry includes a position field and a target address field. The position field includes a position value corresponding one-to-one to at least part of the branch instructions in the corresponding value bundle, and the target address field includes a target address corresponding one-to-one to at least part of the branch instructions in the corresponding value bundle, the position value indicates the position of the corresponding branch instruction in the value bundle to which it belongs, and the target address indicates the address to which the corresponding branch instruction jumps; and the method includes: a processor detects a first instruction; the processor determines that a first entry exists in the branch prediction structure, wherein the value bundle corresponding to the first entry is the first value bundle to which the first instruction belongs, the position field of the first entry matches the first position value in the instruction pointer of the first instruction, and the first position value indicates the position of the first instruction in the first value bundle to which it belongs; and jumps to a first address, which is a target address corresponding to the first position value in the target address field of the first entry.

[0005] The branch prediction structure may be a branch target buffer (BTB), and the execution pointer may be a program counter (PC) value. At least some of the branch instructions in the value bundle may be a branch instruction, or all of the branch instructions in the value bundle may be

[0006] That is, in the embodiment of the present application, the branch prediction structure can record the position information of the branch instruction in the value bundle to which it belongs, and can distinguish different branch instructions in the value bundle. By using the branch prediction structure to perform separate jump information predictions for different branch instructions, the prediction accuracy can be improved.

[0007] In a possible implementation of the first aspect above, each entry also includes a predicted execution field, the predicted execution field includes a jump count value corresponding one-to-one to at least part of the branch instructions in the corresponding value bundle, and the jump count value is used to indicate the number of historical jumps of the corresponding branch instruction; jumping to the first address includes: when the predicted execution field of the first entry indicates a branch instruction jump, jumping to the first address, wherein when the jump count value is greater than a threshold or the jump count value is a preset value, the predicted execution field indicates that the corresponding branch instruction jumps.

[0008] In a possible implementation of the first aspect above, the first position value and the first address are stored in a branch prediction structure when the processor historically detects that the first instruction jumps.

[0009] In a possible implementation of the first aspect above, each entry also includes a tag field and an index field, the tag field includes a tag value that corresponds one-to-one to the value bundle corresponding to the branch instruction, and each entry in the branch prediction structure corresponds to an index value, the tag value is the 1st to nth bits from high to low in the instruction pointer of the branch instruction, the index value is the n+1th to n+kth bits from high to low in the instruction pointer of the branch instruction, and the position value is the n+k+1th to n+k+mth bits from high to low in the instruction pointer of the branch instruction.

[0010] In a possible implementation of the first aspect, the processor stores the first address and the first position value in the branch prediction structure in the following manner: detecting that the first instruction jumps to the first address; corresponding to the existence of a second entry corresponding to the first value bundle in the branch prediction structure and the position field of the second entry including the first position value, updating the third address corresponding to the first position value in the target address field of the second entry to the first address to obtain the first entry; or corresponding to the existence of a second entry corresponding to the first value bundle in the branch prediction structure and the position field of the second entry not including the first position value, writing the first address into the target address field of the second entry and writing the first position value into the position field of the second entry to obtain the first entry; or corresponding to the absence of an entry corresponding to the first value bundle in the branch prediction structure, adding a first entry corresponding to the first value bundle in the branch prediction structure, writing the first address into the target address field of the first entry and writing the first position value into the position field of the first entry, wherein the tag field of the first entry is the 1st to the nth bits from high to low in the execution pointer of the first instruction, wherein the index value of the first entry is the n+1st to the n+kth bits from high to low in the execution pointer of the first instruction.

[0011] In a possible implementation of the first aspect above, the processor stores the first address and the first position value in the branch prediction structure in the following manner: detecting that the first instruction jumps to the first address; corresponding to the existence of a second entry corresponding to the first instruction in the branch prediction structure, and the position field of the second entry is the first position value, updating the third address corresponding to the first position value in the target address field of the second entry to the first address to obtain the first entry; or corresponding to the absence of an entry matching the first instruction in the branch prediction structure, adding the first entry corresponding to the first instruction to the branch prediction structure, writing the first address into the target address field of the first entry, writing the first position value into the position field of the first entry, the label field of the first entry is the 1st to nth bits from high to low in the execution pointer of the first instruction, wherein the index value of the first entry is the n+1st to n+kth bits from high to low in the execution pointer of the first instruction.

[0012] In a possible implementation of the first aspect above, the 1st to nth bits from high to low in the instruction pointer of the first instruction are the same as the first label value of the label field in the first entry, the n+1th to n+kth bits from high to low in the instruction pointer of the first instruction are the same as the first index value corresponding to the first entry, the n+k+1th to n+k+mth bits from high to low in the instruction pointer of the first instruction are the same as the first label value of the label field in the first entry, the index value is the n+1th to n+kth bits from high to low in the instruction pointer of the branch instruction, and the position value is the n+k+1th to n+k+mth bits from high to low in the instruction pointer of the branch instruction.

[0013] In a possible implementation of the first aspect, jumping to the first address includes: incrementing a jump count value in a predicted execution field of the first entry, and jumping to the first address.

[0014] In a second aspect, an embodiment of the present application provides an electronic device, comprising: a memory for storing instructions executed by one or more processors of the electronic device; and a processor, which is one of the processors of the electronic device, for executing instructions so that the electronic device implements the above-mentioned instruction execution method.

[0015] In a third aspect, an embodiment of the present application provides a readable medium, which contains instructions. When the instructions are executed by a processor of an electronic device, the electronic device implements the above-mentioned instruction execution method. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 According to an embodiment, a schematic diagram of the structure of a branch instruction predictor BHR and PHT is shown;

[0017] Figure 2 According to an embodiment, a schematic diagram of the structure of a BTB of a branch instruction predictor is shown;

[0018] Figure 3 According to an embodiment of the present application, a first structural schematic diagram of an incremental BTB is shown;

[0019] Figure 4 According to an embodiment of the present application, a second structural schematic diagram of an incremental BTB is shown;

[0020] Figure 5 A third structural schematic diagram of an incremental BTB is shown according to an embodiment of the present application;

[0021] Figure 6 A fourth structural schematic diagram of an incremental BTB is shown according to an embodiment of the present application;

[0022] Figure 7 According to an embodiment of the present application, an exemplary process of a method for updating a branch prediction structure is shown;

[0023] Figure 8 According to an embodiment of the present application, an exemplary process of an instruction execution method is shown;

[0024] Fig. 9 According to an embodiment of the present application, a structural schematic diagram of an electronic device 100 is shown. DETAILED DESCRIPTION

[0025] Illustrative embodiments of the present application include, but are not limited to, instruction execution methods, readable electronic devices, and readable media.

[0026] To facilitate understanding, the terms involved in the embodiments of the present application are introduced below.

[0027] Branch instruction: An instruction in a computer program that changes the flow of execution, telling the processor to jump to a different program address and continue execution when certain conditions are met.

[0028] Branch instruction predictor: A component of the CPU that predicts the outcome of a branch before executing the branch instruction. The branch instruction predictor includes at least a history register, a pattern history table (PHT), and a branch target buffer (BTB). The branch instruction predictor can be used in a variety of scenarios, such as deciding which pixels to render or omit in rendering, deciding which codec to use in video processing, predicting user actions in user interaction, and so on.

[0029] History register: For example, the history register may be a branch history register (BHR), which has an n-bit width and is used to record the execution results of the most recent n branch instructions in the program. Each bit of the branch history register corresponds to the execution of a branch instruction. If the branch instruction jumps, it is recorded as 1, and if the branch instruction does not jump, it is recorded as 0. It can be understood that a branch instruction jump means that after the branch instruction is executed, the processor jumps to a different program address to continue execution.

[0030] PHT: PHT is used to predict the direction of branch instructions, that is, to predict whether a branch will occur. It dynamically adjusts the prediction strategy by recording the historical behavior of branch instructions. PHT can capture the behavior patterns of branch instructions in the past and predict the future direction of branches based on these patterns. For example, if a branch instruction has caused a jump when executed multiple times in the past, PHT will record the jump history and predict that the branch will also jump in the future.

[0031] BTB: BTB is used to predict the target address of branch instructions, that is, if a branch occurs, which address the program should jump to to continue execution. BTB stores the addresses of branch instructions and their target addresses. When the processor detects a branch instruction, the processor can search the BTB to determine the target address of the branch instruction. Among them, the address of the branch instruction refers to the storage location of the branch instruction in the program; the target address of the branch instruction refers to the address to which the program will jump if the branch instruction is predicted or determined to be executed, that is, the address of the next branch instruction to be executed. For example, when a branch instruction is executed for the first time, the processor can store its target address and store it in the corresponding entry in the BTB.

[0032] According to the following Figure 1, an example is introduced of predicting whether a branch instruction jumps based on the historical branch instruction execution status before the branch instruction by using BHR and PHT.

[0033] Figure 1 According to an embodiment, a schematic diagram of the structure of a branch instruction predictor BHR and PHT is shown.

[0034] according to Figure 1 As shown, the BHR stores the execution status of the six most recent historical branch instructions, namely "111010". According to some embodiments, "1" in the BHR indicates that the branch has been taken, and "0" in the BRT indicates that the branch instruction has not been taken. For example, "111010" indicates that the execution status of the six most recent historical branch instructions are respectively taken, taken, taken, not taken, taken, and not taken.

[0035] What is stored in the PHT is the prediction information associated with the execution result of a specific historical branch instruction. Different prediction information can indicate whether the next branch instruction jumps or not. It can be understood that the next branch instruction is the 7th branch instruction after the last 6 historical branch instructions. According to some embodiments, the prediction information "00" and "01" in the PHT indicates that the branch instruction does not jump, and the prediction information "10" and "11" in the PHT indicates that the branch instruction jumps.

[0036] PHT will predict whether the branch instruction will jump or not according to the "111010" sequence in BHR. Among them, the most recent 6 branch instruction execution results "111010" stored in BHR can be used as an index to find the index corresponding to "111010" in PHT to obtain the prediction information of the next branch instruction. For example, refer to Figure 1 According to the historical branch instruction execution result "111010" in the BRT, the prediction information corresponding to the index "111010" in the PHT is "10", indicating that the prediction information corresponding to the next branch instruction is a jump.

[0037] However, in some processor designs, such as in superscalar processors, multiple instructions may be combined into a value bundle or a group of instructions. It is understood that a value bundle can be a collection of multiple instructions that the processor obtains from the instruction memory at one time, and these instructions can be processed in parallel or serially. Among them, in the program counter (PC) value of each instruction in the same value bundle, the label values ​​from the 1st to the nth bit from high to low are the same, the index values ​​from the n+1st to the n+kth bit are the same, and the values ​​of the n+k+1st bit and other bits thereafter are different. The instructions in the value bundle may include multiple types of instructions, such as branch instructions, arithmetic logic instructions, load / store instructions, data transfer instructions, etc. In some embodiments, before the processor executes the operation corresponding to the instruction, the processor may parse the instruction, obtain the opcode corresponding to the instruction, and determine the type of the instruction according to the opcode of the instruction. For example, the instruction is determined to be a branch instruction according to the opcode of the instruction.

[0038] In a superscalar processor, if Figure 1 The BHR and PHT in the BHR table are used to predict the jump of instructions. The units are value bundles, that is, each bit in the BHR corresponds to the execution status of a value bundle. As long as there is at least one branch instruction in the value bundle that jumps, the position corresponding to the value bundle will be updated to "1" in the BHR table; if the next execution is a value bundle, the prediction information of the PHT, such as Figure 1 The "10" in the PHT shown corresponds to a value bundle, and multiple branch instructions in the value bundle share one prediction information in the PHT. When executing any branch instruction in the value bundle at one time, the processor will use the same prediction information in the PHT to determine whether the branch instruction jumps. In other words, even if the instruction executed by the processor is an instruction with a historical execution status of no jump in the value bundle, if there are other instructions with a historical execution status of jump in the value bundle, then for the instruction with a historical execution status of no jump, the prediction information obtained according to the PHT is a jump, resulting in a prediction error.

[0039] In this way, if the value bundle includes multiple branch instructions, since the BHR or PHT cannot record the information of each branch instruction in the value bundle separately, when using PHT to perform branch prediction based on BHR, a single branch instruction in the value bundle cannot be predicted separately, thereby reducing the prediction accuracy. Figure 1 In addition to the situation shown, in some embodiments, during the operation of a superscalar processor, the target address prediction method using the BTB also has the problem of low accuracy.

[0040] According to the following Figure 2 , an example of predicting the target address of a branch instruction based on the PC value of the branch instruction through BTB is introduced.

[0041] It can be understood that for a branch instruction, if the prediction result through BHR and PHT is a jump, the target address predicted by BTB is the jump address of the branch instruction. Conversely, if the prediction result through BHR and PHT is no jump, the target address predicted by BTB is invalid.

[0042] Figure 2 According to an embodiment, a schematic diagram of the structure of a BTB of a branch instruction predictor is shown.

[0043] according to Figure 2 As shown, the BTB includes multiple entries, one entry corresponds to one index, and each entry includes a tag field, a valid field, and a target field. The tag field is used to provide a tag, the tag field records the high-bit characteristics of the program counter (PC) value of the branch instruction, the valid field is used to indicate whether the corresponding entry is valid, and the target field is used to record the jump address of the branch instruction.

[0044] According to some embodiments, the PC value serves as an instruction pointer for instruction execution, and can tell the processor which instruction to execute next. After each instruction is executed, the PC value can be updated and point to the address of the next instruction. For example, during the execution of a branch instruction, the PC value can be updated to point to the target address corresponding to the branch instruction, so as to instruct the processor to read and execute the next instruction from the target address.

[0045] For a branch instruction, the PC value may include N bits of data, which may be divided into a label value, an index value, and other values ​​by high and low bits, wherein the label value is n bits, the index value may include 4 bits, and the index value and the label value are used together to determine the entry corresponding to the branch instruction in the BTB. For example, refer to Figure 2 , the value of the highest n bits of the PC value can be a label value, and the value of the 4 bits after the highest n bits can be an index value. When a branch instruction is detected, the processor can use the index value as an index to find an entry in the BTB whose index field content is the same as the index value, and verify whether the tag field content in the entry is the same as the label value. If the same, the entry is determined to be the entry corresponding to the branch instruction. Then, when the valid field in the entry indicates that the entry is valid, the address in the target field in the entry is determined as the predicted target address of the branch instruction. For example, if the valid field is "1", it means it is valid, and if the valid field is "0", it means it is invalid. In the case where the valid field is "1", the address in the target field is determined as the target address.

[0046] However, since the PC values ​​of multiple instructions in a value bundle have the same index value, the same label value, and different other values. When one or more branch instructions in a value bundle have a jump, the BTB table will store the entry corresponding to the value bundle, and update the address of the target field to the address to which the last branch instruction in the one or more branch instructions jumps. When executing any branch instruction in the value bundle once, the processor will query the target address corresponding to the last branch instruction and jump to the target address. In other words, even if the instruction executed by the processor is a branch instruction other than the last branch instruction in the value bundle, the processor will jump to the target address corresponding to the last branch instruction, resulting in an erroneous jump.

[0047] When using Figure 2 In the BTB shown in the figure, multiple branch instructions of a value bundle correspond to the same entry in the BTB, that is, the multiple branch instructions correspond to the same target field. When only a part of the branch instructions in the value bundle jump to a certain address, the target address predicted for all branch instructions in the value bundle is the address. In this way, even if multiple branch instructions may jump to different target addresses, they share the same target address as the prediction result in the BTB, resulting in the inability to predict the target address of a single branch instruction, thereby reducing the overall branch prediction accuracy.

[0048] In order to solve the above problems, the present application embodiment proposes an instruction execution method, which can be applied to a superscalar processor, using the above Figure 2 The BTB table shown in the figure has a different branch prediction structure (or called incremental BTB). In the incremental BTB, each entry has Figure 2 In addition to the tag field, valid field, and target field of the BTB, the position (pos) field may also be included. The pos field is used to record the high m bits of other values ​​in the PC value of a branch instruction. For example, m can be 2. The value in the pos field indicates the position information of the branch instruction in the value bundle to which it belongs.

[0049] During the process of the processor executing instructions, when the processor detects a branch instruction, the entry corresponding to the branch instruction can be written or updated in the incremental BTB according to the PC value of the branch instruction. Among them, the PC value may include N-bit data, and the N-bit data can be divided into a label value, an index value, a position value and other values ​​by high and low bits, wherein the label value is n bits, the index value is k bits, and the position value is m bits. Based on the PC value of the branch instruction, the processor determines the entry with the same index field and index value as the entry corresponding to the branch instruction, and writes the label value into the tag field of the entry, and writes the position value into the pos field of the entry. Based on the above method, the incremental BTB can record the position information of the branch instruction in the value bundle to which it belongs, so that different branch instructions in the value bundle can be distinguished.

[0050] Based on the above-mentioned incremental BTB, when the processor detects a branch instruction to be executed, it can determine whether there is an entry corresponding to the reference information in the incremental BTB based on the reference information in the PC value of the branch instruction to be executed (including at least one of the index value, label value and position value); if so, the address in the target field in the entry is determined as the target address of the branch instruction to be executed, so as to jump to the target address to obtain and execute the next instruction.

[0051] According to some embodiments, the index value in the reference information may be used as an index to search for an entry in the incremental BTB whose index field content is the same as the index value, that is, to determine the entry corresponding to the index value.

[0052] According to some embodiments, the pos field includes a value. After determining the entry corresponding to the index value, the address of the target field can be determined as the target address of the branch instruction to be executed when the content of the tag field in the entry is the same as the tag value, the content of the pos field is the same as the position value, and the valid field indicates that the entry is valid.

[0053] According to some embodiments, the pos field may include one or more values, the target field may include one or more addresses, and the one or more values ​​of the pos field and the one or more addresses in the target field correspond one to one. After determining the entry corresponding to the index value, when the content of the tag field in the entry is the same as the tag value, the multiple values ​​of the pos field include the position value, and the valid field indicates that the entry is valid, the address corresponding to the position value in the multiple addresses in the target field can be determined as the target address of the branch instruction to be executed.

[0054] In this way, the BTB can distinguish multiple branch instructions in the same value bundle. For example, when a jump occurs during the execution of a value bundle, the processor can directly obtain the location information of the branch instruction that jumps, and confirm which branch instruction in the value bundle jumps based on the location information, and store the jump address in the target field of the entry of the branch instruction to ensure that the target address corresponds to the pos field in the entry. Moreover, even if multiple branch instructions jump to the same target address, the two branch instructions can be distinguished by the pos field, thereby improving the accuracy of branch prediction.

[0055] According to some embodiments, the incremental BTB also includes prediction information. For example, the prediction information may be Figure 1 The predicted information in the PHT table shown. It can be understood that the incremental BTB can be compared to Figure 2 A new predicted execution (predtaken) field is added to the BTB table in the incremental BTB. It can be understood that for an entry in the incremental BTB, if the pred taken field indicates that the branch instruction corresponding to the entry does not jump, the processor does not jump to the target address under the target field. In this way, a prediction of whether to jump can be made based on the incremental BTB. Since the prediction does not need to be based on the execution status of the historical branch instructions, there is no need to use the PHT, thereby saving storage space.

[0056] According to an example, the pred taken field may be a jump count value, and when the branch instruction corresponding to the entry jumps once, the jump count value is increased by 1. Exemplarily, the jump count value may be represented in binary, wherein the jump count values ​​"00" and "01" indicate that the branch instruction does not jump, and the jump count values ​​"10" and "11" indicate that the branch instruction jumps.

[0057] According to some embodiments, the pred taken field includes a value. After determining the entry corresponding to the index value, it can be determined whether the branch instruction to be executed jumps according to the content of the pred taken field when the content of the tag field in the entry is the same as the tag value, the content of the pos field is the same as the position value, and the valid field indicates that the entry is valid.

[0058] According to some embodiments, the pos field may include one or more values, the pred taken field may include one or more jump count values, and the value of the pos field and the jump count value of the pred taken field correspond one to one. After determining the entry corresponding to the index value, when the content of the tag field in the entry is the same as the tag value, the multiple values ​​of the pos field include a position value, and the valid field indicates that the entry is valid, it is determined whether the branch instruction to be executed jumps according to the content of the pred taken field.

[0059] The following is based on Figure 3-Figure 6 An incremental BTB in an instruction execution method provided in an embodiment of the present application is introduced.

[0060] Figure 3 According to an embodiment of the present application, a first structural schematic diagram of an incremental BTB is shown.

[0061] Understandably, Figure 3-Figure 6 The PC value shown in is the PC value of the branch instruction to be executed. In the embodiment of the present application, the PC value may include 32 bits of data in total. It should be noted that the embodiment of the present application does not limit the number of bits of the PC value.

[0062] like Figure 3 As shown, the incremental BTB includes 2^k entries, where the index of the entries is 0 to 2^k-1. Exemplarily, the value of index corresponds to the index value in the PC value, that is, the value of the n+1th to n+kth bits in the PC value from high to low. Exemplarily, k can be 5. The embodiment of the present application does not limit the value of k.

[0063] The incremental BTB includes a tag field, a valid field, a target field, and a pos field.

[0064] The tag field of the incremental BTB corresponds to the tag value in the PC value, that is, the values ​​of the 1st to nth bits in the PC value from high to low. Exemplarily, n can be 8, and the embodiment of the present application does not limit the value of n.

[0065] The valid field of the incremental BTB is used to indicate whether the entry is valid. For example, if valid is "1", it indicates that the entry is valid, and if valid is "0", it indicates that the entry is invalid.

[0066] The target field of the incremental BTB includes the target address of the branch instruction corresponding to the entry, that is, the address to which the processor jumps when executing the branch instruction.

[0067] The pos field of the incremental BTB is used to indicate the position of the branch instruction corresponding to the entry in the instruction bundle, that is, the value of the n+k+1th to n+k+2th bits in the PC value from high to low. For example, if the branch instruction is the i-th instruction among the four instructions in the instruction bundle, the pos field of the entry corresponding to the branch instruction is the binary representation of i.

[0068] According to an embodiment of the present application, the incremental BTB includes a pos field, wherein the pos field is written with the position of the branch instruction in the value bundle to which it belongs, so that each entry corresponds to each branch instruction in the value bundle, thereby being able to store the predicted result for a single branch instruction.

[0069] exist Figure 3 Based on the incremental BTB shown in the figure, the target field and the pos field can also include one or more contents. Figure 4 Introducing another incremental BTB in which the target field may include at least one address and the pos field may include at least one position.

[0070] Figure 4 According to an embodiment of the present application, a second structural diagram of an incremental BTB is shown. It can be understood that Figure 4 The PC value shown in is the PC value of the branch instruction to be executed.

[0071] like Figure 4 As shown, the incremental BTB includes 2^k entries, where the index of the entries is 0 to 2^k-1. Exemplarily, the value of index corresponds to the index value in the PC value, that is, the value of the n+1th to the n+kth bit in the PC value from high to low.

[0072] The incremental BTB includes a tag field, a valid field, a target field, and a pos field.

[0073] The tag field of the incremental BTB corresponds to the tag value in the PC value, that is, the values ​​of the 1st to the nth bits in the PC value from high to low.

[0074] The valid field of the incremental BTB is used to indicate whether the entry is valid. For example, if valid is "1", it indicates that the entry is valid, and if valid is "0", it indicates that the entry is invalid.

[0075] The target field of the incremental BTB includes the target address of the branch instruction corresponding to the entry, that is, the address to which the processor jumps when executing the branch instruction.

[0076] like Figure 4 As shown, the target field may include one or more addresses. For example, taking the entry with index 2^k-1 as an example, the target includes three target addresses e, f, and g, which correspond to each of the three branch instructions in the same instruction bundle.

[0077] The pos field of the incremental BTB is used to indicate the position of the branch instruction corresponding to the entry in the instruction bundle, that is, the value of the n+k+1th to n+k+2th bits in the PC value from high to low. For example, if the branch instruction is the i-th instruction among the four instructions in the instruction bundle, the pos field of the entry corresponding to the branch instruction is the binary representation of i.

[0078] like Figure 4As shown, the pos field may include one or more positions. For example, taking the entry with index 2^k-1 as an example, the pos field includes three positions of "00", "01", and "11", which correspond to each of the three branch instructions in the same instruction bundle. Among them, "00" indicates that the branch instruction is the first instruction in the value bundle, "01" indicates that the branch instruction is the second instruction in the value bundle, and "11" indicates that the branch instruction is the fourth instruction in the value bundle. It can be understood that the position in the pos field corresponds to the address in the target field one by one. For example, the target address of the branch instruction corresponding to the position "00" in the pos field is "e", the target address of the branch instruction corresponding to the position "01" in the pos field is "f", and the target address of the branch instruction corresponding to the position "11" in the pos field is "g".

[0079] According to an embodiment of the present application, multiple information is written into the pos field and the target field of the incremental BTB respectively, which can reduce the number of entries in the incremental BTB and save storage space.

[0080] exist Figure 3 Based on the incremental BTB shown in FIG. 1 , the incremental BTB may further include a pred taken field, wherein the pred taken field includes a jump count value, which is used to indicate whether the branch instruction jumps. Figure 5 An incremental BTB including a predtaken field is introduced.

[0081] Figure 5 According to an embodiment of the present application, a third structural schematic diagram of an incremental BTB is shown.

[0082] like Figure 5 As shown, the incremental BTB includes 2^k entries, where the index of the entries is 0 to 2^k-1. Exemplarily, the value of index corresponds to the index value in the PC value, that is, the value of the n+1th to n+kth bits in the PC value from high to low. Exemplarily, k can be 5. The embodiment of the present application does not limit the value of k.

[0083] The incremental BTB includes the tag field, valid field, target field, pos field and pred taken field.

[0084] The tag field of the incremental BTB corresponds to the tag value in the PC value, that is, the values ​​of the 1st to nth bits in the PC value from high to low. Exemplarily, n can be 8, and the embodiment of the present application does not limit the value of n.

[0085] The valid field of the incremental BTB is used to indicate whether the entry is valid. For example, if valid is "1", it indicates that the entry is valid, and if valid is "0", it indicates that the entry is invalid.

[0086] The target field of the incremental BTB includes the target address of the branch instruction corresponding to the entry, that is, the address to which the processor jumps when executing the branch instruction.

[0087] The pos field of the incremental BTB is used to indicate the position of the branch instruction corresponding to the entry in the instruction bundle, that is, the value of the n+k+1th to n+k+2th bits in the PC value from high to low. For example, if the branch instruction is the i-th instruction among the four instructions in the instruction bundle, the pos field of the entry corresponding to the branch instruction is the binary representation of i.

[0088] The pred taken of the incremental BTB includes a jump count value. It is understood that if the branch instruction jumps once, the count value in the pred taken field of the entry corresponding to the branch instruction is adjusted by one. According to some embodiments, if the jump count value is "00" and "01", it means that the branch instruction does not jump, and if the jump count value is "10" and "11", it means that the branch instruction jumps.

[0089] According to the embodiment of the present application, the incremental BTB includes a pre taken field, that is, the incremental BTB is Figure 2 The BTB shown is based on the information in the PHT, and the content used to predict whether the branch instruction jumps is added. Compared with using the PHT and BTB separately, storage resources are saved.

[0090] exist Figure 5 Based on the incremental BTB shown in FIG. 1 , the pred taken field, the target field, and the pos field may also include one or more contents. Figure 6 Another incremental BTB is introduced, wherein the pred taken field may include at least one jump count value, the target field may include at least one address, and the pos field may include at least one position.

[0091] Figure 6 According to an embodiment of the present application, a fourth structural schematic diagram of an incremental BTB is shown.

[0092] like Figure 6 As shown, the incremental BTB includes 2^k entries, where the index of the entries is 0 to 2^k-1. Exemplarily, the value of index corresponds to the index value in the PC value, that is, the value of the n+1th to the n+kth bit in the PC value from high to low.

[0093] The incremental BTB includes the tag field, valid field, target field, pos field and pred taken field.

[0094] The tag field of the incremental BTB corresponds to the tag value in the PC value, that is, the values ​​of the 1st to the nth bits in the PC value from high to low.

[0095] The valid field of the incremental BTB is used to indicate whether the entry is valid. For example, if valid is "1", it indicates that the entry is valid, and if valid is "0", it indicates that the entry is invalid.

[0096] The target field of the incremental BTB includes the target address of the branch instruction corresponding to the entry, that is, the address to which the processor jumps when executing the branch instruction.

[0097] like Figure 6 As shown, the target field may include one or more addresses. For example, taking the entry with index 2^k-1 as an example, the target includes three target addresses e, f, and g, which correspond to each of the three branch instructions in the same instruction bundle.

[0098] The pos field of the incremental BTB is used to indicate the position of the branch instruction corresponding to the entry in the instruction bundle, that is, the value of the n+k+1th to n+k+2th bits in the PC value from high to low. For example, if the branch instruction is the i-th instruction among the four instructions in the instruction bundle, the pos field of the entry corresponding to the branch instruction is the binary representation of i.

[0099] like Figure 4 As shown, the pos field may include one or more positions. For example, taking the entry with index 2^k-1 as an example, the pos field includes three positions of "00", "01", and "11", which correspond to each of the three branch instructions in the same instruction bundle. Among them, "00" indicates that the branch instruction is the first instruction in the value bundle, "01" indicates that the branch instruction is the second instruction in the value bundle, and "11" indicates that the branch instruction is the fourth instruction in the value bundle. It can be understood that the position in the pos field corresponds to the address in the target field one by one. For example, the target address of the branch instruction corresponding to the position "00" in the pos field is "e", the target address of the branch instruction corresponding to the position "01" in the pos field is "f", and the target address of the branch instruction corresponding to the position "11" in the pos field is "g".

[0100] The pred taken of the incremental BTB includes a jump count value. It is understood that if the branch instruction jumps once, the count value in the pred taken field of the entry corresponding to the branch instruction is adjusted by one. According to some embodiments, if the jump count value is "00" and "01", it means that the branch instruction does not jump, and if the jump count value is "10" and "11", it means that the branch instruction jumps.

[0101] like Figure 6As shown, the pred taken field may include one or more jump count values. For example, taking the entry with index 2^k-1 as an example, the pred taken field includes three jump count values ​​of "00", "00" and "11", which correspond to each of the three branch instructions in the same instruction bundle. It can be understood that the position in the pos field corresponds to the address in the target field one-to-one. For example, the jump count value of the branch instruction corresponding to the position "00" in the pos field is "00", indicating that the branch instruction does not jump; the jump count value of the branch instruction corresponding to the position "01" in the pos field is "00", indicating that the branch instruction does not jump; the jump count value of the branch instruction corresponding to the position "11" in the pos field is "11", indicating that the branch instruction jumps; accordingly, the target address of the branch instruction corresponding to the position "11" in the target field is "g".

[0102] According to an embodiment of the present application, multiple information are written into the pos field, target field and pred taken field of the incremental BTB respectively, which can reduce the number of entries in the incremental BTB and save storage space.

[0103] The following is based on Figure 7 , combined with the above Figure 3-Figure 6 , introduces an instruction execution method of an embodiment of the present application. Among them, when a branch instruction jump is detected, the processor can write information to the incremental BTB to update the content corresponding to the branch instruction in the incremental BTB, so that the processor can subsequently use the incremental BTB to accurately predict the jump information of more branch instructions, such as predicting whether the instruction jumps and the target address to jump to.

[0104] Figure 7 According to an embodiment of the present application, an exemplary process of a method for updating a branch prediction structure is shown. Figure 7 As shown, the exemplary process includes the following steps.

[0105] S101: Detecting that the first instruction being executed jumps.

[0106] According to some embodiments, the processor may monitor the execution status of the instruction in the program to determine whether it jumps, for example, when executing the instruction or after executing the instruction, the program jumps to a new address to continue execution. For example, the processor parses the opcode of the instruction, determines that the instruction is a branch instruction according to the opcode, and determines that the instruction jumps, that is, the processor detects that the branch instruction jumps.

[0107] S102: Store information of the first instruction in a branch prediction structure.

[0108] When the processor detects that a first instruction jumps during the execution of an instruction, it can be determined that the instruction is a branch instruction.

[0109] According to some embodiments, the branch prediction structure is Figure 3-Figure 6 The incremental BTB shown. The information of the first instruction stored may include at least one of the target address of the first instruction jump, the jump count value, and the position information. After detecting that the first instruction jumps, the information of the first instruction may be written or updated into the incremental BTB.

[0110] It can be understood that in each entry of the incremental BTB, the index value, label value, and position value of the instruction pointer of the branch instruction corresponding to each entry are respectively the same as the index, tag field, and pos field contents of the entry in the incremental BTB.

[0111] As an example, each entry in the incremental BTB corresponds to a branch instruction. Based on the following S1021A or S1022A, a first entry corresponding to the first instruction can be added to the incremental BTB, or the first entry corresponding to the first instruction in the incremental BTB can be updated.

[0112] S1021A: There is a second entry corresponding to the first instruction in the corresponding incremental BTB, and the second entry is updated to the first entry.

[0113] According to some embodiments, if there is a second entry corresponding to the first instruction in the incremental BTB, the target field in the entry of the first instruction can be updated to update the other addresses in the target field to the first address to which the first instruction jumps, and the updated second entry is used as the first entry. The pos field of the second entry is the first position value in the PC value of the first instruction, the index of the second entry is the first index value in the PC value of the first instruction, and the tag field of the second entry is the first tag value in the PC value of the first instruction.

[0114] When the first instruction jump corresponding to the second entry is detected, the target address to be jumped to can be updated to the target field of the entry. Figure 3 or Figure 5, taking the second entry corresponding to the first instruction as the entry with index 0 as an example, after the first instruction corresponding to the entry jumps, the target address "target0" is updated to the target field. Among them, the values ​​of the first instruction's PC value from the 1st to the nth bit from high to low are the first tag value, and are equal to "tag0" of the tag field of the entry; the values ​​of the first instruction's PC value from the n+1st to the n+kth bit from high to low are the first index value, and are equal to "0"; the values ​​of the first instruction's PC value from the n+k+1st to the n+k+2th bit from high to low are the first position value, and are equal to "00" in the pos field, indicating that the first instruction is the first instruction in the value bundle.

[0115] According to some embodiments, after the target field of the second entry corresponding to the first instruction is updated, the valid field of the second entry may also be updated to "1" so that the value of the valid field indicates that the entry is valid.

[0116] In some embodiments, the information of the first instruction stored also includes a jump count value, and the incremental BTB also includes a pred taken field for indicating whether the first instruction jumps. In this embodiment, the jump count value in the pred taken field in the second entry corresponding to the first instruction can also be incremented, such as adding one to the jump count value.

[0117] Optionally, the jump count value of the pred taken field stops increasing when it reaches a threshold. For example, the threshold may be 3. When the first instruction jump is detected, the jump count value of the pred taken field of the entry corresponding to the first instruction may be increased by one until the threshold 3 is reached, that is, the binary representation "11" is reached. For example, refer to Figure 5 If the first instruction corresponds to the entry with index 0, after the first instruction jumps, the jump count value in the pred taken field is already "11", so the value is no longer increased. The embodiment of the present application does not limit the threshold.

[0118] S1022A: If there is no entry corresponding to the first instruction in the corresponding incremental BTB, a first entry corresponding to the first instruction is added to the incremental BTB.

[0119] According to some embodiments, if there is no entry corresponding to the first instruction in the incremental BTB, a new first entry can be added in the incremental BTB, the first index value is the index of the first entry, the first label value is written into the tag field of the first entry, the first position value is written into the pos field of the first entry, and the first address to which the first instruction jumps is written into the target field in the first entry.

[0120] For example, refer to Figure 3 or Figure 5 , the following takes the entry corresponding to the first instruction as an example of the entry with index 0. Specifically, the index values ​​of the n+1th to n+kth bits of the PC value of the first instruction from high to low are 0. When the first instruction jump is detected for the first time, Figure 3 or Figure 5 The first entry, i.e., the entry with index 0, is added to the incremental BTB shown, and the tag values ​​"tag0" from the 1st to the nth bits of the PC value of the first instruction from high to low are written into the tag field of the entry; the position values ​​"00" from the n+k+1 to n+k+2 bits of the PC value of the first instruction from high to low are written into the pos field; and the first address "target0" to which the first instruction jumps is written into the target field.

[0121] According to some embodiments, after writing the first address to the target field of the entry corresponding to the first instruction, the valid field of the first entry may also be updated to "1" so that the value of the valid field indicates that the entry is valid.

[0122] In some embodiments, the information of the first instruction stored also includes a jump count value, and the incremental BTB also includes a pred taken field for indicating whether the branch instruction jumps. In this embodiment, the initial jump count value can also be written into the pred taken field. For example, after adding the first entry in the incremental BTB, "01" is written into the pred taken field of the first entry.

[0123] As another example, each entry in the incremental BTB corresponds to a value bundle, or corresponds to at least one branch instruction in a value bundle. Based on the following S1021B or S1022B, a first entry corresponding to the first value bundle to which the first instruction belongs may be added to the incremental BTB, or a first entry corresponding to the first value bundle to which the first instruction belongs in the incremental BTB may be updated.

[0124] S1021B: If there is a second entry corresponding to the first value bundle in the corresponding incremental BTB, the second entry is updated to the first entry.

[0125] According to some embodiments, when a first instruction jump is detected, the first address of the first instruction jump can be updated to the target field of the second entry corresponding to the first value bundle according to the position of the first instruction in the value bundle to which it belongs, so as to update the second entry to the first entry. That is, the updated second entry can be determined as the first entry.

[0126] For example, refer to Figure 4 or Figure 6, the following is explained by taking the case where the second entry corresponding to the first value bundle is the entry with index 2^k-1, and the first position value in the PC value of the first instruction is "11" as an example.

[0127] Specifically, the values ​​of the 1st to nth bits of the PC value of the first instruction from high to low are the first tag values, and are equal to "tag(2^k-1)" of the tag field of the second entry; the values ​​of the n+1th to n+kth bits of the PC value of the first instruction from high to low are the first index values, and are equal to "2^k-1"; the values ​​of the n+k+1th to n+k+2th bits of the PC value of the first instruction from high to low are the first position values, and are equal to "11" in the pos field, indicating that the first instruction is the 4th instruction in the first value bundle.

[0128] It can be understood that in the second entry, the pos field includes "00", "01" and "11", three branch instructions, corresponding to the first, second and fourth instructions in the first value bundle, respectively.

[0129] Two methods of updating the entry with index 2^k-1 in S1021B are introduced below.

[0130] Exemplarily, if the pos field of the second entry includes the first position value of the PC value of the first instruction, the address can be updated. For example, in the entry with index 2^k-1, since the position value "11" of the first instruction is the third value in the pos field, after the fourth instruction corresponding to "11" jumps, the third address of the target field can be updated to "g".

[0131] Exemplarily, if the pos field of the second entry does not include the first position value of the PC value of the first instruction, the first position value may be written into the second entry, and the first address may be written into the second entry. For example, in the entry with index 2^k-1, if the position value "11" of the first instruction does not exist in the pos field, "11" may be written into the pos field, and the first address "g" may be written into the target field.

[0132] It can be understood that the position of the first address in the target field corresponds to the position of the first position value in the pos field, such as both are 3 in the above example.

[0133] In some embodiments, the information of the first instruction stored also includes a jump count value, and the incremental BTB also includes a pred taken field for indicating whether the first instruction jumps. In this embodiment, the jump count value corresponding to the position in the pred taken field can also be incremented according to the position of the first instruction in the first value bundle to which it belongs, such as adding one to the jump count value.

[0134] Optionally, the jump count value of the pred taken field stops increasing when it reaches a threshold. For example, the threshold may be 3. When the first instruction jump is detected, the jump count value of the pred taken field of the entry corresponding to the first instruction may be increased by one until the threshold 3 is reached, that is, the binary representation "11" is reached. For example, refer to Figure 6 , if the second entry corresponding to the first instruction is the entry with index 2^k-1, and the first position value of the first instruction is "11", after the first instruction jumps, since the third jump count value in the entry with index 2^k-1 in the predtaken field is already "11", the value is no longer increased. It can be understood that the embodiment of the present application does not limit the threshold.

[0135] It can be understood that the position of the jump count value for the increment operation in the pred taken field corresponds to the position of the position value in the pos field, such as both are 3 in the above example.

[0136] S1022B: If there is no entry corresponding to the first value bundle in the corresponding incremental BTB, a first entry corresponding to the first instruction is added to the incremental BTB.

[0137] According to some embodiments, if there is no entry corresponding to the first value bundle in the incremental BTB, a first entry can be added to the incremental BTB, where the first index value is the index of the first entry, the first label value is written into the tag field of the first entry, the first position value is written into the pos field of the first entry, and the first address to which the first instruction jumps is written into the target field in the first entry.

[0138] For example, refer to Figure 4 or Figure 6 , the following takes the entry corresponding to the first value bundle as the entry with index 0 as an example. Specifically, the index values ​​of the n+1th to n+kth bits of the PC value of the first instruction from high to low are 0. When the first instruction jump is detected, Figure 4 or Figure 6 An entry with index 0 is added to the incremental BTB shown, and the label values ​​"tag0" from the 1st to the nth bits of the PC value of the first instruction from high to low are written into the tag field of the entry; the position values ​​"00" from the n+k+1 to n+k+2 bits of the PC value of the first instruction from high to low are written into the pos field; and the first address "target0" to which the first instruction jumps is written into the target field.

[0139] According to some embodiments, after writing the first address to the target field of the entry corresponding to the first instruction, the valid field of the first entry may also be updated to "1" so that the value of the valid field indicates that the entry is valid.

[0140] In some embodiments, the information of the first instruction stored also includes a jump count value, and the incremental BTB also includes a pred taken field for indicating whether the branch instruction jumps. In this embodiment, the initial jump count value can also be written into the pred taken field. For example, after adding the first entry in the incremental BTB, "01" is written into the pred taken field of the first entry.

[0141] In an embodiment of the present application, by writing the target address of the branch instruction jump to the branch prediction structure, the jump address of the branch instruction to be executed can be predicted. When the branch instruction actually jumps, the processor will update the target field, so that the correct jump address can be quickly and accurately accessed in future branch predictions. By updating the jump count value representing the number of historical executions in the branch prediction structure, when the actual jump of the branch instruction occurs, the value of the pred taken field corresponding to the branch instruction will increase, so that the probability of the branch instruction being predicted as a jump in history can be reflected through the jump count value, thereby improving the accuracy of branch prediction.

[0142] When there are instructions to be executed by the processor, the branch prediction structure can be dynamically updated, for example, by Figure 7 The method is updated as Figure 3-Figure 6 The branch prediction structure shown in Figure 1 predicts the jump information of branch instructions. Figure 8 An exemplary process of an instruction execution method is introduced.

[0143] S201: Detecting a first instruction to be executed.

[0144] It can be understood that the first instruction is a branch instruction.

[0145] According to some embodiments, the processor is a superscalar processor, and the instructions corresponding to the processing request can be composed of a value bundle and executed by the processor. For example, each value bundle can include 4 instructions, wherein the 4 instructions may include branch instructions or may not include branch instructions, which is not limited in the embodiments of the present application.

[0146] According to some embodiments, a front end of an electronic device, such as a display screen, may detect a user operation, so that a processor may receive a processing request triggered by the user operation.

[0147] According to some embodiments, an application program of the electronic device may submit a processing request, so that the processor receives the processing request of the program.

[0148] According to some embodiments, S201 may further include: determining that the first instruction is a branch instruction by parsing an operation code of the first instruction.

[0149] S202: Determine whether there is a first entry corresponding to the first instruction in the incremental BTB.

[0150] It can be understood that the first entry corresponds to the first value bundle described by the first instruction. For example, the first entry corresponds to all branch instructions in the first value bundle. For another example, the first entry corresponds to one branch instruction, namely the first instruction in the first value bundle, and does not correspond to other branch instructions.

[0151] According to some embodiments, when the pos field of the first entry is the first position value in the PC value of the first instruction, the index of the first entry is the first index value in the PC value of the first instruction, and the tag field of the first entry is the first tag value in the PC value of the first instruction, it can be determined that the first entry corresponds to the first instruction.

[0152] It can be understood that the incremental BTB is a dynamically updated branch prediction structure that uses the first index value to locate the entry corresponding to the branch instruction. According to some embodiments, each entry in the incremental BTB corresponds to an index value, and the index values ​​are arranged from small to large starting from 0. For example, referring to Figure 3-Figure 6 , arranged from 0 to 2^k-1. Based on this, the processor can determine the first entry corresponding to the first index value in the incremental BTB.

[0153] For example, refer to Figure 3 or Figure 5 For the entry with index "0", if the index value of the PC value of the first instruction is 0, "tag0" in the tag field is the first tag value in the PC value of the first instruction, and "00" in the pos field is the first position value in the PC value of the first instruction, then the entry can be determined as the first entry corresponding to the first instruction.

[0154] For example, refer to Figure 4 or Figure 6 For the entry with index "2^k-1", if the index value of the PC value of the first instruction is 2^k-1, the "tag(2^k-1)" of the tag field is the first tag value in the PC value of the first instruction, and the "00", "01", "11" in the pos field include the first position value "11" in the PC value of the first instruction, then the entry can be determined as the first entry corresponding to the first instruction.

[0155] According to some embodiments, when the incremental BTB macro does not have a first entry corresponding to the first instruction, the first instruction does not jump, and the processor continues to execute at the current address.

[0156] It can be understood that the information in the first entry can be used to guide the execution of the first instruction and the next instruction after the first instruction, such as jumping to the first address to execute the instruction, or continuing to read and execute the next instruction at the current address, that is, the address where the first instruction is stored. The following introduces two execution modes of the processor based on S203A-S203B.

[0157] S203A: Determine a first instruction jump according to the first entry, and jump to a first address.

[0158] According to some embodiments, the first address is the address in the target field of the first entry.

[0159] According to some embodiments, in case the first entry exists in the branch prediction structure, the first instruction jump may be determined directly.

[0160] In some scenarios, due to interference factors such as the capacity limit of the incremental BTB, the first entry may become invalid, and the valid field changes from "1" to "0". According to some embodiments, the valid field can indicate whether the first instruction jumps. If the valid field is "1", it means that the first entry is valid and the first instruction jumps.

[0161] For example, refer to Figure 3 If the index of the first entry is "2", since the valid field is "1", the first instruction jump is determined and jumps to the first address "target0" in the target field.

[0162] According to some embodiments, the first address is an address in the target field of the first entry corresponding to a first position value of the PC value of the first instruction.

[0163] For example, refer to Figure 4 , if the index of the first entry is "2^k-1" and the valid field is "1", the first instruction jumps. And the first position value in the PC value of the first instruction is "11". Since "g" is the third of the three addresses in the target field, and "11" is the third of the three position values ​​in the pos field, "11" and "g" have the same position in their respective fields, and the two correspond to each other, then the "g" corresponding to the first position value "11" in the target field in this entry is the first address corresponding to the first instruction. Based on this, it can be determined to jump to the first address "g".

[0164] According to some embodiments, the first entry of the delta BTB also includes a pred taken field.

[0165] According to some embodiments, the pred taken field of the first entry may be used alone to determine whether the first instruction jumps, wherein when the pred taken field is greater than a threshold or equal to a preset value, it may be determined that the first instruction jumps.

[0166] Exemplarily, the threshold is 1, that is, in the pred taken field, the jump count values ​​corresponding to the first instruction are "11" and "10" which are greater than the threshold, and "00" and "01" which are less than or equal to the threshold.

[0167] For example, refer to Figure 6 If the index of the first entry is "0", since the pred taken field of the first entry is "11", the first instruction jump is determined and jumps to the first address "target0" in the target field to continue executing instructions at the first address.

[0168] According to some embodiments, the pred taken field and the valid field of the first entry may be used together to determine whether the first instruction jumps. When the pred taken field is greater than a threshold or equal to a preset value, and the valid field indicates that the first entry is valid, it may be determined that the first instruction jumps.

[0169] Exemplarily, in the pred taken field, the preset value may include “11.” The embodiment of the present application does not limit the preset value.

[0170] For example, refer to Figure 6 , if the index of the first entry is "2^k-1", and the first position value in the PC value of the first instruction is "11". Since "11" is the third of the three position values ​​in the pos field, the jump count value corresponding to the first instruction is the third jump count value "11" in the predtaken field. Since "11" is greater than the threshold, and the valid field of the first entry is "1", indicating that the first entry is valid; then the first instruction is determined to jump, and jumps to the first address in the target field, that is, the third address "g", to continue executing the instruction.

[0171] According to some embodiments, if the first instruction jumps to the first address, the jump count value in the predtaken field of the first entry may be incremented, for example, added by one.

[0172] S203B: Determine according to the first entry that the first instruction does not jump, and continues to execute at the current address.

[0173] According to some embodiments, the first address is the address in the target field of the first entry.

[0174] According to some embodiments, the valid field may indicate whether the first instruction jumps. If the valid field is "0", it indicates that the first entry is invalid, and it is determined that the first instruction does not jump, and the processor continues to execute at the current address. The current address is the address at which the processor reads the first instruction.

[0175] For example, refer to Figure 3 If the index of the first entry is "2", since the valid field of the first entry is "0", it is determined that the first instruction does not jump.

[0176] According to some embodiments, the first entry of the delta BTB also includes a pred taken field.

[0177] According to some embodiments, the pred taken field may indicate whether the first instruction jumps. When the pred taken field is less than or equal to a threshold value and is not a preset value, it may be determined that the first instruction does not jump.

[0178] Exemplarily, the threshold is 1. In the pred taken field, the jump count values ​​corresponding to the first instruction are "11", "10", which are greater than the threshold, and "00" and "01", which are less than or equal to the threshold.

[0179] Exemplarily, in the pred taken field, the preset value may include “11.” The embodiment of the present application does not limit the preset value.

[0180] For example, refer to Figure 6 , if the index of the first entry is "2^k-1", and the first position value in the PC value of the first instruction is "01". Since "01" is the second of the three position values ​​in the pos field, the jump count value corresponding to the first instruction is the second jump count value "00" in the predtaken field. Since "00" is less than the threshold, the processor does not jump and continues to execute instructions at the current address.

[0181] According to some embodiments, the pred taken field and the valid field of the first entry may be used together to determine whether the first instruction jumps to the first address. When the pred taken field is less than or equal to a threshold and is not a preset value, or the valid field indicates that the first entry is invalid, it may be determined that the first instruction does not jump.

[0182] According to some embodiments, after the branch instruction jumps, if there are unexecuted instructions in the value bundle, the processor no longer executes other instructions after the branch instruction in the value bundle; the processor obtains the next value bundle from the target address jumped to to continue executing the instructions in the next value bundle.

[0183] It is understandable that the instruction execution method of S201-S203 can be used to process different processing requests. The following introduces two optional embodiments in different application scenarios. It should be noted that the following application scenarios are only examples and are not limited to this application.

[0184] According to some embodiments, the processing request is triggered based on a user operation, and the user intention of the user operation is to request to play the video. The processing request includes the identification of the video, user identity information, etc. The branch instruction can be used to determine the video quality, such as high definition or standard definition. In response to the branch instruction jumping to the target address, the processor can render the video based on the determined video quality and send the rendered video to the display.

[0185] According to some embodiments, when a user logs into an online platform, such as an online game, a processor in a server receives a processing request in S201, wherein the processing request may include user information, a service area desired by the user, etc., and the processing task corresponding to the processing request is to assign the user to a server area. The processor may predict which server area to register to. In response to a branch instruction jumping to a target address, the processor may assign the user to the predicted server area.

[0186] Through the embodiments of the present application, the incremental BTB can be used for branch prediction, wherein branch instructions at different positions in the value bundle are distinguished, and separate jump information prediction is performed for different branch instructions, thereby improving the prediction accuracy. In addition, by merging the PHT and BTB in the incremental BTB so that the incremental BTB includes execution information (i.e., information indicating whether the branch instruction executes a jump), the predicted branch no longer needs to be based on two branch prediction structures, thereby saving storage space, reducing computing power consumption, and improving prediction efficiency.

[0187] further, Fig. 9 According to some embodiments of the present application, a schematic diagram of the structure of an electronic device 100 is shown. Fig. 9 As shown, the electronic device 100 includes one or more processors 101, a system memory 102, a non-volatile memory (NVM) 103, a communication interface 104, an input / output (I / O) device 105, and a system control logic 106 for coupling the processor 101, the system memory 102, the non-volatile memory 103, the communication interface 104 and the input / output (I / O) device 105.

[0188] Wherein: the processor 101 may include one or more processing units, for example, a central processing unit CPU (Central Processing Unit), an image processor GPU (Graphics Processing Unit), a digital signal processor DSP (Digital Signal Processor), a microprocessor MCU (Micro-programmed Control Unit), an AI (Artificial Intelligence, artificial intelligence) processor or a programmable logic device FPGA (Field Programmable Gate Array), a neural network processor (Neural-network Processing Unit, NPU), etc. The processing module or processing circuit may include one or more single-core or multi-core processors. According to some embodiments, the processor is a superscalar processor.

[0189] The system memory 102 is a volatile memory, such as a random-access memory (RAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), etc. The system memory is used to temporarily store data and / or instructions.

[0190] The non-volatile memory 103 may include one or more tangible, non-transitory computer-readable media for storing data and / or instructions. In some embodiments, the non-volatile memory 103 may include any suitable non-volatile memory such as flash memory and / or any suitable non-volatile storage device, such as a hard disk drive (HDD), a compact disc (CD), a digital versatile disc (DVD), a solid-state drive (SSD), etc. In some embodiments, the non-volatile memory 103 may also be a removable storage medium, such as a secure digital (SD) memory card, etc. For example, in some embodiments, the system memory 102 may be used to store, for example, Figure 3-Figure 6 Incremental BTB shown.

[0191] In particular, the system memory 102 and the non-volatile memory 103 may respectively include: a temporary copy and a permanent copy of the instruction 107. The instruction 107 may include: when executed by at least one of the processors 101, the electronic device 100 implements the instruction execution method provided in each embodiment of the present application.

[0192] The communication interface 104 may include a transceiver for providing a wired or wireless communication interface for the electronic device 100, thereby communicating with any other suitable device through one or more networks. In some embodiments, the communication interface 104 may be integrated into other components of the electronic device 100, for example, the communication interface 104 may be integrated into the processor 101. In some embodiments, the electronic device 100 may communicate with other devices through the communication interface 104.

[0193] The input / output (I / O) device 105 can be an input device such as a keyboard, a mouse, etc., and an output device such as a display, etc. A user can interact with the electronic device 100 through the input / output (I / O) device 105, for example, inputting a neural network model to be run, etc.

[0194] System control logic 106 may include any suitable interface controller to provide any suitable interface with other modules of electronic device 100. For example, in some embodiments, system control logic 106 may include one or more memory controllers to provide interfaces to system memory 102 and non-volatile memory 103.

[0195] In some embodiments, at least one of the processors 101 may be packaged together with the logic of one or more controllers for the system control logic 106 to form a system in package (SiP). In other embodiments, at least one of the processors 101 may also be integrated with the logic of one or more controllers for the system control logic 106 on the same chip to form a system-on-chip (SoC).

[0196] Understandably, Fig. 9 The structure of the electronic device 100 shown is only an example. In other embodiments, the electronic device 100 may include more or fewer components than shown, or combine some components, or separate some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0197] It can be understood that the electronic device 100 can be any electronic device, including but not limited to mobile phones, wearable devices (such as smart watches, etc.), tablet computers, desktops, laptops, handheld computers, notebook computers, ultra-mobile personal computers (ultra-mobile personal computers, UMPC), netbooks, as well as cellular phones, personal digital assistants (personal digital assistants, PDAs), augmented reality (augmented reality, AR) / virtual reality (virtual reality, VR) devices, etc., and the embodiments of the present application are not limited thereto.

[0198] The various embodiments of the mechanism disclosed in the present application can be implemented in hardware, software, firmware or a combination of these implementation methods. The embodiments of the present application can be implemented as a computer program or program code executed on a programmable system, which includes at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device and at least one output device.

[0199] Program code can be applied to input instructions to perform the functions described in this application and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, a processing system includes any system having a processor such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

[0200] Program code can be implemented with high-level programming language or object-oriented programming language to communicate with the processing system. When necessary, program code can also be implemented with assembly language or machine language. In fact, the mechanism described in this application is not limited to the scope of any specific programming language. In either case, the language can be a compiled language or an interpreted language.

[0201] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, instructions may be distributed over a network or through other computer-readable media. Therefore, machine-readable media may include any mechanism for storing or transmitting information in a machine (e.g., computer) readable form, including, but not limited to, floppy disks, optical disks, optical disks, read-only memories (CD-ROMs), magneto-optical disks, read-only memories (ROM), random access memories (RAM), erasable programmable read-only memories (EPROM), electrically erasable programmable read-only memories (EEPROM), magnetic cards or optical cards, flash memory, or tangible machine-readable memories for transmitting information (e.g., carrier waves, infrared signal digital signals, etc.) using the Internet in electrical, optical, acoustic, or other forms of propagation signals. Accordingly, machine-readable media include any type of machine-readable media suitable for storing or transmitting electronic instructions or information in a form readable by a machine (eg, a computer).

[0202] In the accompanying drawings, some structural or method features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be required. Instead, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. In addition, the inclusion of structural or method features in a particular figure does not mean that such features are required in all embodiments, and in some embodiments, these features may not be included or may be combined with other features.

[0203] It should be noted that the units / modules mentioned in the various device embodiments of the present application are all logical units / modules. Physically, a logical unit / module can be a physical unit / module, or a part of a physical unit / module, or can be implemented as a combination of multiple physical units / modules. The physical implementation method of these logical units / modules themselves is not the most important. The combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed by the present application. In addition, in order to highlight the innovative part of the present application, the above-mentioned device embodiments of the present application do not introduce units / modules that are not closely related to solving the technical problems proposed by the present application, which does not mean that there are no other units / modules in the above-mentioned device embodiments.

[0204] It should be noted that in the examples and description of this patent, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, an element defined by the sentence "comprises one" does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0205] Although the present application has been illustrated and described with reference to certain preferred embodiments thereof, it will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present application.

Claims

1. A command execution method, applied to an electronic device, characterized in that: A branch prediction structure is stored in the processor of the electronic device, wherein the branch prediction structure includes a plurality of entries, each of the entries corresponds to at least part of the branch instructions in a value bundle, each of the entries includes a position field and a target address field, the position field includes a position value corresponding to at least part of the branch instructions in the corresponding value bundle, the target address field includes a target address corresponding to at least part of the branch instructions in the corresponding value bundle, the position value indicates the position of the corresponding branch instruction in the value bundle to which it belongs, and the target address indicates the address to which the corresponding branch instruction jumps; Furthermore, the method comprises: The processor detects a first instruction; The processor determines that a first entry exists in the branch prediction structure, wherein the value bundle corresponding to the first entry is a first value bundle to which the first instruction belongs, and the position field of the first entry matches a first position value in an instruction pointer of the first instruction, and the first position value indicates a position of the first instruction in the first value bundle to which it belongs; Jump to a first address, where the first address is a target address in the target address field of the first entry corresponding to the first position value.

2. The method according to claim 1, characterized in that Each of the entries further includes a predicted execution field, the predicted execution field including a jump count value corresponding to at least part of the branch instructions in the corresponding value bundle, the jump count value is used to indicate the number of historical jumps of the corresponding branch instruction; The jumping to the first address comprises: If the predicted execution field of the first entry indicates that the branch instruction jumps, jump to a first address, Wherein, when the jump count value is greater than a threshold value or the jump count value is a preset value, the predicted execution field indicates the corresponding branch instruction jump.

3. The method according to claim 1 or 2, characterized in that: The first location value and the first address are stored in the branch prediction structure when the processor historically detects that a jump occurs to the first instruction.

4. The method according to any one of claims 1 to 3, characterized in that: Each of the entries further includes a tag field and an index field, the tag field includes a tag value corresponding to a value bundle corresponding to the branch instruction, and each of the entries in the branch prediction structure corresponds to an index value, The label value is the 1st to nth bits from high to low in the instruction pointer of the branch instruction, the index value is the n+1th to n+kth bits from high to low in the instruction pointer of the branch instruction, and the position value is the n+k+1th to n+k+mth bits from high to low in the instruction pointer of the branch instruction.

5. The method according to claim 4, characterized in that The processor stores the first address and the first location value in the branch prediction structure in the following manner: detecting that the first instruction jumps to the first address; Corresponding to the branch prediction structure, there is a second entry corresponding to the first value bundle and the position field of the second entry includes the first position value, and a third address corresponding to the first position value in the target address field of the second entry is updated to the first address to obtain the first entry; or Corresponding to the branch prediction structure, there is a second entry corresponding to the first value bundle and the position field of the second entry does not include the first position value, the first address is written into the target address field of the second entry, and the first position value is written into the position field of the second entry to obtain the first entry; or Corresponding to the absence of an entry corresponding to the first value bundle in the branch prediction structure, adding the first entry corresponding to the first value bundle in the branch prediction structure, writing the first address into the target address field of the first entry, and writing the first position value into the position field of the first entry, The tag field of the first entry is the 1st to nth bits from high to low in the execution pointer of the first instruction, wherein the index value of the first entry is the n+1th to n+kth bits from high to low in the execution pointer of the first instruction.

6. The method according to claim 4, characterized in that The processor stores the first address and the first location value in the branch prediction structure in the following manner: detecting that the first instruction jumps to the first address; A second entry corresponding to the first instruction exists corresponding to the branch prediction structure, and the position field of the second entry is the first position value, and a third address corresponding to the first position value in the target address field of the second entry is updated to the first address to obtain the first entry; or Corresponding to the absence of an entry matching the first instruction in the branch prediction structure, adding the first entry corresponding to the first instruction to the branch prediction structure, writing the first address into the target address field of the first entry, and writing the first position value into the position field of the first entry, The tag field of the first entry is the 1st to nth bits from high to low in the execution pointer of the first instruction, wherein the index value of the first entry is the n+1th to n+kth bits from high to low in the execution pointer of the first instruction.

7. The method according to claim 4, characterized in that The 1st to nth bits from high to low in the instruction pointer of the first instruction are the same as the first label value of the label field in the first entry, the n+1th to n+kth bits from high to low in the instruction pointer of the first instruction are the same as the first index value corresponding to the first entry, the n+k+1th to n+k+mth bits from high to low in the instruction pointer of the first instruction are the same as the first label value of the label field in the first entry, the index value is the n+1th to n+kth bits from high to low in the instruction pointer of the branch instruction, and the position value is the n+k+1th to n+k+mth bits from high to low in the instruction pointer of the branch instruction.

8. The method according to claim 2, characterized in that: The jumping to the first address comprises: The jump count value in the predicted execution field of the first entry is incremented, and a jump is made to the first address.

9. An electronic device, characterized in that: include: a memory for storing instructions to be executed by one or more processors of the electronic device; and a processor, which is one of the processors of the electronic device, configured to execute the instruction so that the electronic device implements the instruction execution method according to any one of claims 1 to 8.

10. A readable medium, characterized in that: The readable medium contains instructions, which, when executed by a processor of an electronic device, enable the electronic device to implement the instruction execution method according to any one of claims 1 to 8.

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