An instruction stream generation method, apparatus, electronic device, and storage medium

Abstract

An embodiment of the present invention provides an instruction stream generation method, apparatus, electronic device, and storage medium, which relate to the field of computer technology. In this method, an operation code is selected from an operation code set as the first operation code; an operation code is selected from the subsequent operation code set corresponding to the first operation code as the second operation code to obtain a dependent operation code pair composed of the first operation code and the second operation code; based on the inclusion relationship between the second operation code and the previous operation code set, the next dependent operation code pair is obtained from the operation code set until all dependent operation code pairs corresponding to a preset dependency relationship are obtained; the target instructions generated for each operation code in each dependent operation code pair are obtained to obtain an instruction stream composed of each target instruction. It can efficiently generate all dependent operation code pairs under a preset dependency relationship, which helps to improve the accuracy of testing the CPU through the instruction stream. And it can improve the efficiency of testing the CPU through the instruction stream to a certain extent.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of computer technologies, and particularly to an instruction stream generation method, apparatus, electronic device, and storage medium. Background Art

[0002] Currently, with the continuous development of computer technologies, the design of a central processing unit (CPU) has become increasingly complex. How to verify it during the design and development process of the CPU has become increasingly important in the CPU development process.

[0003] Generally, an instruction generator is used to randomly generate a continuous stream of instructions and input them into an emulated CPU core or a physical CPU core, and the CPU is tested by observing its processing and response to these instruction streams. In these instruction streams, not only instructions with different operation codes need to be included, but also instruction pairs composed of operation code pairs with dependency relationships need to be included, so as to test whether the CPU can correctly process different instructions and instruction combinations.

[0004] However, by randomly selecting operation codes and randomly generating instruction streams for testing, in order to include as many operation code combination methods with dependency relationships as possible in the instruction streams, a huge amount of instruction streams usually need to be generated for testing, and even if a huge amount of instruction streams are generated, there may still be missing combination methods, resulting in poor efficiency and accuracy when using the instruction streams generated in the above manner to test the CPU. Summary of the Invention

[0005] Embodiments of the present invention provide an instruction stream generation method, apparatus, electronic device, and storage medium, which can generate instruction streams with higher test efficiency and test accuracy, and improve the efficiency and accuracy of testing the CPU through the instruction streams.

[0006] To solve the above problems, embodiments of the present invention disclose an instruction stream generation method, and the method includes:

[0007] Select an operation code from an operation code set as a first operation code; wherein, the first operation code belongs to a set of pre-order operation codes, and the set of pre-order operation codes is determined from the operation code set based on a preset dependency relationship;

[0008] Select an operation code from the set of post-order operation codes corresponding to the first operation code as a second operation code, and obtain a dependency operation code pair composed of the first operation code and the second operation code; wherein, the set of post-order operation codes is determined from the operation code set based on the preset dependency relationship;

[0009] Obtain the next dependent opcode pair from the opcode set based on the inclusion relationship between the second opcode and the set of previous opcodes, until all dependent opcode pairs corresponding to the preset dependency relationship are obtained;

[0010] Obtain the target instructions generated for each opcode in each dependent opcode pair to obtain an instruction stream composed of each target instruction; wherein, the target instructions corresponding to the opcodes in the same dependent opcode pair have the same register encoding, and the instruction stream is used to test the central processing unit.

[0011] Optionally, the method further includes:

[0012] Obtain the dependent register encoding from the target instruction corresponding to the previous opcode in the dependent opcode pair based on the preset dependency relationship;

[0013] Determine the target instruction corresponding to the latter opcode in the dependent opcode pair based on the preset dependency relationship and the dependent register encoding.

[0014] Optionally, the method further includes:

[0015] Randomly generate the target instruction corresponding to the previous opcode and the target instruction corresponding to the latter opcode in the dependent opcode pair;

[0016] In the case where the target instruction corresponding to the latter opcode has the same dependent register encoding corresponding to the preset dependency relationship as the target instruction corresponding to the previous opcode, delete the latter opcode from the set of subsequent opcodes corresponding to the first opcode.

[0017] Optionally, the method further includes:

[0018] After obtaining any dependent opcode pair, delete the latter opcode in the dependent opcode pair from the set of subsequent opcodes corresponding to the previous opcode.

[0019] Optionally, the method further includes:

[0020] After deleting an opcode from any set of subsequent opcodes, detect whether the set of subsequent opcodes is empty;

[0021] In the case where it is detected that the set of subsequent opcodes is empty, delete the opcode corresponding to the set of subsequent opcodes from the set of previous opcodes;

[0022] In the case where it is detected that the set of previous opcodes is empty, determine that all dependent opcode pairs corresponding to the preset dependency relationship have been obtained.

[0023] Optionally, the method further includes:

[0024] Concatenate the instruction streams corresponding to multiple preset dependency relationships to obtain a target instruction stream; or, insert the dependency instruction pairs of the instruction stream corresponding to other preset dependency relationships between the dependency instruction pairs of the instruction stream corresponding to the preset dependency relationship to obtain a target instruction stream.

[0025] Optionally, the selecting an operation code from the operation code set as the first operation code includes:

[0026] Select an operation code from the operation code set, and determine the inclusion relationship between the operation code and the set of previous operation codes;

[0027] In the case where the inclusion relationship is inclusion, use the operation code as the first operation code;

[0028] In the case where the inclusion relationship is non-inclusion, use the operation code as an independent operation code, and re-select an operation code from the operation code set as the first operation code; wherein, the independent operation code is used to generate the independent operation code included in the instruction stream.

[0029] Optionally, the preset dependency relationship includes a read-after-write dependency relationship, a write-after-write dependency relationship, a read-after-write dependency relationship, or a read-after-read dependency relationship.

[0030] On the other hand, an embodiment of the present invention discloses an instruction stream generation device, and the device includes:

[0031] A first operation code module, configured to select an operation code from the operation code set as the first operation code; wherein, the first operation code belongs to a set of previous operation codes, and the set of previous operation codes is determined from the operation code set based on a preset dependency relationship;

[0032] A second operation code module, configured to select an operation code from the set of subsequent operation codes corresponding to the first operation code as the second operation code, to obtain a dependency operation code pair formed by the first operation code and the second operation code; wherein, the set of subsequent operation codes is determined from the operation code set based on the preset dependency relationship;

[0033] A dependency operation code pair module, configured to obtain the next dependency operation code pair from the operation code set based on the inclusion relationship between the second operation code and the set of previous operation codes, until all the dependency operation code pairs corresponding to the preset dependency relationship are obtained;

[0034] An instruction stream module, configured to obtain target instructions generated for each operation code in each dependency operation code pair, to obtain an instruction stream formed by each target instruction; wherein, the target instructions corresponding to the operation codes in the same dependency operation code pair have the same register encoding, and the instruction stream is used to test a central processing unit.

[0035] In another aspect, an embodiment of the present invention discloses an electronic device, including: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface complete communication with each other through the communication bus. The memory is used to store at least one executable instruction, and the executable instruction causes the processor to execute the foregoing method.

[0036] An embodiment of the present invention also discloses a computer-readable storage medium, on which instructions are stored. When executed by one or more processors, the instructions cause the processors to execute the method as described above.

[0037] The embodiments of the present invention have the following advantages: In the instruction stream generation method provided in the embodiments of the present invention, an opcode is selected from the opcode set as the first opcode. Among them, the first opcode belongs to the set of previous opcodes, and the set of previous opcodes is determined from the opcode set based on a preset dependency relationship. An opcode is selected from the set of subsequent opcodes corresponding to the first opcode as the second opcode to obtain a dependent opcode pair composed of the first opcode and the second opcode. Among them, the set of subsequent opcodes is determined from the opcode set based on a preset dependency relationship. Based on the inclusion relationship between the second opcode and the set of previous opcodes, the next dependent opcode pair is obtained from the opcode set until all dependent opcode pairs corresponding to the preset dependency relationship are obtained. The target instructions generated for each opcode in each dependent opcode pair are obtained to obtain an instruction stream composed of each target instruction. Among them, the target instructions corresponding to the opcodes in the same dependent opcode pair have the same register encoding, and the instruction stream is used to test the central processing unit. In this way, all dependent opcode pairs under the preset dependency relationship can be efficiently generated, and the instruction stream generated according to these dependent opcode pairs can include all possible instruction combination methods with the preset dependency relationship, which helps to improve the accuracy of testing the CPU through the instruction stream. And because the opcode can be specifically selected from the set of subsequent opcodes of the opcode to form a dependent opcode pair, the efficiency of obtaining the dependent opcode pair can be improved to a certain extent, which helps to increase the instruction density of the instructions with a dependency relationship in the generated instruction stream, thereby reducing the length of the instruction stream required to test the CPU and improving the efficiency of testing the CPU with the instruction stream. Description of the Drawings

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0039] Figure 1 It is a flowchart of the steps of an instruction stream generation method provided by an embodiment of the present invention;

[0040] Figure 2 is a flowchart of opcode selection provided by an embodiment of the present invention;

[0041] Figure 3 is a block diagram of an instruction stream generation device provided by an embodiment of the present invention;

[0042] Figure 4 is a schematic structural diagram of an electronic device provided by an embodiment of the present invention. Detailed implementation manners

[0043] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0044] Referring to Figure 1 , a step flowchart of an instruction stream generation method provided by an embodiment of the present invention is shown. As Figure 1 shown, the method may specifically include the following steps:

[0045] Step 101: Select an opcode as the first opcode from the opcode set; wherein, the first opcode belongs to the set of pre-order opcodes, and the set of pre-order opcodes is determined from the opcode set based on a preset dependency relationship.

[0046] In an embodiment of the present invention, an opcode represents a part of a computer instruction and is used to represent a specific operation or task. Each instruction usually consists of an opcode and an operand. The opcode defines the operation that the CPU should execute, while the operand defines the data position of the operation and / or the storage position of the operation result. The opcode can also be called the instruction name. The opcode set represents the set of all opcodes that need to be tested for the CPU or CPU core to be tested during in-core verification of the CPU. The set of pre-order opcodes represents the opcodes in the opcode set whose operation results can be used as the operation conditions for the subsequent opcodes, that is, there is a preset dependency relationship between a pre-order opcode and a subsequent opcode of the pre-order opcode.

[0047] In the embodiments of the present invention, there can be multiple preset dependency relationships. According to each dependency relationship, a corresponding set of previous opcodes can be determined from the opcode set. The preset dependency relationships can include, but are not limited to, read-after-write dependency relationships, write-after-write dependency relationships, read-after-write dependency relationships, read-after-read dependency relationships, etc. Among them, the read-after-write dependency relationship means that when the subsequent opcode is executed, it can read the register written when the previous opcode is executed, that is, the source register of the instruction generated by the subsequent opcode can be the same as the destination register of the instruction generated by the previous opcode; the write-after-write dependency relationship means that when the subsequent opcode is executed, it can write to the register written when the previous opcode is executed, that is, the destination register of the instruction generated by the subsequent opcode can be the same as the destination register of the instruction generated by the previous opcode; the read-after-write dependency relationship means that when the subsequent opcode is executed, it can write to the register read when the previous opcode is executed, that is, the destination register of the instruction generated by the subsequent opcode can be the same as the source register of the instruction generated by the previous opcode; the read-after-read dependency relationship means that when the subsequent opcode is executed, it can read the register read when the previous opcode is executed, that is, the source register of the instruction generated by the subsequent opcode can be the same as the source register of the instruction generated by the previous opcode.

[0048] Exemplarily, if an opcode set is [ADD, LUI, ORI, BEQ]. Among them, ADD is used to perform an addition operation on the values of two registers and store the result in a destination register; LUI is used to add an immediate value to a register; ORI is used to perform an addition operation on the value of a register and an immediate value and store the result in a destination register; BEQ is used to jump to the specified instruction address to continue execution when the values of two registers are equal. Since the above opcodes ADD, LUI, and ORI need to perform register writes during execution, for the read-after-write dependency relationship, it can be determined that ADD, LUI, and ORI in the above opcode set can form the set of previous opcodes corresponding to the read-after-write dependency relationship, and can also form the set of previous opcodes corresponding to the write-after-write dependency relationship.

[0049] In the embodiments of the present invention, when an opcode is selected from the opcode set, if the opcode belongs to one of the sets of previous opcodes corresponding to the preset dependency relationships, the opcode can be used as the first opcode. Specifically, the selection method can include, but is not limited to, random selection, sequential selection, reverse selection, alternating selection, etc., and the embodiments of the present invention do not make specific limitations.

[0050] It should be noted that in the embodiments of the present invention, an opcode can be selected from the opcode set and recorded. If the selected opcode does not belong to the previous opcode set, continue to select an opcode from the opcode set until an opcode belonging to the previous opcode set is selected and used as the first opcode; alternatively, an opcode can be directly selected from the previous opcode set corresponding to the opcode set as the first opcode.

[0051] Step 102: Select an opcode from the subsequent opcode set corresponding to the first opcode as the second opcode, and obtain a dependent opcode pair composed of the first opcode and the second opcode; wherein, the subsequent opcode set is determined from the opcode set based on the preset dependency relationship.

[0052] In the embodiments of the present invention, each previous opcode in the previous opcode set can correspond to a subsequent opcode set. The subsequent opcode set corresponding to the previous opcode contains the subsequent opcode having a corresponding preset dependency relationship with the previous opcode.

[0053] Exemplarily, if an opcode set is [ADD, LUI, ORI, BEQ], the previous opcode set corresponding to the write-after-read dependency relationship is [ADD, LUI, ORI]. Since ADD, ORI, and BEQ in the opcode set need to perform register reads during execution, the subsequent opcode set ADD_SET corresponding to ADD in the previous opcode set is [ADD, ORI, BEQ], the subsequent opcode set LUI_SET corresponding to LUI is [ADD, ORI, BEQ], and the subsequent opcode set ORI_SET corresponding to ORI is [ADD, ORI, BEQ].

[0054] In the embodiments of the present invention, an opcode can be selected from the subsequent opcode set corresponding to the first opcode selected above as the second opcode corresponding to the first opcode. The method of selecting the opcode can include but is not limited to random selection, sequential selection, reverse selection, alternating selection, etc., and the embodiments of the present invention do not make specific limitations.

[0055] Since the first opcode and the second opcode selected above are respectively selected from the previous opcode and the subsequent opcode corresponding to the preset dependency relationship, the selected first opcode and the corresponding second opcode can form a dependent opcode pair that conforms to the preset dependency relationship, that is, the dependent opcode pair represents a set of opcodes that conform to the preset dependency relationship.

[0056] Exemplarily, if the set of preceding opcodes corresponding to the write-after-read dependency is [ADD, LUI, ORI], the first opcode selected is ADD, and the set of subsequent opcodes ADD_SET corresponding to ADD is [ADD, ORI, BEQ], then an opcode (such as ORI) can be selected from the set ADD_SET as the second opcode corresponding to the first opcode ADD. Then, ADD and ORI form a pair of dependent opcodes (ADD, ORI) corresponding to the write-after-read dependency.

[0057] Step 103: Based on the inclusion relationship between the second opcode and the set of preceding opcodes, obtain the next pair of dependent opcodes from the opcode set until all pairs of dependent opcodes corresponding to the preset dependency are obtained.

[0058] In the embodiments of the present invention, according to the inclusion relationship between the second opcode and the set of preceding opcodes, the next pair of dependent opcodes can be continuously obtained from the opcode set. Specifically, if the second opcode belongs to the set of preceding opcodes, the second opcode can be used as the next preceding opcode, and the next subsequent opcode can be obtained from the set of subsequent opcodes corresponding to the next preceding opcode. Then, the next preceding opcode and the next subsequent opcode can form the next pair of dependent opcodes; if the second opcode does not belong to the set of preceding opcodes, an opcode belonging to the set of preceding opcodes can be reselected from the opcode set as the next preceding opcode, and the next subsequent opcode can be obtained from the set of subsequent opcodes corresponding to the next preceding opcode. Then, the next preceding opcode and the next subsequent opcode can form the next pair of dependent opcodes.

[0059] Exemplarily, if the set of previous opcodes corresponding to the write-after-read dependency is [ADD, LUI, ORI], the first opcode selected is ADD, and the set of subsequent opcodes ADD_SET corresponding to ADD is [ADD, ORI, BEQ], after obtaining the dependency opcode pair (ADD1, ORI2) corresponding to a write-after-read dependency formed by ADD and ORI, it can be determined whether ORI2 belongs to the set of previous opcodes. After determining that the inclusion relationship between ORI2 and the set of previous opcodes is belonging, a subsequent opcode (such as BEQ) can be selected from the set of subsequent opcodes ORI_SET = [ADD, ORI, BEQ] corresponding to the next previous opcode ORI2 as the next subsequent opcode, then the next dependency opcode pair (ORI2, BEQ3) is obtained. After that, it can be continued to determine whether BEQ3 belongs to the set of previous opcodes. After determining that the inclusion relationship between BEQ3 and the set of previous opcodes is not belonging, an opcode (such as LUI) belonging to the set of previous opcodes can be selected from the opcode set as the third previous opcode, and a third subsequent opcode (such as ORI) can be selected from the set of subsequent opcodes LUI_SET = [ADD, ORI, BEQ] corresponding to LUI, then the third dependency opcode pair is (LUI4, ORI5).

[0060] In the embodiment of the present invention, the above process can be repeated until all dependency opcode pairs corresponding to the preset dependency are obtained, that is, all dependency opcode pairs that can be formed by combining all opcodes in the opcode set under the preset dependency are obtained.

[0061] Step 104, obtain target instructions generated for each opcode in each dependency opcode pair, and obtain an instruction stream composed of each target instruction; wherein, the target instructions corresponding to the opcodes in the same dependency opcode pair have the same register encoding, and the instruction stream is used to test the central processing unit.

[0062] In the embodiment of the present invention, for each obtained dependency opcode pair, target instructions corresponding to each opcode therein can be generated. The target instruction can be composed of an opcode and an operand. Among them, the opcode in the target instruction is used to represent the operation type executed by the instruction, and the operand in the target instruction is used to indicate the data and / or data storage location of the operation. The operand can include but is not limited to source register encoding, destination register encoding, immediate number, etc. Among the target instructions generated for the opcodes in the same dependency opcode pair, there can be at least one pair of the same register encoding.

[0063] Specifically, the operation codes in all the selected dependent operation code pairs in the above steps can be arranged in the selected order to form an operation code sequence. The target instructions generated based on the operation codes in the operation code sequence can constitute the above instruction stream. Further, in addition to the operation codes in each dependent operation code pair, the above operation code sequence may also include independent operation codes selected from the operation code set that do not form dependent operation code pairs. These independent operation codes and the operation codes in the dependent operation code pairs can all be arranged in the operation code sequence in the selected order. Thus, the instruction stream constituted by the target instructions generated based on the operation codes in the operation code sequence can include richer operation codes, which helps to increase the complexity of the instruction stream and improve the test effect of in-core testing of the processor through the instruction stream.

[0064] Exemplarily, if 3 dependent operation code pairs are obtained for the read-after-write dependency relationship, including (ADD1, ORI2), (ORI2, BEQ3), and (LUI4, ORI5), then the first dependent operation code pair (ADD1, ORI2) corresponds to two target instructions, namely the ADD1 instruction and the ORI2 instruction; the second dependent operation code pair (ORI2, BEQ3) corresponds to two target instructions, namely the ORI2 instruction and the BEQ3 instruction; the first dependent operation code pair (LUI, ORI) corresponds to two target instructions, namely the LUI4 instruction and the ORI5 instruction. Then the above dependent operation code pairs can form an operation code sequence [ADD1, ORI2, BEQ3, LUI4, ORI5]. Among them, one source register encoding of the ORI2 instruction can be the same as the destination register encoding of the ADD1 instruction, one source register encoding of the BEQ3 instruction can be the same as the destination register encoding of the ORI2 instruction, and one source register encoding of the ORI5 instruction can be the same as the destination register encoding of the LUI4 instruction. That is to say, one source register encoding of the ORI2 instruction can be directly determined according to the destination register encoding of the ADD1 instruction, one source register encoding of the BEQ3 instruction can be directly determined according to the destination register encoding of the ORI2 instruction, and so on. It should be noted that for the register encodings in each target instruction that do not need to be determined according to the register encoding of the previous target instruction, they can be selected from the set of register encodings that it can use. The selection methods may include but are not limited to random selection, sequential selection, reverse selection, alternating selection, etc., and the embodiments of the present invention do not make specific limitations.

[0065] In summary, in the instruction stream generation method provided by an embodiment of the present invention, an operation code is selected from an operation code set as a first operation code; wherein, the first operation code belongs to a set of previous operation codes, and the set of previous operation codes is determined from the operation code set based on a preset dependency relationship; an operation code is selected from the set of subsequent operation codes corresponding to the first operation code as a second operation code to obtain a dependency operation code pair composed of the first operation code and the second operation code; wherein, the set of subsequent operation codes is determined from the operation code set based on a preset dependency relationship; based on the inclusion relationship between the second operation code and the set of previous operation codes, the next dependency operation code pair is obtained from the operation code set until all dependency operation code pairs corresponding to the preset dependency relationship are obtained; target instructions generated for each operation code in each dependency operation code pair are obtained to obtain an instruction stream composed of each target instruction; wherein, the target instructions corresponding to the operation codes in the same dependency operation code pair have the same register encoding, and the instruction stream is used to test a central processing unit. In this way, all dependency operation code pairs under a preset dependency relationship can be efficiently generated, and the instruction stream generated according to these dependency operation code pairs can include all possible instruction combination methods with a preset dependency relationship, which helps to improve the accuracy of testing the CPU through the instruction stream. And because the operation code can be specifically selected from the set of subsequent operation codes of the operation code to form a dependency operation code pair, the efficiency of selecting the dependency operation code pair can be improved to a certain extent, which helps to increase the instruction density of instructions with a dependency relationship in the generated instruction stream, thereby reducing the length of the instruction stream required to test the CPU and improving the efficiency of testing the CPU with the instruction stream.

[0066] Optionally, in some embodiments, the instruction stream further includes independent instructions generated based on independent operation codes. The step of selecting an operation code from the operation code set as the first operation code may specifically include:

[0067] Step 1011, select an operation code from the operation code set and determine the inclusion relationship between the operation code and the set of previous operation codes.

[0068] In an embodiment of the present invention, not only can dependency operation code pairs be selected from the operation code set, but also independent operation codes that cannot form dependency operation code pairs with other operation codes can be selected, so that the instruction stream generated based on the selected operation codes can include not only target instructions with a dependency relationship, but also independent instructions, which helps to increase the complexity of the instruction stream and improve the accuracy and test effect of in-core testing of the processor based on the instruction stream.

[0069] Specifically, the set of previous operation codes corresponding to the preset dependency relationship can be first determined from the operation code set, and then an operation code is selected from the set of previous operation codes, and the inclusion relationship between the selected operation code and the set of previous operation codes is judged, that is, whether the set of previous operation codes includes the operation code, and the inclusion relationship can include inclusion and non-inclusion.

[0070] Refer to Figure 2 , Figure 2 which shows a flowchart of opcode selection provided by an embodiment of the present invention. As Figure 2 shown, first, the set of previous opcodes can be determined according to the preset dependency relationship, and the set of subsequent opcodes corresponding to each opcode in the set of previous opcodes can be determined. Then, the selection of the first opcode starts. When selecting an opcode, it is judged whether the opcode to be selected currently is the first opcode. If the opcode to be selected currently is the first opcode, an opcode is selected from the opcode set, and a corresponding instruction is randomly generated. Then, the selection of the second opcode starts. Since the opcode to be selected currently is not the first opcode at this time, it is judged whether the previous opcode belongs to the set of previous opcodes, that is, it is judged whether the first opcode selected above is in the set of previous opcodes, and a judgment result is obtained. It should be noted that the above-mentioned random generation of the corresponding instruction means randomly determining the source register code and / or the destination register code to obtain the corresponding instruction.

[0071] Exemplarily, if the instruction set architecture of a processor to be tested includes a total of 4 opcodes, namely ADD, LUI, ORI, and BEQ. For the write-after-read dependency relationship, the corresponding set of previous opcodes INST_SET = [ADD, LUI, ORI] can be determined. The set of subsequent opcodes ADD_SET corresponding to ADD = [ADD, ORI, BEQ], the set of subsequent opcodes LUI_SET corresponding to LUI = [ADD, ORI, BEQ], and the set of subsequent opcodes ORI_SET corresponding to ORI = [ADD, ORI, BEQ]. If the first opcode ADD is randomly selected from the opcode set and the register is randomly encoded for it: the destination register rd = 16, one source register rs1 = 3, and another source register rs2 = 9, then the instruction corresponding to the first opcode ADD can be obtained as "ADD rd = 16 rs1 = 3 rs2 = 9".

[0072] Step 1012, in the case where the inclusion relationship is inclusion, use the opcode as the first opcode.

[0073] In an embodiment of the present invention, if the inclusion relationship between the opcode selected from the opcode set and the set of previous opcodes is inclusion, the opcode belongs to the set of previous opcodes, and the opcode can be determined as the first opcode. Then, an opcode is selected from the set of subsequent opcodes corresponding to the first opcode as the second opcode to form a pair of dependent opcodes.

[0074] Such as Figure 2As shown, when selecting the second opcode, it is possible to determine whether the previous opcode belongs to the set of previous opcodes, that is, to determine the inclusion relationship between the first opcode selected above and the set of previous opcodes. If the judgment result is yes, the first opcode selected above is used as the first opcode, and a subsequent opcode is selected from the set of subsequent opcodes corresponding to the previous opcode, that is, the second opcode is selected from the set of subsequent opcodes corresponding to this first opcode, that is, the second opcode. This second opcode can form a dependent opcode pair with the first opcode. For this second opcode, the target instruction of the subsequent opcode can be generated according to the target instruction of the previous opcode, that is, according to the preset dependency relationship and the dependent register encoding corresponding to the previous opcode in the dependent opcode pair, its corresponding target instruction is generated.

[0075] Continuing the above example, since the first opcode selected belongs to the set of previous opcodes INST_SET, the first ADD opcode can be used as the first opcode, and an opcode is selected from the set of subsequent opcodes ADD_SET = [ADD, ORI, BEQ] as the second opcode (for example, BEQ), that is, the second opcode, and the destination register encoding 16 in the target instruction corresponding to the first opcode is used as a source register encoding of the second opcode BEQ. The remaining register encodings of the second opcode BEQ can be randomly generated, and its target instruction can be "BEQ rs1 = 16 rs2 = 23".

[0076] Step 1013, in the case where the inclusion relationship is non-inclusion, use the opcode as an independent opcode, and re-select an opcode from the opcode set as the first opcode; wherein, the independent opcode is used to generate the independent opcode included in the instruction stream.

[0077] In the embodiment of the present invention, if the inclusion relationship between the opcode selected from the opcode set and the set of previous opcodes is non-inclusion, then this opcode does not belong to the set of previous opcodes, and this opcode can be used as an independent opcode, and an independent instruction randomly generated based on the independent opcode is stored in the instruction stream. Continue to select an opcode from the opcode set, continue to judge the inclusion relationship between the selected opcode and the set of previous opcodes, and repeat the above process until the selected opcode belongs to the set of previous opcodes, and use the latest selected opcode as the first opcode.

[0078] Such as Figure 2As shown, when selecting an opcode, it is possible to determine whether the previous opcode belongs to the set of previous opcodes. For example, when selecting the second opcode, it is possible to determine whether the first opcode belongs to the set of previous opcodes. If the judgment result is negative, it means that the opcode to be selected currently cannot form a dependent opcode pair with the previous opcode. In one implementation, an opcode can be selected from the set of previous opcodes / opcode set, and a corresponding instruction can be randomly generated. In another implementation, an opcode can also be selected from the opcode set, and a corresponding instruction can be randomly generated. Exemplarily, if neither the first selected opcode nor the second selected opcode belongs to the set of previous opcodes, when selecting the third opcode, an opcode can be selected from the set of previous opcodes / opcode set to obtain the third opcode, and then it is continued to determine whether the third opcode belongs to the set of previous opcodes until the nth opcode belonging to the set of previous opcodes is selected as the first opcode. Then, a second opcode, i.e., the (n + 1)th opcode, is selected from the set of subsequent opcodes corresponding to the first opcode. This second opcode can form a dependent opcode pair with the first opcode. For this (n + 1)th opcode, its corresponding target instruction can be generated according to the preset dependency relationship and the dependency register encoding corresponding to the previous opcode in the dependent opcode pair, and the instruction generated according to the nth opcode is the target instruction.

[0079] Continuing the above example, if the first selected opcode is BEQ, since the first selected opcode does not belong to the set of previous opcodes INST_SET, it can be determined that the first opcode is an independent opcode. Then, the second opcode can be continuously selected from the opcode set or the set of previous opcodes INST_SET. If the second selected opcode is ADD, since the second selected opcode belongs to the set of previous opcodes INST_SET, the second opcode ADD can be used as the first opcode, and an opcode is selected from the set of subsequent opcodes ADD_SET = [ADD, ORI, BEQ] as the second opcode (for example, BEQ), that is, the third opcode. Then, the first opcode is an independent opcode, and the second opcode and the third opcode form a dependent opcode pair. The independent instruction of the first opcode and the target instruction corresponding to the second opcode can be randomly generated, and the target instruction corresponding to the third opcode can be generated according to the target instruction corresponding to the second opcode.

[0080] In the embodiments of the present invention, an opcode can be selected from the opcode set to determine the inclusion relationship between the opcode and the set of previous opcodes; in the case where the inclusion relationship is inclusion, the opcode is used as the first opcode; in the case where the inclusion relationship is non-inclusion, the opcode is used as an independent opcode, and an opcode is reselected from the opcode set as the first opcode. This helps to improve the complexity and randomness of the subsequent obtained instruction stream, and helps to improve the accuracy of in-core testing through the instruction stream.

[0081] Optionally, in some embodiments, the target instruction can be determined through the following steps:

[0082] Step A1: Based on the preset dependency relationship, obtain the dependent register encoding from the target instruction corresponding to the previous opcode in the dependent opcode pair.

[0083] In the embodiments of the present invention, the target instructions corresponding to the opcodes in each dependent opcode pair can be generated in the selected order. For the latter opcode in each dependent opcode pair, its target instruction can be determined according to the target instruction corresponding to the previous opcode in the dependent opcode pair where it is located; for the previous opcode in each dependent opcode pair, its target instruction can be randomly generated. It should be noted that since the previous opcode of a dependent opcode may belong to the latter opcode of the previous dependent opcode pair, in this case, the dependent opcode generates the corresponding target instruction as the latter opcode of the previous dependent opcode pair.

[0084] In the embodiments of the present invention, the dependent register encoding represents the encoding of the register that the previous opcode in the dependent opcode pair needs to be consistent with the latter opcode under the preset dependency relationship. Exemplarily, in the write-after-read dependency relationship, the destination register of the previous opcode serves as the dependent register; in the read-after-write dependency relationship, one of the source registers of the previous opcode serves as the dependent register.

[0085] Step A2: Based on the preset dependency relationship and the dependent register encoding, determine the target instruction corresponding to the latter opcode in the dependent opcode pair.

[0086] In the embodiments of the present invention, the target instruction corresponding to the latter opcode in the dependent opcode pair can be determined based on the preset dependency relationship and the dependent register encoding corresponding to the previous opcode in the dependent opcode pair.

[0087] Continuing with the above example, if the first opcode extracted is ADD and the second opcode is BEQ, then the target instruction corresponding to the first opcode ADD can be randomly generated, such as "ADD rd=16 rs1=3 rs2=9", and 16 is used as one of the source register encodings of the target instruction corresponding to the second opcode BEQ, and other register encodings are randomly generated, for example, "BEQ rs1=16 rs2=23" can be obtained.

[0088] In an embodiment of the present invention, a dependency register encoding can be obtained from a target instruction corresponding to a previous operation code in a dependency operation code pair based on a preset dependency relationship; based on the preset dependency relationship and the dependency register encoding, a target instruction corresponding to a subsequent operation code in the dependency operation code pair is determined, so that the target instructions generated by the dependency operation code pair can have corresponding register encodings, which helps to improve the efficiency and accuracy of the subsequent generated instruction stream.

[0089] Optionally, in some embodiments, the target instruction can also be determined through the following steps:

[0090] Step B1, randomly generate a target instruction corresponding to the previous operation code and a target instruction corresponding to the subsequent operation code in the dependency operation code pair.

[0091] In an embodiment of the present invention, the same dependency operation code pair can appear multiple times during the selection process. For each selected dependency operation code pair, corresponding target instructions can be randomly generated for both the previous operation code and the subsequent operation code in the dependency operation code pair. Among them, the same dependency operation code pair means a dependency operation code pair in which the previous operation code is the same and the subsequent operation code is also the same.

[0092] Exemplarily, if a sequence of 4 operation codes is obtained through selection: [operation code 1, operation code 2, operation code 3, operation code 4]. Among them, operation code 1 can be the same as operation code 3, operation code 2 can be the same as operation code 4, operation code 1 and 2 can form a dependency operation code pair, and operation code 3 and 4 can form another dependency operation code pair, then these two dependency operation code pairs belong to the same dependency operation code pair.

[0093] Step B2, when there is the same dependency register encoding corresponding to the preset dependency relationship between the target instruction corresponding to the subsequent operation code and the target instruction corresponding to the previous operation code, delete the subsequent operation code from the set of subsequent operation codes corresponding to the first operation code.

[0094] In the embodiments of the present invention, since the target instructions corresponding to the latter opcode and the former opcode in the dependency opcode pair can be randomly generated, the dependency register encodings of these two target instructions may be the same or different, that is, these two target instructions may have the same dependency register encoding corresponding to the preset dependency relationship, or may not have the same dependency register encoding corresponding to the preset dependency relationship. Exemplarily, in the case where the preset dependency relationship is a read-after-write dependency relationship, if the target instruction corresponding to the latter opcode ADD in a dependency opcode pair is ADD14 17 54, and the target instruction corresponding to the former opcode SUB is SUB 17 34 38, then the destination register encoding 17 of the target instruction of the former opcode SUB is the same as the source register encoding 17 of the target instruction of the latter opcode ADD, and these two target instructions have the same dependency register encoding 17 corresponding to the preset dependency relationship.

[0095] If the target instructions corresponding to the latter opcode and the former opcode in a dependency opcode pair do not contain the same dependency register encoding, then the latter opcode is continued to be retained in the subsequent opcode set corresponding to the former opcode, so that the dependency opcode pair can still be selected in the subsequent selection process to randomly generate the corresponding target instructions. If the target instructions corresponding to the latter opcode and the former opcode in a dependency opcode pair contain the same dependency register encoding, it indicates that the dependency instruction pair corresponding to the dependency opcode has been generated, and the latter opcode can be deleted from the subsequent opcode set corresponding to the former opcode, so that the dependency opcode pair will not be generated in the subsequent selection process.

[0096] In the embodiments of the present invention, by randomly generating the target instructions corresponding to the former opcode and the latter opcode in the dependency opcode pair; in the case where the target instruction corresponding to the latter opcode and the target instruction corresponding to the former opcode have the same dependency register encoding corresponding to the preset dependency relationship, the latter opcode is deleted from the subsequent opcode set corresponding to the first opcode. It is possible to generate multiple different instruction sets for a dependency opcode pair and ensure that one of the instruction sets belongs to the dependency instruction pair of the dependency opcode pair, avoiding repeated generation of multiple dependency instruction pairs for the same dependency opcode pair and improving the instruction generation efficiency.

[0097] Optionally, in some embodiments, after obtaining any dependency opcode pair, the latter opcode of the dependency opcode pair is deleted from the subsequent opcode set corresponding to the former opcode of the dependency opcode pair.

[0098] Exemplarily, the first operation code can be selected, and an operation code can be selected from the subsequent operation code set corresponding to the first operation code as the second operation code, to obtain a dependent operation code pair composed of the first operation code and the second operation code, and then the second operation code can be deleted from the subsequent operation code set corresponding to the first operation code. Thereby, it is avoided to repeatedly obtain the same dependent operation code pair composed of the first operation code and the second operation code during the subsequent selection process, and the efficiency of obtaining all dependent operation code pairs is improved. Correspondingly, after obtaining any dependent operation code pair, the second operation code in the dependent operation code pair can also be deleted from the subsequent operation code set corresponding to the first operation code in the dependent operation code pair.

[0099] Optionally, in some embodiments, after deleting an operation code from any subsequent operation code set, the following steps may further be included:

[0100] Step C1, detecting whether the subsequent operation code set is empty.

[0101] In the embodiments of the present invention, after an operation code in any subsequent operation code set is deleted, the subsequent operation code set can be detected to determine whether the subsequent operation code set is empty.

[0102] Step C2, in the case where it is detected that the subsequent operation code set is empty, deleting the operation code corresponding to the subsequent operation code set from the previous operation code set.

[0103] In the embodiments of the present invention, if it is detected that a subsequent operation code set is empty, it indicates that the subsequent operation code set no longer contains any operation codes, that is, all dependent operation code pairs that can be formed between the subsequent operation code set and its corresponding operation code have been selected, and the operation code corresponding to the subsequent operation code set can be directly deleted from the previous operation code set. If it is detected that the subsequent operation code set is not empty, it indicates that the subsequent operation code set still contains operation codes, and the subsequent operation code set can be retained to continue selecting dependent operation code pairs.

[0104] Step C3, in the case where it is detected that the previous operation code set is empty, determining that all dependent operation code pairs corresponding to the preset dependency relationship are obtained.

[0105] In the embodiments of the present invention, after deleting an operation code from the previous operation code set, the previous operation code set can be detected to determine whether the previous operation code set is empty. In the case where it is detected that the previous operation code set is empty, it can be indicated that all dependent operation code pairs of the corresponding preset dependency relationship have been selected and generated, and all dependent operation code pairs corresponding to the preset dependency relationship can be determined.

[0106] In an embodiment of the present invention, after deleting an opcode from any subsequent opcode set, it is detected whether the subsequent opcode set is empty; when it is detected that the subsequent opcode set is empty, the opcode corresponding to the subsequent opcode set is deleted from the previous opcode set; when it is detected that the previous opcode set is empty, all dependent opcode pairs corresponding to a preset dependency relationship are determined. It is possible to timely remove the opcode that has formed a dependent opcode pair from the subsequent opcode set, and timely remove the opcode that has formed all possible dependent opcode pairs from the previous opcode, which can avoid the repeated generation of dependent opcode pairs and improve the efficiency of traversing all dependent opcode pairs corresponding to the preset dependency relationship.

[0107] As Figure 2 shown, after generating the target instruction of the subsequent opcode according to the target instruction of the previous opcode, the subsequent opcode can be removed from the subsequent opcode set corresponding to the previous opcode, and then it is determined whether the subsequent opcode set corresponding to the previous opcode is empty. If the determination result is no, the selection of the next opcode continues. If the determination result is yes, the previous opcode is removed from the previous opcode set, and then it is determined whether the previous opcode set is empty. If the determination result is no, the selection of the next opcode continues. If the determination result is yes, the selection stops and the required instruction stream is obtained.

[0108] Exemplarily, if the instruction set architecture of a processor to be tested contains a total of 4 opcodes, namely ADD, LUI, ORI, and BEQ. For the read-after-write dependency, the corresponding set of preceding opcodes INST_SET = [ADD, LUI, ORI] can be determined. The set of subsequent opcodes ADD_SET corresponding to ADD = [ADD, ORI, BEQ], the set of subsequent opcodes LUI_SET corresponding to LUI = [ADD, ORI, BEQ], and the set of subsequent opcodes ORI_SET corresponding to ORI = [ADD, ORI, BEQ]. If the first opcode ADD is randomly selected from the opcode set and random encodings are generated for its registers: destination register rd = 16, one source register rs1 = 3, and another source register rs2 = 9, then the target instruction corresponding to the first opcode ADD can be obtained as "ADD rd = 16 rs1 = 3 rs2 = 9". Since the first opcode ADD belongs to the set of preceding opcodes INST_SET, the second opcode BEQ can be randomly selected from the set of subsequent opcodes ADD_SET corresponding to ADD. Under the condition that the encoding of one source register corresponding to the second opcode BEQ is the same as the encoding of the destination register (16) of the target instruction corresponding to the first opcode ADD, the target instruction corresponding to the second opcode BEQ is randomly generated as "BEQ rs1 = 16 rs2 = 23", and the opcode BEQ can be removed from the set of subsequent opcodes ADD_SET corresponding to ADD to obtain the updated ADD_SET = [ADD, ORI]. Since BEQ does not belong to the set of preceding opcodes INST_SET, the third opcode LUI can be randomly selected from the set of preceding opcodes INST_SET, and its corresponding target instruction is randomly generated as "LUI rd = 4". Since LUI belongs to the set of preceding opcodes INST_SET, the fourth opcode ADD can be randomly selected from the set of subsequent opcodes LUI_SET = [ADD, ORI, BEQ] corresponding to the opcode LUI to form a dependent opcode pair with the third opcode LUI. Based on the third opcode LUI, with 4 as the source register encoding, the target instruction is randomly generated as "ADD rd = 19 rs1 = 4 rs2 = 30", and the opcode ADD is deleted from the set of subsequent opcodes LUI_SET to obtain the updated set of subsequent opcodes ORI_SET = [ORI, BEQ].Since ADD belongs to the set of pre-order operation codes, the 5th operation code randomly selected from the set of post-order operation codes ADD_SET is ADD, which forms a dependent operation code pair with the 4th operation code ADD. Based on the 5th operation code being ADD and the source register encoding 19, the target instruction corresponding to the 5th operation code ADD is randomly generated as "ADD rd=17 rs1=12 rs2=19", and the operation code ADD is deleted from the set of post-order operation codes ADD_SET. The updated ADD_SET = [ORI].

[0109] Since ADD belongs to the set of pre-order operation codes, the 6th operation code randomly selected from the set of post-order operation codes ADD_SET is ORI, which forms a dependent operation code pair with the 5th operation code ADD. Based on the 6th operation code being ORI and the source register encoding 17, the target instruction corresponding to the 6th operation code ORI is randomly generated as "ORI rs1=17", and the operation code ORI is deleted from the set of post-order operation codes ADD_SET. The updated ADD_SET = []. Since the set of post-order operation codes ADD_SET is empty, the corresponding operation code ADD is deleted from the set of pre-order operation codes. The updated set of pre-order operation codes INST_SET = [LUI, ORI]. And so on, the 7th to 14th operation codes selected can be BEQ, ORI, ADD, LUI, ORI, ORI, LUI, BEQ respectively. The target instructions generated by the 1st to 14th operation codes, the corresponding operation codes and operands can be as shown in Table 1 below:

[0110] Table 1

[0111]

[0112] Since after selecting the 14th operation code BEQ as above, the operation code BEQ is deleted from the LUI_SET, and the updated LUI_SET is empty, then after deleting the operation code LUI from the set of pre-order operation codes INST_SET, the set of pre-order operation codes INST_SET is updated to be empty. At this time, it can be determined that all possible dependent operation code pairs under the write-after-read dependency relationship have been obtained.

[0113] Optionally, in some embodiments, after the step of obtaining the instruction stream composed of each target instruction, instruction streams corresponding to multiple preset dependency relationships can also be spliced to obtain the target instruction stream; or, between the dependent instruction pairs of the instruction stream corresponding to the preset dependency relationship, the dependent instruction pairs of the instruction stream corresponding to other preset dependency relationships can be inserted to obtain the target instruction stream.

[0114] In the embodiments of the present invention, in order to improve the test efficiency, the above-mentioned instruction stream generation method can be adopted to separately generate instruction streams corresponding to different preset dependency relationships, and then combine the instruction streams corresponding to different preset dependency relationships to obtain a target instruction stream including dependency instruction pairs with different preset dependency relationships. Thus, a variety of instruction combinations with different dependency relationships can be tested through one target instruction stream, which helps to further improve the efficiency of testing the CPU through the instruction stream.

[0115] Specifically, in one implementation, the instruction streams corresponding to multiple preset dependency relationships can be directly concatenated at the head and tail to obtain the target instruction stream. In another implementation, the dependency instruction pairs of the instruction streams corresponding to other preset dependency relationships can be inserted between the dependency instruction pairs of the instruction streams corresponding to the preset dependency relationships to obtain the target instruction stream. Among them, the dependency instruction pair represents a pair of instructions with the same dependency register encoding generated for the dependency opcode pair. The above insertion methods can include but are not limited to random insertion, sequential insertion, reverse insertion, etc., and the embodiments of the present invention do not make specific limitations.

[0116] Refer to Figure 3 , which shows a block diagram of an instruction stream generation device provided by an embodiment of the present invention. As Figure 3 shown, the device may specifically include:

[0117] The first opcode module 301 is used to select an opcode from the opcode set as the first opcode; wherein, the first opcode belongs to the set of previous opcodes, and the set of previous opcodes is determined from the opcode set based on the preset dependency relationship;

[0118] The second opcode module 302 is used to select an opcode from the set of subsequent opcodes corresponding to the first opcode as the second opcode to obtain a dependency opcode pair composed of the first opcode and the second opcode; wherein, the set of subsequent opcodes is determined from the opcode set based on the preset dependency relationship;

[0119] The dependency opcode pair module 303 is used to obtain the next dependency opcode pair from the opcode set based on the inclusion relationship between the second opcode and the set of previous opcodes until all the dependency opcode pairs corresponding to the preset dependency relationship are obtained;

[0120] The instruction stream module 304 is used to obtain the target instructions generated for each opcode in each dependency opcode pair to obtain an instruction stream composed of each target instruction; wherein, the target instructions corresponding to the opcodes in the same dependency opcode pair have the same register encoding, and the instruction stream is used to test the central processing unit.

[0121] Optionally, the device further includes:

[0122] A dependency register encoding module, configured to obtain a dependency register encoding from a target instruction corresponding to a previous opcode in a dependency opcode pair based on the preset dependency relationship;

[0123] A first target instruction module, configured to determine a target instruction corresponding to a subsequent opcode in the dependency opcode pair based on the preset dependency relationship and the dependency register encoding.

[0124] Optionally, the apparatus further includes:

[0125] A second target instruction module, configured to randomly generate a target instruction corresponding to a previous opcode and a target instruction corresponding to a subsequent opcode in the dependency opcode pair;

[0126] A first deletion module, configured to delete the subsequent opcode from a set of subsequent opcodes corresponding to the first opcode when there is the same dependency register encoding corresponding to the preset dependency relationship between the target instruction corresponding to the subsequent opcode and the target instruction corresponding to the previous opcode.

[0127] Optionally, the apparatus further includes:

[0128] A second deletion module, configured to delete the subsequent opcode in the dependency opcode pair from a set of subsequent opcodes corresponding to the previous opcode in the dependency opcode pair after obtaining any dependency opcode pair.

[0129] Optionally, the apparatus further includes:

[0130] A detection sub-module, configured to detect whether the set of subsequent opcodes is empty after deleting an opcode from any set of subsequent opcodes;

[0131] A previous opcode set deletion sub-module, configured to delete the opcode corresponding to the set of subsequent opcodes from the set of previous opcodes when it is detected that the set of subsequent opcodes is empty;

[0132] A determination sub-module, configured to determine that all dependency opcode pairs corresponding to the preset dependency relationship are obtained when it is detected that the set of previous opcodes is empty.

[0133] Optionally, the apparatus further includes:

[0134] A target instruction stream module, configured to splice instruction streams corresponding to multiple preset dependency relationships to obtain a target instruction stream; or insert instruction pairs corresponding to other preset dependency relationships between dependency instruction pairs of the instruction stream corresponding to the preset dependency relationship to obtain a target instruction stream.

[0135] Optionally, the first opcode module includes:

[0136] A relationship sub-module, configured to select an operation code from an operation code set and determine an inclusion relationship between the operation code and the set of previous operation codes;

[0137] A first selection sub-module, configured to use the operation code as a first operation code when the inclusion relationship is inclusion;

[0138] A second selection sub-module, configured to use the operation code as an independent operation code when the inclusion relationship is non-inclusion, and re-select an operation code from the operation code set as the first operation code; wherein, the independent operation code is used to generate the independent operation code included in the instruction stream.

[0139] Optionally, the preset dependency relationship includes a write-after-read dependency relationship, a write-after-write dependency relationship, a read-after-write dependency relationship, or a read-after-read dependency relationship.

[0140] In summary, in the instruction stream generation device provided by the embodiment of the present invention, an operation code is selected from an operation code set as a first operation code; wherein, the first operation code belongs to a set of previous operation codes, and the set of previous operation codes is determined from the operation code set based on a preset dependency relationship; an operation code is selected from the set of subsequent operation codes corresponding to the first operation code as a second operation code to obtain a dependency operation code pair composed of the first operation code and the second operation code; wherein, the set of subsequent operation codes is determined from the operation code set based on a preset dependency relationship; based on the inclusion relationship between the second operation code and the set of previous operation codes, the next dependency operation code pair is obtained from the operation code set until all dependency operation code pairs corresponding to the preset dependency relationship are obtained; target instructions generated for each operation code in each dependency operation code pair are obtained to obtain an instruction stream composed of each target instruction; wherein, the target instructions corresponding to the operation codes in the same dependency operation code pair have the same register encoding, and the instruction stream is used to test a central processing unit. In this way, all dependency operation code pairs under a preset dependency relationship can be efficiently generated, and the instruction stream generated according to these dependency operation code pairs can include all possible instruction combination methods with a preset dependency relationship, which helps to improve the accuracy of testing the CPU through the instruction stream. And because the operation codes can be specifically selected from the set of subsequent operation codes of the operation code to form a dependency operation code pair, the efficiency of selecting the dependency operation code pair can be improved to a certain extent, which helps to increase the instruction density of the instructions with a dependency relationship in the generated instruction stream, thereby reducing the length of the instruction stream required to test the CPU and improving the efficiency of testing the CPU with the instruction stream.

[0141] Refer to Figure 4 FIG. is a schematic structural diagram of an electronic device provided by an embodiment of the present invention. As Figure 4As shown in the figure, the electronic device includes: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface complete communication with each other through the communication bus. The memory is used to store at least one executable instruction, and the executable instruction causes the processor to execute the instruction stream generation method of the foregoing embodiment. The executable instructions can form a program.

[0142] An embodiment of the present invention provides a computer-readable storage medium, on which instructions are stored. When executed by one or more processors, the instructions enable the processors to execute the instruction stream generation method of the foregoing embodiment.

[0143] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is the difference from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0144] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a device, or a computer program product. Therefore, the embodiments of the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memories, CD-ROMs, optical memories, etc.) containing computer-usable program codes. It should be noted that all actions of obtaining signals, information, or data in the present invention are carried out on the premise of complying with the corresponding data protection regulations and policies of the country where it is located and obtaining authorization from the owner of the corresponding device. The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, and the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processors of general-purpose computers, special-purpose computers, embedded processors, or other programmable data processing terminal devices to generate a machine, so that the instructions executed by the processors of the computer or other programmable data processing terminal devices generate a device for implementing the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0145] These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing terminal device to work in a predictive manner, so that the instructions stored in the computer-readable memory generate a manufactured product including an instruction device, and the instruction device implements the functions in the process Figure 1 one process or multiple processes and / or blocksFigure 1 The functions specified in one or more boxes.

[0146] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device, so that a series of operation steps are executed on the computer or other programmable terminal device to generate a computer-implemented process. Thus, the instructions executed on the computer or other programmable terminal device provide steps for implementing the functions specified in one Figure 1 One process or more processes and / or boxes Figure 1 The steps of the functions specified in one or more boxes.

[0147] Although the preferred embodiments of the embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications to these embodiments once they learn the basic creative concept. Therefore, the appended claims are intended to be construed as including the preferred embodiments and all changes and modifications falling within the scope of the embodiments of the present invention.

[0148] Finally, it should also be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or terminal device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or terminal device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the existence of additional identical elements in the process, method, article or terminal device comprising the element.

[0149] The above has introduced in detail an instruction stream generation method, an instruction stream generation device, an electronic device and a storage medium provided by the present invention. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A method for generating an instruction stream, characterized in that: The method comprises: Select an opcode from the opcode set as a first opcode; wherein the first opcode belongs to a preceding opcode set, and the preceding opcode set is determined from the opcode set based on a preset dependency relationship; Selecting an opcode from a post-order opcode set corresponding to the first opcode as a second opcode, and obtaining a dependent opcode pair consisting of the first opcode and the second opcode; wherein the post-order opcode set is determined from the opcode set based on the preset dependency relationship; Based on the inclusion relationship between the second opcode and the preceding opcode set, obtaining a next dependent opcode pair from the opcode set until all dependent opcode pairs corresponding to the preset dependency relationship are obtained; Obtaining target instructions generated for each opcode in each dependent opcode pair, and obtaining an instruction stream composed of each target instruction; wherein the target instructions corresponding to the opcodes in the same dependent opcode pair have the same register encoding, and the instruction stream is used to test the central processing unit; The instruction streams corresponding to multiple preset dependencies are spliced ​​together to obtain the target instruction stream.

2. The instruction stream generation method according to claim 1, characterized in that: The method further comprises: Based on the preset dependency relationship, obtaining a dependent register encoding from a target instruction corresponding to a previous opcode in a dependent opcode pair; Based on the preset dependency relationship and the dependent register encoding, a target instruction corresponding to a latter opcode in the dependent opcode pair is determined.

3. The instruction stream generation method according to claim 1, characterized in that: The method further comprises: After obtaining any dependent opcode pair, the subsequent opcode of the dependent opcode pair is deleted from the subsequent opcode set corresponding to the previous opcode of the dependent opcode pair.

4. The instruction stream generation method according to claim 3, characterized in that: The method further comprises: After deleting an opcode from any subsequent opcode set, detecting whether the subsequent opcode set is empty; When it is detected that the post-order operation code set is empty, deleting the operation code corresponding to the post-order operation code set from the pre-order operation code set; When it is detected that the preceding operation code set is empty, all dependent operation code pairs corresponding to the preset dependency relationship are determined.

5. The instruction stream generation method according to claim 1, characterized in that: The method further comprises: Randomly generate a target instruction corresponding to a previous opcode and a target instruction corresponding to a subsequent opcode in the dependent opcode pair; When the target instruction corresponding to the subsequent opcode and the target instruction corresponding to the previous opcode have the same dependent register encoding corresponding to the preset dependency relationship, the subsequent opcode is deleted from the subsequent opcode set corresponding to the first opcode.

6. The instruction stream generation method according to claim 1, characterized in that: The method further comprises: Between the dependent instruction pairs of the instruction stream corresponding to the preset dependency relationship, the dependent instruction pairs of the instruction stream corresponding to other preset dependency relationships are inserted to obtain the target instruction stream.

7. The instruction stream generation method according to claim 1, characterized in that: The step of selecting an operation code from the operation code set as the first operation code comprises: Select an operation code from the operation code set, and determine the inclusion relationship between the operation code and the preceding operation code set; When the inclusion relationship is inclusion, the operation code is used as the first operation code; When the inclusion relationship is non-inclusion, the opcode is used as an independent opcode, and an opcode is reselected from the opcode set as the first opcode; wherein the independent opcode is used to generate an independent opcode included in the instruction stream.

8. The instruction stream generation method according to claim 1, characterized in that: The preset dependency relationship includes a read-after-write dependency relationship, a write-after-write dependency relationship, a read-after-write dependency relationship, or a read-after-read dependency relationship.

9. An instruction stream generating device, characterized in that: The device comprises: A first operation code module, configured to select an operation code from the operation code set as a first operation code; wherein the first operation code belongs to a preceding operation code set, and the preceding operation code set is determined from the operation code set based on a preset dependency relationship; a second operation code module, configured to select an operation code from a post-order operation code set corresponding to the first operation code as a second operation code, and obtain a dependent operation code pair consisting of the first operation code and the second operation code; wherein the post-order operation code set is determined from the operation code set based on the preset dependency relationship; A dependent opcode pair module, configured to obtain a next dependent opcode pair from the opcode set based on an inclusion relationship between the second opcode and the preceding opcode set, until all dependent opcode pairs corresponding to the preset dependency relationship are obtained; An instruction stream module, used for acquiring target instructions generated for each opcode in each dependent opcode pair, and obtaining an instruction stream composed of each target instruction; wherein the target instructions corresponding to the opcodes in the same dependent opcode pair have the same register encoding, and the instruction stream is used for testing the central processing unit; The target instruction stream module is used to splice the instruction streams corresponding to multiple preset dependencies to obtain the target instruction stream.

10. An electronic device, characterized in that: include: A processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store executable instructions, and the executable instructions enable the processor to execute the instruction stream generation method according to any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that: Instructions are stored thereon, and when executed by one or more processors, the processors are caused to execute the instruction stream generation method according to any one of claims 1 to 8.

Images