Data interaction method and device, electronic equipment and storage medium
By setting a transparent transmission channel on the FPGA end and using the system on chip to replace the FPGA for PCIe device enumeration data interaction, the problem of difficulty in expansion and long iteration cycle during the FPGA enumeration implementation is solved, and more efficient system updates and stability improvements are achieved.
Patent Information
- Application Number
- CN202411706812.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-26
- Publication Date
- 2025-04-11
AI Technical Summary
The PCIe device enumeration implementation process based on FPGA has problems such as difficulty in scaling and long iteration cycle.
By setting a transparent transmission channel at the field programmable gate array, a data interaction channel between the host side and the on-chip system end is established, and the enumeration data interaction of PCIe devices is replaced by the FPGA, and transparent transmission of related configuration packets is achieved through the transparent transmission channel.
The system update iteration cycle is reduced, the system stability is improved, and the system development and expansion is reduced by utilizing the rich storage resources and software characteristics of the system on chip.
Smart Images
Figure CN119806857A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of communication technology, and in particular to a data interaction method and device, electronic equipment, and a storage medium. Background Art
[0002] Cloud computing usually refers to obtaining the required resources (hardware, platform, software) through the network in an on-demand and easily scalable manner. The network that provides resources is called the "cloud". The resources in the "cloud" are infinitely scalable in the eyes of users, and can be obtained at any time, used on demand, expanded at any time, and paid for by use. This feature is often referred to as using IT infrastructure like water and electricity.
[0003] A cloud host is an IT infrastructure that is configured with certain resources according to user needs. The current cloud host solution based on FPGA (Field Programmable Gate Array) generally communicates with the FPGA board through the PCIe (Peripheral Component Interconnect Express) bus. The FPGA completes the data interaction with the host and implements the enumeration process of the PCIe device.
[0004] However, the FPGA-based PCIe device enumeration implementation process is limited by the FPGA on-chip resources and its hardware characteristics, and has the disadvantages of being difficult to expand and having a long iteration cycle. Summary of the invention
[0005] In view of the above problems, a data interaction method and device, electronic device, and storage medium are proposed to overcome the above problems or at least partially solve the above problems, including:
[0006] A data interaction method is applied to a field programmable gate array end, the method comprising:
[0007] In response to a device enumeration requirement of the host side; establishing a transparent transmission channel between the host side and the system on chip side through the field programmable gate array side; wherein the device enumeration requirement is a device enumeration requirement generated when the host side performs a device loading operation;
[0008] Obtaining an enumeration request data packet sent by the host end, and sending the enumeration request data packet to the system-on-chip end through the transparent transmission channel; wherein the system-on-chip end is used to obtain the enumeration request data packet through the transparent transmission channel, and parse the enumeration request data packet to generate a return data packet;
[0009] The return data packet is obtained, and the return data packet is sent to the host end through the transparent transmission channel.
[0010] Optionally, sending the enumeration request data packet to the system on chip end through the transparent transmission channel includes:
[0011] Under the condition that the enumeration request data packet is used as a payload, encapsulating the enumeration request data packet to generate a memory write data packet;
[0012] The memory write data packet is written into the memory of the system on chip through the transparent transmission channel.
[0013] Optionally, the obtaining the returned data packet includes:
[0014] In response to the return notification sent by the system-on-chip end, the return data packet is obtained in the target memory area of the system-on-chip end; wherein the system-on-chip end is further used to store the return data packet in the target memory area and send the return notification to the field programmable gate array end in response to the generation of the return data packet;
[0015] Optionally, sending the return data packet to the host end through the transparent transmission channel includes:
[0016] Performing a credit query on the returned data packet to obtain a credit query result, and performing conversion processing on the returned data packet according to the credit query result;
[0017] The converted return data packet is sent to the host end through the transparent transmission channel.
[0018] Optionally, converting the returned data packet according to the credit query result includes:
[0019] According to the credit query result, the return data packet is converted into a response operation request data packet or a response operation request data packet carrying data.
[0020] Optionally, sending the converted return data packet to the host end through the transparent transmission channel includes:
[0021] The response operation request data packet or the response operation request data packet carrying data is sent to the host end through the transparent transmission channel.
[0022] A data interaction method, applied to a system-on-chip end, comprises:
[0023] An enumeration request data packet is obtained through a transparent transmission channel set at a field programmable gate array end, and the enumeration request data packet is parsed to generate a return data packet; wherein the field programmable gate array end is used to respond to the device enumeration demand of the host end; the transparent transmission channel between the host end and the system on chip end is established through the field programmable gate array end; the enumeration request data packet sent by the host end is obtained, and the enumeration request data packet is sent to the system on chip end through the transparent transmission channel; wherein the device enumeration demand is the device enumeration demand generated when the host end performs a device loading operation.
[0024] Optionally, the method further includes:
[0025] In response to the generation of the return data packet, the return data packet is stored in a target memory area and a return notification is sent to the field programmable gate array end; wherein the field programmable gate array end is also used to respond to the return notification issued by the system on chip end and obtain the return data packet in the target memory area of the system on chip end.
[0026] A data interaction device, applied to a field programmable gate array end, comprising:
[0027] A transparent transmission channel establishment module is used to respond to the device enumeration requirement of the host end; establish a transparent transmission channel between the host end and the system on chip end through the field programmable gate array end; wherein the device enumeration requirement is a device enumeration requirement generated when the host end performs a device loading operation;
[0028] An enumeration request data packet sending module is used to obtain the enumeration request data packet sent by the host end, and send the enumeration request data packet to the system-on-chip end through the transparent transmission channel; wherein the system-on-chip end is used to obtain the enumeration request data packet through the transparent transmission channel, and parse the enumeration request data packet to generate a return data packet;
[0029] The return data packet acquisition module is used to acquire the return data packet and send the return data packet to the host end through the transparent transmission channel.
[0030] A data interaction device, applied to a system-on-chip end, comprising:
[0031] An enumeration request packet parsing module is used to obtain an enumeration request packet through a transparent transmission channel set on a field programmable gate array end, and parse the enumeration request packet to generate a return packet; wherein the field programmable gate array end is used to respond to the device enumeration demand of the host end; establish the transparent transmission channel between the host end and the system on chip end through the field programmable gate array end; obtain the enumeration request packet sent by the host end, and send the enumeration request packet to the system on chip end through the transparent transmission channel; wherein the device enumeration demand is the device enumeration demand generated when the host end performs a device loading operation.
[0032] An electronic device comprises a processor, a memory and a computer program stored in the memory and capable of running on the processor, wherein the computer program implements the data interaction method as described above when executed by the processor.
[0033] A computer-readable storage medium, characterized in that a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the data interaction method as described above is implemented.
[0034] A computer program product includes a computer program, and when the computer program is executed by a processor, the computer program implements the data interaction method as described above.
[0035] The embodiments of the present invention have the following advantages:
[0036] The present invention provides a data interaction method, which is applied to a field programmable gate array end and is provided with a transparent transmission channel, by responding to the device enumeration demand of the host end; establishing a transparent transmission channel between the host end and the system on chip end through the field programmable gate array end; then obtaining an enumeration request data packet sent by the host end, and sending the enumeration request data packet to the system on chip end through the transparent transmission channel; wherein the system on chip end is used to obtain the enumeration request data packet through the transparent transmission channel, and parse the enumeration request data packet to generate a return data packet; and then obtain the return data packet and send the return data packet to the host end through the transparent transmission channel. The enumeration data interaction process of the PCIe device is realized by replacing the FPGA with the SOC (system on chip), and the transparent transmission channel set by the FPGA end is used to realize the transparent transmission of the relevant configuration package, which can not only reduce the development and expansion difficulty of the system itself based on the rich storage resources and software characteristics of the SOC, but also enable the FPGA resources to focus more effectively on the acceleration of the data channel based on the setting of the transparent transmission channel, thereby reducing the update iteration cycle of the system and improving the stability of the system. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] In order to more clearly illustrate the technical solution of the present invention, the accompanying drawings required for use in the description of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.
[0038] Figure 1 is a flowchart of steps of a data interaction method provided by some embodiments of the present invention;
[0039] Figure 2 is an overall system architecture diagram of the present invention provided by some embodiments of the present invention;
[0040] Figure 3 It is a schematic diagram of the interaction process between the FPGA transparent transmission channel and the SoC provided in some embodiments of the present invention;
[0041] Figure 4 is a flowchart of steps of a data interaction method provided by some embodiments of the present invention;
[0042] Figure 5 is a structural schematic diagram of a data interaction device provided by some embodiments of the present invention;
[0043] Figure 6 It is a structural schematic diagram of a data interaction device provided in some embodiments of the present invention. DETAILED DESCRIPTION
[0044] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0045] In the embodiments of the present application, words such as "first" and "second" are used to distinguish between identical or similar items with basically the same functions and effects. This is only for the purpose of clearly describing the technical solutions of the embodiments of the present application, and shall not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.
[0046] In the embodiments of the present application, the terms "upper", "lower", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.
[0047] FPGA is a product further developed on the basis of programmable devices such as PAL (Programmable Array Logic) and GAL (General Array Logic). It appears as a semi-custom circuit in the field of Application Specific Integrated Circuit (ASIC), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of gate circuits of the original programmable devices.
[0048] SoC (System on Chip) is called system-level chip, also known as system on chip, which means it is a product, an integrated circuit with a dedicated purpose, which contains all the contents of a complete system and embedded software.
[0049] PCI-Express is a high-speed serial computer expansion bus standard. The enumeration process of PCI-Express devices is the process by which the system automatically discovers and configures devices connected to the PCIe bus at startup.
[0050] Cloud computing usually refers to obtaining the required resources (hardware, platform, software) through the network in an on-demand and easily scalable manner. The network that provides resources is called the "cloud". The resources in the "cloud" are infinitely scalable in the eyes of users, and can be obtained at any time, used on demand, expanded at any time, and paid for by use. This feature is often referred to as using IT infrastructure like water and electricity.
[0051] A cloud host is an IT infrastructure that has been configured with certain resources according to user needs. The current FPGA-based cloud host solution communicates with the FPGA board through the PCIe bus. The FPGA completes the interaction with the Host and realizes the creation of multiple PFs (physical functions) and VFs (virtual functions). PCIe PF (physical function) is the main entity on the PCIe bus. A PCIe device has one or more PFs, and I / O devices with SR-IOV functions can manage and create multiple VFs (virtual functions) based on the PCIe specification. Like the enumeration process of other PCIe devices, the FPGA-based PF and VF enumeration process is the process by which the system automatically discovers and configures devices connected to the PCIe bus at startup. The following are the general steps of the PCIe device enumeration process:
[0052] Bus Scan: When the computer system starts, the PCIe host controller begins scanning the PCIe bus to identify all devices connected to the bus.
[0053] Device detection: The host controller sends a specific PCIe TLP (Transaction Layer Packet, which can also be called an enumeration request packet in this scenario) to detect whether there is a PCIe device on the slot. Each device has a unique device number.
[0054] Device initialization: If a device is detected, the host controller assigns a unique device number to the device and initializes the device. This may include initializing some of the device's registers and allocating resources to the device, such as memory address space and interrupts.
[0055] Function-level enumeration: If a PCIe device supports multiple functions, the system will assign a unique function number to each function. Each function has its own set of associated registers.
[0056] Configuration space access: The system accesses the configuration space of the PCIe device through configuration transactions. The configuration space contains important information of the device, such as device ID, manufacturer ID, BAR (Base Address Registers), interrupt information, etc.
[0057] BAR Allocation: Base Address Registers (BARs) are used to tell the system how to address the memory and I / O resources of the device. The system will assign the appropriate address range to the BAR to ensure that the device can correctly address its resources in the address space.
[0058] Interrupt assignment: The system may assign interrupt vectors to devices so that the devices can notify the host system about the occurrence of specific events through interrupts.
[0059] Driver loading: Once the PCIe device is enumerated and initialized, the system will load the appropriate driver to communicate with and control the device.
[0060] In general, the PCIe device enumeration process ensures that the system can discover and effectively communicate with all connected devices. This process is defined by the PCIe specification to ensure that devices can be configured and managed correctly.
[0061] In the current big data network environment, the demand for network, storage, and computing resources is increasing. Under limited resource conditions, it is particularly important to achieve resource segmentation and high utilization. However, cloud hosts based on FPGA are limited by the on-chip resources of FPGA. The PCIe PF and PCIe VF that can be implemented by a single FPGA are limited. In addition, when the demand changes, it is necessary to iterate the FPGA version to achieve different PCIe PF and PCIe VF scales.
[0062] In order to solve the above problems, the present invention is based on the core technical concept of using SOC (system on chip) instead of FPGA to perform the enumeration data interaction process of PCIe devices, and using the transparent transmission channel set on the FPGA end to realize the transparent transmission of relevant configuration packages. The data interaction method in the related art is improved. The present invention will be described in detail in conjunction with the accompanying drawings as follows:
[0063] Reference Figure 1 , shows a flow chart of the steps of a data interaction method provided by some embodiments of the present invention, which is applied to a field programmable gate array end and may specifically include the following steps:
[0064] Step 101, in response to a device enumeration requirement of the host side, a transparent transmission channel is established between the host side and the system on chip side through the field programmable gate array side; wherein the device enumeration requirement is a device enumeration requirement generated when the host side performs a device loading operation;
[0065] In the specific implementation, as mentioned above, the host side will initiate the device enumeration process in order to realize the loading of the PCIe device. Therefore, in response to the device enumeration requirement of the host side, a transparent transmission channel between the host side and the system on chip side can be established through the field programmable gate array side, so that the complete config tlp packet (i.e., enumeration request data packet) sent by the Host (host side) is encapsulated as a payload (payload) into a Memory Write (memory write) tlp packet and written into the SoC memory through the FPGA transparent transmission channel, and the SoC actually handles the enumeration process.
[0066] like Figure 2 The figure shows the overall architecture of the present invention. The corresponding data channel (passthrouth_channel) in the figure is the pass-through channel described in the present invention. In this architecture, the management software can run on the SoC to implement the configuration of PCIe PF and PCIeVF. The host can scan the FPGA board through the PCIe interface, and the FPGA can pass the config tlp package to the SoC, which actually handles the enumeration process. The FPGA is mainly used to assume the transmission role between the host and the SoC. Since the software update of the SoC is more flexible and the resources are richer than the FPGA, the solution can expand the PCIe PF and PCIe VF more flexibly and be better applied to the current big data background.
[0067] Step 102, obtaining an enumeration request data packet sent by the host end, and sending the enumeration request data packet to the system-on-chip end through the transparent transmission channel; wherein the system-on-chip end is used to obtain the enumeration request data packet through the transparent transmission channel, and parse the enumeration request data packet to generate a return data packet;
[0068] In actual applications, the FPGA can obtain the config tlp packet sent by the host, and encapsulate the complete config tlp packet sent by the host as a payload into a Memory Write tlp packet and write it into the SoC memory through the transparent channel. After the SoC parses the tlp packet and completes the relevant processing, it can store the tlp packet (return data packet) that needs to be returned to the Host in another memory space and notify the FPGA. After receiving the corresponding notification, the FPGA can read back the tlp packet and convert it into a CPL (Completion, response operation request data packet) or CPLD (Completion with Data, response operation request data packet carrying data) packet and return it to the Host side, thus completing a data interaction between the Host and the SoC. Repeat multiple times until a complete enumeration process is completed, and the SoC sends the final configuration result to the FPGA for subsequent data channel processing. Specifically, if Figure 2 As shown in the figure, the transparent transmission channel completes a complete data interaction process between the Host and the SoC, which can be summarized as follows:
[0069] (1) FPGA diverts the tlp packets in the rx (Receive) direction of the host side, and the packets of the control channel enter the transparent transmission channel;
[0070] (2) Control the transparent transmission channel to divert traffic and access the relevant information through credit access;
[0071] (3) The complete config tlp packet is encapsulated as a payload into a Memory Write tlp packet and written into the SoC memory;
[0072] (4) After the SoC parses the TLP packet and completes related processing, it stores the TLP packet that needs to be returned to the Host into another memory space and notifies the FPGA, which then reads back the TLP packet.
[0073] (5) FPGA diverts the return data packets read back by FPGA on the SoC side;
[0074] (6) FPGA performs credit query management on the returned data packets read back from the SoC side;
[0075] (7) Based on the credit query result, the FPGA converts the return data packet into a CPL or CPLD packet and returns it to the Host side.
[0076] In some embodiments of the present invention, sending the enumeration request data packet to the system on chip through the transparent transmission channel includes:
[0077] Under the condition that the enumeration request data packet is used as a payload, encapsulating the enumeration request data packet to generate a memory write data packet;
[0078] The memory write data packet is written into the memory of the system-on-chip end through the transparent transmission channel.
[0079] In the specific implementation, the config tlp packet sent by the host can be obtained through the FPGA, and the complete config tlp packet sent by the host can be encapsulated as a payload into a Memory Write tlp packet (i.e., a memory write data packet) through the transparent transmission channel. Then, the memory write data packet can be written into the SoC memory through the transparent transmission channel for the SoC to perform corresponding processing.
[0080] Further, such as Figure 3 As shown in the figure, for the specific interaction process between the FPGA transparent transmission channel and the SoC, the FPGA transparent transmission channel and the SoC can rely on the ring mechanism to realize the data interaction between the FPGA and the SoC. For a single control channel, it is composed of the trans block ring and trans cpl ring in the rx direction, and the trans block ring and trans cpl ring in the tx (Transmit) direction. Among them, the tx trans block is used to store the complete tlp packet on the host side transmitted by the FPGA, and the txtrans cpl is used for the FPGA to write the pointer tail (tail) and tlp packet length information of the currently written tx trans block, while the rx trans block is used to store the tlp packet that needs to be returned to the host after processing by the SoC, and the rx trans cpl is used for the FPGA to write the pointer tail and tlp packet length information of the currently read rx trans block. The FPGA register internally maintains the pointer header of the SoC and the pointer tail of the FPGA, and the pointer header on the SoC side is updated by the SoC by writing to the register. The specific process can be:
[0081] (1) After the SoC and FPGA are started, the SoC performs the initialization process, applies for 4 blocks of continuous memory space for the transblock ring and trans cpl ring, and writes the ring pointer, size, header, tail and other information into the FPGA register. After completion, the FPGA's SIOErdy signal (SIOE Ready Signal) is pulled high, indicating that the transparent transmission channel is available;
[0082] (2) When the transparent transmission channel is working, the FPGA can write the Memorywrite packet encapsulated with the config tlp as the payload into the SoC tx trans block;
[0083] (3) FPGA updates FPGA tx tail, and writes FPGA tx tail and the length of the memory write packet written in step (2) to SoC tx trans cpl;
[0084] (4) SoC detects the update of tx trans cpl, reads the tlp packet in the tx trans block and parses it. After the processing is completed, the tlp packet that needs to be returned to the host is written into the rx trans block;
[0085] (5) SoC updates the SoC tx header and SoC rx header, and writes the SoC rx header into the FPGA register;
[0086] (6) When the FPGA detects the update of the SoC rx header, it will initiate a Memory Read operation to read the rx trans block of the SoC.
[0087] (7) FPGA receives and processes the tlp packet of the rx trans block returned by the SoC;
[0088] (8) FPGA updates FPGA rx tail and writes FPGA rx tail into SoC rx trans cpl;
[0089] (9)SoC detects the update of rx trans cpl and releases the corresponding rx trans block.
[0090] Step 103, obtaining the return data packet, and sending the return data packet to the host end through the transparent transmission channel;
[0091] In the specific implementation, after the SoC parses the tlp packet and completes the relevant processing, it can store the tlp packet (return data packet) that needs to be returned to the host in another memory space and notify the FPGA. After receiving the corresponding notification, the FPGA can read back the tlp packet and convert it into a CPL packet or CPLD packet and return it to the host side, thus completing a data exchange between the host and the SoC. Repeat multiple times until a complete enumeration process is completed, and the SoC sends the final configuration result to the FPGA for subsequent data channel processing.
[0092] In some embodiments of the present invention, the obtaining of the returned data packet includes:
[0093] In response to a return notification issued by the system-on-chip end, the return data packet is obtained in a target memory area of the system-on-chip end; wherein the system-on-chip end is also used to store the return data packet in the target memory area and send the return notification to the field programmable gate array end in response to the generation of the return data packet.
[0094] In actual applications, after the SoC parses the TLP packet and completes related processing, it can store the TLP packet (return data packet) that needs to be returned to the Host into another memory space (i.e., the target memory area) and send a return notification to the FPGA side. After receiving the return notification, the FPGA can read back the TLP packet in the target memory area and convert it into a CPL packet or CPLD packet and return it to the Host side.
[0095] Specifically, Figure 3As shown in the figure, for the specific interaction process between the FPGA transparent transmission channel and the SoC, the FPGA transparent transmission channel and the SoC can rely on the ring mechanism to realize the data interaction between the FPGA and the SoC. For a single control channel, it is composed of the trans block ring and trans cpl ring in the rx direction, and the trans block ring and trans cpl ring in the tx (Transmit) direction. Among them, the tx trans block is used to store the complete tlp packet on the host side transmitted by the FPGA, and the txtrans cpl is used for the FPGA to write the pointer tail (tail) and tlp packet length information of the currently written tx trans block, while the rx trans block is used to store the tlp packet that needs to be returned to the host after processing by the SoC, and the rx trans cpl is used for the FPGA to write the pointer tail and tlp packet length information of the currently read rx trans block. The FPGA register internally maintains the pointer header of the SoC and the pointer tail of the FPGA, and the pointer header on the SoC side is updated by the SoC by writing to the register. The specific process can be:
[0096] (1) After the SoC and FPGA are started, the SoC performs the initialization process, applies for 4 blocks of continuous memory space for the transblock ring and trans cpl ring, and writes the ring pointer, size, header, tail and other information into the FPGA register. After completion, the FPGA's SIOErdy signal (SIOE Ready Signal) is pulled high, indicating that the transparent transmission channel is available;
[0097] (2) When the transparent transmission channel is working, the FPGA can write the Memorywrite packet encapsulated with the config tlp as the payload into the SoC tx trans block;
[0098] (3) FPGA updates FPGA tx tail, and writes FPGA tx tail and the length of the memory write packet written in step (2) to SoC tx trans cpl;
[0099] (4) SoC detects the update of tx trans cpl, reads the tlp packet in the tx trans block and parses it. After the processing is completed, the tlp packet that needs to be returned to the host is written into the rx trans block;
[0100] (5) SoC updates the SoC tx header and SoC rx header, and writes the SoC rx header into the FPGA register;
[0101] (6) When the FPGA detects the update of the SoC rx header, it will initiate a Memory Read operation to read the rx trans block of the SoC.
[0102] (7) FPGA receives and processes the tlp packet of the rx trans block returned by the SoC;
[0103] (8) FPGA updates FPGA rx tail and writes FPGA rx tail into SoC rx trans cpl;
[0104] (9)SoC detects the update of rx trans cpl and releases the corresponding rx trans block.
[0105] In some embodiments of the present invention, sending the return data packet to the host end through the transparent transmission channel includes:
[0106] Performing a credit query on the returned data packet to obtain a credit query result, and performing conversion processing on the returned data packet according to the credit query result;
[0107] The converted return data packet is sent to the host end through the transparent transmission channel.
[0108] In a specific implementation, after reading back the return data packet, the FPGA can divert the return data packet and perform credit query management on the return data packet. The FPGA can then convert the return data packet according to the credit query result, for example, it can convert the return data packet into a CPL or CPLD packet, and send the converted return data packet to the host end through a transparent channel.
[0109] In some embodiments of the present invention, the converting process of the returned data packet according to the credit query result includes:
[0110] According to the credit query result, the return data packet is converted into a response operation request data packet or a response operation request data packet carrying data.
[0111] In a specific implementation, the FPGA can convert the return data packet into a CPL or CPLD packet according to the credit query result, and send the converted return data packet to the host end through a transparent channel.
[0112] In some embodiments of the present invention, sending the converted return data packet to the host end through the transparent transmission channel includes:
[0113] The response operation request data packet or the response operation request data packet carrying data is sent to the host end through the transparent transmission channel.
[0114] In practical applications, FPGA can convert the return data packet into a CPL or CPLD packet according to the credit query result, and send the CPL or CPLD packet to the host through the transparent channel.
[0115] Reference Figure 4 , shows a flow chart of a data interaction method provided by some embodiments of the present invention, which is applied to a system-on-chip end and may specifically include the following steps:
[0116] Step 401, obtaining an enumeration request data packet through a transparent transmission channel set at the field programmable gate array end, parsing the enumeration request data packet, and generating a return data packet; wherein the field programmable gate array end is used to respond to the device enumeration demand of the host end; establishing the transparent transmission channel between the host end and the system on chip end through the field programmable gate array end; obtaining the enumeration request data packet issued by the host end, and sending the enumeration request data packet to the system on chip end through the transparent transmission channel; wherein the device enumeration demand is the device enumeration demand generated when the host end performs a device loading operation.
[0117] In the specific implementation, the host side will initiate the device enumeration process in order to realize the loading of PCIe devices. Therefore, in response to the device enumeration requirements of the host side, a transparent transmission channel between the host side and the system on chip side can be established through the field programmable gate array side, so that the complete config tlp packet sent by the host is encapsulated as a payload into a Memory Write tlp packet and written into the SoC memory through the FPGA transparent transmission channel, and the SoC actually handles the enumeration process.
[0118] Furthermore, after the SoC parses the tlp packet and completes the related processing to generate the return data packet, it can store the return data packet in another memory space and notify the FPGA. After receiving the corresponding notification, the FPGA can read back the tlp packet and convert it into a CPL or CPLD packet and return it to the Host side, thus completing a data exchange between the Host and the SoC. Repeat this process many times until a complete enumeration process is completed, and the SoC sends the final configuration result to the FPGA for subsequent data channel processing.
[0119] In some embodiments of the present invention, the method further comprises:
[0120] In response to the generation of the return data packet, the return data packet is stored in a target memory area and a return notification is sent to the field programmable gate array end; wherein the field programmable gate array end is also used to respond to the return notification issued by the system on chip end and obtain the return data packet in the target memory area of the system on chip end.
[0121] In the specific implementation, after the SoC parses the tlp packet and completes the related processing to generate the return data packet, it can store the return data packet in another memory space and notify the FPGA. After receiving the corresponding notification, the FPGA can read back the tlp packet and convert it into a CPL or CPLD packet and return it to the Host side, thus completing a data exchange between the Host and the SoC. Repeat multiple times until a complete enumeration process is completed, and the SoC sends the final configuration result to the FPGA for subsequent data channel processing.
[0122] The present invention provides a data interaction method, which is applied to a field programmable gate array end and is provided with a transparent transmission channel, by responding to the device enumeration demand of the host end; establishing a transparent transmission channel between the host end and the system on chip end through the field programmable gate array end; then obtaining an enumeration request data packet sent by the host end, and sending the enumeration request data packet to the system on chip end through the transparent transmission channel; wherein the system on chip end is used to obtain the enumeration request data packet through the transparent transmission channel, and parse the enumeration request data packet to generate a return data packet; and then obtain the return data packet and send the return data packet to the host end through the transparent transmission channel. The enumeration data interaction process of the PCIe device is realized by replacing the FPGA with the SOC (system on chip), and the transparent transmission channel set by the FPGA end is used to realize the transparent transmission of the relevant configuration package, which can not only reduce the development and expansion difficulty of the system itself based on the rich storage resources and software characteristics of the SOC, but also enable the FPGA resources to focus more effectively on the acceleration of the data channel based on the setting of the transparent transmission channel, thereby reducing the update iteration cycle of the system and improving the stability of the system.
[0123] Through the data interaction process setting in the embodiment of the present invention, the SoC resource advantage can be fully utilized to achieve larger-scale PCIe PF and PCIe VF loading. In the related art, the scale of PCIe PF and PCIe VF is limited by FPGA resources, and the expansion is difficult. The present invention can achieve larger-scale PCIe PF and PCIe VF loading, meeting the growing resource requirements for computing, networking, and storage in the current big data network environment.
[0124] The data interaction of the PCIe PF and PCIe VF enumeration process on the Host side is realized by SoC, which can improve the flexibility and stability of the system. In the related technology, the loading of PCIe PF and PCIe VF is realized by the interaction between FPGA and Host, and the scale is fixed and the update iteration cycle is long. Compared with the existing technical solutions, the present invention relies more on software implementation, has the advantage of a short development cycle, can flexibly update the scale of PCIe PF and PCIe VF, and better meet the efficiency requirements of update iterations in the current network environment; at the same time, because the software is more maintainable, it also reduces the difficulty of system development and improves the stability of the system.
[0125] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.
[0126] Reference Figure 5 , shows a schematic diagram of the structure of a data interaction device provided by some embodiments of the present invention; applied to a field programmable gate array end, it may specifically include the following modules:
[0127] The transparent transmission channel establishment module 501 is used to respond to the device enumeration requirement of the host end; establish a transparent transmission channel between the host end and the system on chip end through the field programmable gate array end; wherein the device enumeration requirement is the device enumeration requirement generated when the host end performs a device loading operation;
[0128] The enumeration request packet sending module 502 is used to obtain the enumeration request packet sent by the host end, and send the enumeration request packet to the system-on-chip end through the transparent transmission channel; wherein the system-on-chip end is used to obtain the enumeration request packet through the transparent transmission channel, and parse the enumeration request packet to generate a return packet;
[0129] The return data packet acquisition module 503 is used to acquire the return data packet and send the return data packet to the host end through the transparent transmission channel.
[0130] In some embodiments of the present invention, the enumeration request data packet sending module 502 includes:
[0131] A memory write data packet generation submodule, used to encapsulate the enumeration request data packet under the condition that the enumeration request data packet is used as a payload, so as to generate a memory write data packet;
[0132] The data packet writing submodule is used to write the memory write data packet into the memory of the on-chip system end through the transparent transmission channel.
[0133] In some embodiments of the present invention, the return data packet acquisition module 503 includes:
[0134] A return data packet acquisition submodule is used to respond to a return notification issued by the system-on-chip end and acquire the return data packet in a target memory area of the system-on-chip end; wherein the system-on-chip end is also used to respond to the generation of the return data packet, store the return data packet in the target memory area and send the return notification to the field programmable gate array end.
[0135] In some embodiments of the present invention, the return data packet acquisition module 503 includes:
[0136] A conversion processing submodule, used to perform a credit query on the returned data packet, obtain a credit query result, and perform conversion processing on the returned data packet according to the credit query result;
[0137] The return data packet sending submodule is used to send the return data packet after conversion to the host end through the transparent transmission channel.
[0138] In some embodiments of the present invention, the conversion processing submodule includes:
[0139] The conversion processing unit is used to convert the return data packet into a response operation request data packet or a response operation request data packet carrying data according to the credit query result.
[0140] In some embodiments of the present invention, the backhaul data packet sending submodule includes:
[0141] The data packet sending unit is used to send the response operation request data packet or the response operation request data packet carrying data to the host end through the transparent transmission channel.
[0142] Reference Figure 6 , shows a schematic diagram of the structure of a data interaction device provided by some embodiments of the present invention; applied to a system-on-chip end, it may specifically include the following modules:
[0143] The enumeration request packet parsing module 601 is used to obtain an enumeration request packet through a transparent transmission channel set on the field programmable gate array end, and parse the enumeration request packet to generate a return packet; wherein the field programmable gate array end is used to respond to the device enumeration demand of the host end; establish the transparent transmission channel between the host end and the system on chip end through the field programmable gate array end; obtain the enumeration request packet sent by the host end, and send the enumeration request packet to the system on chip end through the transparent transmission channel; wherein the device enumeration demand is the device enumeration demand generated when the host end performs a device loading operation.
[0144] In some embodiments of the present invention, the device further comprises:
[0145] A return notification sending module is used to store the return data packet in a target memory area and send a return notification to the field programmable gate array end in response to the generation of the return data packet; wherein the field programmable gate array end is also used to obtain the return data packet in the target memory area of the system on chip end in response to the return notification issued by the system on chip end.
[0146] Some embodiments of the present invention further provide an electronic device, which may include a processor, a memory, and a computer program stored in the memory and capable of running on the processor, and the computer program implements the above data interaction method when executed by the processor.
[0147] Some embodiments of the present invention further provide a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the above data interaction method is implemented.
[0148] Some embodiments of the present invention further provide a computer program product, including a computer program, which implements the above data interaction method when executed by a processor.
[0149] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.
[0150] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.
[0151] Those skilled in the art will appreciate that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.
[0152] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0153] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.
[0154] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.
[0155] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.
[0156] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the above elements.
[0157] The above provides a detailed introduction to a data interaction method and device, an electronic device, and a storage medium. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for a person skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.
Claims
1. A data interaction method, characterized in that: Applied to a field programmable gate array, the method comprises: In response to a device enumeration requirement of the host side; establishing a transparent transmission channel between the host side and the system on chip side through the field programmable gate array side; wherein the device enumeration requirement is a device enumeration requirement generated when the host side performs a device loading operation; Obtaining an enumeration request data packet sent by the host end, and sending the enumeration request data packet to the system-on-chip end through the transparent transmission channel; wherein the system-on-chip end is used to obtain the enumeration request data packet through the transparent transmission channel, and parse the enumeration request data packet to generate a return data packet; The return data packet is obtained, and the return data packet is sent to the host end through the transparent transmission channel.
2. The method according to claim 1, characterized in that The step of sending the enumeration request data packet to the system on chip end through the transparent transmission channel includes: Under the condition that the enumeration request data packet is used as a payload, encapsulating the enumeration request data packet to generate a memory write data packet; The memory write data packet is written into the memory of the system on chip through the transparent transmission channel.
3. The method according to claim 1 or 2, characterized in that: The obtaining of the returned data packet comprises: In response to a return notification issued by the system-on-chip end, the return data packet is obtained in a target memory area of the system-on-chip end; wherein the system-on-chip end is also used to store the return data packet in the target memory area and send the return notification to the field programmable gate array end in response to the generation of the return data packet.
4. The method according to claim 1 or 2, characterized in that: The sending the return data packet to the host end through the transparent transmission channel includes: Performing a credit query on the returned data packet to obtain a credit query result, and performing conversion processing on the returned data packet according to the credit query result; The converted return data packet is sent to the host end through the transparent transmission channel.
5. The method according to claim 4, characterized in that The converting and processing the returned data packet according to the credit query result includes: According to the credit query result, the return data packet is converted into a response operation request data packet or a response operation request data packet carrying data.
6. The method according to claim 5, characterized in that The step of sending the converted return data packet to the host end through the transparent transmission channel includes: The response operation request data packet or the response operation request data packet carrying data is sent to the host end through the transparent transmission channel.
7. A data interaction method, characterized in that: Applied to a system-on-chip, the method comprises: An enumeration request data packet is obtained through a transparent transmission channel set at a field programmable gate array end, and the enumeration request data packet is parsed to generate a return data packet; wherein the field programmable gate array end is used to respond to the device enumeration demand of the host end; the transparent transmission channel between the host end and the system on chip end is established through the field programmable gate array end; the enumeration request data packet sent by the host end is obtained, and the enumeration request data packet is sent to the system on chip end through the transparent transmission channel; wherein the device enumeration demand is the device enumeration demand generated when the host end performs a device loading operation.
8. The method according to claim 7, characterized in that The method further comprises: In response to the generation of the return data packet, the return data packet is stored in a target memory area and a return notification is sent to the field programmable gate array end; wherein the field programmable gate array end is also used to respond to the return notification issued by the system on chip end and obtain the return data packet in the target memory area of the system on chip end.
9. A data interaction device, characterized in that: Applied to a field programmable gate array, the device comprises: A transparent transmission channel establishment module is used to respond to the device enumeration requirement of the host end; establish a transparent transmission channel between the host end and the system on chip end through the field programmable gate array end; wherein the device enumeration requirement is a device enumeration requirement generated when the host end performs a device loading operation; An enumeration request data packet sending module is used to obtain the enumeration request data packet sent by the host end, and send the enumeration request data packet to the system-on-chip end through the transparent transmission channel; wherein the system-on-chip end is used to obtain the enumeration request data packet through the transparent transmission channel, and parse the enumeration request data packet to generate a return data packet; The return data packet acquisition module is used to acquire the return data packet and send the return data packet to the host end through the transparent transmission channel.
10. A data interaction device, characterized in that: Applied to a system-on-chip, the device comprises: An enumeration request packet parsing module is used to obtain an enumeration request packet through a transparent transmission channel set on a field programmable gate array end, and parse the enumeration request packet to generate a return packet; wherein the field programmable gate array end is used to respond to the device enumeration demand of the host end; establish the transparent transmission channel between the host end and the system on chip end through the field programmable gate array end; obtain the enumeration request packet sent by the host end, and send the enumeration request packet to the system on chip end through the transparent transmission channel; wherein the device enumeration demand is the device enumeration demand generated when the host end performs a device loading operation.