Chip pin cross-domain configuration method and chip

Abstract

The invention provides a chip pin cross-domain configuration method and a chip, the method is applied to the chip with a plurality of hardware domains, the plurality of hardware domains comprise a first domain and at least one second domain, the chip is provided with a plurality of chip pins, each chip pin is provided with a register of a different type, and the register of the first domain and the register of the second domain are different. The method comprises the steps that a first domain determines a to-be-detected function and an execution domain of the to-be-detected function according to a to-be-detected target chip pin, wherein the execution domain is any second domain using the to-be-detected function of the target chip pin; the first domain configures different types of registers of the target chip pin based on the to-be-detected function and the execution domain, so that the execution domain can apply the target chip pin to execute the to-be-detected function; and the execution domain configures a specified type register of the target chip pin to detect whether the target chip pin can execute the to-be-detected function on the execution domain.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of system on chip, and in particular to a chip pin cross-domain configuration method and a chip. Background Art

[0002] When chip manufacturers test new chips, there are multiple stages of testing, such as using large ATE testing tools to test the functions of each pin of each chip.

[0003] After the test is passed, the chip will be attached to a specific motherboard with various peripherals for further testing and debugging in combination with the peripherals. Usually, the chip will be equipped with an operating system to complete the test at this stage, such as Linux or Android. Therefore, the tester needs to make good configurations at the compilation stage, assign the corresponding pins in the chip to specific functions, and then make the test firmware, burn it to the machine, and then test it.

[0004] However, for multi-core heterogeneous systems and systems with multiple hardware domains, it is necessary to configure the functions of the pins corresponding to each domain in the chip, then burn them accordingly, and then test them. The overall process is cumbersome and complicated. Summary of the invention

[0005] In order to solve the above technical problems, an embodiment of the present invention provides a chip pin cross-domain configuration method, which is applied to a chip having multiple hardware domains, wherein the multiple hardware domains include a first domain and at least one second domain, and the chip has multiple chip pins, each of which has a different type of register, and the method includes:

[0006] The first domain determines the function to be detected and the execution domain of the function to be detected according to the pin of the target chip to be detected, and the execution domain is any second domain of the function to be detected that uses the pin of the target chip;

[0007] The first domain configures different types of registers of the target chip pin based on the function to be detected and the execution domain, so that the execution domain can use the target chip pin to execute the function to be detected;

[0008] The execution domain configures the designated type register of the target chip pin to detect whether the target chip pin can execute the function to be detected on the execution domain.

[0009] In one embodiment, the different types of registers include permission configuration class registers and function control class registers. The permission configuration class registers are used to configure the permissions for different second domains to use the chip pins, and the function control class registers are used to configure the functions of the chip pins.

[0010] In one embodiment, the first domain configures different types of registers of the target chip pins based on the execution domain, including:

[0011] The first domain configures the permission configuration class register of the target chip pin according to the execution domain, so that the execution domain has the permission to use the target chip pin.

[0012] In one embodiment, the first domain configures different types of registers of the target chip pin based on the function to be detected, including:

[0013] The first domain determines the functional configuration information of the pin of the target chip according to the function to be detected;

[0014] The first domain configures the function control register of the target chip pin based on the function configuration information, so that the target chip pin is configured to execute the function to be detected.

[0015] In one embodiment, the method further comprises:

[0016] The first domain determines the chip pins involved in the execution of the function to be detected;

[0017] The chip pins involved in the first domain are all determined as the target chip pins, and a plurality of the target chip pins are used to cooperate in implementing the execution of the function to be detected.

[0018] In one embodiment, the first domain configures different types of registers of the target chip pin based on the function to be detected and the execution domain, including:

[0019] The first domain configures the permission configuration class register of the target chip pin according to the execution domain, so that the execution domain has the permission to use each of the target chip pins;

[0020] The first domain determines the functional configuration information of each pin of the target chip according to the function to be detected;

[0021] The first domain configures the function control registers of each of the target chip pins based on each of the function configuration information, so that a plurality of the target chip pins are configured to cooperate in executing the function to be detected.

[0022] In one embodiment, the method further comprises:

[0023] The first domain records multiple target chip pins that participate in cooperating to execute the function to be detected, so as to determine that the function detection of each of the target chip pins is completed;

[0024] When the detection of one function of the pin of the target chip is completed, the first domain switches another function of the pin of the target chip to a function to be detected, and detects the new function to be detected;

[0025] When the detection of each function of the target chip pin is completed, the first domain switches a new chip pin to the target chip pin, and performs detection of each function on the new target chip pin.

[0026] In one embodiment, the execution domain configures the designated type register of the target chip pin to detect whether the target chip pin can execute the function to be detected on the execution domain, including:

[0027] The execution domain determines a register of a specified type to be configured according to the function to be detected;

[0028] The execution domain configures the designated type register accordingly according to the function to be detected, so that the target chip pin responds to the configuration of the designated type register, executes the function to be detected, and outputs the execution result;

[0029] The execution domain determines whether the target chip pin can execute the function to be detected on the execution domain by receiving and detecting the execution result.

[0030] In one embodiment, the method further comprises:

[0031] After completing the detection of various functions of the target chip pins on an execution domain, the first domain switches a new second domain as the execution domain by configuring different types of registers of the target chip pins.

[0032] Another embodiment of the present invention also provides a chip having multiple hardware domains, the multiple hardware domains including a first domain and at least one second domain, the chip having multiple chip pins, each of the chip pins having a different type of register, wherein:

[0033] The first domain determines the function to be detected and the execution domain of the function to be detected according to the pin of the target chip to be detected, and the execution domain is any second domain of the function to be detected that uses the pin of the target chip;

[0034] The first domain configures different types of registers of the target chip pin based on the function to be detected and the execution domain, so that the execution domain can use the target chip pin to execute the function to be detected;

[0035] The execution domain configures the designated type register of the target chip pin to detect whether the target chip pin can execute the function to be detected on the execution domain.

[0036] Based on the disclosure of the above embodiments, it can be known that the beneficial effects of the embodiments of the present invention include enabling multi-core heterogeneous, multi-hardware domain chips to be configured without human participation. Only relevant instructions need to be input, and the chip can automatically determine the pins that need to be functionally configured in response to the instructions, and perform relevant functional configuration on the pins, or configure the pins for use in different hardware domains. The overall configuration process is simple and fast, which provides a more efficient configuration method for chip testing and subsequent use, and lays a foundation for testing efficiency and operating efficiency.

[0037] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained by the structures specifically pointed out in the written description, claims, and drawings.

[0038] The technical solution of the present application is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0040] Figure 1 The figure is a flowchart of a chip pin cross-domain configuration method in an embodiment of the present invention.

[0041] Figure 2 The figure is a schematic diagram of the application flow of the chip pin cross-domain configuration method in an embodiment of the present invention.

[0042] Figure 3 The figure is a schematic diagram of the application flow of a chip pin cross-domain configuration method in another embodiment of the present invention.

[0043] Figure 4 Schematic diagram of the chip structure in an embodiment of the present invention. DETAILED DESCRIPTION

[0044] The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings, but are not intended to limit the present invention.

[0045] It should be understood that various modifications may be made to the embodiments disclosed herein. Therefore, the following description should not be considered as limiting, but merely as an example of an embodiment. Other modifications within the scope of the present disclosure will occur to those skilled in the art.

[0046] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the general description of the present disclosure given above and the detailed description of the embodiments given below, serve to explain the principles of the present disclosure.

[0047] These and other characteristics of the invention will become apparent from the following description of a preferred form of embodiment given as a non-limiting example, with reference to the accompanying drawings.

[0048] It should also be understood that, although the invention has been described with reference to some specific examples, those skilled in the art will be able to realize many other equivalent forms of the invention that have the characteristics recited in the claims and are therefore within the scope of protection defined thereby.

[0049] The above and other aspects, features and advantages of the present disclosure will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.

[0050] Specific embodiments of the present disclosure are described hereinafter with reference to the accompanying drawings; however, it should be understood that the disclosed embodiments are merely examples of the present disclosure, which may be implemented in a variety of ways. Well-known and / or repeated functions and structures are not described in detail to avoid obscuring the present disclosure with unnecessary or redundant details. Therefore, the specific structural and functional details disclosed herein are not intended to be limiting, but merely serve as a basis and representative basis for the claims to teach those skilled in the art to use the present disclosure in a variety of ways with substantially any suitable detailed structure.

[0051] This specification may use the phrases "in one embodiment," "in another embodiment," "in a further embodiment," or "in other embodiments," all of which may refer to one or more of the same or different embodiments according to the present disclosure.

[0052] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0053] like Figure 1As shown, an embodiment of the present invention provides a chip pin cross-domain configuration method, which is applied to a chip with multiple hardware domains. For example, the method of this embodiment is applicable to but not limited to any chip with multiple hardware domains such as a digital signal processing chip, a microcontroller chip, a field programmable gate array (FPGA) chip, etc. Wherein, the multiple hardware domains include a first domain and at least one second domain. For example, the chip includes multiple different processor cores, and the processor cores in the chip form corresponding domains with their corresponding hardware resources. The domains include a first domain and multiple second domains, and each processor core runs an operating system, such as FreeRTOS, Android system, Linux system, OS system, etc. The first domain and the second domain can communicate with each other. Specifically, the chip of the embodiment of the present application can be a SOC, or a chip containing a SOC. The chip includes multiple processor cores, and the processor cores and their corresponding hardware resources can form corresponding domains, wherein the formed domain can include one or more processor cores, for example, one domain can have one or more processor cores. The domain includes a first domain and multiple second domains, the first domain can be a security domain, and the second domain can be an application domain or other functional domain. There is a communication link between the first domain and the second domain, which enables inter-core communication, so that the first domain and the second domain can interact with each other and share functions in a secure and high-speed transmission.

[0054] Further, the chip has a plurality of chip pins, each of the chip pins has a register of a different type, and the method includes:

[0055] S1: The first domain determines a function to be detected and an execution domain of the function to be detected according to the pin of the target chip to be detected, and the execution domain is any second domain of the function to be detected that uses the pin of the target chip;

[0056] Exemplarily, a pin function mapping table is stored in a non-volatile memory inside the chip in advance, and the first domain needs to determine the function to be detected of the target chip pin to be detected and the execution domain of the function to be detected when responding to the input instruction. For example, the first domain can first read the pin function mapping table stored in the non-volatile memory inside the chip, and then determine the configuration parameters and application requirements of the current system, such as the detection requirements, which can be obtained through the instructions input by the user, or determined according to the application started by the current system, such as the test program, or other non-test programs, such as the application started by the chip during subsequent normal use. After determining the system configuration parameters and application requirements, the first domain can combine the determined information with the mapping table for comprehensive analysis, and then determine the function to be detected corresponding to the target chip pin to be detected. To determine the execution domain, it can be determined based on the domain information indicated in the input instruction, or based on a preset test order. It can also be determined based on the function to be tested of the pin, as well as the communication links and function sharing rules between hardware domains to determine the second domain that executes the function to be tested, that is, determine the second domain that can currently execute the pin function test, and the second domain can be a domain that is currently idle and supports function detection.

[0057] S2: The first domain configures different types of registers of the target chip pin based on the function to be detected and the execution domain, so that the execution domain can use the target chip pin to execute the function to be detected;

[0058] In this embodiment, the first domain can be configured to the first type of register of the target chip pin according to the type of function to be detected, such as data transmission function, interrupt trigger function, etc., including but not limited to setting the working mode, transmission rate, data type and other parameters of the pin; at the same time, other types of registers can be initialized and configured according to the electrical characteristics of the execution domain and the communication protocol supported during data transmission to ensure the correct storage and transmission of data. Of course, the specific registers involved are not fixed, and the specific configuration is also not fixed, and can be flexibly changed based on actual conditions.

[0059] S3: The execution domain configures the designated type register of the target chip pin to detect whether the target chip pin can execute the function to be detected on the execution domain.

[0060] The execution domain in this embodiment instructs and controls the target chip pin to execute the function to be detected by configuring in a specified type of register. For example, the execution domain writes specific test data to a specified type of register of the target chip pin, such as a status register, and determines whether the target chip pin executes the function to be detected as expected by reading the value of the register, that is, when the target chip pin executes a specific function, it is necessary to configure data for various registers corresponding to the function, so that the target chip pin can execute the corresponding function.

[0061] The first domain in this embodiment is a security domain, which has the function configuration of the chip pins, the permission to use the permission configuration, and the permission to access any second domain. The second domain is each functional domain in the chip. The number of pins of the chip is not fixed, and it can have any number of chip pins. Different chip pins can support one or more different functions. The addition or modification of the pin function can be implemented through the first domain, such as updating the relevant function mapping table and configuration parameters. This method can make the method of this embodiment have good adaptability and a wide range of applications.

[0062] Furthermore, the different types of registers described in this embodiment include permission configuration registers and function control registers. The permission configuration registers are used to configure the permissions granted to different second domains to use the chip pins, such as configuring the second domain A to have the permission to use the chip pins. The function control registers are used to configure the functions that the chip pins need to have, and the functions may be, for example, but not limited to, receiving specified data, transmitting specified data, etc. The function control registers include, but are not limited to, control registers, which are used to set the working mode of the pins, such as input mode, output mode, bidirectional mode, etc. The different types of registers may also include, but are not limited to, status registers, which are used to feedback the current electrical state of the pins, such as high level state, low level state, open circuit state, etc.; data registers, which are used to temporarily store data transmitted through the pins, etc.

[0063] When the execution domain detects whether the target chip pin can execute the function to be detected, the execution domain can write specific test data to a specified type of register, such as a status register, that is, configure the status register, and then read the value in the register that represents whether the target chip pin responds to the data write operation and executes the corresponding function to determine whether the target chip pin has executed the function to be detected as expected. If the read value is consistent with the preset standard value, it is determined that the pin can execute the function to be detected on the execution domain. Otherwise, if the read value does not match the preset standard value, it is determined that the pin cannot execute the function to be detected on the execution domain, and the chip is an abnormal chip.

[0064] Based on the method of this embodiment, the user does not need to perform many operations. He only needs to input corresponding instructions to control the first domain to implement operations such as function modification and function addition of chip pins, and switching of specific execution domains. Moreover, when the user inputs a specified test instruction, the first domain can control the target chip pins to perform tests of different functions and corresponding to different execution domains in turn. The intermediate process does not require user participation, which significantly improves test efficiency, simplifies user operations, and provides convenience for the functional configuration of chip pins when the chip is used normally in the subsequent process.

[0065] In one embodiment, the first domain configures different types of registers of the target chip pins based on the execution domain, including:

[0066] S4: The first domain configures the permission configuration class register of the target chip pin according to the execution domain, so that the execution domain has the permission to use the target chip pin.

[0067] For example, when the second domain A completes the function test of the target chip pin, the data in the permission configuration register of the target chip pin is updated and rewritten to cancel the permission of the second domain A and grant the second domain B the permission to use the target chip pin.

[0068] like Figure 2 As shown, the first domain is the security domain. After the system is powered on, the processor cores of each domain are started and run their respective operating systems. After the startup is completed, the first domain modifies the data in the permission configuration class register of the target chip pin pin1, and configures pin1 to form a resource in the form of the secure domain, and at the same time notifies the secure domain as the execution domain to perform the function detection operation of pin1.

[0069] The execution domain can be determined based on preset configuration information, such as preset detection configuration information, or based on instructions input by the user to indicate detection, or based on the function of the target chip pin to be detected, the configuration parameters of the processor core, etc., to ensure that the selected execution domain can transmit data with the target chip pin, has the ability to perform functional detection of the target chip pin, and can realize functional detection of the target chip pin.

[0070] When determining the target chip pin, the method includes:

[0071] S5: The first domain determines the chip pins involved in the execution of the function to be detected;

[0072] S6: The first domain determines all the chip pins involved as the target chip pins, and a plurality of the target chip pins are used to cooperate in implementing the execution of the function to be detected.

[0073] Since each chip pin has multiple different functions, that is, it supports configuration of multiple different functions, different chip pins support different functions. For example, two chip pins support configurations of the same or different functions. When determining the target chip pin, the first domain first determines the functions that each chip pin supports configuration, and then determines the target chip pin based on the functions it supports and the functions to be detected.

[0074] Furthermore, the first domain configures different types of registers of the target chip pin based on the function to be detected, including:

[0075] S7: The first domain determines the function configuration information of the pin of the target chip according to the function to be detected;

[0076] S8: The first domain configures the function control register of the target chip pin based on the function configuration information, so that the target chip pin is configured to execute the function to be detected.

[0077] For example, when the first domain determines that the function to be detected is an input or output function, the function of the target chip pin can be configured accordingly, including specific configuration as an input or output function. Afterwards, the first domain can configure the function control register of the target chip pin, such as the function control register, based on the determined function configuration information, so that the target chip pin is configured to have the effect of input or output function.

[0078] Combination Figure 2 As shown, the first domain configures different types of registers of the target chip pin based on the function to be detected and the execution domain, including:

[0079] S9: the first domain configures the permission configuration class register of the target chip pin according to the execution domain, so that the execution domain has the permission to use each of the target chip pins;

[0080] S10: The first domain determines the function configuration information of each pin of the target chip according to the function to be detected;

[0081] S11: The first domain configures the function control registers of each of the target chip pins based on each of the function configuration information, so that a plurality of the target chip pins are configured to cooperate in executing the function to be detected.

[0082] Exemplarily, when switching the execution domain, the first domain configures the permission configuration class register of the target chip pin according to the execution domain, and adds the information of the specified execution domain so that the execution domain has the right to use the target chip pin. Then, the first domain determines the function that the target chip pin needs to have based on the function to be detected that needs to be executed, and then determines the function configuration information of the target chip pin accordingly, and configures the function control register of the target chip pin based on the information. Since the chip pins involved are not unique when executing a certain function to be detected, usually multiple chip pins cooperate to perform the task to be detected, such as data input and output. Therefore, when the first domain determines the target chip pin, it determines multiple chip pins that can cooperate to perform the task to be detected. After that, each chip pin determined as the target chip pin is configured with the execution domain and function, so that it is triggered to perform the corresponding function for the next test.

[0083] In order to avoid repeated testing of a certain function on some chip pins in the future, the first domain can record the target chip pins that have completed a certain function to be tested, so that when it is the turn of the chip pin to perform the test of the function to be tested in the future, it can be skipped directly to avoid repeated testing and waste of testing resources.

[0084] Specifically, the method further includes:

[0085] S12: the first domain records multiple target chip pins that participate in cooperating to execute the function to be detected, so as to determine that the function detection of each of the target chip pins is completed;

[0086] S13: when the detection of one function of the pin of the target chip is completed, the first domain switches another function of the pin of the target chip to a function to be detected, and detects the new function to be detected;

[0087] S14: When the detection of each function of the target chip pin is completed, the first domain switches a new chip pin to the target chip pin, and performs detection of each function on the new target chip pin.

[0088] Exemplarily, when the user instructs the first domain to perform a functional test on all chip pins, the first domain records multiple target chip pins that participate in cooperating to execute the first function to be detected. After completing the first functional test of the target chip pins, the first domain can automatically configure the current target chip pins for the next function to be detected. The specific configuration method is as above, including deleting the existing function configuration information in the register and writing new function configuration information. The switching method for the execution domain is similar, which also deletes the existing execution domain configuration information in the register and writes new execution domain configuration information. The switching of the above functions and the switching of the execution domain are all automatically determined and executed by the first domain without user participation, and the automation performance is strong.

[0089] For example, Figure 2 As shown, the first domain modifies the function of pin1 to a common output port function, and at the same time configures its execution domain to be the AP1 domain corresponding to the AP1 core. After the function detection is completed, pin1 is modified to the uart function, and the execution domain remains unchanged. After the function detection is completed, the first domain modifies the function of pin1 to the spi function and continues to test. After all functions of pin1 have been tested, the target chip pin can be switched to the next chip pin, and the function test can be continued in the same execution domain.

[0090] Further, the execution domain configures a designated type register of the target chip pin to detect whether the target chip pin can execute the function to be detected on the execution domain, including:

[0091] S15: the execution domain determines a register of a specified type to be configured according to the function to be detected;

[0092] S16: the execution domain configures the designated type register accordingly according to the function to be detected, so that the target chip pin responds to the configuration of the designated type register, executes the function to be detected, and outputs the execution result;

[0093] S17: The execution domain determines whether the target chip pin can execute the function to be detected on the execution domain by receiving and detecting the execution result.

[0094] Continue to combine Figure 2As shown, in this embodiment, after completing the configuration of the chip pin's functions and usage permissions, the first domain will send a notification to the execution domain to inform it to perform the relevant configuration of the function to be detected and execute the function to be detected. For example, the status register in pin1 is set to a high level, and then it is determined whether it is a high level when the oscilloscope tests pin1. If so, it indicates that pin1 functions normally when it is a normal output port, otherwise it is abnormal. Alternatively, a specified type register in pin1 is configured with a uart waveform, and then it is determined whether the oscilloscope receives the uart waveform when testing pin1. If so, it indicates that pin1 functions normally when executing the uart function, otherwise it is abnormal. Alternatively, a specified register in pin1 is configured with a spi waveform, such as running a spi test program to continuously configure the spi waveform in the register, and then using an oscilloscope to test whether pin1 has a spi waveform. If so, it indicates that pin1 can execute the spi function, otherwise it is abnormal, indicating that pin1 cannot execute the spi function.

[0095] Furthermore, when performing cross-domain detection, the method further includes:

[0096] S18: After completing the detection of various functions of the target chip pins on an execution domain, the first domain switches a new second domain as the execution domain by configuring different types of registers of the target chip pins.

[0097] like Figure 3 As shown, for example, pin1 is modified to be a resource of the secure domain, that is, the authority is configured to the secure domain, so that the secure domain is an execution domain. After completing the configuration of the relevant authority register, the first domain sends a notification to the secure domain to inform it that it is an execution domain. Then the first domain configures the function to be detected of pin1 and notifies the execution domain to start the execution function detection. When the execution domain is to be changed, such as changing the current secure domain to the AP1 domain, the first domain uses the information of the AP1 domain to update the configuration information in the permission class register in pin1 to switch the use authority of pin1 to the AP1 domain, and then notifies the AP1 domain to inform it that it is an execution domain. Then the first domain can choose whether to configure and update the function to be detected of pin1 as needed, that is, whether to change the function to be detected. If so, the function control register of pin1 is configured to change the function to be detected, and the AP1 domain is notified to start the detection of the new function to be detected. If the function to be detected does not need to be changed, the AP1 domain can be directly notified to execute the current function to be detected.

[0098] Based on the contents of the above embodiments, it can be seen that the method provided in this embodiment can enable multi-core heterogeneous, multi-hardware domain chips to be configured without human participation. Only relevant instructions need to be input, and the chip can respond to the instruction and automatically determine the chip pins that need to be functionally configured, and perform relevant functional configuration on the pins, or configure the pins for use in different hardware domains. The overall configuration process is simple and fast, which provides a more efficient configuration method for chip testing and subsequent use, and lays the foundation for testing efficiency and operation efficiency.

[0099] like Figure 4 As shown, another embodiment of the present invention also provides a chip, having multiple hardware domains, the multiple hardware domains include a first domain and at least one second domain, the chip has multiple chip pins, each of the chip pins has a different type of register, wherein:

[0100] The first domain determines the function to be detected and the execution domain of the function to be detected according to the pin of the target chip to be detected, and the execution domain is any second domain of the function to be detected that uses the pin of the target chip;

[0101] The first domain configures different types of registers of the target chip pin based on the function to be detected and the execution domain, so that the execution domain can use the target chip pin to execute the function to be detected;

[0102] The execution domain configures the designated type register of the target chip pin to detect whether the target chip pin can execute the function to be detected on the execution domain.

[0103] In one embodiment, the different types of registers include permission configuration class registers and function control class registers. The permission configuration class registers are used to configure the permissions for different second domains to use the chip pins, and the function control class registers are used to configure the functions of the chip pins.

[0104] In one embodiment, the first domain configures different types of registers of the target chip pins based on the execution domain, including:

[0105] The first domain configures the permission configuration class register of the target chip pin according to the execution domain, so that the execution domain has the permission to use the target chip pin.

[0106] In one embodiment, the first domain configures different types of registers of the target chip pin based on the function to be detected, including:

[0107] The first domain determines the functional configuration information of the pin of the target chip according to the function to be detected;

[0108] The first domain configures the function control register of the target chip pin based on the function configuration information, so that the target chip pin is configured to execute the function to be detected.

[0109] In one embodiment, the first domain is further used for:

[0110] The first domain determines the chip pins involved in the execution of the function to be detected;

[0111] The chip pins involved in the first domain are all determined as the target chip pins, and a plurality of the target chip pins are used to cooperate in implementing the execution of the function to be detected.

[0112] In one embodiment, the first domain configures different types of registers of the target chip pin based on the function to be detected and the execution domain, including:

[0113] The first domain configures the permission configuration class register of the target chip pin according to the execution domain, so that the execution domain has the permission to use each of the target chip pins;

[0114] The first domain determines the functional configuration information of each pin of the target chip according to the function to be detected;

[0115] The first domain configures the function control registers of each of the target chip pins based on each of the function configuration information, so that a plurality of the target chip pins are configured to cooperate in executing the function to be detected.

[0116] In one embodiment, the first domain is further used for:

[0117] The first domain records multiple target chip pins that participate in cooperating to execute the function to be detected, so as to determine that the function detection of each of the target chip pins is completed;

[0118] When the detection of one function of the pin of the target chip is completed, the first domain switches another function of the pin of the target chip to a function to be detected, and detects the new function to be detected;

[0119] When the detection of each function of the target chip pin is completed, the first domain switches a new chip pin to the target chip pin, and performs detection of each function on the new target chip pin.

[0120] In one embodiment, the execution domain configures the designated type register of the target chip pin to detect whether the target chip pin can execute the function to be detected on the execution domain, including:

[0121] The execution domain determines a register of a specified type to be configured according to the function to be detected;

[0122] The execution domain configures the designated type register accordingly according to the function to be detected, so that the target chip pin responds to the configuration of the designated type register, executes the function to be detected, and outputs the execution result;

[0123] The execution domain determines whether the target chip pin can execute the function to be detected on the execution domain by receiving and detecting the execution result.

[0124] In one embodiment, the first domain is further used for:

[0125] After completing the detection of various functions of the target chip pins on an execution domain, the first domain switches a new second domain as the execution domain by configuring different types of registers of the target chip pins.

[0126] Furthermore, an embodiment of the present invention also provides a storage medium having a computer program stored thereon, which implements the chip pin cross-domain configuration method as described above when the program is executed by a processor including the chip. It should be understood that each solution in this embodiment has the corresponding technical effect in the above method embodiment, which will not be repeated here.

[0127] Furthermore, an embodiment of the present invention also provides a computer program product, which is tangibly stored on a computer-readable medium and includes computer-readable instructions, which, when executed, enable at least one processor including the chip to perform a chip pin cross-domain configuration method such as the one in the embodiment described above.

[0128] It should be noted that the computer storage medium of the present invention may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, system or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access storage medium (RAM), a read-only storage medium (ROM), an erasable programmable read-only storage medium (EPROM or flash memory), an optical fiber, a portable compact disk read-only storage medium (CD-ROM), an optical storage medium, a magnetic storage medium, or any suitable combination of the above. In the present invention, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, system or device. In the present invention, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, wherein a computer-readable program code is carried. This propagated data signal may take a variety of forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can send, propagate or transmit a program configured to be used by or in conjunction with an instruction execution system, system or device. The program code contained on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, antenna, optical cable, RF, etc., or any suitable combination of the above.

[0129] In addition, it will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) containing computer-usable program code.

[0130] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1A process or multiple processes and / or boxes Figure 1 A system that specifies the functions of a box or multiple boxes.

[0131] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction system, which is implemented in the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0132] A person skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of protection of the present application is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of different aspects of one or more embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0133] The above embodiments are only exemplary embodiments of the present invention and are not intended to limit the present invention. The protection scope of the present invention is defined by the claims. Those skilled in the art may make various modifications or equivalent substitutions to the present invention within the essence and protection scope of the present invention, and such modifications or equivalent substitutions shall also be deemed to fall within the protection scope of the present invention.

Claims

1. A chip pin cross-domain configuration method, applied to a chip having multiple hardware domains, the multiple hardware domains including a first domain and at least one second domain, the chip having multiple chip pins, each of the chip pins having a different type of register, the method comprising: The first domain determines the function to be detected and the execution domain of the function to be detected according to the pin of the target chip to be detected, and the execution domain is any second domain of the function to be detected that uses the pin of the target chip; The first domain configures different types of registers of the target chip pin based on the function to be detected and the execution domain, so that the execution domain can use the target chip pin to execute the function to be detected; The execution domain configures the designated type register of the target chip pin to detect whether the target chip pin can execute the function to be detected on the execution domain.

2. The chip pin cross-domain configuration method according to claim 1, characterized in that: The different types of registers include permission configuration registers and function control registers. The permission configuration registers are used to configure the permissions for different second domains to use the chip pins, and the function control registers are used to configure the functions of the chip pins.

3. The chip pin cross-domain configuration method according to claim 2, characterized in that: The first domain configures different types of registers of the target chip pins based on the execution domain, including: The first domain configures the permission configuration class register of the target chip pin according to the execution domain, so that the execution domain has the permission to use the target chip pin.

4. The chip pin cross-domain configuration method according to claim 2, characterized in that: The first domain configures different types of registers of the target chip pin based on the function to be detected, including: The first domain determines the functional configuration information of the pin of the target chip according to the function to be detected; The first domain configures the function control register of the target chip pin based on the function configuration information, so that the target chip pin is configured to execute the function to be detected.

5. The chip pin cross-domain configuration method according to claim 2, characterized in that: The method further comprises: The first domain determines the chip pins involved in the execution of the function to be detected; The chip pins involved in the first domain are all determined as the target chip pins, and a plurality of the target chip pins are used to cooperate in implementing the execution of the function to be detected.

6. The chip pin cross-domain configuration method according to claim 5, characterized in that: The first domain configures different types of registers of the target chip pin based on the function to be detected and the execution domain, including: The first domain configures the permission configuration class register of the target chip pin according to the execution domain, so that the execution domain has the permission to use each of the target chip pins; The first domain determines the functional configuration information of each pin of the target chip according to the function to be detected; The first domain configures the function control registers of each of the target chip pins based on each of the function configuration information, so that a plurality of the target chip pins are configured to cooperate in executing the function to be detected.

7. The chip pin cross-domain configuration method according to claim 6, characterized in that: The method further comprises: The first domain records multiple target chip pins that participate in cooperating to execute the function to be detected, so as to determine that the function detection of each of the target chip pins is completed; When the detection of one function of the pin of the target chip is completed, the first domain switches another function of the pin of the target chip to a function to be detected, and detects the new function to be detected; When the detection of each function of the target chip pin is completed, the first domain switches a new chip pin to the target chip pin, and performs detection of each function on the new target chip pin.

8. The chip pin cross-domain configuration method according to claim 1, characterized in that: The execution domain configures the designated type register of the target chip pin to detect whether the target chip pin can execute the function to be detected on the execution domain, including: The execution domain determines a register of a specified type to be configured according to the function to be detected; The execution domain configures the designated type register accordingly according to the function to be detected, so that the target chip pin responds to the configuration of the designated type register, executes the function to be detected, and outputs the execution result; The execution domain determines whether the target chip pin can execute the function to be detected on the execution domain by receiving and detecting the execution result.

9. The chip pin cross-domain configuration method according to claim 1, characterized in that: The method further comprises: After completing the detection of various functions of the target chip pins on an execution domain, the first domain switches a new second domain as the execution domain by configuring different types of registers of the target chip pins.

10. A chip having a plurality of hardware domains, the plurality of hardware domains comprising a first domain and at least one second domain, the chip having a plurality of chip pins, each of the chip pins having a different type of register, wherein: The first domain determines the function to be detected and the execution domain of the function to be detected according to the pin of the target chip to be detected, and the execution domain is any second domain of the function to be detected that uses the pin of the target chip; The first domain configures different types of registers of the target chip pin based on the function to be detected and the execution domain, so that the execution domain can use the target chip pin to execute the function to be detected; The execution domain configures the designated type register of the target chip pin to detect whether the target chip pin can execute the function to be detected on the execution domain.

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