Data transfer during maintenance operations

Abstract

The invention relates to data transfer during maintenance operations. A memory system may utilize an auto-pause feature to parallelize aspects of maintenance operations. For example, the memory system may suspend performing a program operation on a first block of memory cells. The memory system may read data from a second memory cell block when the program operation is suspended, and may transfer the data from the second memory cell block (e.g., to a controller) while resuming the program operation on the first memory cell block. The memory system may transfer the data read from the second memory cell block to a third memory cell block while resuming the program operation on the first memory cell block.

Description

[0001] Cross Reference

[0002] This patent application claims priority to U.S. patent application No. 18 / 776,201, filed by He et al. on July 17, 2024, entitled “DATA TRANSFER DURING MAINTENANCE OPERATIONS,” and U.S. provisional patent application No. 63 / 588,978, filed by He et al. on October 9, 2023, entitled “DATA TRANSFER DURING MAINTENANCE OPERATIONS,” each of which is assigned to its assignee and each of which is expressly incorporated herein by reference in its entirety.

[0003] The technical field relates to data transfer during maintenance operations. Background Art

[0004] Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically represented by a logical 1 or a logical 0. In some examples, a single memory cell can support more than two states, either of which can be stored. To access stored information, a memory device can read (e.g., sense, detect, retrieve, determine) a state from a memory cell. To store information, a memory device can write (e.g., program, set, assign) a state to a memory cell.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selection memory, chalcogenide memory technology, NOR and NAND memory devices, and others. Memory cells can be described in terms of volatile configurations or non-volatile configurations. Memory cells configured in a non-volatile configuration can maintain a stored logic state for a long time, even in the absence of external power. Memory cells configured in a volatile configuration lose their stored state when disconnected from the external power source. Summary of the invention

[0006] An apparatus is described. The apparatus may include: a memory device; and a controller coupled to the memory device and configured to cause the apparatus to: write a first subset of a first set of data to one or more multi-level memory cells of the memory device during a first duration of a maintenance operation; suspend writing of the first set of data to the one or more multi-level memory cells of the memory device during a second duration of the maintenance operation; read a first subset of a second set of data from one or more memory cells of the memory device during the second duration; transfer the first subset of the second set of data from the one or more multi-level memory cells to the controller via a bus during a third duration of the maintenance operation based at least in part on reading the first subset of the second set of data; and write a second subset of the first set of data to the one or more multi-level memory cells of the memory device during the third duration and concurrently with transferring the first subset of the second set of data.

[0007] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code including instructions that, when executed by a processor of an electronic device, cause the electronic device to: write a first subset of a first set of data to one or more multi-level memory cells of a memory system during a first duration of a maintenance operation; suspend writing of the first set of data to the one or more multi-level memory cells of the memory system during a second duration of the maintenance operation; read a first subset of a second set of data from one or more memory cells of the memory system during the second duration; transfer the first subset of the second set of data from the one or more multi-level memory cells to a controller of the memory system via a bus during a third duration of the maintenance operation based at least in part on reading the first subset of the second set of data; and write a second subset of the first set of data to the one or more multi-level memory cells of the memory system during the third duration and concurrently with transferring the first subset of the second set of data.

[0008] A method is described. The method may include: writing a first subset of a first set of data to one or more multilevel memory cells of a memory system during a first duration of a maintenance operation; suspending writing of the first set of data to the one or more multilevel memory cells of the memory system during a second duration of the maintenance operation; reading a first subset of a second set of data from one or more memory cells of the memory system during the second duration; transferring the first subset of the second set of data from the one or more multilevel memory cells to a controller of the memory system via a bus during a third duration of the maintenance operation based at least in part on reading the first subset of the second set of data; and writing a second subset of the first set of data to the one or more multilevel memory cells of the memory system during the third duration and concurrently with transferring the first subset of the second set of data. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example of a system supporting data transfer during maintenance operations according to examples disclosed herein is presented.

[0010] Figure 2A An example of a timing diagram supporting continuous data transfer and maintenance operations according to examples disclosed herein is shown.

[0011] Figure 2B An example of a timing diagram is shown to support data transfer during maintenance operations according to examples disclosed herein.

[0012] Figure 3 An example of a process flow supporting data transfer during a maintenance operation according to examples disclosed herein is presented.

[0013] Figure 4 A block diagram of a memory system supporting data transfer during maintenance operations according to examples disclosed herein is shown.

[0014] Figure 5 A flow chart illustrating one or several methods of supporting data transfer during maintenance operations according to examples disclosed herein is shown. DETAILED DESCRIPTION

[0015] A memory system may include a memory device (e.g., a NAND memory device), a memory controller, and a bus (e.g., an Open NAND Flash Interface (ONFI) bus) coupling the memory device and the memory controller. In some cases, during a maintenance operation (e.g., a waste collection operation), data may be read from a memory cell block of the memory device and may be transferred to the memory controller via the bus. The memory controller may receive the data and transfer (e.g., program) the data to a different memory cell block using the bus. However, in such examples, the data may be read to the controller and programmed to the memory cell block during non-overlapping durations (e.g., the operations may be performed serially). Performing the operations serially may add undesirable latency to the maintenance operation, which may affect the overall performance of the memory system. Therefore, a memory system configured to perform aspects of the maintenance operation in parallel may be desirable.

[0016] A memory system configured to perform aspects of maintenance operations in parallel is described herein. For example, the memory system described herein may transfer data from a memory controller to a first block of memory cells (e.g., block N) via a bus, and may begin programming the data (e.g., during a maintenance operation). In some examples, the memory system may suspend programming the data and may read data from a second block of memory cells (e.g., block N+1) to the memory controller via a bus. After reading the data from the second block, the memory system may resume programming the data to the first block and may transfer the data from the memory controller to the second block while programming the first block. Thus, while programming the first block, the memory system may begin programming the second block of memory cells. By performing such operations in parallel, the memory system may mitigate delays that would otherwise be caused by performing the operations serially. Thus, the overall performance of the memory system may be improved.

[0017] In addition to being applied in the memory systems described herein, the techniques for performing data transfer during maintenance operations may generally be implemented to improve the performance of various electronic devices and systems, including games. Some electronic device applications, including games and other high-performance applications, may be associated with relatively high processing requirements while benefiting from relatively fast response times to improve the user experience. Thus, it may be desirable to increase processing speed, reduce response time, or otherwise improve electronic device performance. Implementing the techniques described herein may improve electronic device performance by allowing maintenance operations (e.g., waste item collection procedures) to occur and reduce the overall time cost, which may reduce processing or latency time, improve response time, or otherwise improve overall performance, among other benefits.

[0018] In addition to being applied in the memory systems described herein, the techniques for data transfer during maintenance operations may generally be implemented to support artificial intelligence applications. As the use of artificial intelligence increases to support machine learning, analysis, decision making, or other related applications, electronic devices that support artificial intelligence applications and processes may be desirable. For example, artificial intelligence applications may be associated with accessing relatively large amounts of data for analytical purposes and may benefit from memory devices that can effectively and efficiently store relatively large amounts of data or access stored data relatively quickly. Implementing the techniques described herein may improve electronic device performance by allowing maintenance operations (e.g., waste item collection procedures) to occur and reduce overall time costs, which may reduce processing or latency time, improve response time, or otherwise improve overall performance, among other benefits.

[0019] First, in reference Figure 1 Features of the present disclosure are described in the context of systems, devices, and circuits. Figure 2A , 2B The features of the present disclosure are described in the context of the timing diagrams and process flows of FIG. 3. These and other features of the present disclosure are described in the context of the timing diagrams and process flows of FIG. Figure 4 and 5 The device diagrams and flow charts related to data transfer during maintenance operations are further illustrated and described in the context of the device diagrams and flow charts.

[0020] Figure 1 An example of a system 100 supporting data transfer during maintenance operations according to examples disclosed herein is shown. The system 100 includes a host system 105 coupled to a memory system 110. The system 100 may be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (such as an airplane, drone, train, car, or other transportation), an Internet of Things (IoT) enabled device, an embedded computer (such as an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or any other computing device including a memory and a processing device.

[0021] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash storage (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital (SD) card, a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), among other devices.

[0022] The system 100 may include a host system 105 that may be coupled to a memory system 110. In some examples, this coupling may include an interface with a host system controller 106, which may be an example of a controller or control component configured to cause the host system 105 to perform various operations according to the examples described herein. The host system 105 may include one or more devices and, in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or a device therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a peripheral component interconnect express (PCIe) controller, a serial advanced technology attachment (SATA) controller). For example, the host system 105 may use the memory system 110 to write data to the memory system 110 and read data from the memory system 110. Although Figure 1 One memory system 110 is shown in FIG. 1 , but the host system 105 may be coupled to any number of memory systems 110 .

[0023] The host system 105 may be coupled to the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 may be configured to communicate (e.g., exchange or otherwise transfer control, address, data, and other signals between the memory system 110 and the host system 105) via the physical host interface using an associated protocol. Examples of physical host interfaces may include, but are not limited to, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a DIMM interface (e.g., a DDR-capable DIMM slot interface), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more such interfaces may be included in or otherwise supported between a host system controller 106 of the host system 105 and a memory system controller 115 of the memory system 110. In some examples, the host system 105 may be coupled to the memory system 110 via a respective physical host interface of each memory device 130 included in the memory system 110 or via a respective physical host interface of each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 may be coupled to the memory system controller 115).

[0024] The memory system 110 may include a memory system controller 115 and one or more memory devices 130. The memory devices 130 may include one or more memory arrays of any type of memory cells, such as non-volatile memory cells, volatile memory cells, or any combination thereof. Figure 1 , two memory devices 130-a and 130-b are shown in the example of , but the memory system 110 may include any number of memory devices 130. Furthermore, if the memory system 110 includes more than one memory device 130, different memory devices 130 within the memory system 110 may include the same or different types of memory cells.

[0025] The memory system controller 115 may be coupled and communicated with the host system 105 (e.g., via a physical host interface) and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 may also be coupled and communicated with the memory device 130 to perform operations such as reading data, writing data, erasing data, or refreshing data at the memory device 130, and other such operations, which may be collectively referred to as access operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access of the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise associated with commands from the host system 105). For example, the memory system controller 115 may convert responses associated with the memory devices 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0026] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations (such as error detection operations or error correction operations), encryption operations, cache operations, media management operations, background refreshes, health monitoring, and address translation between logical addresses (such as logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (such as physical block addresses) associated with memory cells within the memory device 130.

[0027] The memory system controller 115 may include hardware such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware may include circuitry having dedicated (e.g., hard-coded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry such as a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP), or any other suitable processor or processing circuitry.

[0028] The memory system controller 115 may also include a local memory 120. In some cases, the local memory 120 may include a read-only memory (ROM) or other memory that may store operating code (e.g., executable instructions) that may be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, the local memory 120 may additionally or alternatively include a static random access memory (SRAM) or other memory that may be used by the memory system controller 115, for example, for internal storage or computations related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, the local memory 120 may be used as a cache for the memory system controller 115. For example, data may be stored in the local memory 120 when it is read from or written to the memory device 130, and the data may be used within the local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 according to a cache policy (e.g., with reduced latency relative to the memory device 130).

[0029] although Figure 1 The example of the memory system 110 in has been illustrated as including a memory system controller 115, but in some cases, the memory system 110 may not include a memory system controller 115. For example, the memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by the host system 105) or one or more local controllers 135, which may each be internal to the memory device 130 to perform the functions attributed herein to the memory system controller 115. In general, in some cases, one or more functions attributed herein to the memory system controller 115 may instead be performed by the host system 105, the local controller 135, or any combination thereof. In some cases, a memory device 130 that is at least partially managed by the memory system controller 115 may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0030] The memory device 130 may include one or more arrays of non-volatile memory cells. For example, the memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric random access memory (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridge RAM (CBRAM), resistance random access memory (RRAM), oxide-based RRAM (OxRAM), and electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, the memory device 130 may include one or more arrays of volatile memory cells. For example, the memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0031] In some examples, the memory devices 130 may include (e.g., on the same die or within the same package) a local controller 135 that may perform operations on one or more memory cells of the respective memory devices 130. The local controller 135 may operate in conjunction with the memory system controller 115 or may perform one or more functions attributed herein to the memory system controller 115. For example, Figure 1 As illustrated in FIG. 1 , memory device 130 - a may include a local controller 135 - a and memory device 130 - b may include a local controller 135 - b .

[0032] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a die 160 (e.g., a memory die). For example, in some cases, memory device 130 may be a package that includes one or more die 160. In some examples, die 160 may be a piece of electronic grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a set of corresponding blocks 170, wherein each block 170 may include a set of corresponding pages 175, and each page 175 may include a set of memory cells.

[0033] In some cases, the NAND memory device 130 may include memory cells configured to store one bit of information each, which may be referred to as single-level cells (SLC). Additionally or alternatively, the NAND memory device 130 may include memory cells configured to store multiple bits of information each, which may be referred to as multi-level cells (MLC) when configured to store two bits of information each, triple-level cells (TLC) when configured to store three bits of information each, quad-level cells (QLC) when configured to store four bits of information each, or more generally, multi-level memory cells. Multi-level memory cells may provide greater storage density relative to SLC memory cells, but in some cases may involve narrower read or write margins or greater complexity for supporting circuitry.

[0034] In some cases, a plane 165 may refer to a number of group blocks 170, and in some cases, concurrent operations may be performed on different planes 165. For example, concurrent operations may be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, individual blocks 170 may be referred to as physical blocks, and a virtual block 180 may refer to a group of blocks 170 within which concurrent operations may occur. For example, concurrent operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d within planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as virtual blocks 180. In some cases, a virtual block may include blocks 170 from different memory devices 130 (e.g., blocks in one or more planes including memory device 130-a and memory device 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be "block 0" of plane 165-a, block 170-b may be "block 0" of plane 165-b, etc.). In some cases, performing concurrent operations in different planes 165 may be subject to one or more restrictions, such as performing concurrent operations on memory cells in different pages 175 having the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0035] In some cases, block 170 may include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share (e.g., be coupled to) a common word line, and memory cells in the same string may share (e.g., be coupled to) a common digit line (which may alternatively be referred to as a bit line).

[0036] For some NAND architectures, memory cells may be read and programmed (e.g., written) at a first granularity (e.g., at a page granularity or portions thereof) but may be erased at a second granularity (e.g., at a block granularity). That is, a page 175 may be the smallest unit of memory (e.g., a group of memory cells) that may be independently programmed or read (e.g., concurrently programmed or read as part of a single programming or reading operation), and a block 170 may be the smallest unit of memory (e.g., a group of memory cells) that may be independently erased (e.g., concurrently erased as part of a single erase operation). Furthermore, in some cases, a NAND memory cell may be erased before it may be rewritten with new data. Thus, for example, in some cases, a used page 175 may not be updated until the entire block 170 including the page 175 is erased.

[0037] The system 100 may include any number of non-transitory computer-readable media that support data transfer during maintenance operations. For example, the host system 105 (e.g., host system controller 106), the memory system 110 (e.g., memory system controller 115), or the memory device 130 (e.g., local controller 135) may include or otherwise have access to one or more non-transitory computer-readable media storing instructions (e.g., firmware, logic, code) for performing the functions attributed herein to the host system 105, the memory system 110, or the memory device 130. For example, such instructions, when executed by the host system 105 (e.g., host system controller 106), the memory system 110 (e.g., memory system controller 115), or the memory device 130 (e.g., local controller 135), may cause the host system 105, the memory system 110, or the memory device 130 to perform the associated functions described herein.

[0038] The memory system 110 described herein may transfer data from the memory system controller 115 to a first block 170-a (e.g., block N) via a bus, and may begin programming the data (e.g., during a maintenance operation). In some examples, the memory system controller 115 may suspend programming the data and may read data from a second block 170-b via a bus. After reading the data from the second block, the memory system controller 115 may resume programming the data to the first block and may transfer the data to a third block 170-c (e.g., block N+1) while programming the first block 170-a. Thus, if the first block 170-a is programmed, the memory system controller 115 may begin programming the third block 170-c. By performing such operations in parallel, the memory system 110 may mitigate undesirable delays that would otherwise be caused by performing operations serially. Thus, the overall performance of the memory system 110 may be improved.

[0039] Figure 2AAn example of a timing diagram 200-a for supporting data transfer during maintenance operations is shown in contrast to the examples disclosed herein. The timing diagram 200-a may illustrate the example of a timing diagram 200-a for supporting data transfer during maintenance operations. Figure 1 For example, the memory system 110 may illustrate data transfer via a bus 205 (e.g., an ONFI bus) and may illustrate programming operations at one or more NAND devices 210. In some examples, the bus 205 may communicate with the NAND devices 210 and a controller (e.g., reference 100). Figure 1 The memory system controller 115 described herein is coupled to the memory system controller 115. Figure 2A Aspects of the described conventional methods may be performed serially, which may add undesirable latency to maintenance operations performed by the memory system, which may affect its overall performance.

[0040] In some cases, conventional systems or methods for data transfer during maintenance operations may be limited to serial (e.g., non-overlapping) operations, and the memory system may not be able to transfer data for the next sequential program (e.g., N+1) while performing programming for the current program (e.g., N). For example, as shown by timing diagram 200-a, a first portion of data may be read from a block of memory cells of NAND device 210 during a first duration 215. During a second duration 220, the first portion of data may be transferred (e.g., read xFer) to a memory system controller via bus 205. In some examples, a second portion of data may be read from a block of memory cells of NAND device 210 during a third duration 225, and the second portion of data may be transferred to the memory system controller via bus 205 during a fourth duration 230.

[0041] During the fifth duration 235, the memory system controller may transfer (eg, write xFer) the data read from the memory cell block to the second memory cell block of the NAND device 210 via the bus 205. During the sixth duration 240, the data may be programmed into the second memory cell block of the NAND device 210. Figure 2A 2, a memory system may serially perform maintenance operations on a block of memory cells (e.g., block N). That is, data may be read from the NAND devices, transferred to the memory system controller via bus 205, and written (e.g., programmed) to the NAND devices 210 during the serial operation. Similar processes may occur in response to performing maintenance operations on additional blocks (e.g., block N+1, block N+2, etc.).

[0042] Due to the serialization of aspects of each maintenance operation, the time for each maintenance operation may include a relatively long duration allocated to transferring data (e.g., read xFer, write xFer) via bus 205. For example, in response to performing a maintenance operation on a TLC block, bus 205 transfers may be up to half of the total duration of the maintenance operation. In addition, as illustrated by timing diagram 200-a, the memory system is to perform subsequent maintenance operations (e.g., for block N+1) after the current maintenance operation (e.g., for block N) is completed. Performing operations serially adds latency to the maintenance operations, which can affect the overall performance of the memory system. Therefore, a memory system configured to perform aspects of the maintenance operations in parallel may be desirable.

[0043] Figure 2B An example of a timing diagram 200-b is shown for supporting data transfer during maintenance operations according to examples disclosed herein. The timing diagram 200-b may illustrate the data transfer during maintenance operations according to examples disclosed herein. Figure 1 For example, the memory system 110 may illustrate data transfer via a bus 205 (e.g., an ONFI bus) and may illustrate programming operations at one or more NAND devices 210. In some examples, the bus 205 may communicate with the NAND devices 210 and a controller (e.g., reference 100). Figure 1 The timing diagram 200-b may illustrate aspects of maintenance operations performed in parallel, which may mitigate undesirable delays that would otherwise be caused by serially performing operations. Thus, the overall performance of the associated memory system may be improved.

[0044] In some cases, the memory system controller may be operable to transfer data to and from the NAND device 210 via the bus 205 during one or more maintenance operations (e.g., garbage collection, write-back refresh operations, or the like). For example, during a maintenance operation, the memory system controller may move (e.g., transfer) data from a first block of the NAND device 210 to a second block of the NAND device 210. In some examples, the first block and the second block may be SLC blocks, MLC blocks, TLC blocks, QLC blocks, or combinations thereof.

[0045] In some cases, to move (e.g., transfer) data, the memory system controller may transfer (e.g., read xFer) data from a first memory block of NAND devices 210 to the memory system controller via bus 205. For example, the memory system controller may receive one or more portions of data from the NAND device 210 via bus 205. Similarly, the memory system controller may transfer (e.g., write xFer) data to a second block of NAND devices 210 via bus 205. For example, once the one or more portions of data are received by the memory controller, the memory system controller may transfer the portions of data to the second block of NAND devices 210 (e.g., via bus 205) for programming.

[0046] In some cases, data may be transferred over the bus 205 when performing one or more programming operations on the NAND device 210. For example, during the first duration 245, data may be programmed (e.g., written) to a first block (e.g., block N) of the NAND device 210. Although not illustrated, the data may have previously been read from the block, transferred to the memory system controller via the bus 205, and transferred from the memory system controller to the block via the bus 205.

[0047] During the second duration 250, the memory system may enable an auto-suspend feature. In some examples, the auto-suspend feature may be enabled based on the memory system (e.g., a memory system controller) receiving a command from the host system. In some instances, the auto-suspend feature may be defined by a standard or specification, such as a Joint Electronic Device Engineering Council (JEDEC) standard or an ONFI specification. The auto-suspend feature may suspend (e.g., temporarily suspend, suspend during the second duration 250) data programming to the first block of the NAND device 210.

[0048] Additionally or alternatively, during the second duration 250, at least a portion (e.g., a first portion, a first subset) of the data may be read from a second block (e.g., block N+1) of the NAND device 210. In some examples, the second block may be an SLC, MLC, TLC, or QLC block. For example, if the maintenance operation is a write buffer (WB) refresh operation, the second block may be an SLC block, and if the maintenance operation is a garbage collection operation, the second block may be a TLC block.

[0049] During the third duration 255, the first subset of data may be transferred to the memory system controller via the bus 205. In parallel operation, the programming operation on the first block may be resumed. That is, the programming of data to block N that was suspended during the second duration 250 may be resumed during the third duration 255. Therefore, during the third duration 255, the first subset of data may be transferred to the memory system controller via the bus 205 in parallel with the programming of data to block N, which may reduce the latency of the maintenance operation.

[0050] During the fourth duration 260, the memory system may enable an auto-suspend feature (e.g., a second auto-suspend feature, a second auto-suspend feature). In some examples, the auto-suspend feature may be enabled based on the memory system (e.g., a memory system controller) receiving a command from the host system. As described herein, the auto-suspend feature may be defined by a JEDEC standard or an ONFI specification. The auto-suspend feature may suspend (e.g., temporarily suspend, suspend during the fourth duration 260) programming of data to the first block of the NAND device 210. Additionally or alternatively, during the fourth duration 260, at least a portion (e.g., a second portion, a second subset) of the data may be read from a second block (e.g., block N+1) of the NAND device 210.

[0051] During the fifth duration 265, the programming operation on the first block may be resumed. That is, the data programming to the block N that was suspended during the fourth duration 260 may be resumed during the fifth duration 265. During the parallel operation (e.g., during the duration 270 that at least partially overlaps with the fifth duration 265), the second subset of data may be transferred to the memory system controller via the bus 205.

[0052] Additionally, during the second parallel operation (e.g., during the duration 275 that at least partially overlaps with the fifth duration 265), data may be transferred from the memory system controller to a second block of memory cells (e.g., block N+1) of the NAND device 210 via the bus 205. In some examples, due to one or more characteristics of the memory system, the data for block N+1 may be transferred as a single data set, whereas in a previous programming operation (e.g., for block N), the data may have been transferred as multiple data sets. In other examples (e.g., for programming blocks N+2, N+3, etc.), the associated data may be transferred in a single data set. Thus, during the fifth duration 265, a second subset of the data may be transferred to the memory system controller via the bus 205 and the transfer of the data to block N+1 may be in parallel with the programming of the data to block N, which may reduce latency for maintenance operations.

[0053] During the sixth duration 280, a programming operation may be performed on the second block (e.g., block N+1). In some examples, the sixth duration may occur immediately after the fifth duration 265. That is, the programming operation on block N+1 may begin after the programming operation on block N is completed (e.g., immediately after the programming operation on block N is completed). Figure 2B , operations for programming block N and block N+1 can be used to program subsequent blocks during one or more maintenance operations. By performing operations in parallel as described herein, the memory system can mitigate undesirable delays that would otherwise be caused by performing operations in series. Thus, the overall performance of the memory system can be improved.

[0054] Figure 3 An example of a process flow 300 for supporting data transfer during maintenance operations according to examples disclosed herein is shown. The process flow 300 may illustrate reference Figure 1 For example, process flow 300 may depict operations at host system 305 and memory system 310, which may be referenced as Figure 1 3. The process flow 300 is an example of a host system 105 and a memory system 110 described herein. According to the operations described herein, the memory system 310 may include a memory system controller 315, a first block 320, a second block 325, and a third block 330. The process flow 300 may illustrate aspects of maintenance operations performed in parallel, which may mitigate undesirable delays that would otherwise be caused by serially performing operations. Therefore, the overall performance of the memory system 310 may be improved.

[0055] In the following description of the process flow 300, the methods, techniques, processes, and operations may be performed in a different order or at a different time. In addition, some operations may be omitted from the process flow 300, or other operations may be added to the process flow 300.

[0056] At 335, data may be programmed (e.g., written) to the first block 320. In some examples, the data may have been previously read from another block and transferred during a duration (e.g., a seventh duration, not shown) to the memory system controller 315. As described herein, the first block 320 may be an SLC block when the programming operation is associated with a WB refresh and may be a TLC block when the programming operation is associated with a garbage collection operation.

[0057] At 340, a command can be received by the memory system controller 315. In some examples, the command can be transmitted from the host system 305 to the memory system controller 315. The command can activate an auto-suspend feature at the memory system 310.

[0058] At 345, the auto-suspend feature may be enabled and data may be read from the second block 325. In some examples, the memory system controller 315 may enable the auto-suspend feature based on receiving a command (e.g., at 340) and read data from the second block 325. As described herein, the auto-suspend feature may suspend (e.g., suspend) performing a programming operation on the first block 320 (e.g., at 335).

[0059] At 350, data may be transferred from the second block 325. In some examples, the transferred data may be a subset of a set of data stored to the second block 325. The data may be transferred to the memory system controller 315 via a bus, such as the bus 205 described with reference to FIG.

[0060] At 355, data may be programmed (e.g., written) to the first block 320. In some examples, the programming operation may resume on the first block 320 after being paused (e.g., at 345). In some examples, the operations performed at 350 and 355 may occur in parallel (e.g., during the same duration) and thus may be collectively referred to as a single operation 360.

[0061] At 365, an auto-suspend feature (e.g., a second auto-suspend feature, a second auto-suspend feature) may be enabled and data may be read from the second block 325. In some examples, the memory system controller 315 may enable the auto-suspend feature based on receiving a second command (not shown) and read data from the second block 325. As described herein, the auto-suspend feature may suspend (e.g., suspend) performing a programming operation on the first block 320 (e.g., at 355).

[0062] At 370, data may be transferred from the second block 325. In some examples, the transferred data may be a subset (e.g., a second subset) of a set of data stored to the second block 325. The data may be transferred to the memory system controller 315 via a bus (e.g., bus 205 described with reference to FIG. 2 ).

[0063] At 375, data may be programmed (e.g., written) to the first block 320. In some examples, the programming operation may resume on the first block 320 after being suspended (e.g., at 365). In some examples, the programming operation may be completed at 375 (e.g., data may be fully programmed to the first block 320).

[0064] At 380, the data read from the second block 325 may be transferred to the third block 330. In some examples, the data may be transferred from the memory system controller 315 to the third block 330 via a bus. In some examples, the operations performed at 370, 375, and 380 may occur concurrently (e.g., during the same duration) and thus may be collectively referred to as a single operation 385.

[0065] At 390, data may be programmed (e.g., written) to the third block 330. In some examples, the data may be written to the third block 330 based on its transfer from the memory system controller 315 (e.g., at 380). As described herein, the third block 330 may be an SLC block when the programming operation is associated with a WB refresh and may be a TLC block when the programming operation is associated with a discarded item collection operation. By performing operations in parallel as described herein, the memory system 310 may mitigate undesirable delays that would otherwise be caused by performing operations serially. Therefore, the overall performance of the memory system 310 may be improved.

[0066] Figure 4 A block diagram 400 is shown of a memory system 420 that supports data transfer during maintenance operations according to examples disclosed herein. The memory system 420 may be a reference Figures 1 to 5 4. The memory system 420 or its various components may be examples of means for performing various aspects of data transfer during maintenance operations, as described herein. For example, the memory system 420 may include a write component 425, a pause component 430, a read component 435, a transfer component 440, a receive component 445, or any combination thereof. Each of these components may communicate directly or indirectly with each other (e.g., via one or more buses).

[0067] The write component 425 may be configured as or otherwise support means for writing a first subset of a first set of data to one or more multi-level memory cells of a memory system during a first duration of a maintenance operation. The pause component 430 may be configured as or otherwise support means for pausing writing of the first set of data to one or more multi-level memory cells of a memory system during a second duration of a maintenance operation. The read component 435 may be configured as or otherwise support means for reading a first subset of a second set of data from one or more memory cells of a memory system during a second duration. The transfer component 440 may be configured as or otherwise support means for transferring the first subset of the second set of data from one or more memory cells to a controller of the memory system via a bus during a third duration of a maintenance operation based at least in part on reading the first subset of the second set of data. In some examples, the write component 425 may be configured as or otherwise support means for writing a second subset of the first set of data to one or more multi-level memory cells of a memory system during the third duration and concurrently with transferring the first subset of the second set of data.

[0068] In some examples, the pause component 430 can be configured to or otherwise support means for pausing reading the second set of data from the one or more memory cells of the memory system and writing the second subset of the first set of data to the one or more multi-level memory cells of the memory system during the fourth duration of the maintenance operation. In some examples, the read component 435 can be configured to or otherwise support means for reading the second subset of the second set of data from the one or more memory cells of the memory system during the fourth duration of the maintenance operation based at least in part on pausing reading the second set of data from the one or more memory cells of the memory system.

[0069] In some examples, transfer component 440 can be configured as or otherwise support means for transferring a second subset of the second set of data from one or more memory cells of the memory system to the controller via the bus during a fifth duration of the maintenance operation based at least in part on reading the second subset of the second set of data. In some examples, write component 425 can be configured as or otherwise support means for writing a third subset of the first set of data to one or more multi-level memory cells of the memory system during the fifth duration and concurrently with transferring the second subset of the second set of data.

[0070] In some examples, transfer component 440 may be configured as or otherwise support means for transferring a second set of data from a controller of the memory system to one or more multi-level memory cells of the memory system via the bus during a fifth duration based at least in part on transferring a second subset of the second set of data from the one or more memory cells to the controller via the bus.

[0071] In some examples, write component 425 may be configured as or otherwise support means for writing a first subset of the second set of data to one or more multi-level memory cells of the memory system during a sixth duration of the maintenance operation based at least in part on communicating the second set of data from the controller to the one or more multi-level memory cells of the memory system via the bus.

[0072] In some examples, concurrently with writing the third subset of the first set of data to the one or more multi-level memory cells of the memory system, the second set of data is transferred from the controller to the one or more multi-level memory cells.

[0073] In some examples, the first set of data includes a first subset, a second subset, and a third subset. In some examples, the second set of data includes the first subset and the second subset.

[0074] In some examples, a first subset of the second set of data is read from one or more memory cells of the memory system while a second subset of the first set of data is written to one or more multi-level memory cells of the memory system.

[0075] In some examples, read component 435 can be configured or otherwise support means for reading the first set of data from one or more memory cells of the memory system during a seventh duration of the maintenance operation prior to the first duration. In some examples, transfer component 440 can be configured or otherwise support means for transferring the first set of data from a controller of the memory system to one or more multi-level memory cells of the memory system during the seventh duration based at least in part on reading the first set of data from the one or more memory cells, wherein writing the first subset of the first set of data is based at least in part on transferring the first set of data from the controller to the one or more multi-level memory cells of the memory system.

[0076] In some examples, receiving component 445 may be configured to or otherwise support means for receiving a command prior to the second duration of the maintenance operation, wherein suspending writing of the first set of data to the one or more multi-level memory cells and reading of the first subset of the second set of data from the one or more memory cells of the memory system is based at least in part on receiving the command.

[0077] In some examples, one or more memory cells of the memory system include single level memory cells or triple level memory cells.

[0078] Figure 5 A flowchart illustrating a method 500 for supporting data transfer during maintenance operations according to examples disclosed herein is shown. The operations of the method 500 may be implemented by a memory system or components thereof described herein. For example, the operations of the method 500 may be implemented by reference to Figures 1 to 4 The wireless memory system may perform the described functions. In some examples, the memory system may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the wireless memory system may use dedicated hardware to perform aspects of the described functions.

[0079] At 505, the method may include writing a first subset of a first set of data to one or more multi-level memory cells of a memory system during a first duration of a maintenance operation. Operation 505 may be performed according to examples disclosed herein. In some examples, aspects of operation 505 may be described with reference to Figure 4 The write component 425 described performs.

[0080] At 510, the method may include suspending writing of the first set of data to one or more multi-level memory cells of the memory system during a second duration of the maintenance operation. Operation 510 may be performed according to examples disclosed herein. In some examples, aspects of operation 510 may be described with reference to Figure 4 The described pause component 430 executes.

[0081] At 515, the method may include reading a first subset of the second set of data from one or more memory cells of the memory system during a second duration. Operation 515 may be performed according to examples disclosed herein. In some examples, aspects of operation 515 may be described with reference to Figure 4 The described read component 435 executes.

[0082] At 520, the method may include transferring the first subset of the second set of data from the one or more memory cells to a controller of the memory system via the bus during the third duration of the maintenance operation based at least in part on reading the first subset of the second set of data. Operation 520 may be performed according to examples disclosed herein. In some examples, aspects of operation 520 may be described with reference to Figure 4 The described transfer component 440 performs.

[0083] At 525, the method may include writing a second subset of the first set of data to one or more multi-level memory cells of the memory system during a third duration and concurrently with transmitting the first subset of the second set of data. Operation 525 may be performed according to examples disclosed herein. In some examples, aspects of operation 525 may be described with reference to Figure 4 The write component 425 described performs.

[0084] In some examples, the apparatus described herein may perform one or several methods, such as method 500. The apparatus may include features, circuitry, logic, means, or instructions (such as a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0085] Aspect 1: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: writing a first subset of a first set of data to one or more multi-level memory cells of a memory system during a first duration of a maintenance operation; suspending writing of the first set of data to the one or more multi-level memory cells of the memory system during a second duration of the maintenance operation; reading a first subset of a second set of data from one or more memory cells of the memory system during the second duration; transferring the first subset of the second set of data from the one or more memory cells to a controller of the memory system via a bus during a third duration of the maintenance operation based at least in part on reading the first subset of the second set of data; and writing a second subset of the first set of data to the one or more multi-level memory cells of the memory system during the third duration and concurrently with transferring the first subset of the second set of data.

[0086] Aspect 2: The method, apparatus, or non-transitory computer-readable medium of Aspect 1, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: suspending reading of the second set of data from the one or more memory cells of the memory system and writing the second subset of the first set of data to the one or more multi-level memory cells of the memory system during a fourth duration of the maintenance operation; and reading a second subset of the second set of data from the one or more memory cells of the memory system during the fourth duration of the maintenance operation based at least in part on suspending reading of the second set of data from the one or more memory cells of the memory system.

[0087] Aspect 3: The method, apparatus, or non-transitory computer-readable medium of Aspect 2, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: transferring the second subset of the second set of data from the one or more memory cells of the memory system to the controller via the bus during a fifth duration of the maintenance operation based at least in part on reading the second subset of the second set of data; and writing a third subset of the first set of data to the one or more multi-level memory cells of the memory system during the fifth duration and concurrently with transferring the second subset of the second set of data.

[0088] Aspect 4: The method, apparatus, or non-transitory computer-readable medium of Aspect 3, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for transferring the second set of data from the controller of the memory system to one or more multi-level memory cells of the memory system via the bus during the fifth duration based at least in part on transferring the second subset of the second set of data from the one or more memory cells to the controller via the bus.

[0089] Aspect 5: The method, apparatus, or non-transitory computer-readable medium of Aspect 4, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for writing the first subset of the second set of data to the one or more multi-level memory cells of the memory system during a sixth duration of the maintenance operation based at least in part on transferring the second set of data from the controller to the one or more multi-level memory cells of the memory system via the bus.

[0090] Aspect 6: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 4 to 5, wherein the second set of data is transferred from the controller to the one or more multi-level memory cells concurrently with the third subset of the first set of data being written to the one or more multi-level memory cells of the memory system.

[0091] Aspect 7: A method, apparatus, or non-transitory computer-readable medium according to any one of aspects 3 to 6, wherein the first set of data includes the first subset, the second subset, and the third subset, and the second set of data includes the first subset and the second subset.

[0092] Aspect 8: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 7, wherein the first subset of the second set of data is read from the one or more memory cells of the memory system, and the second subset of the first set of data is written to the one or more multi-level memory cells of the memory system.

[0093] Aspect 9: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 8, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: reading the first set of data from one or more memory cells of the memory system during a seventh duration of the maintenance operation prior to the first duration; and transferring the first set of data from a controller of the memory system to the one or more multi-level memory cells of the memory system during the seventh duration based at least in part on reading the first set of data from the one or more memory cells, wherein writing the first subset of the first set of data is based at least in part on transferring the first set of data from the controller to the one or more multi-level memory cells of the memory system.

[0094] Aspect 10: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 9, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: receiving a command before the second duration of the maintenance operation, wherein suspending writing of the first set of data to the one or more multi-level memory cells and reading of the first subset of the second set of data from the one or more memory cells of the memory system is based at least in part on receiving the command.

[0095] Aspect 11: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 to 10, wherein the one or more memory cells of the memory system include single-level memory cells or triple-level memory cells.

[0096] It should be noted that the described techniques include possible implementations, and that the operations and steps may be rearranged or otherwise modified and other implementations are possible. Furthermore, portions from two or more of the methods may be combined.

[0097] The information and signals described herein may be represented using any of a variety of different techniques and technologies. For example, data, instructions, commands, information, signals, bits, or signaling symbols that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, a signal may represent a signal bus, where the bus may have various bit widths.

[0098] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication (or in conductive contact or connected or coupled) with each other if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact or connected or coupled) with each other may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some examples, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0099] The term "coupled" (e.g., "electrically coupled") may refer to a condition that transitions from an open circuit relationship between components (where signals cannot currently pass between components via conductive paths) to a closed circuit relationship between components (where signals can pass between components via conductive paths). If a component, such as a controller, couples other components together, the component causes a change that allows signals to flow between the other components via conductive paths that previously did not allow signals to flow.

[0100] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. If an open circuit exists between the components, then the components are isolated from each other. For example, if a switch positioned between two components is open, then the components separated by the switch are isolated from each other. If a controller isolates two components, then the controller causes a change that prevents a signal from flowing between the components using a conductive path that previously permitted the signal to flow.

[0101] The terms "if," "when," "based on," or "based at least in part on" may be used interchangeably. In some instances, if the terms "if," "when," "based on," or "based at least in part on" are used to describe a connection between conditional actions, conditional processes, or parts of processes, the terms may be interchangeable.

[0102] The term "responsive to" may refer to one condition or action occurring at least in part, if not entirely, as a result of a preceding condition or action. For example, a first condition or action may be performed and a second condition or action may occur at least in part as a result of the preceding condition or action occurring (whether directly after the first condition or action or after one or more other intermediate conditions or actions occurring after the first condition or action).

[0103] The devices discussed herein, including memory arrays, may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping may be performed by ion implantation during the initial formation or growth of the substrate or by any other doping method.

[0104] The switch components or transistors discussed herein may represent field effect transistors (FETs) and include three-terminal devices including a source, a drain, and a gate. The terminals may be connected to other electronic components by conductive materials such as metals. The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most carriers are holes), the FET may be referred to as a p-type FET. The channel may be covered by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. If a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". If a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0105] The description set forth herein describes example configurations in conjunction with the accompanying drawings and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" rather than "preferred" or "superior to other examples". The "Detailed Description" includes specific details for providing an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0106] In the accompanying drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a hyphen and a second label that distinguishes the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0107] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted by a computer-readable medium as one or more instructions or codes. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the described functions may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. Features that implement the functions may also be physically located at various locations, including being distributed so that portions of the functions are implemented at different physical locations.

[0108] For example, the various illustrative blocks and components described herein in connection with the present disclosure may be implemented or performed with a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0109] As used herein (including in the claims), "or" used in a list of items (e.g., a list of items preceded by a phrase such as "at least one of" or "one or more of") indicates an inclusive list, so that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be interpreted as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0110] Computer-readable media include both non-transitory computer storage media and communication media, including any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media may be any available media that can be accessed by a general or special computer. For example, but not limited to, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage device, magnetic disk storage device or other magnetic storage device or can be used to carry or store the desired program code components in the form of instructions or data structures and can be accessed by a general or special computer or a general or special processor. Any other non-transitory media. Moreover, any connection is appropriately referred to as computer-readable media. For example, if the software is transmitted from a website, server or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology (such as infrared, radio and microwave), then coaxial cable, fiber optic cable, twisted pair, DSL or wireless technology (such as infrared, radio and microwave) are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of these are also included within the scope of computer-readable media.

[0111] The description herein is provided to enable persons skilled in the art to make or use the present disclosure. Persons skilled in the art will appreciate various modifications of the present disclosure, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but should be given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: Memory device; and a controller coupled to the memory device and configured to cause the apparatus to: writing a first subset of a first set of data to one or more multi-level memory cells of the memory device during a first duration of a maintenance operation; suspending writing of the first set of data to the one or more multi-level memory cells of the memory device during a second duration of the maintenance operation; reading a first subset of a second set of data from one or more memory cells of the memory device during the second duration; transferring the first subset of the second set of data from the one or more multi-level memory cells to the controller via a bus during a third duration of the maintenance operation based at least in part on reading the first subset of the second set of data; and A second subset of the first set of data is written to the one or more multi-level memory cells of the memory device during the third duration and concurrently with transferring the first subset of the second set of data.

2. The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to: suspending reading the second set of data from the one or more memory cells of the memory device and writing the second subset of the first set of data to the one or more multi-level memory cells of the memory device during a fourth duration of the maintenance operation; and A second subset of the second set of data is read from the one or more memory cells of the memory device during the fourth duration of the maintenance operation based at least in part on suspending reading of the second set of data from the one or more memory cells of the memory device.

3. The apparatus of claim 2, wherein the controller is further configured to cause the apparatus to: transferring the second subset of the second set of data from the one or more memory cells of the memory device to the controller via the bus during a fifth duration of the maintenance operation based at least in part on reading the second subset of the second set of data; and A third subset of the first set of data is written to the one or more multi-level memory cells of the memory device during the fifth duration and concurrently with transferring the second subset of the second set of data.

4. An apparatus according to claim 3, wherein the controller is further configured to cause the apparatus to: transfer the second set of data from the controller of the memory device to the one or more multi-level memory cells of the memory device via the bus during the fifth time duration based at least in part on transferring the second subset of the second set of data from the one or more memory cells to the controller via the bus.

5. An apparatus according to claim 4, wherein the controller is further configured to cause the apparatus to: write the first subset of the second set of data to the one or more multi-level memory cells of the memory device during a sixth duration of the maintenance operation based at least in part on transmitting the second set of data from the controller to the one or more multi-level memory cells of the memory device via the bus.

6. The apparatus of claim 4, wherein concurrently with writing the third subset of the first set of data to the one or more multi-level memory cells of the memory device, the second set of data is transferred from the controller to the one or more multi-level memory cells.

7. The apparatus of claim 3, wherein: The first set of data includes the first subset, the second subset, and the third subset, and The second set of data includes the first subset and the second subset.

8. The apparatus of claim 1, wherein the first subset of the second set of data is read from the one or more memory cells of the memory device while the second subset of the first set of data is written to the one or more multi-level memory cells of the memory device.

9. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: reading the first set of data from the one or more memory cells of the memory device during a seventh duration of the maintenance operation preceding the first duration; and The first set of data is transferred from the controller to the one or more multi-level memory cells of the memory device during the seventh time duration based at least in part on reading the first set of data from the one or more memory cells, wherein writing the first subset of the first set of data is based at least in part on transferring the first set of data from the controller to the one or more multi-level memory cells of the memory device.

10. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: receive a command prior to the second duration of the maintenance operation, wherein suspending writing of the first set of data to the one or more multi-level memory cells and reading of the first subset of the second set of data from the one or more memory cells of the memory device is based at least in part on receiving the command.

11. The apparatus of claim 1, wherein the one or more memory cells of the memory device comprise single level memory cells or triple level memory cells.

12. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: writing a first subset of a first set of data to one or more multi-level memory cells of a memory system during a first duration of a maintenance operation; suspending writing of the first set of data to the one or more multi-level memory cells of the memory system during a second duration of the maintenance operation; reading a first subset of a second set of data from one or more memory cells of the memory system during the second duration; transferring the first subset of the second set of data from the one or more multi-level memory cells to a controller of the memory system via a bus during a third duration of the maintenance operation based at least in part on reading the first subset of the second set of data; and A second subset of the first set of data is written to the one or more multi-level memory cells of the memory system during the third duration and concurrently with transferring the first subset of the second set of data.

13. The non-transitory computer-readable medium of claim 12, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: suspending reading the second set of data from the one or more memory cells of the memory system and writing the second subset of the first set of data to the one or more multi-level memory cells of the memory system during a fourth duration of the maintenance operation; and A second subset of the second set of data is read from the one or more memory cells of the memory system during the fourth duration of the maintenance operation based at least in part on suspending reading of the second set of data from the one or more memory cells of the memory system.

14. The non-transitory computer-readable medium of claim 13, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: transferring the second subset of the second set of data from the one or more memory cells of the memory system to the controller via the bus during a fifth duration of the maintenance operation based at least in part on reading the second subset of the second set of data; and A third subset of the first set of data is written to the one or more multi-level memory cells of the memory system during the fifth duration and concurrently with transferring the second subset of the second set of data.

15. The non-transitory computer-readable medium of claim 14, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: The second set of data is transferred from the controller of the memory system to the one or more multi-level memory units of the memory system via the bus during the fifth time duration based at least in part on transferring the second subset of the second set of data from the one or more memory units to the controller via the bus.

16. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: The first subset of the second set of data is written to the one or more multilevel memory cells of the memory system during a sixth duration of the maintenance operation based at least in part on transferring the second set of data from the controller to the one or more multilevel memory cells of the memory system via the bus.

17. The non-transitory computer-readable medium of claim 15, wherein concurrently with the third subset of the first set of data being written to the one or more multi-level memory cells of the memory system, the second set of data is transferred from the controller to the one or more multi-level memory cells.

18. The non-transitory computer-readable medium of claim 14, wherein: The first set of data includes the first subset, the second subset, and the third subset, and The second set of data includes the first subset and the second subset.

19. The non-transitory computer-readable medium of claim 12, wherein the first subset of the second set of data is read from the one or more memory cells of the memory system while the second subset of the first set of data is written to the one or more multi-level memory cells of the memory system.

20. The non-transitory computer-readable medium of claim 12, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: reading the first set of data from the one or more memory cells of the memory system during a seventh duration of the maintenance operation preceding the first duration; and The first set of data is transferred from the controller of the memory system to the one or more multi-level memory cells of the memory system during the seventh time duration based at least in part on reading the first set of data from the one or more memory cells, wherein writing the first subset of the first set of data is based at least in part on transferring the first set of data from the controller to the one or more multi-level memory cells of the memory system.

21. The non-transitory computer-readable medium of claim 12, wherein the instructions are further executable by the processor to: A command is received prior to the second duration of the maintenance operation, wherein suspending writing of the first set of data to the one or more multi-level memory cells and reading of the first subset of the second set of data from the one or more memory cells of the memory system is based at least in part on receiving the command.

22. The non-transitory computer-readable medium of claim 12, wherein: The one or more memory cells of the memory system include single-level memory cells or triple-level memory cells.

23. A method comprising: writing a first subset of a first set of data to one or more multi-level memory cells of a memory system during a first duration of a maintenance operation; suspending writing of the first set of data to the one or more multi-level memory cells of the memory system during a second duration of the maintenance operation; reading a first subset of a second set of data from one or more memory cells of the memory system during the second duration; transferring the first subset of the second set of data from the one or more multi-level memory cells to a controller of the memory system via a bus during a third duration of the maintenance operation based at least in part on reading the first subset of the second set of data; and A second subset of the first set of data is written to the one or more multi-level memory cells of the memory system during the third duration and concurrently with transferring the first subset of the second set of data.

24. The method of claim 23, further comprising: suspending reading the second set of data from the one or more memory cells of the memory system and writing the second subset of the first set of data to the one or more multi-level memory cells of the memory system during a fourth duration of the maintenance operation; and A second subset of the second set of data is read from the one or more memory cells of the memory system during the fourth duration of the maintenance operation based at least in part on suspending reading of the second set of data from the one or more memory cells of the memory system.

25. The method of claim 24, further comprising: transferring the second subset of the second set of data from the one or more memory cells of the memory system to the controller via the bus during a fifth duration of the maintenance operation based at least in part on reading the second subset of the second set of data; and A third subset of the first set of data is written to the one or more multi-level memory cells of the memory system during the fifth duration and concurrently with transferring the second subset of the second set of data.

26. The method of claim 25, further comprising: The second set of data is transferred from the controller of the memory system to the one or more multi-level memory units of the memory system via the bus during the fifth time duration based at least in part on transferring the second subset of the second set of data from the one or more memory units to the controller via the bus.

27. The method of claim 26, further comprising: The first subset of the second set of data is written to the one or more multilevel memory cells of the memory system during a sixth duration of the maintenance operation based at least in part on transferring the second set of data from the controller to the one or more multilevel memory cells of the memory system via the bus.

28. The method of claim 26, wherein concurrently with writing the third subset of the first set of data to the one or more multi-level memory cells of the memory system, the second set of data is transferred from the controller to the one or more multi-level memory cells.

29. The method of claim 25, wherein: The first set of data includes the first subset, the second subset, and the third subset, and The second set of data includes the first subset and the second subset.

30. The method of claim 23, wherein the first subset of the second set of data is read from the one or more memory cells of the memory system while the second subset of the first set of data is written to the one or more multi-level memory cells of the memory system.

31. The method of claim 23, further comprising: reading the first set of data from the one or more memory cells of the memory system during a seventh duration of the maintenance operation preceding the first duration; and The first set of data is transferred from the controller of the memory system to the one or more multi-level memory cells of the memory system during the seventh time duration based at least in part on reading the first set of data from the one or more memory cells, wherein writing the first subset of the first set of data is based at least in part on transferring the first set of data from the controller to the one or more multi-level memory cells of the memory system.

32. The method of claim 23, further comprising: A command is received prior to the second duration of the maintenance operation, wherein suspending writing of the first set of data to the one or more multi-level memory cells and reading of the first subset of the second set of data from the one or more memory cells of the memory system is based at least in part on receiving the command.

33. The method of claim 23, wherein the one or more memory cells of the memory system comprise single level memory cells or triple level memory cells.

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