Signal transmission method and device

Abstract

The embodiment of the invention provides a signal transmission method and device, and the method comprises the steps: receiving a first PCIE bus signal transmitted by a first part through a PCIE bus through a first target chip, carrying out the first processing of the first PCIE bus signal, obtaining a first processing result, and transmitting the first processing result to a second target chip; and receiving the first processing result sent by the first target chip through the second target chip, performing second processing on the first processing result to obtain a second processing result, and sending the second processing result to the second component through the PCIE bus. According to the technical scheme, on the basis of the PCIE bus, chips used for different processing are combined to conduct signal transmission in the device, multiple channels do not need to be occupied by adopting the PCIE bus, the signal transmission quality is improved, two-way transmission can be achieved, and multiple video interfaces are supported.

Description

Technical Field

[0001] The present invention relates to the technical field of signal processing, and in particular to a method and device for signal transmission. Background Art

[0002] With the development of science and technology, the electronic and electrical architecture of automobiles and other equipment is constantly being upgraded. Functions such as unmanned driving, assisted driving, and automatic parking are gradually being applied in automobiles. These functions require the use of a large number of sensors such as cameras and radars to achieve environmental perception and decision-making control. For example, a car's automatic driving system can use up to 20 cameras of various types.

[0003] Due to the allocation and limitation of the spatial structure of automobile equipment, the SOC (System on Chip) that processes data is not arranged together with the display panel, and the sensor that obtains the image is not together with the ECU (Electronic Control Unit), so these sensors need to use serializers (SERializer) and deserializers (DESerializer) to transmit signals such as high-definition video data. For example, video data generally uses parallel high-speed data such as RGB interface or HDMI (High Definition Multimedia Interface) or DSI (Display Serial Interface) or CSI (Camera Serial Interface), which is serialized by the serializer for long-distance transmission.

[0004] like Figure 1 The existing parallel signal transmission requires multiple (such as 4) signal channels and a clock channel. The synchronization between multiple parallel signals and the clock can easily affect the quality of signal transmission, and parallel data can only be transmitted in one direction. If the system needs to achieve two-way communication, an additional reverse transmission channel is required, and a serializer or deserializer can only support one video interface. Summary of the invention

[0005] In view of the above problems, a method and device for signal transmission is proposed to overcome the above problems or at least partially solve the above problems, including:

[0006] A signal transmission method, wherein a device is deployed with multiple target chips, including a first target chip connected to a first component via a PCIE bus and a second target chip connected to a second component via a PCIE bus, the method comprising:

[0007] Receiving, by the first target chip, a first PCIE bus signal sent by the first component via the PCIE bus, performing a first process on the first PCIE bus signal to obtain a first process result, and sending the first process result to the second target chip;

[0008] The first processing result sent by the first target chip is received through the second target chip, a second processing is performed on the first processing result to obtain a second processing result, and the second processing result is sent to the second component via the PCIE bus, wherein the second processing is different from the first processing.

[0009] Optionally, the first PCIE bus signal is a first PCIE parallel bus signal, the first processing is a data encoding processing, the first processing result is a first serial signal, the second processing is a data decoding processing, and the second processing result is a second PCIE parallel bus signal.

[0010] Optionally, sending the second processing result to the second component via a PCIE bus includes:

[0011] Detecting a data analysis requirement, where the data analysis requirement is used to indicate whether data analysis needs to be performed on the data carried by the second processing result;

[0012] When the data analysis requirement indicates that data analysis needs to be performed on the data carried by the second processing result, the second processing result is sent to the third component via the PCIE bus, so that the third component analyzes the second processing result and outputs it to the second component;

[0013] When the data analysis requirement indicates that data analysis is not required for the data carried by the second processing result, the second processing result is sent to the second component via the PCIE bus.

[0014] Optionally, the third component includes any one of the following: a system-level chip, a PCIE switch.

[0015] Optionally, in the case where the second component is a display, the display displays the second processing result when receiving the second processing result;

[0016] Alternatively, when the second component is an executor, the executor performs a corresponding operation upon receiving the second processing result.

[0017] Optionally, sending the first processing result to the second target chip includes:

[0018] In the case where the first processing result is a coaxial cable signal, sending the first processing result to the second target chip via the coaxial cable;

[0019] In the case where the first processing result is an optical fiber serial signal, the first processing result is sent to the second target chip via an optical fiber.

[0020] Optionally, it also includes:

[0021] receiving, by the first target chip, a second serial signal, and performing a third process on the second serial signal to obtain a third process result;

[0022] And / or, receiving a fourth PCIE parallel bus signal through the second target chip, performing a fourth process on the fourth PCIE parallel bus signal, and obtaining a fourth process result.

[0023] Optionally, the third processing is a data decoding processing, and the third processing result is a third PCIE parallel bus signal; the fourth processing is a data encoding processing, and the fourth processing result is a third serial signal.

[0024] Optionally, the first component is a sensor in the vehicle, and the sensor includes a camera.

[0025] A signal transmission device, wherein the device is equipped with a plurality of target chips, including a first target chip connected to a first component via a PCIE bus and a second target chip connected to a second component via a PCIE bus, wherein the device is used for:

[0026] Receiving, by the first target chip, a first PCIE bus signal sent by the first component via the PCIE bus, performing a first process on the first PCIE bus signal to obtain a first process result, and sending the first process result to the second target chip;

[0027] The first processing result sent by the first target chip is received through the second target chip, the first processing result is subjected to second processing to obtain a second processing result, and the second processing result is sent to the second component via the PCIE bus.

[0028] A vehicle comprises a processor, a memory and a computer program stored in the memory and capable of running on the processor, wherein the computer program implements the method described above when executed by the processor.

[0029] An electronic device comprises a processor, a memory and a computer program stored in the memory and capable of running on the processor, wherein the computer program implements the method described above when executed by the processor.

[0030] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method described above is implemented.

[0031] A computer program product comprises a computer program, wherein when the computer program is executed by a processor, the computer program implements the method as described above.

[0032] The embodiments of the present invention have the following advantages:

[0033] In an embodiment of the present invention, a device is deployed with multiple target chips, including a first target chip connected to a first component via a PCIE bus and a second target chip connected to a second component via a PCIE bus. The first target chip receives a first PCIE bus signal sent by the first component via the PCIE bus, performs a first processing on the first PCIE bus signal, obtains a first processing result, and sends the first processing result to the second target chip. Then, the second target chip receives the first processing result sent by the first target chip, performs a second processing on the first processing result, obtains a second processing result, and sends the second processing result to the second component via the PCIE bus. This realizes signal transmission within the device by combining chips for different processing on the basis of the PCIE bus. The use of the PCIE bus does not require the occupation of multiple channels, improves the quality of signal transmission, can realize bidirectional transmission, and supports multiple video interfaces. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solution of the present invention, the accompanying drawings required for use in the description of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0035] Figure 1 It is a system architecture diagram provided by related technologies;

[0036] Figure 2a is a system architecture diagram provided by some embodiments of the present invention;

[0037] Figure 2b is another system architecture diagram provided by some embodiments of the present invention;

[0038] Figure 2c is another system architecture diagram provided by some embodiments of the present invention;

[0039] Figure 3 is a flowchart of a signal transmission method provided by some embodiments of the present invention;

[0040] Figure 4 is a flowchart of another signal transmission method provided by some embodiments of the present invention;

[0041] Figure 5 is a flowchart of another signal transmission method provided by some embodiments of the present invention;

[0042] Figure 6 is a flowchart of another signal transmission method provided by some embodiments of the present invention;

[0043] Figure 7 is a flowchart of another signal transmission method provided by some embodiments of the present invention;

[0044] Figure 8 is a flowchart of another signal transmission method provided by some embodiments of the present invention;

[0045] Fig. 9 It is a step flow chart of another signal transmission method provided by some embodiments of the present invention. DETAILED DESCRIPTION

[0046] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0047] In an embodiment of the present invention, multiple target chips are arranged in a device such as a vehicle for data decoding and data encoding. The target chip may be a serialization and deserialization chip with image and video interface functions, such as Figure 2a The MCU (Microcontroller Unit) in the device, the target chip and the first component such as the sensor can be connected by a PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) bus, and the target chip and the second component in the vehicle and the like can be connected by a PCIE bus. Figure 2a The target chip can also be connected to a third component via a PCIE bus, such as a SOC, in which case the second component may be a Display (such as a display component) or an Actor (an actuator).

[0048] Through the target chip, the PCIE parallel bus signal can be processed and serialized into a coaxial cable signal, or designed as an optical fiber serial signal, which can be transmitted in the network using optical fiber to adapt to the upgrade of the increasingly developed electronic and electrical architecture. Moreover, since the PCIE bus has the function of bidirectional transmission, the target chip can both encode and decode data.

[0049] In practical applications, at least two target chips can be set, such as Figure 2b In the MCU and MCU2, in signal transmission, one of the target chips can be connected to the first component, and two target chips can be connected to the second component, such as Figure 2b Display or Actor in the same file, and can be connected to a third component, such as Figure 2b Medium SOC.

[0050] Through this new PCIE parallel data processing interface, the target chip can be used as a serializer to achieve interconnection with sensors. With the widespread use of intelligent sensors in the future, as the connection methods of a large number of sensors are being changed, this PCIE parallel bus type smart camera sensor module can be directly connected to the target chip. Currently, the PCIE4.0 bus single LANE data transmission can reach 16Gbps, which can accelerate the transmission of high-definition images and videos. In some examples, multiple cameras can also be synthesized for transmission, which can simplify chips, simplify wiring harnesses, and save costs.

[0051] Moreover, the target chip can also be used as a deserializer to decode the high-speed serial signal and convert it into a PCIE parallel bus signal, which can be directly interconnected with the high-computing power chip SoC chip. After analysis and processing by the SoC chip, it can realize the output and display function of graphics or video, or output it to the executor after calculation to complete the corresponding operation.

[0052] In some examples, after being serialized by the target chip, if the SoC does not need to perform synchronous analysis, the graphic and video data can be directly output and directly interconnected through the PCIE bus to be output to another target chip for deserialization and data exchange and output, which can save computing chip resources and speed up data output.

[0053] like Figure 2c , the target chip can be provided with internal power supply, clock, and storage structure. For the target chip used for serial data decoding, different serial data types, including high-speed links such as optical fiber and multimedia, can be decoded and calculated by the target chip and output in PCIE parallel data format. In some examples, some low-speed control data can also be output for enabling, chip selection, power control, etc.

[0054] Compared with the prior art, the solution provided by the embodiment of the present invention has the following effects:

[0055] 1. Using PCIE parallel bus, the data rate can be increased by more than 10 times compared with the current mainstream CSI (Camera Serial Interface), which can meet the needs of multi-channel high-speed data transmission.

[0056] 2. PCIE parallel bus is more flexible to use than multiple LANE (cables), has a longer transmission length, and better control of signal quality.

[0057] 3. Parallel data can be transmitted bidirectionally, and can achieve encoding and decoding functions at the same time, simplifying chip types, simplifying hardware design, and reducing costs.

[0058] 4. Unify the video interface data transmission format, simplify the chip interface circuit, and improve adaptability.

[0059] 5. Greatly reduce SoC interface resources. The chip data can also be exchanged with each other, integrating IO port resources to achieve optimal configuration.

[0060] 6. SoC can also use PCIE switches to achieve resource optimization

[0061] 7. Serialize coaxial or optical fiber to simplify wiring harness, save space in the car, and save wiring harness costs.

[0062] The present invention is further described below:

[0063] Reference Figure 3 , showing a step flow chart of a signal transmission method provided by some embodiments of the present invention, such as a vehicle and other equipment can be deployed with multiple target chips for data decoding and data encoding, and the target chip can be a serialization and deserialization chip with image and video interface functions.

[0064] Specifically, the target chip may include a first target chip connected to the first component via a PCIE bus and a second target chip connected to the second component via a PCIE bus, such as Figure 2b MCU is the first target chip, and MCU2 is the second target chip.

[0065] In some examples, the first component may be a sensor in a vehicle, the sensor may include a camera, and the transmitted data may be video data. The second component may be a display or an actuator, the display may be used to display data, and the actuator may be used to perform corresponding operations.

[0066] Specifically, the following steps may be included:

[0067] Step 301: receive, through the first target chip, a first PCIE bus signal sent by the first component via the PCIE bus, perform a first process on the first PCIE bus signal to obtain a first process result, and send the first process result to the second target chip.

[0068] As an example, the first PCIE bus signal may be a first PCIE parallel bus signal.

[0069] In practical applications, a first component such as a sensor can collect relevant data, and then a first PCIE bus signal carrying the collected relevant data can be sent to a first target chip via a PCIE bus. For example, the sensor can be a camera, and the collected relevant data can be video data.

[0070] After receiving the first PCIE bus signal, the first target chip can perform a first process on the first PCIE bus signal to obtain a first process result, the first process can be a data encoding process, and the first process result can be a first serial signal, that is, the first target chip can be used as a serializer to encode the data. After obtaining the first serial data, the first target chip can send the first process result to the second target chip.

[0071] Through this new PCIE parallel data processing interface, the target chip can be used as a serializer to achieve interconnection with sensors. With the widespread use of intelligent sensors in the future, as the connection methods of a large number of sensors are being changed, this PCIE parallel bus type smart camera sensor module can be directly connected to the target chip. Currently, the PCIE4.0 bus single LANE data transmission can reach 16Gbps, which can accelerate the transmission of high-definition images and videos. In some examples, multiple cameras can also be synthesized for transmission, which can simplify chips, simplify wiring harnesses, and save costs.

[0072] In some embodiments of the present invention, sending the first processing result to the second target chip includes:

[0073] When the first processing result is a coaxial cable signal, the first processing result is sent to the second target chip via a coaxial cable; when the first processing result is an optical fiber serial signal, the first processing result is sent to the second target chip via an optical fiber.

[0074] The first target chip and the second target chip can use corresponding communication methods according to the actual situation of the vehicle, such as communication through a coaxial cable or through an optical fiber.

[0075] In practical applications, the PCIE bus signal can be processed by the target chip and serialized into a coaxial cable signal. It can also be designed as an optical fiber serial signal and transmitted through optical fiber in the network to adapt to the upgrade of the increasingly developed electronic and electrical architecture.

[0076] Step 302: receive the first processing result sent by the first target chip through the second target chip, perform a second processing on the first processing result to obtain a second processing result, and send the second processing result to the second component via the PCIE bus, wherein the second processing is different from the first processing.

[0077] In some embodiments of the present invention, the second processing may be a data decoding process, and the second processing result may be a second PCIE parallel bus signal, and the second PCIE parallel bus signal may be the same as the first PCIE parallel bus signal.

[0078] After receiving the first processing result sent by the first target chip, the second target chip can perform a second processing on the first processing result to obtain a second processing result. The second processing can be a data decoding process, and the second processing result can be a second PCIE parallel bus signal, that is, the second target chip acts as a deserializer to decode the data.

[0079] After obtaining the second processing result, the second target chip may send the second processing result to the second component via the PCIE bus.

[0080] In some embodiments of the present invention, sending the second processing result to the second component via the PCIE bus includes:

[0081] Detecting data analysis requirements; when the data analysis requirement indicates that data analysis needs to be performed on the data carried by the second processing result, sending the second processing result to a third component in the vehicle via a PCIE bus, so that the third component analyzes the second processing result and outputs it to the second component; when the data analysis requirement indicates that data analysis does not need to be performed on the data carried by the second processing result, sending the second processing result to the second component via the PCIE bus.

[0082] In practical applications, it is possible to detect whether the second processing result carries data analysis requirements, and the data analysis requirements can be used to indicate whether it is necessary to perform data analysis on the data carried by the second processing result, and then perform different processing on the data according to different requirements.

[0083] Specifically, the target chip can also be used as a deserializer to decode the high-speed serial signal and convert it into a PCIE bus signal. When the data analysis requirement indicates that data analysis needs to be performed on the data carried by the second processing result, it is directly interconnected with the high-computing power chip SoC chip. After analysis and processing by the SoC chip, the output display function of the graphics or video is realized, or the calculation is performed and then output to the executor to complete the corresponding operation.

[0084] In some examples, after serialization through the target chip, if the SoC does not need to perform synchronous analysis, that is, the data analysis requirement indication unit needs to perform data analysis on the data carried by the second processing result and directly output the graphic video data, it can be directly interconnected through the PCIE bus and output to the target chip for deserialization to perform data exchange and output, thereby saving more computing chip resources and speeding up data output.

[0085] In some embodiments of the present invention, the third component includes any one of the following:

[0086] System-on-chip, PCIE switch.

[0087] In some embodiments of the present invention, the second component may be a display or an actuator.

[0088] In the case where the second component is a display, the display displays the second processing result when receiving the second processing result; or, in the case where the second component is an executor, the executor performs a corresponding operation when receiving the second processing result.

[0089] After the second processing result is generated, the second processing result may be displayed by a display serving as the second component, or an executor serving as the second component may execute an operation corresponding to the second processing result.

[0090] Specifically, there are at least two situations:

[0091] 1. Send the second processing result to a third component (such as SOC), and the third component analyzes and processes the second processing data and outputs it to a display or actuator serving as the second component.

[0092] 2. The second processing result is directly sent to the display or actuator as the second component without the need for analysis and processing by the third component.

[0093] In some embodiments of the present invention, in the case where a third component needs to perform analysis and processing, the third component analyzes the second processing result and outputs it to the second component, including:

[0094] In the case where the second component is a display, the second processing result is analyzed by the third component and output to the display for data display; or, in the case where the second component is an actuator, the second processing result is analyzed by the third component and output to the actuator to perform a corresponding operation.

[0095] In some embodiments of the present invention, in the case where the third component does not need to perform analysis and processing, sending the second processing result to the second component via the PCIE bus includes:

[0096] When the second component is a display, the second processing result is sent to the display via the second target chip via the PCIE bus for data display; or, when the second component is an executor, the second processing result is sent to the executor via the PCIE bus through the second target chip to perform a corresponding operation.

[0097] In some embodiments of the present invention, it also includes:

[0098] A second serial signal is received through the first target chip, and a third processing is performed on the second serial signal to obtain a third processing result; and / or a fourth PCIE parallel bus signal is received through the second target chip, and a fourth processing is performed on the fourth PCIE parallel bus signal to obtain a fourth processing result.

[0099] In some embodiments of the present invention, the third processing may be a data decoding processing, and the third processing result may be a third PCIE parallel bus signal. The fourth processing may be a data encoding processing, and the fourth processing result may be a third serial signal.

[0100] In practical applications, since the PCIE bus has the function of bidirectional transmission, the target chip can perform both data encoding and decoding. Specifically, for the first target chip, it can also be used as a deserializer to decode data, and for the second target chip, it can also be used as a serializer to encode data. Through the bidirectional transmission of parallel data, the encoding and decoding functions can be achieved at the same time, simplifying the chip types, simplifying hardware design and reducing costs.

[0101] In an embodiment of the present invention, a device is deployed with multiple target chips, including a first target chip connected to a first component via a PCIE bus and a second target chip connected to a second component via a PCIE bus. The first target chip receives a first PCIE bus signal sent by the first component via the PCIE bus, performs a first processing on the first PCIE bus signal, obtains a first processing result, and sends the first processing result to the second target chip. Then, the second target chip receives the first processing result sent by the first target chip, performs a second processing on the first processing result, obtains a second processing result, and sends the second processing result to the second component via the PCIE bus. This realizes signal transmission within the device by combining chips for different processing on the basis of the PCIE bus. The use of the PCIE bus does not require the occupation of multiple channels, improves the quality of signal transmission, can realize bidirectional transmission, and supports multiple video interfaces.

[0102] Reference Figure 4 , shows a flowchart of another signal transmission method provided by some embodiments of the present invention, which may specifically include the following steps:

[0103] Step 401: receive, through the first target chip, a first PCIE bus signal sent by the first component via the PCIE bus, perform a first process on the first PCIE bus signal to obtain a first process result, and send the first process result to the second target chip.

[0104] Step 402: receive the first processing result sent by the first target chip through the second target chip, perform a second processing on the first processing result to obtain a second processing result, and detect a data analysis requirement, wherein the data analysis requirement is used to indicate whether data analysis is required for the data carried by the second processing result.

[0105] Step 403, when the data analysis requirement indicates that data analysis needs to be performed on the data carried by the second processing result, the second processing result is sent to the third component in the vehicle via the PCIE bus, so that the third component analyzes the second processing result and outputs it to the second component.

[0106] Reference Figure 5 , shows a flowchart of another signal transmission method provided by some embodiments of the present invention, which may specifically include the following steps:

[0107] Step 501: receive, through the first target chip, a first PCIE bus signal sent by the first component via the PCIE bus, perform a first process on the first PCIE bus signal to obtain a first process result, and send the first process result to the second target chip.

[0108] Step 502: receive the first processing result sent by the first target chip through the second target chip, perform a second processing on the first processing result to obtain a second processing result, and detect a data analysis requirement, wherein the data analysis requirement is used to indicate whether data analysis is required for the data carried by the second processing result.

[0109] Step 503: When the data analysis requirement indicates that data analysis needs to be performed on the data carried by the second processing result, the second processing result is sent to the system-level chip via the PCIE bus.

[0110] Step 504, when the second component is a display, the second processing result is analyzed by the system-level chip and outputted to the display, and the display displays the second processing result when receiving the second processing result; or, when the second component is an actuator, the second processing result is analyzed by the system-level chip and outputted to the actuator in the vehicle, and the actuator performs a corresponding operation when receiving the second processing result.

[0111] Reference Figure 6 , shows a flowchart of another signal transmission method provided by some embodiments of the present invention, which may specifically include the following steps:

[0112] Step 601: receive, through the first target chip, a first PCIE bus signal sent by the first component via the PCIE bus, perform a first process on the first PCIE bus signal to obtain a first process result, and send the first process result to the second target chip.

[0113] Step 602: receive the first processing result sent by the first target chip through the second target chip, perform a second processing on the first processing result to obtain a second processing result, and detect a data analysis requirement, wherein the data analysis requirement is used to indicate whether data analysis is required for the data carried by the second processing result.

[0114] Step 603: When the data analysis requirement indicates that data analysis is not required for the data carried by the second processing result, the second processing result is sent to the second component via the PCIE bus.

[0115] Reference Figure 7 , shows a flowchart of another signal transmission method provided by some embodiments of the present invention, which may specifically include the following steps:

[0116] Step 701: receive, through the first target chip, a first PCIE bus signal sent by the first component via the PCIE bus, perform a first process on the first PCIE bus signal to obtain a first process result, and send the first process result to the second target chip.

[0117] Step 702: receive the first processing result sent by the first target chip through the second target chip, perform a second processing on the first processing result to obtain a second processing result, and detect a data analysis requirement, wherein the data analysis requirement is used to indicate whether data analysis is required for the data carried by the second processing result.

[0118] Step 703, when the data analysis requirement indicates that data analysis is not required, in the case where the second component is a display, the second processing result is sent to the display via the PCIE bus through the second target chip, and the display displays the second processing result when receiving the second processing result; or, in the case where the second component is an executor, the second processing result is sent to the executor via the PCIE bus through the second target chip, and the executor performs a corresponding operation when receiving the second processing result.

[0119] Reference Figure 8 , shows a flowchart of another signal transmission method provided by some embodiments of the present invention, which may specifically include the following steps:

[0120] Step 801: receive, through the first target chip, a first PCIE bus signal sent by the first component via the PCIE bus, perform a first processing on the first PCIE bus signal to obtain a first processing result, and when the first processing result is a coaxial cable signal, send the first processing result to the second target chip via the coaxial cable.

[0121] Step 802: receiving, through the second target chip, a first processing result sent by the first target chip, performing a second processing on the first processing result to obtain a second processing result, and sending the second processing result to a second component via a PCIE bus.

[0122] Reference Fig. 9 , shows a flowchart of another signal transmission method provided by some embodiments of the present invention, which may specifically include the following steps:

[0123] Step 901: receive, through the first target chip, a first PCIE bus signal sent by the first component via the PCIE bus, perform a first processing on the first PCIE bus signal to obtain a first processing result, and when the first processing result is an optical fiber serial signal, send the first processing result to the second target chip via an optical fiber.

[0124] Step 902: receiving, through the second target chip, a first processing result sent by the first target chip, performing a second processing on the first processing result to obtain a second processing result, and sending the second processing result to a second component via a PCIE bus.

[0125] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0126] Some embodiments of the present invention also provide a signal transmission device, wherein the device is deployed with multiple target chips, including a first target chip connected to the first component through a PCIE bus and a second target chip connected to the second component through a PCIE bus, and the device is used to:

[0127] receiving, by the first target chip, a first PCIE bus signal sent by the first component via the PCIE bus, performing a first process on the first PCIE bus signal to obtain a first process result, and sending the first process result to the second target chip;

[0128] The first processing result sent by the first target chip is received through the second target chip, a second processing is performed on the first processing result to obtain a second processing result, and the second processing result is sent to the second component via the PCIE bus, wherein the second processing is different from the first processing.

[0129] In some embodiments of the present invention, the first PCIE bus signal is a first PCIE parallel bus signal, the first processing is a data encoding processing, the first processing result is a first serial signal, the second processing is a data decoding processing, and the second processing result is a second PCIE parallel bus signal.

[0130] In some embodiments of the present invention, sending the second processing result to the second component via the PCIE bus includes:

[0131] Detecting a data analysis requirement, where the data analysis requirement is used to indicate whether data analysis needs to be performed on the data carried by the second processing result;

[0132] When the data analysis requirement indicates that data analysis needs to be performed on the data carried by the second processing result, the second processing result is sent to the third component via the PCIE bus, so that the third component analyzes the second processing result and outputs it to the second component;

[0133] When the data analysis requirement indicates that data analysis is not required for the data carried by the second processing result, the second processing result is sent to the second component via the PCIE bus.

[0134] In some embodiments of the present invention, the third component includes any one of the following: a system-level chip, a PCIE switch.

[0135] In some embodiments of the present invention, when the second component is a display, the display displays the second processing result when receiving the second processing result;

[0136] Alternatively, when the second component is an executor, the executor performs a corresponding operation upon receiving the second processing result.

[0137] In some embodiments of the present invention, sending the first processing result to the second target chip includes:

[0138] In the case where the first processing result is a coaxial cable signal, sending the first processing result to the second target chip via the coaxial cable;

[0139] In the case where the first processing result is an optical fiber serial signal, the first processing result is sent to the second target chip via an optical fiber.

[0140] In some embodiments of the present invention, it is also used for:

[0141] receiving, by the first target chip, a second serial signal, and performing a third process on the second serial signal to obtain a third process result;

[0142] And / or, receiving a fourth PCIE parallel bus signal through the second target chip, performing a fourth process on the fourth PCIE parallel bus signal, and obtaining a fourth process result.

[0143] In some embodiments of the present invention, the third process is a data decoding process, and the third process result is a third PCIE parallel bus signal. The fourth process is a data encoding process, and the fourth process result is a third serial signal.

[0144] In some embodiments of the present invention, the first component is a sensor in a vehicle, and the sensor includes a camera.

[0145] In an embodiment of the present invention, a device is deployed with multiple target chips, including a first target chip connected to a first component via a PCIE bus and a second target chip connected to a second component via a PCIE bus. The first target chip receives a first PCIE bus signal sent by the first component via the PCIE bus, performs a first processing on the first PCIE bus signal, obtains a first processing result, and sends the first processing result to the second target chip. Then, the second target chip receives the first processing result sent by the first target chip, performs a second processing on the first processing result, obtains a second processing result, and sends the second processing result to the second component via the PCIE bus. This realizes signal transmission within the device by combining chips for different processing on the basis of the PCIE bus. The use of the PCIE bus does not require the occupation of multiple channels, improves the quality of signal transmission, can realize bidirectional transmission, and supports multiple video interfaces.

[0146] Some embodiments of the present invention further provide an electronic device, comprising a processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein the above method is implemented when the computer program is executed by the processor.

[0147] Some embodiments of the present invention further provide a computer-readable storage medium, on which a computer program is stored, and the computer program implements the above method when executed by a processor.

[0148] Some embodiments of the present invention further provide a computer program product, including a computer program, which implements the above method when executed by a processor.

[0149] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0150] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0151] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0152] Those skilled in the art will appreciate that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0153] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0154] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0155] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0156] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0157] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the above elements.

[0158] The above is a detailed introduction to a signal transmission method and device provided. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A signal transmission method, characterized in that: The device is deployed with multiple target chips, including a first target chip connected to the first component through a PCIE bus and a second target chip connected to the second component through a PCIE bus. The method includes: receiving, by the first target chip, a first PCIE bus signal sent by the first component via the PCIE bus, performing a first process on the first PCIE bus signal to obtain a first process result, and sending the first process result to the second target chip; The first processing result sent by the first target chip is received through the second target chip, a second processing is performed on the first processing result to obtain a second processing result, and the second processing result is sent to the second component via the PCIE bus, wherein the second processing is different from the first processing.

2. The method according to claim 1, characterized in that The first PCIE bus signal is a first PCIE parallel bus signal, the first processing is a data encoding processing, the first processing result is a first serial signal, the second processing is a data decoding processing, and the second processing result is a second PCIE parallel bus signal.

3. The method according to claim 1, characterized in that The sending the second processing result to the second component via the PCIE bus includes: Detecting a data analysis requirement, where the data analysis requirement is used to indicate whether data analysis needs to be performed on the data carried by the second processing result; When the data analysis requirement indicates that data analysis needs to be performed on the data carried by the second processing result, the second processing result is sent to the third component via the PCIE bus, so that the third component analyzes the second processing result and outputs it to the second component; When the data analysis requirement indicates that data analysis is not required for the data carried by the second processing result, the second processing result is sent to the second component via the PCIE bus.

4. The method according to claim 3, characterized in that The third component includes any one of the following: a system-level chip, a PCIE switch.

5. The method according to any one of claims 1 to 4, characterized in that: In the case where the second component is a display, the display displays the second processing result when receiving the second processing result; Alternatively, when the second component is an executor, the executor performs a corresponding operation upon receiving the second processing result.

6. The method according to any one of claims 1 to 4, characterized in that: The sending the first processing result to the second target chip includes: In the case where the first processing result is a coaxial cable signal, sending the first processing result to the second target chip via the coaxial cable; In the case where the first processing result is an optical fiber serial signal, the first processing result is sent to the second target chip via an optical fiber.

7. The method according to any one of claims 1 to 4, characterized in that: Also includes: receiving, by the first target chip, a second serial signal, and performing a third process on the second serial signal to obtain a third process result; And / or, receiving a fourth PCIE parallel bus signal through the second target chip, performing a fourth process on the fourth PCIE parallel bus signal, and obtaining a fourth process result.

8. The method according to claim 7, characterized in that The third process is a data decoding process, and the third process result is a third PCIE parallel bus signal. The fourth process is a data encoding process, and the fourth process result is a third serial signal.

9. The method according to claim 1, characterized in that: The first component is a sensor in the vehicle, and the sensor includes a camera.

10. A signal transmission device, characterized in that: The device is deployed with multiple target chips, including a first target chip connected to the first component through a PCIE bus and a second target chip connected to the second component through a PCIE bus, and the device is used to: Receiving, by the first target chip, a first PCIE bus signal sent by the first component via the PCIE bus, performing a first process on the first PCIE bus signal to obtain a first process result, and sending the first process result to the second target chip; The first processing result sent by the first target chip is received through the second target chip, the first processing result is subjected to second processing to obtain a second processing result, and the second processing result is sent to the second component via the PCIE bus.

11. A vehicle, characterized in that: The method comprises a processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein the computer program implements the method according to any one of claims 1 to 9 when executed by the processor.

12. An electronic device, characterized in that: The method comprises a processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein the computer program implements the method according to any one of claims 1 to 9 when executed by the processor.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 9 is implemented.

14. A computer program product, characterized in that The invention comprises a computer program which, when executed by a processor, implements the method according to any one of claims 1 to 9.

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