Method for communicating data between slave device and master device and corresponding integrated system

Abstract

The invention relates to a method for communicating data between a slave device and a master device and a corresponding integrated system. A method for communicating data between a slave device and a master device according to a communication protocol is provided. An example includes recording data in a memory belonging to a slave device, the method including generating, by a master device, a command specified by a communication protocol, and using a field of the command to select an indirect register belonging to the slave device and containing an address of a region of the memory that includes the data.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to French patent application FR2310823, filed on October 10, 2023, entitled “Procede De Communication DeDonnees Entre Un Dispositif Esclave Et Un Dispositif Maitre, Et Systeme Integre Correspondant”, which patent application is incorporated herein by reference to the maximum extent permitted by law. Technical Field

[0003] Embodiments and implementations relate to methods of data communication in an integrated system, and in particular, to communications compliant with the "Secure Digital Input Output ("SDIO")" standard defined by the "SD Association" organization. Background Art

[0004] "SDIO" type communications between a master and a slave device are traditionally performed using commands specific to that standard.

[0005] SDIO commands are defined by the standard and contain fixed fields intended to contain useful information such as an indication of the command type ("command index"), a function number, the address of the read / write data to be transferred, etc.

[0006] The SDIO standard specifically allows the possibility of 8 functions. Function 0 is reserved for implementing the standard. Functions 1 to 7 are free. Each function can be mapped into its own memory space.

[0007] The standard allows a 17-bit address field for direct and extended read / write commands (usually "IO_RW_DIRECT" and "IO_RW_EXTENDED", respectively).

[0008] This limits the address range to 128kB (kilobytes).

[0009] Even with these 7 functions, the range of 128 kB*7=896 kB is insufficient for use cases of slave device functionality, such as for example for sending and receiving data packets placed in the memory of the slave device implementing WiFi type communications.

[0010] In order to increase the size of the address range accessible in memory using SDIO commands, it has been proposed to use a linked list of descriptors in the memory of the slave device. However, this previous solution has the following disadvantages: the master device cannot program the linked list, the master device cannot control the address range, and the transfer amount is limited, for example, each transfer is limited to 128kB.

[0011] Therefore, greater flexibility in SDIO communications is needed to benefit, particularly to allow larger transfers. Summary of the invention

[0012] The various aspects and embodiments and examples defined below propose indirect addressing via indirect registers, thereby allowing direct memory access channel type access so that a single read or write command can reach any area of ​​memory (e.g., up to 1MB) or any location in memory (e.g., 4GB).

[0013] Furthermore, the indirect registers may be configured by the master on the one hand in order to benefit from functionality adapted to the needs and capabilities of the master, or by the slave on the other hand in order to be able to enforce security measures such as firewall type filtering when accessing the memory.

[0014] According to one aspect, a method for communicating data between a slave device and a master device according to a communication protocol is provided, wherein the data is recorded in a memory belonging to the slave device, the method comprising: generating, by the master device, a command specified by the communication protocol; and using a field of the command to select an indirect register belonging to the slave device and containing an address of an area of ​​the memory including the data.

[0015] According to one embodiment, the communication protocol provides that the command field is intended to contain the address of a memory location on a first number of bits; and the indirect register comprises a second number of bits greater than the first number to contain the address of the area of ​​memory comprising the data.

[0016] According to one embodiment, the indirect register contains a base address and the size of said area of ​​memory containing said data.

[0017] For example, using a register with 32 bits for the base address and 20 bits for the size of the region of memory, the data communicated can be 1MB in size, within the full range of 4GB of memory.

[0018] According to one embodiment, the usage command field includes:

[0019] - a code in the most significant bit of this field for identifying the indirect register containing the address of said area of ​​memory containing said data among several indirect registers of the slave device containing addresses of other corresponding areas of memory; and

[0020] - Quantification of the address offset starting at the least significant bit of this field locating the location of the data in the area.

[0021] According to one embodiment, the command also includes the size of said data communicated.

[0022] Thus, in both implementations, the master device can precisely define the start and end addresses of the memory data (by the size of the location) in the command.

[0023] According to one embodiment, the communication protocol complies with the "Secure Digital Input Output - SDIO" communication standard defined by the "SD Association" organization, and wherein the command is an extended block read / write command.

[0024] According to one embodiment, the method further comprises another use of the command field to address a register of a function compliant with said protocol, including a dedicated code on the most significant bits of said field to identify this other use.

[0025] According to another aspect, an integrated system is also provided, which includes a slave device and a master device capable of communicating data therebetween according to a communication protocol, the data being recorded in a memory belonging to the slave device, the master device being configured to generate a command specified by the communication protocol and to use a field of the command to select an indirect register belonging to the slave device and capable of containing an address of an area of ​​the memory including the data.

[0026] According to one embodiment, the communication protocol provides that the command field is intended to contain the address of a memory location on a first number of bits; the indirect register comprising a second number of bits greater than the first number to contain the address of the area of ​​memory comprising the data.

[0027] According to one embodiment, the indirect register can contain a base address and the size of said region of memory containing said data.

[0028] According to one embodiment, the master device is configured to use the command field by incorporating:

[0029] - a code in the most significant bit of this field for identifying the indirect register containing the address of said area of ​​memory containing said data among several indirect registers of the slave device containing addresses of other corresponding areas of memory; and

[0030] - Quantification of the address offset starting at the least significant bit of this field locating the location of the data in the area.

[0031] According to one embodiment, the master device is configured to further incorporate the size of the communicated data into the command.

[0032] According to one embodiment, the slave device and the master device can communicate data with each other according to a communication protocol complying with the "Secure Digital Input Output-SDIO" communication standard defined by the "SD Association" organization.

[0033] According to one embodiment, the master device is also configured to use the command field in other ways to address registers of functions compliant with the protocol, identifying this other use by incorporating a corresponding dedicated code on the most significant bits of this field. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Other advantages and features of the present disclosure will become apparent upon examination of the detailed description of embodiments and examples, which are not limiting in any sense, and the accompanying drawings, in which:

[0035] [ Figure 1 ]、[ Figure 2 ]、[ Figure 3 ]、[ Figure 4 ]、[ Figure 5 ]、[ Figure 6 ]and[ Figure 7 ] illustrate embodiments and implementations of the present disclosure. DETAILED DESCRIPTION

[0036] Figure 1 An example of an integrated SOC system, such as a system on a chip, is illustrated, including a master device HST (commonly referred to as a “host”) and a slave device SLV, which can communicate data with each other over an SDIO channel according to a communication protocol.

[0037] The master device HST is, for example, an application processor of an integrated system, while the slave device SLV is, for example, a peripheral device providing resources to implement a given functionality (eg, wireless communication functionality of the Wifi type).

[0038] The master device HST and the slave devices SLV are manufactured, for example, on the same fully integrated silicon chip of the system-on-chip type, or from separate chips connected to the same printed circuit board (usually abbreviated to "PCB") in an integrated system.

[0039] In particular, the slave device SLV comprises an SDIOS slave interface adapted to the “Secure Digital Input Output” communication protocol defined by the standard established by the “SD Association” organization, a memory MEM, and an internal central unit adapted to the functionality.

[0040] In particular, the slave interface advantageously comprises at least one indirect register DMAi ( Figure 2 ), intended to contain the memory MEM that can be used by the master device in the communication protocol adaptation command CMD ( Figure 5 ) in the selected area.

[0041] In practice, the master device is advantageously configured to generate a command CMD ( Figure 5 ), by using the command field RegAdd( Figure 5 ) is adapted so as to select the indirect register DMAi of the slave device. Thus, the device can reach the address contained in the indirect register DMAi in the memory MEM, for example in the context of a read or write data communication in the memory MEM.

[0042] Figure 2 An exemplary embodiment of an SDIOS slave interface is illustrated.

[0043] On the one hand, the SDIOS interface includes a general-purpose input / output GPIO terminal, a bus interface SD / SPI_INTF compatible with the SDIO protocol (or even with other protocols, such as the serial data bus protocol "SPI" (standing for Serial Peripheral Interface)), including, for example, a command and response interface CMD_RESP_INTF, an input data interface D_IN_INTF, and an output data interface D_OUT_INTF.

[0044] The bus interface SD / SPI_INTF can be commanded by a command unit, which may include a state machine SDIO_FSM, a command decoder CMD_DEC, a response generator RESP_GEN, and communicate with the main bus controller AHB_MSTR_CONT and the register groups SDIO_F0_STDREG and SDIO_F1_REG via a multiplexing circuit using an incoming WDFIFO buffer and an outgoing RDFIFO buffer.

[0045] A master bus controller AHB_MSTR_CONT, for example of a bus of the "AHB" type (standing for "Advanced High Performance Bus"), can for example generate communications to the internal central processing unit of a slave device SLV on a corresponding master bus port AHB_MSTR_PRT and receive a clock signal from the master bus ahbm_clk. Furthermore, slave AHB bus communications can be received on a slave bus port AHB_SLV_PRT, as well as a slave bus clock signal ahbs_clk.

[0046] Other incoming and outgoing signals sdios_sgnl_i / o that are general and comply with the SDIO protocol may be provided and will not be described in detail here.

[0047] On the other hand, a reserved register group SDIO_F0_STDREG and a first register group SDIO_F1_REG are provided in the SDIOS slave interface.

[0048] The reserved register set SDIO_F0_STDREG includes the instructions CCCRx, F1BRx in a manner mandated by the corresponding SDIO standard, thereby allowing the implementation of the SDIO protocol. The SDIO protocol also allows seven other different functions to utilize the resources of the slave device SLV.

[0049] The first register set SDIO_F1_REG allows the implementation of a first function of the slave device SLV. The first function may be the only function of the SDIO protocol used by the slave device SLV. In other words, all resources of the slave device SLV can be accessed by implementing a single function of the SDIO protocol. For example, this may be the case where the slave device SLV implements a wireless communication of the Wifi type.

[0050] In this regard, the first register group SDIO_F1_REG may include, for example, a control register SDIOS_CTRL, registers for internal interrupt INTRNL_IT and event notification HST_EVNT to the host, and registers for external interrupt EXTRNL_IT and event notification SLV_EVNT to the peripheral device.

[0051] The first SDIO_F1_REG group also advantageously includes at least one indirect register DMAi that can contain the address of the area of ​​the memory MEM including the data to be read or written according to the command from the master device HST. In this way, the address usually allows multiple bits to be identified in the memory, such as 8-bit bytes, depending on the granularity of the memory access. "The address of the memory area" for example represents the starting address of the area, and the size of the area, or alternatively the end address of the area. In this regard, the indirect register DMAi can for example contain the base address DMAi_BAdd and the size DMAi_Sz of the area of ​​the memory containing the data.

[0052] Figure 3 An example of a 32-bit register DMAi_BAdd belonging to one of the indirect registers DMAi is illustrated to contain the base address of a region of the memory MEM.

[0053] So, on 32-bit, any address of 4GB (gigabytes) of memory can be contained in the base address register DMAi_BAdd.

[0054] From the point of view of read and write access "rw", the content of the base address register DMAi_BAdd can be for example:

[0055] - write access only by the master device HST and read access by the master device HST and the slave device SVL; or

[0056] - Write and read access is only by the slave SLV.

[0057] Figure 4 An example of a 32-bit register DMAi_BAdd belonging to one of the indirect registers DMAi is illustrated, in which 20 bits are allocated to quantify the size of the memory MEM area.

[0058] Thus, at 20 bits, the region size register DMAi_Sz can contain sizes from 1 bit to 1MB (Megabyte).

[0059] From the perspective of read and write access "rw", the content of the region size register DMAi_Sz can be write-accessed only by the master device HST, or only by the slave device SLV; and in both cases, it can be read-accessed by the master device HST and the slave device SVL.

[0060] Figure 5 The command CMD issued by the host device HST is illustrated, and is specified by a communication protocol conforming to the “Secure Digital Input Output” standard defined by the “SD Association” organization, and is particularly an extended block read / write command, for example.

[0061] A 6-bit field CMD_INDX is provided to communicate a command index or identifier. In this example, the binary index 110101 (53 in decimal) allows identification of an extended command (as opposed to the "direct command" of the protocol), in particular allowing read / write by byte or by block, depending on the BLC bit.

[0062] The field RegAdd of the command is used in a manner prescribed by the standard, but still compatible with the standard, in order to select an indirect register DMAi belonging to the slave device and containing the address of a region of the memory MEM containing data.

[0063] In the communication protocol according to the standard, the field RegAdd of the command is intended to contain the address of the memory location on a first number of bits that is less than a second number of bits of the address of the communication memory area in the indirect registers DMAi, DMAi_BAdd, DMAi_Sz. In the SDIO standard protocol, the field RegAdd comprises 17 bits (the first number), which is much less than the 32 bits (the second number) of the base address register DMAi_BAdd.

[0064] The use of the field RegAdd of the command CMD may advantageously include a code on the most significant bit of this field to identify the indirect register DMAi containing the address of the area of ​​memory containing said data among several indirect registers of the slave device containing the addresses of other corresponding areas of memory, and an address offset AddOffst( Figure 6 ) is quantified, the address offset AddOffst locates the data in the area RgAdd / DMAi( Figure 7 ) in the position RgAdd / CMD( Figure 7 ) begins. Special reference Figure 6 .

[0065] Furthermore, the command CMD contains in a 9-bit field BYT / BLC CNT provided for this purpose the amount of data to be communicated (or transferred) with this command CMD, counted as the number of bytes (BYT) or blocks (BLC) of fixed size in a register, which may be greater than one byte.

[0066] Figure 6 An example of a code on the most significant bit of the field RegAdd is illustrated, allowing the indirect register DMAi to be selected from two indirect registers "DMA0", "DMA1" or from eight indirect registers "DMA0-7". Each indirect register contains addressing of a different area of ​​memory.

[0067] On the one hand, looking first at 61, the code "111" can be provided on the three most significant bits 16, 15, 14 to identify the standard use of the field RegAdd, i.e., addressing with the remaining fourteen least significant bits 13-0 of the register SDIO_F1_REG of the first function, which is located inside the SDIOS slave interface peripheral device.

[0068] On the other hand, in the case 62, 64 of selection between two indirect registers, the code "0x" (where x=0 or 1) may be provided on the two most significant bits 16, 15 to identify the corresponding indirect register DMAi (i=[0;1]).

[0069] The quantization of the address offset AddOffst can be done on the remaining least significant bits 14:0 or on 14:1, if bit 0 is reserved for "r" e.g. to communicate the end of the session; that is, up to 64 kB (kilobytes) or respectively 32 kB. This corresponds in particular to the technique of center alignment of memory words (usually "halfword aligned offset").

[0070] In the case 63, 65 of selecting between eight indirect registers, the code "1xxx" (where xxx = [000; 001; 010; 011; 100; 101]) can be provided on the four most significant bits 16, 15, 14, 13 to identify the corresponding indirect register DMAi (i = [2; 3; 4; 5; 6; 7]). Registers DMA0 and DMA1 can be identified in the same manner as "0x" described above in the case 62, 64.

[0071] The quantization of the address offset AddOffst can be done on the remaining least significant bits 12:0, or on 12:1 if bit 0 is reserved "r" for example to convey the end of the session; that is, up to 16kB (kilobytes) or 8kB respectively. Again, this corresponds to the technique of center alignment of memory words (usually "halfword aligned offset").

[0072] Figure 7 The memory MEM of the slave device SLV is shown and in particular according to the use of the above Figures 1 to 6 A method is described for accessing data contained in a memory MEM using the technique of commands CMD and indirect registers DMAi.

[0073] The communication data RgAdd / CMD is located between the start address “start@” and the end address “end@” in the memory area RgAdd / DMAi.

[0074] The content of the indirect register DMAi defines the address range of the memory region RgAdd / DMAi; in particular, it is defined by the base address DMAi_BAdd in the base address register and the region size DMAi_Sz in the region size register.

[0075] In addition to the identification code of the indirect register DMAi to be used, the content of the command CMD also defines the address range of the data of the communication RgAdd / CMD, positioning the starting address start@ with the address offset AddOffst relative to the base address BMAi_BAdd of the area, and positioning the end address with the byte or block count CNT of the corresponding 9-bit field of the command CMD.

[0076] Thus, in summary, embodiments and implementations have been described in which function 1 of the SDIO protocol allows benefiting from up to 8 "direct memory access" channels configured with indirect registers DMAi, for example to provide 32-bit base addresses and 20-bit memory region sizes, providing 1MB of data per channel over a 4GB memory range. In particular, the SDIO protocol allows such transfers in multi-block mode, such as extended block read / write commands. Advantageously, access to the memory regions can also be configured by the host HST or by the peripheral SLV, while the communication data can be finely located in the region by information in the content of the command CMD.

Claims

1. A method for communicating data between a slave device and a master device according to a communication protocol, the data being recorded in a memory belonging to the slave device, the method comprising: The master device generates commands specified by the communication protocol; as well as A field of the command is used to select an indirect register belonging to the slave device and containing the address of the area of ​​memory that includes the data.

2. The method of claim 1 , wherein the communication protocol provides that the command field is intended to contain an address of a memory location with respect to a first number of bits; and an indirect register includes a second number of bits greater than the first number to contain the address of the area of ​​memory including the data.

3. The method of claim 2, wherein an indirect register contains a base address and a size of the region of memory containing the data.

4. The method of claim 1, wherein the fields of the usage command include: a code on one or more most significant bits of the field for identifying, among a number of indirect registers of the slave device containing addresses of other corresponding regions of memory, the indirect register containing the address of the region of memory containing the data; as well as A quantification of an address offset starting at one or more least significant bits of the field that locates the location of the data in the region. The method of claim 4 , wherein the command further includes a size of the data communicated.

6. The method of claim 1, wherein the communication protocol complies with a “Secure Digital Input Output—SDIO” communication standard defined by an “SD Association” organization, and wherein the command is an extended block read / write command.

7. The method of claim 1 further comprising another use of the command field to address a register of a function compliant with the protocol, including a corresponding dedicated code on one or more most significant bits of the field to identify the other use.

8. An integrated system comprising a slave device and a master device capable of communicating data with each other according to a communication protocol, the data being recorded in a memory belonging to the slave device, the master device being configured to generate a command specified by the communication protocol and to use a field of the command to select an indirect register belonging to the slave device and capable of containing the address of an area of ​​the memory including the data.

9. An integrated system as described in claim 8, wherein the communication protocol provides that the command field is intended to contain the address of a memory location with respect to a first number of bits; the indirect register is capable of including a second number of bits greater than the first number to contain the address of the area of ​​memory including the data.

10. The integrated system of claim 9, wherein an indirect register is capable of containing a base address and a size of the region of memory containing the data.

11. The integrated system of claim 8, wherein the master device is configured to use the command field by incorporating: a code on one or more most significant bits of the field for identifying the indirect register containing the address of the region of memory containing the data among a number of indirect registers of the slave device containing addresses of other corresponding regions of memory; and A quantification of the address offset starting at one or more of the least significant bits of the field that locates the location of the data in the region.

12. The integrated system of claim 11, wherein the master device is configured to further incorporate a size of the data communicated into the command.

13. The integrated system of claim 8, wherein the slave device and the master device are capable of communicating data with each other according to a communication protocol complying with a "Secure Digital Input Output - SDIO" communication standard defined by an "SD Association" organization, and the master device is configured to generate a command of an extended block read / write command type.

14. An integrated system as described in claim 8, wherein the master device is further configured to use the command field in other ways to address registers of functions that comply with the protocol, and the other use is identified by incorporating a corresponding dedicated code on one or more most significant bits of the field.

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