Sensor data caching method, apparatus, system, storage medium, and product

Abstract

The present disclosure provides a sensor data caching method, device, system, storage medium and product, relates to the field of data processing, and particularly relates to the field of automatic driving. The specific implementation scheme is as follows: acquiring to-be-cached data collected by any preset sensor, storing the to-be-cached data into a first cache area associated with the preset sensor in a field programmable gate array; in response to meeting a data writing condition, writing the to-be-cached data in the first cache area into a second cache area associated with the preset sensor in a target storage device which is in communication connection with the field programmable gate array; and writing the update state of the to-be-cached data into a preset cache area in a first-in-first-out manner. Thus, the sensor data can be cached by initializing the off-chip DDR storage device of the FPGA. The technical problem of system performance reduction caused by caching sensor data through the CPU and causing data processing link delay fluctuation is solved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to automatic driving in data processing, and in particular to a sensor data caching method, device, system, storage medium and product. BACKGROUND

[0002] In the unmanned driving scene, a variety of sensors for data acquisition are often pre-installed on the vehicle. Due to the variety of sensors and the inconsistent data size, the data needs to be pre-processed in the time synchronization system. In particular, before the data fusion operation, efficient cache management needs to be performed on various types of data.

[0003] However, how to implement cache management for various types of data collected by multiple sensors has become a problem to be solved. SUMMARY

[0004] The present disclosure provides a sensor data caching method, device, system, storage medium and product for caching multiple sensor data before sensor data preprocessing.

[0005] According to a first aspect of the present disclosure, a sensor data caching method is provided, comprising:

[0006] Obtaining the to-be-cached data collected by any preset sensor, and storing the to-be-cached data in a first cache area associated with the preset sensor in a field programmable logic gate array;

[0007] In response to satisfying a preset data writing condition, writing the to-be-cached data in the first cache area into a second cache area associated with the preset sensor in a target storage connected in communication with the field programmable logic gate array;

[0008] Writing the update state of the to-be-cached data into a preset cache area in a first-in-first-out manner, the update state including the data type and operation length of a plurality of data packets corresponding to the current writing operation.

[0009] According to a second aspect of the present disclosure, a data caching system is provided, comprising a field programmable logic gate array and a preset target storage; the field programmable logic gate array is connected in communication with a plurality of sensors;

[0010] The field programmable logic gate array includes a plurality of data caching units, and the data caching units correspond one-to-one to a plurality of preset sensors;

[0011] The double data rate synchronous dynamic random access memory includes a plurality of second cache areas, and the second cache areas correspond one-to-one to the sensors;

[0012] The data caching unit is configured to write the to-be-cached data sent by the sensor into a second cache area corresponding to the sensor in the target memory when a preset write condition is met, wherein a cache control of the second cache area is dynamically configured based on a data amount of the to-be-cached data and a preset transmission parameter.

[0013] The data caching unit comprises a preset cache area configured to store data in a first-in-first-out manner, and the preset cache area is configured to store an update state associated with the current write operation.

[0014] The data caching unit is further configured to determine target data to be read in a second cache area in the preset cache area in a first-in-first-out manner when a preset read condition is met, and read the target data into the data caching unit.

[0015] According to a third aspect of the present disclosure, a sensor data caching apparatus is provided, comprising:

[0016] The acquisition module is configured to acquire to-be-cached data collected by any preset sensor, and store the to-be-cached data into a first cache area associated with the preset sensor in the field programmable logic gate array.

[0017] The write module is configured to write the to-be-cached data in the first cache area into a second cache area associated with the preset sensor in a target memory in communication connection with the field programmable logic gate array in response to a preset data write condition being met.

[0018] The update module is configured to write an update state of the to-be-cached data into a preset cache area in a first-in-first-out manner, and the update state comprises data types and operation lengths of a plurality of data packets corresponding to the current write operation.

[0019] According to a fourth aspect of the present disclosure, an electronic device is provided, comprising:

[0020] at least one processor; and

[0021] a memory in communication connection with the at least one processor; wherein

[0022] The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method of the first aspect.

[0023] According to a fifth aspect of the present disclosure, a non-transitory computer readable storage medium storing computer instructions is provided, wherein the computer instructions are used to enable the computer to execute the method of the first aspect.

[0024] According to a sixth aspect of the present disclosure, a computer program product is provided, which comprises a computer program stored in a readable storage medium, at least one processor of an electronic device can read the computer program from the readable storage medium, and the at least one processor executes the computer program to enable the electronic device to perform the method of the first aspect.

[0025] The technical solution according to the present disclosure solves the technical problem of system performance reduction caused by sensor data caching by a vehicle central processor and causes data processing link delay fluctuation.

[0026] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present disclosure, nor to limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0027] The accompanying drawings are used to better understand the present scheme and do not limit the present disclosure. Among them:

[0028] Figure 1 A structural schematic diagram of a data caching system provided by an embodiment of the present disclosure is provided;

[0029] Figure 2 A structural schematic diagram of a cache writing module provided by an embodiment of the present disclosure is provided;

[0030] Figure 3 A structural schematic diagram of a cache reading module provided by an embodiment of the present disclosure is provided;

[0031] Figure 4 A flow schematic diagram of a sensor data caching method provided by an embodiment of the present disclosure is provided;

[0032] Figure 5 A flow schematic diagram of a sensor data caching method provided by another embodiment of the present disclosure is provided;

[0033] Figure 6 A flow schematic diagram of a sensor data caching method provided by another embodiment of the present disclosure is provided;

[0034] Figure 7 A data schematic diagram of packet grouping and DDR writing provided by an embodiment of the present disclosure is provided;

[0035] Figure 8 A flow schematic diagram of a sensor data caching method provided by another embodiment of the present disclosure is provided;

[0036] Figure 9 A structural schematic diagram of a sensor data caching device provided by an embodiment of the present disclosure is provided;

[0037] Figure 10A structural schematic diagram of an electronic device provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0038] Exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings, which include various details of the embodiments of the present disclosure to assist in understanding them. These should be considered as merely exemplary. Thus, those skilled in the art will recognize that variations and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, in the following description, descriptions of well-known functions and constructions are omitted for clarity and conciseness.

[0039] Glossary:

[0040] Field Programmable Gate Array (FPGA): A type of semi-custom integrated circuit in the field of special-purpose integrated circuits, which is a programmable logic array that can effectively solve the problem of fewer gate circuits in the original device. The basic structure of FPGA includes programmable input and output unit, configurable logic block, digital clock management module, embedded block RAM, wiring resource, embedded special hard core, and bottom embedded function unit. Due to the characteristics of rich wiring resources, repeatable programming, high integration, and low investment, FPGA has been widely used in the field of digital circuit design.

[0041] Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM): SDRAM with double data rate, its data transmission speed is twice the system clock frequency, and its transmission performance is better than that of traditional SDRAM due to the increase in speed. Data transmission can be performed on both the rising and falling edges of the system clock.

[0042] First Input First Output (FIFO): A traditional in-order execution method, the first instruction entered is completed and retired first, and the second instruction is executed next.

[0043] The present disclosure provides a sensor data caching method, device, system, storage medium and product, which is applied to automatic driving in the field of data processing to achieve the technical effect of data caching of data collected by various sensors.

[0044] In the unmanned driving scene, the vehicle is often pre-configured with multiple sensors for data collection. Due to the variety of sensors and the inconsistency of data size, these data need to be pre-processed in the time synchronization system.

[0045] In the related art, a CPU is generally directly used to perform cache management on data collected by multiple sensors. However, the above method for data caching often occupies limited system resources and causes the performance of the system to decrease. Meanwhile, the CPU management method introduces large fluctuations in the data processing link delay, affects the function, and has a security risk.

[0046] In the process of solving the above technical problems, the inventors have found through research that sensor data can be cached by initializing an off-chip DDR memory of an FPGA. In addition, for different sensors, a corresponding first-level cache can be set in the FPGA, which can be a BRAM in the FPGA, and a second-level cache can be set in the DDR. When sensor data is obtained, the sensor data is first temporarily stored in the first-level cache, and when a preset writing condition is met, the data in the first-level cache is written into the second-level cache.

[0047] Optionally, for each sensor, multiple channels can be divided in the DDR memory to realize storage of data of different sensors. In addition, the size of each burst access can be preset, that is, the size of the data written in and read from the DDR, so that the caching of sensor data is more in line with the data size of the sensor collected data.

[0048] It should be noted that the head model in this embodiment is not a head model of a specific user and cannot reflect the personal information of a specific user. It should be noted that the two-dimensional face image in this embodiment comes from a public data set.

[0049] In the technical solution of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information comply with relevant laws and regulations and do not violate public order and good customs.

[0050] To enable the reader to have a more profound understanding of the implementation principle of the present disclosure, the following Figures 1-10 The embodiments provided by the present disclosure are further refined.

[0051] Figure 1 The structure diagram of the data caching system provided by the embodiments of the present disclosure is shown in Figure 1 The data caching system 11 includes a field programmable logic gate array 12 and a preset target memory 13. The field programmable logic gate array 12 is in communication connection with multiple sensors 14 respectively.

[0052] The field programmable logic gate array 12 includes multiple data caching units 15, and the data caching units 15 correspond to the multiple sensors 14 respectively.

[0053] The data caching unit 15 is configured to write the to-be-cached data sent by the sensor 14 into a second cache area in the target memory 13 when a preset write condition is met, wherein a cache control of the second cache area is dynamically configured based on a data amount of the to-be-cached data and a preset transmission parameter.

[0054] The data caching unit 15 comprises a preset cache area for storing data in a first-in-first-out manner, and the preset cache area is configured to store an update state associated with the current write operation.

[0055] The data caching unit 15 is further configured to determine, in the preset cache area, target data to be read in a second cache area in a first-in-first-out manner when a preset read condition is met, and read the target data into the data caching unit 15.

[0056] In this embodiment, the data caching system 11 comprises a field programmable logic gate array 12 and a target memory 13. The field programmable logic gate array 12 is in communication connection with a plurality of sensors 14. In order to store the to-be-cached data collected by different sensors, a plurality of data caching units 15 can be arranged in the FPGA, and the data caching units 15 correspond to the plurality of sensors 14 in a one-to-one manner. The target memory can be a double data rate synchronous dynamic random access memory.

[0057] In addition, a plurality of second cache areas can be arranged in the target memory 13, and the second cache areas correspond to the sensors 14 in a one-to-one manner. Therefore, the to-be-cached data collected by each sensor 14 can be stored in blocks.

[0058] Based on the above system architecture, the target memory 13 comprises a plurality of second cache areas, and the second cache areas correspond to the sensors in a one-to-one manner. The cache control of the second cache area corresponding to each sensor can be dynamically configured based on a data amount of the to-be-written to-be-cached data and a transmission parameter.

[0059] After obtaining the to-be-cached data sent by the sensor 14, the to-be-cached data can be temporarily stored in the data caching unit. The data caching unit 15 is configured to write the temporarily stored to-be-cached data into a second cache area in the target memory 13 when a preset write condition is met.

[0060] The data caching unit comprises a preset cache area for storing data in a first-in-first-out manner, and the preset cache area is configured to store an update state associated with the current write operation. Therefore, subsequent positioning and reading operations on the target data can be performed based on the FIFO and in the order of data writing.

[0061] The data caching unit 15 is further configured to determine, in a first-in first-out manner, target data to be read in the second cache area in the preset cache area when a preset reading condition is met, and read the target data into the data caching unit.

[0062] The storage space of the first cache area and the third cache area is smaller than that of the second cache area.

[0063] The data caching system provided in the embodiment can acquire the data to be cached collected by the plurality of sensors, temporarily store the data to be cached, and write the data to be cached into the second cache area corresponding to each sensor in the target memory when a preset writing condition is met. Thus, the sensor data does not need to be cached in the CPU, and the technical problem of system performance reduction and data processing link delay fluctuation caused by caching sensor data through the vehicle central processor is avoided.

[0064] In addition, the update data is stored in the preset cache area in a first-in first-out manner, so that the sensor data cached in the second cache area can be read into the third cache area in a first-in first-out manner when a preset reading condition is met. The read and write operations of the data to be cached collected by the sensors can be more flexible.

[0065] Optionally, the data caching unit further comprises a cache writing module and a cache reading module.

[0066] The cache writing module and the cache reading module are respectively in communication connection with the preset cache area.

[0067] The cache writing module is configured to cache the data to be cached sent by the sensor into a preset first cache area, and write the data to be cached into the second cache area corresponding to the sensor in the target memory when a preset writing condition is met.

[0068] The cache reading module is configured to determine, in a first-in first-out manner, target data to be read in the second cache area in the preset cache area when a preset reading condition is met, and read the target data into a third cache area in the cache reading module.

[0069] In the embodiment, the data cache unit can include a cache writing module and a cache reading module. The cache writing module and the cache reading module are respectively in communication connection with the preset cache area. Therefore, the cache writing module is used for caching the to-be-cached data sent by the sensor into the preset first cache area, and when the preset writing condition is met, writing the to-be-cached data into the second cache area corresponding to the sensor in the target storage; the cache reading module is used for determining the target data to be read in the second cache area in the preset cache area in a first-in-first-out manner when the preset reading condition is met, and reading the target data into a third cache area in the cache reading module.

[0070] It should be noted that the first cache area and the third cache area can be the same cache area. Thus, the temporary storage of the to-be-written data and the temporary storage of the current reading data can be simultaneously performed in the same cache area.

[0071] Figure 2 The structure schematic diagram of the cache writing module provided by the embodiment of the present disclosure is shown in FIG. 2, which is based on any of the above embodiments. Figure 2 As shown in FIG. 2, the cache writing module 21 includes a first cache area 22, a packet assembling module 23 and a writing state control module 24. The packet assembling module 23 is in communication connection with the first cache area 22, the writing state control module 24 and the second cache area 25 respectively.

[0072] The first cache area 22 is used for performing a cache operation on the to-be-cached data collected by the sensor.

[0073] The writing state control module 24 is used for controlling the packet assembling module 23 to perform a packet assembling operation on the to-be-cached data and writing the packet-assembled to-be-cached data into the second cache area 25 when the preset data writing condition is met.

[0074] In the embodiment, the cache writing module 21 includes a first cache area 22, a packet assembling module 23 and a writing state control module 24. The packet assembling module 23 is in communication connection with the first cache area 22, the writing state control module 24 and the second cache area 25 respectively.

[0075] After the sensor collects the to-be-cached data, the first cache area 22 is used for performing a cache operation on the to-be-cached data.

[0076] The writing state control module 24 is used for determining whether the preset data writing condition is met in real time based on the storage states of the first cache area and the second cache area. When the preset data writing condition is met, the writing state control module 24 controls the packet assembling module 23 to perform a packet assembling operation on the to-be-cached data and writes the packet-assembled to-be-cached data into the second cache area 25.

[0077] The data cache system provided by the embodiment can temporarily store the to-be-cached data collected by the sensor in the first cache area, detect a data writing condition by the writing state control module, perform a packetizing operation on the to-be-cached data by the packetizing module when the data writing condition is met, and write the packetized to-be-cached data into the second cache area. Therefore, the FPGA can initialize the off-chip DDR memory to cache the sensor data.

[0078] Figure 3 The structure diagram of the cache reading module provided by the embodiment of the present disclosure is shown in FIG. 3, which is based on any of the above embodiments. Figure 3 The cache reading module 31 includes a third cache area 32, a packetizing module 33, and a reading state control module 34.

[0079] The packetizing module 33 is in communication connection with the third cache area 32, the reading state control module 34, and the second cache area 35.

[0080] The reading state control module 34 is configured to determine the target data to be read currently in the preset cache area in a first-in first-out manner when a reading condition is met, and perform a reading operation on the target data from the second cache area 35.

[0081] The packetizing module 33 is configured to perform a packetizing operation on the target data, and read the valid data in the target data to the third cache area 32.

[0082] In the embodiment, the cache reading module 31 includes a third cache area 32, a packetizing module 33, and a reading state control module 34.

[0083] The packetizing module 33 is in communication connection with the third cache area 32, the reading state control module 34, and the second cache area 35.

[0084] The reading state control module 34 is configured to detect whether a preset data reading condition is met in real time based on the storage states of the second cache area and the third cache area. When the reading condition is met, the reading state control module 34 determines the target data to be read currently based on a first-in first-out queue, and performs a reading operation on the target data from the second cache area 35.

[0085] Since a packetizing operation is performed on the to-be-cached data before the to-be-cached data is written into the second cache area, a packetizing operation is needed during the data reading process. Therefore, the packetizing module 33 is configured to perform a packetizing operation on the target data, and read the valid data in the target data to the third cache area 32.

[0086] Further, after the valid data is read to the third cache area, the valid data can also be subjected to data fusion, data preprocessing and the like by a preset processing module. The present disclosure does not limit this.

[0087] The data cache system provided by the embodiment can determine whether the preset data reading condition is met based on the read state control module, automatically determine the target data to be read based on the first-in first-out queue when the data reading condition is met, and perform the reading operation on the target data from the second cache area. The target data is subjected to unpacking operation based on the unpacking module, and the valid data in the target data is read to the third cache area. Thus, on the basis of storing the data to be cached to the FPGA initialization off-chip DDR memory, the reading and writing operation of the data to be cached can be flexibly performed.

[0088] Figure 4 The flowchart of the sensor data cache method provided by the embodiment of the present disclosure is shown in Figure 4 The method comprises the following steps:

[0089] In step 401, the data to be cached collected by any preset sensor is acquired, and the data to be cached is stored to a first cache area associated with the preset sensor in a field programmable gate array.

[0090] In step 402, in response to the preset data writing condition being met, the data to be cached in the first cache area is written to a second cache area associated with the preset sensor in a target memory in communication connection with the field programmable gate array.

[0091] In step 403, the update state of the data to be cached is written to a preset cache area in a first-in first-out manner, and the update state comprises the data type and operation length of a plurality of data packets corresponding to the current writing operation.

[0092] The execution subject of the embodiment is a sensor data cache device, which can be coupled to a field programmable gate array. The field programmable gate array can be in communication connection with a preset target memory, so that after the data to be cached collected by the sensor is acquired, the data to be cached can be stored to the target memory before data preprocessing and data fusion, avoiding the use of cpu for data cache operation.

[0093] It should be noted that the target memory can be a double rate synchronous dynamic random access memory. The double rate synchronous dynamic random access memory has a relatively large storage space, and the double rate synchronous dynamic random access memory has a faster cache speed than other memories. Therefore, for a camera or other sensor that collects a large amount of data, using a double rate synchronous dynamic random access memory to cache sensor data can improve cache efficiency and effectively store a large amount of sensor data.

[0094] In the embodiment, the plurality of data cache units in the field programmable logic gate array correspond one-to-one to a plurality of preset sensors. The data cache unit includes a cache write module, a cache read module, and a first-in-first-out queue. The cache write module and the cache read module are respectively in communication connection with a preset cache area that uses a first-in-first-out method for data storage. The cache write module is used to temporarily store the to-be-cached data transmitted by the sensor and write the to-be-cached data into a second cache area in the target memory when a preset data write condition is met. After the data is written, the data state can be updated and written into the preset cache area in a FIFO manner. Therefore, when the cache read module determines that the preset data read condition is met, the target data in the second cache area can be determined in the preset cache area based on the FIFO manner, and the target data in the second cache area can be read into a preset third cache area in the cache read module.

[0095] Based on the above system architecture, the to-be-cached data collected by any preset sensor can be obtained and stored in the first cache area in the FPGA associated with the preset sensor.

[0096] Further, whether the preset data write condition is met can be determined in real time based on the current storage state of the first cache area and the second cache area. In response to the preset data write condition being met, the to-be-cached data in the first cache area is written into the second cache area in the target memory associated with the preset sensor and in communication connection with the field programmable logic gate array.

[0097] Optionally, to facilitate subsequent data read operations, the update state of the to-be-cached data can also be written into the preset cache area in a first-in-first-out manner. The update state includes the data type and operation length of a plurality of data packets corresponding to this write operation, and the preset cache area includes the update state corresponding to all the data cached in the second cache area.

[0098] The sensor data caching method provided in the embodiment can temporarily store the to-be-cached data in the first cache area after the to-be-cached data is acquired. When the preset data writing condition is met, the to-be-cached data is written into the second cache area in the target storage that matches the sensor. Thus, the caching of the sensor data in the CPU is not needed, and the technical problems of system performance reduction and data processing link delay fluctuation are avoided.

[0099] In addition, the update data is written into the preset cache area in a first-in first-out manner, so that the sensor data cached in the second cache area can be automatically read into the third cache area in the preset cache area in a FIFO manner when the preset reading condition is met. The read and write operations on the to-be-cached data collected by the sensor can be more flexible.

[0100] Figure 5 The flowchart of the sensor data caching method provided in another embodiment of the disclosure is shown in FIG. 4, which is based on any of the above embodiments. Figure 5 As shown in FIG. 4, step 402 includes:

[0101] Step 501: in response to the to-be-cached data in the first cache area meeting a preset trigger condition, determining a first storage state, wherein the first storage state includes a cache state associated with the first cache area and a cache state associated with the second cache area.

[0102] Step 502: in response to the first storage state meeting a preset condition, writing the to-be-cached data into the second cache area.

[0103] In the embodiment, the trigger condition can be preset. When the trigger condition is met, the monitoring of the first storage state associated with the first cache area and the second cache area is triggered, so the first storage state can be acquired. The first storage state includes the cache state associated with the first cache area and the cache state associated with the second cache area. For example, the first storage state includes the data storage amount in the first cache area and the second cache area, whether there is storage space, and other information.

[0104] Optionally, the trigger condition can be that the data amount in the first cache area reaches a preset data amount threshold. Alternatively, because the to-be-cached data collected by different sensors has different sizes, different trigger conditions can be set for different sensors, which is not limited in the disclosure. For example, when the to-be-cached data is small, if it is detected that the sensor does not perform the transmission of the next round of data for a preset time length, the monitoring of the first storage state associated with the first cache area and the second cache area is triggered.

[0105] Further, whether the preset condition is met can be determined based on the first storage state, and in response to the first storage state meeting the preset condition, the to-be-cached data is written into the second cache area.

[0106] Optionally, in order to ensure the accuracy of subsequent write operations, the first storage state of the first buffer area and the second buffer area can also be updated after the completion of the write operation.

[0107] The sensor data caching method provided in this embodiment can further determine the first storage state associated with the first buffer area and the second buffer area when the trigger condition is met, so as to determine whether the preset condition is met based on the first storage state. Then, flexible write operations can be performed on the data to be cached based on the processing result.

[0108] Further, based on any of the above embodiments, step 502 comprises:

[0109] If it is determined based on the first storage state that the first buffer area and the second buffer area are both full, and there is overflow data, the data to be cached is discarded.

[0110] If it is determined based on the first storage state that the first buffer area and the second buffer area are both full, but there is no overflow data, the step of determining the first storage state is returned to be executed until there is storage space in the second buffer area, and the data to be cached is written into the second buffer area.

[0111] If it is determined based on the first storage state that there is storage space in the second buffer area, the data to be cached is written into the second buffer area.

[0112] In this embodiment, when there is buffer space in the second buffer area, it indicates that data can be written into the second buffer area. Conversely, if the second buffer area is full, data cannot be written into the second buffer area. At this time, if the first buffer area is also full but there is no overflow data, or the first buffer area is not full, the monitoring operation of the first storage state can be continued, and the data write operation is performed when it is determined that there is storage space in the second buffer area. If it is determined based on the first storage state that the first buffer area and the second buffer area are both full, and there is overflow data, a channel reset operation can be performed.

[0113] Therefore, if it is determined based on the first storage state that the first buffer area and the second buffer area are both full, and there is overflow data, the data to be cached is discarded. If it is determined based on the first storage state that the first buffer area and the second buffer area are both full, but there is no overflow data, the step of determining the first storage state associated with the first buffer area and the second buffer area is returned to be executed until there is storage space in the second buffer area, and the data to be cached is written into the second buffer area. If it is determined based on the first storage state that there is storage space in the second buffer area, the data to be cached is written into the second buffer area.

[0114] The sensor data caching method provided in this embodiment can flexibly perform the write-in processing of the to-be-cached data based on the first storage state, and is suitable for more data write-in scenarios.

[0115] Further, on the basis of any of the above embodiments, step 501 comprises:

[0116] determining whether the data amount of the to-be-cached data in the first cache area reaches a preset data amount threshold.

[0117] If yes, the first storage state corresponding to the first cache area and the second cache area is determined.

[0118] In this embodiment, the preset trigger condition can be to monitor the first storage state when the data amount of the to-be-cached data in the first cache area reaches the preset data amount threshold. For example, the data amount threshold can be 256 bytes.

[0119] Therefore, it can be detected in real time whether the data amount of the to-be-cached data in the first cache area reaches the preset data amount threshold. If yes, the first storage state associated with the first cache area and the second cache area is determined.

[0120] The sensor data caching method provided in this embodiment can pre-set a trigger condition, so that the first storage state associated with the first cache area and the second cache area can be further determined when the trigger condition is met. Therefore, the write-in operation of subsequent data can be flexibly performed based on the current data amount of the to-be-cached data temporarily stored.

[0121] Figure 6 The flowchart of the sensor data caching method provided in another embodiment of the present disclosure is shown in FIG. 4B, which is based on any of the above embodiments. As shown in FIG. 4B, step 402 comprises: Figure 6

[0122] Step 601: determining the data amount corresponding to the to-be-cached data, and determining the transmission parameter pre-set by the user, wherein the transmission parameter comprises the number of bytes transmitted per clock beat.

[0123] Step 602: performing a packetizing operation on the to-be-cached data based on the data amount and the transmission parameter, to obtain a plurality of to-be-transmitted data packets.

[0124] ​In step 603, the plurality of to-be-transmitted data packets are written into the second cache area.

[0125] In the embodiment, the data packet operation can be performed on the to-be-cached data before data writing.

[0126] Optionally, the data amount corresponding to the to-be-cached data can be determined, and a transmission parameter set by a user in advance can be determined, wherein the transmission parameter includes the number of bytes transmitted per clock beat. The user can set the number of bytes transmitted per clock beat to 16, 8, or 4 according to actual needs, and the present disclosure does not limit this.

[0127] Further, the to-be-cached data can be packetized based on the data amount and the transmission parameter to obtain a plurality of to-be-transmitted data packets. The plurality of to-be-transmitted data packets are written into the second cache area.

[0128] The sensor data caching method provided in the embodiment can improve the success rate of data writing by performing the packet operation on the to-be-cached data before data writing, thereby avoiding the problem of data loss in the data transmission process.

[0129] Further, on the basis of any of the above embodiments, step 602 includes:

[0130] The effective data matched with the transmission parameter is obtained from the to-be-cached data, and the to-be-transmitted data packet is constructed based on the effective data.

[0131] In response to the data amount of the remaining effective data in the to-be-cached data being less than the transmission parameter, the number of byte difference between the remaining effective data and the transmission parameter is determined.

[0132] The padding code matched with the number of byte difference is inserted into the remaining to-be-cached data to obtain the to-be-transmitted data packet.

[0133] In the embodiment, the to-be-cached data can be written into the DDR according to the preset transmission parameter. The transmission parameter can include the number of bytes written per clock beat. In the process of data transmission according to the fixed clock beat, if the actual data amount transmitted is less than the number of bytes written per clock beat in the transmission parameter, the frame structure can be incomplete, so that the DDR can not correctly identify the start and end of the frame after obtaining the to-be-transmitted data. In addition, since the transmission parameter is set in advance, when the actual data amount transmitted is less than the number of bytes written per clock beat in the transmission parameter, there are irregular gaps or inconsistent beats in the data stream, and the receiving side DDR can be a channel part, which can cause data parsing errors.

[0134] In the process of solving the above problems, the inventors have found that, when the actual amount of data to be transmitted is less than the number of clock beats written in the transmission parameters, a data padding operation can be performed by padding characters to match the actual amount of data to be transmitted with the number of clock beats written in the transmission parameters, so as to ensure the effectiveness and accuracy of data transmission.

[0135] Therefore, valid data matching the transmission parameters can be obtained from the data to be cached, and a data packet to be transmitted is constructed based on the valid data. The data packet to be transmitted is sequentially written, and it is determined whether the current remaining valid field is less than the transmission parameters. In response to the amount of data of the remaining valid data in the data to be cached being less than the transmission parameters, a byte quantity difference between the remaining valid data and the transmission parameters is determined. A padding code matching the byte quantity difference is inserted in the remaining data to be cached, and a data packet to be transmitted is obtained.

[0136] For example, in an actual application, the data of a burst write to DDR is 64 bytes, but the actual valid data is 62 bytes, and 16 bytes are written per clock beat. The first clock beat is sop (the first data of the valid packet text data), and 16 bytes are written. The second clock beat is data (the data signal to be transmitted), and 16 bytes are written. The third clock beat is data, and 16 bytes are written. The fourth beat is eop (the last data of the valid packet text data), and 16 bytes are written. However, the last beat actually has 14 bytes of valid data, and the remaining 2 bytes are padded with pad, which is a unique code in the data.

[0137] Figure 7 A data grouping write DDR diagram provided by the embodiments of the present disclosure is shown in Figure 7 When the remaining valid data in the data to be cached 71 does not match the number of bytes transmitted per clock beat, a padding operation can be performed by padding code (pad) 72 to obtain a grouping result.

[0138] The sensor data caching method provided in this embodiment performs a data padding operation using padding code when the amount of data of the remaining valid data is less than the transmission parameters. Therefore, the effectiveness and accuracy of data transmission can be ensured.

[0139] Further, on the basis of any of the above embodiments, step 403 comprises:

[0140] The update state is encoded according to a preset encoding mode to obtain encoded data, wherein the encoded data is used to indicate the data type and operation length of the plurality of data packets corresponding to the current write operation.

[0141] The encoded data is added to the first-in-first-out queue.

[0142] In the embodiment, the encoding mode can be preset. In the encoding mode, the width of the encoded data is four bits, and the encoding mode is used to indicate that 2-3 bits in the encoded data represent the data type of the data packet, and 0-1 bits represent the operation length corresponding to the current write operation. Among them, bit[3:2] is used to represent the data type, wherein sop=01, eop=10, D=00, and seop=11. bit[1:0] represents the operation length of the current burst. sop represents the frame header, eop represents the frame tail, seop represents that sop and eop occur in the same beat, and D represents a normal data packet. For example, 00 represents a length of 256, 01 represents a length of 128, 10 represents a length of 64, and 11 represents a length of 32.

[0143] Therefore, the update state can be encoded according to the preset encoding mode to obtain encoded data. Therefore, the encoded data can indicate the data type and the operation length of the plurality of data packets corresponding to the current write operation. The encoded data can be added to the preset cache area in a first-in-first-out manner.

[0144] The FIFO is arranged in the FPGA chip. The FIFO has a small bit width, a long depth, and consumes very few resources. For example, the width of the FIFO is 4 bits, and the depth is 8192. Therefore, the resources occupied by the FIFO in the FPGA are 32Kbits.

[0145] The sensor data caching method provided in the embodiment encodes the update state according to the preset encoding mode to obtain encoded data, and adds the encoded data to the preset cache area in a FIFO manner. Therefore, in the subsequent data caching process, the data type and the operation length of each data packet can be accurately determined based on the update state stored in the FIFO, and therefore the target data to be read can be more accurately positioned and read.

[0146] Figure 8 The flowchart of the sensor data caching method provided in another embodiment of the present disclosure is shown in the above embodiment, as shown in Figure 8 After step 403, the method further includes:

[0147] Step 801, in response to the preset data reading condition being met, determining the target data to be read in the preset cache area in a first-in-first-out manner.

[0148] Step 802, reading the target data from the second cache area to a third cache area associated with the preset sensor in the field programmable logic gate array.

[0149] In the embodiment, after the data is written, the update state is written into the preset cache area in a FIFO manner, and therefore, when the data reading condition is met, the reading operation of the target data can be performed in the preset cache area in a FIFO manner. The update state associated with all the sensor data in the second cache area is stored in the preset cache area in a first-in first-out manner, and therefore, the reading operation of the target data can be performed in a first-in first-out manner.

[0150] Optionally, when it is detected that the data reading condition is met, the target data to be read currently can be determined in the preset cache area in a first-in first-out manner. The cache reading module in the field programmable logic gate array can determine whether the data reading condition is met. In addition, the third cache area is included in the cache reading module, and therefore, the target data can be read from the second cache area to the third cache area associated with the preset sensor in the field programmable logic gate array.

[0151] Optionally, the first cache area and the third cache area can be the same cache area. Therefore, the temporary storage of the data to be written and the temporary storage of the current reading data can be performed in the same cache area.

[0152] The sensor data caching method provided in the embodiment can determine the target data to be read currently in the preset cache area in a first-in first-out manner when the data reading condition is met, and therefore, the data reading operation can be accurately performed according to the data writing sequence.

[0153] Further, on the basis of any of the above embodiments, the step 801 comprises:

[0154] In response to the fact that the third cache area has cache space, the second cache state is determined, wherein the second cache state comprises the cache state associated with the second cache area and the cache state associated with the third cache area.

[0155] If it is determined that the third cache area has cache space based on the second cache state and there is cache data in the second cache area, the target data to be read currently is determined in the preset cache area in a first-in first-out manner.

[0156] In the embodiment, whether the third cache area has cache space can be detected constantly in the idle state. In response to the fact that the third cache area has cache space, the second cache state associated with the second cache area and the third cache area is determined. For example, the cache depth of the third cache area can be 1 kbyte, and when it is determined that there are still 256 bytes in the third cache area, the second cache state associated with the second cache area and the third cache area is determined. The second cache state comprises the current data storage amount and whether there is storage space in the second cache area and the third cache area.

[0157] Further, after obtaining the second cache state, if there is cache space in the third cache area, the target data to be read currently is determined based on the first-in first-out queue.

[0158] Optionally, if there is no cache space in the third cache area and the second cache area, and there is data overflow, a channel reset operation can be performed. If there is no cache space in the third cache area and the second cache area, but there is no data overflow, the second cache state can be continuously detected, and when there is cache space in the third cache area, there is cache data in the second cache area, and no data overflow occurs, a data writing operation is performed.

[0159] In order to ensure the accuracy of subsequent data reading operations, the second cache state can be updated based on the data reading operation after each data reading operation is completed.

[0160] The sensor data caching method provided in the embodiment can perform data reading operation more flexibly based on the data reading condition on the basis of writing the data to be cached into the FPGA initialized off-chip DDR memory by pre-setting the data reading condition.

[0161] Further, on the basis of any of the above embodiments, step 801 comprises:

[0162] The plurality of data packets to be read currently in the preset cache area are determined in the first-in first-out manner.

[0163] For each data packet, the update state associated with the data packet in the preset cache area is decoded based on the preset decoding manner to obtain the data type and operation length corresponding to the data packet.

[0164] The memory space and memory address of the data type, operation length corresponding to the data packet, and the transmission parameter set by the user in the second cache area are determined.

[0165] Step 802 comprises:

[0166] The target data is read from the second cache area to the third cache area based on the memory space and the memory address.

[0167] In the embodiment, the update state associated with all sensor data in the second cache area is stored in the FIFO in the first-in first-out manner. Therefore, the reading operation of the target data can be realized in the first-in first-out manner.

[0168] Optionally, the current to-be-read data packets are determined in the preset cache area in a FIFO manner. Since the update state in the preset cache area is the encoded state, for each data packet, the update state associated with the data packet in the first-in-first-out queue is decoded based on the preset decoding manner to obtain the data type and operation length corresponding to the data packet.

[0169] The memory space and memory address of the data type, operation length corresponding to the data packet, and the transmission parameter set by the user in the second cache area are determined. The target data is read from the second cache area to the third cache area based on the memory space and memory address.

[0170] Optionally, based on any of the above embodiments, after step 401, the method further includes:

[0171] The data amount corresponding to the to-be-cached data and the preset transmission parameter are determined.

[0172] The cache control of the second cache area is configured through the preset configuration interface according to the data amount and the transmission parameter.

[0173] In this embodiment, the user can dynamically configure the second cache area in the target memory according to the actual data caching requirement.

[0174] Optionally, the data amount of the to-be-cached data currently transmitted by the sensor and the preset transmission parameter can be determined. The transmission parameter can be the number of bytes written per clock beat. The transmission parameter can be set by the user according to the actual requirement, which is not limited in the present disclosure. Therefore, the cache space of the second cache area can be configured through the preset configuration interface.

[0175] For example, the memory space of the FIFO mapped to the DDR can be configured. For example, the number of bytes per clock beat can be configured as 16 or 8 bytes or 4 bytes. At the same time, the maximum transmission length initiated each time is 256. The user can set the transmission parameter according to the actual requirement. For example, for different sensors, since the data amount of the sensor data collected by the sensors is different, different transmission parameters can be set for different sensors, which is not limited in the present disclosure.

[0176] Optionally, when the number of bytes per clock beat is configured as 16, the memory range of the FIFO depth of 8192 mapping is [512B, 32MB]. Similarly, when the number of bytes per clock beat is configured as 8, the memory range of the FIFO depth of 8192 mapping is [256B, 16MB]. When the number of bytes per clock beat is configured as 4, the memory range of the FIFO depth of 8192 mapping is [128B, 8MB].

[0177] The specific second cache area write address memory mapping process is that, assuming that the number of bytes per clock cycle is configured as 16, according to a preset encoding mode, if bit [1:0] of the FIFO is 00, the memory address is added by 256*16B on the basis of the original memory address, if bit [1:0] of the FIFO is 01, the memory address is added by 128*16B on the basis of the original memory address, if bit [1:0] of the FIFO is 10, the memory address is added by 64*16B on the basis of the original memory address, and if bit [1:0] of the FIFO is 11, the memory address is added by 32*16B on the basis of the original memory address. The second cache area can be a ring address, for example, the entire depth is 1024 bytes, and the starting relative address is counted from 0, and when 1024 is written, the address will return to 0 again to start counting.

[0178] Assuming that the number of bytes per clock cycle is configured as 8, if bit [1:0] of the FIFO is 00, the memory address is added by 256*8B on the basis of the original memory address, if bit [1:0] of the FIFO is 01, the memory address is added by 128*8B on the basis of the original memory address, if bit [1:0] of the FIFO is 10, the memory address is added by 64*8B on the basis of the original memory address, and if bit [1:0] of the FIFO is 11, the memory address is added by 32*8B on the basis of the original memory address.

[0179] The sensor data caching method provided in the embodiment can accurately implement data reading operation according to the data writing sequence, by determining the memory space and the memory address mapped to the DDR based on the FIFO.

[0180] Further, on the basis of any of the above embodiments, step 802 comprises:

[0181] The target data is unpacked to obtain valid data corresponding to the target data.

[0182] The valid data is read into the third cache area.

[0183] In the embodiment, the data to be cached needs to be packed during the data writing process. Therefore, the data needs to be unpacked during the data reading process.

[0184] Optionally, the target data can be unpacked to obtain valid data corresponding to the target data. Therefore, the valid data can be read into the third cache area.

[0185] The sensor data caching method provided in the embodiment can extract valid data from the target data by unpacking the target data, and implement reading operation of the valid data.

[0186] Further, based on any of the above embodiments, the unpacking operation on the target data is performed to obtain valid data corresponding to the target data, and the unpacking operation includes:

[0187] extracting a first data packet, a last data packet, and at least one intermediate data packet in the target data.

[0188] determining the first data packet and the at least one intermediate data packet as the valid data.

[0189] determining whether the last data packet includes padding code.

[0190] if the padding code exists, deleting the padding code and determining a remaining field in the last data packet as the valid data.

[0191] In this embodiment, since the padding code is inserted in the valid data for packetization in a case where the remaining valid data does not match a preset byte amount sent per clock cycle during the writing of the data to be cached, the padding code can be determined in the unpacking process, and the padding code is deleted in a case where the padding code exists.

[0192] Optionally, a first data packet (sop), a last data packet (eop), and at least one intermediate data packet (data) in the target data can be extracted.

[0193] Further, since the padding code is generally filled in the eop, the first data packet and the at least one intermediate data packet can be directly determined as the valid data. It is determined whether the eop includes the padding code. If the padding code exists, the padding code is deleted, and a remaining field in the last data packet is determined as the valid data. Otherwise, if the eop does not include the padding code, the eop can be directly determined as the valid data.

[0194] The sensor data caching method provided in this embodiment can accurately obtain the valid data by discarding the padding code in the unpacking process, and thus can perform the reading operation on the valid data.

[0195] Figure 9 A structural diagram of a sensor data caching apparatus provided in the embodiments of the present disclosure is shown in FIG. 1. Figure 9As shown, the apparatus comprises: an acquisition module 91, a write module 92, and an update module 93. The acquisition module 91 is configured to acquire to-be-cached data collected by any preset sensor, and store the to-be-cached data into a first cache area associated with the preset sensor in a field programmable logic gate array. The write module 92 is configured to, in response to a preset data write condition being met, write the to-be-cached data in the first cache area into a second cache area associated with the preset sensor in a target memory in communication connection with the field programmable logic gate array. The update module 93 is configured to write an update state of the to-be-cached data into a preset cache area in a first-in-first-out manner, the update state including data types and operation lengths of a plurality of data packets corresponding to a current write operation.

[0196] Further, on the basis of any of the above embodiments, the write module comprises: a determination unit configured to, in response to the to-be-cached data in the first cache area meeting a preset trigger condition, determine a first storage state, wherein the first storage state includes a cache state associated with the first cache area and a cache state associated with the second cache area. A write unit configured to, in response to the first storage state meeting a preset condition, write the to-be-cached data into the second cache area.

[0197] Further, on the basis of any of the above embodiments, the write unit comprises: a first processing sub-unit configured to, if it is determined based on the first storage state that the first cache area and the second cache area are both full and there is overflow data, discard the to-be-cached data. A second processing sub-unit configured to, if it is determined based on the first storage state that the first cache area and the second cache area are both full but there is no overflow data, return to perform the step of determining the first storage state until there is storage space in the second cache area, and write the to-be-cached data into the second cache area. A write sub-unit configured to, if it is determined based on the first storage state that there is storage space in the second cache area, write the to-be-cached data into the second cache area.

[0198] Further, on the basis of any of the above embodiments, the determination unit comprises: a determination sub-unit configured to determine whether a data amount of the to-be-cached data in the first cache area reaches a preset data amount threshold. The determination sub-unit is configured to, if yes, determine the first storage state.

[0199] Further, based on any of the above embodiments, the writing module comprises: a determining unit configured to determine a data amount corresponding to the data to be cached, and determine a transmission parameter set by a user in advance, wherein the transmission parameter comprises a number of bytes transmitted per clock cycle; a packetizing unit configured to packetize the data to be cached based on the data amount and the transmission parameter to obtain a plurality of data packets to be transmitted; and a writing unit configured to write the plurality of data packets to be transmitted into the second cache area.

[0200] Further, based on any of the above embodiments, the packetizing unit comprises: an obtaining subunit configured to obtain valid data matching the transmission parameter from the data to be cached, and construct the data packets to be transmitted based on the valid data; a determining subunit configured to determine a difference in the number of bytes between the remaining valid data and the transmission parameter in response to the data amount of the remaining valid data being less than the transmission parameter; and a padding subunit configured to insert padding codes matching the difference in the number of bytes into the remaining data to be cached to obtain the data packets to be transmitted.

[0201] Further, based on any of the above embodiments, the updating module comprises: an encoding unit configured to encode the update state according to a preset encoding mode to obtain encoded data, wherein the encoded data is used to indicate a data type and an operation length of a plurality of data packets corresponding to the current writing operation; and an updating unit configured to write the encoded data into the preset cache area in a first-in first-out manner.

[0202] Further, based on any of the above embodiments, the apparatus further comprises: a determining module configured to determine target data to be read in the preset cache area in a first-in first-out manner in response to a preset data reading condition being met; and a reading module configured to read the target data from the second cache area into a third cache area associated with the preset sensor in the field programmable logic gate array.

[0203] Further, based on any of the above embodiments, the third cache area and the first cache area are the same cache area.

[0204] Further, based on any of the above embodiments, the determining module comprises: a determining unit configured to determine a second cache state in response to the third cache area having a cache space, wherein the second cache state comprises a cache state associated with the second cache area and a cache state associated with the third cache area; and a reading unit configured to determine target data to be read in the preset cache area in a first-in first-out manner in response to the third cache area having a cache space and the second cache area having cached data based on the second cache state.

[0205] Further, on the basis of any of the above embodiments, wherein the determining unit comprises: a determining sub-unit, configured to determine, in a preset cache area, a plurality of data packets to be read currently in the first-in first-out manner; a decoding sub-unit, configured to, for each data packet, perform a decoding operation on an update state associated with the data packet in the preset cache area based on a preset decoding manner, to obtain a data type and an operation length corresponding to the data packet; and a mapping sub-unit, configured to determine a memory space and a memory address of the data type, the operation length, and a transmission parameter set by a user in the second cache area. The reading unit comprises: a reading sub-unit, configured to read the target data from the second cache area to the third cache area based on the memory space and the memory address.

[0206] Further, on the basis of any of the above embodiments, wherein the reading module comprises: an unpacking unit, configured to perform an unpacking operation on the target data to obtain valid data corresponding to the target data; and a reading unit, configured to read the valid data into the third cache area.

[0207] Further, on the basis of any of the above embodiments, wherein the unpacking unit comprises: an extracting sub-unit, configured to extract a first data packet, a last data packet, and at least one intermediate segment data packet in the target data; a determining sub-unit, configured to determine the first data packet and the at least one intermediate segment data packet as the valid data; an identifying sub-unit, configured to, for the last data packet, determine whether the last data packet includes padding coding; and a deleting sub-unit, configured to, if the padding coding exists, delete the padding coding and determine remaining fields in the last data packet as the valid data.

[0208] Further, on the basis of any of the above embodiments, the target memory comprises a double data rate synchronous dynamic random access memory.

[0209] Further, on the basis of any of the above embodiments, the apparatus further comprises: a determining module, configured to determine a data amount corresponding to the data to be cached and a preset transmission parameter; and a configuring module, configured to perform a configuration operation on a cache control of the second cache area through a preset configuration interface according to the data amount and the transmission parameter.

[0210] According to embodiments of the present disclosure, the present disclosure further provides an electronic device, a readable storage medium, and a computer program product.

[0211] According to embodiments of the present disclosure, the present disclosure further provides an electronic device, comprising:

[0212] at least one processor; and

[0213] A memory communicatively connected to the at least one processor; wherein,

[0214] The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method described in any of the above embodiments.

[0215] According to embodiments of this disclosure, this disclosure also provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause the computer to perform the methods described in any of the above embodiments.

[0216] According to embodiments of this disclosure, this disclosure also provides a computer program product comprising: a computer program stored in a readable storage medium, at least one processor of an electronic device being able to read the computer program from the readable storage medium, and the at least one processor executing the computer program causing the electronic device to perform the scheme provided in any of the above embodiments.

[0217] Figure 10 This is a schematic diagram of the structure of an electronic device provided according to an embodiment of the present disclosure. The electronic device 1000 is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0218] like Figure 10 As shown, device 1000 includes a computing unit 1001, which can perform various appropriate actions and processes according to a computer program stored in read-only memory (ROM) 1002 or a computer program loaded from storage unit 1008 into random access memory (RAM) 1003. The RAM 1003 may also store various programs and data required for the operation of device 1000. The computing unit 1001, ROM 1002, and RAM 1003 are interconnected via bus 1004. Input / output (I / O) interface 1005 is also connected to bus 1004.

[0219] The various components in the device 1000 are connected to the I / O interface 1005, including: an input unit 1006, such as a keyboard, a mouse, etc.; an output unit 1007, such as various types of displays, speakers, etc.; a storage unit 1008, such as a magnetic disk, an optical disk, etc.; and a communication unit 1009, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 1009 allows the device 1000 to exchange information / data with other devices through computer networks, such as the Internet, and / or various telecommunication networks.

[0220] The computing unit 1001 can be various general and / or special purpose processing components with processing and computing capabilities. Some examples of the computing unit 1001 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The computing unit 1001 performs various methods and processes described above, such as the sensor data caching method. For example, in some embodiments, the sensor data caching method can be implemented as a computer software program tangibly embodied in a machine-readable medium, such as the storage unit 1008. In some embodiments, part or all of the computer program can be loaded and / or installed onto the device 1000 via the ROM 1002 and / or the communication unit 1009. When the computer program is loaded onto the RAM 1003 and executed by the computing unit 1001, one or more steps of the sensor data caching method described above can be performed. Alternatively, in other embodiments, the computing unit 1001 can be configured to perform the sensor data caching method by any other appropriate means, such as by means of firmware.

[0221] The various implementations of the systems and techniques described above herein can be realized in a digital electronic circuit system, an integrated circuit system, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), an application specific standard product (ASSP), a system on a chip system (SOC), a complex programmable logic device (CPLD), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0222] Program code for carrying out methods of the present disclosure can be written in any combination of one or more programming languages. The program code can be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the program code, when executed by the processor or controller, produces the functions / operations specified in the flowcharts and / or block diagrams. The program code can be executed entirely on a machine, partially on a machine, partially on a machine as a standalone software package, or entirely on a remote machine or server.

[0223] In the context of the present disclosure, a machine-readable medium can be a tangible medium that contains or stores a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include but is not limited to an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of the machine-readable storage medium will include one or more lines of electrical connections, portable computer disks, hard disk drives, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or Flash memory), optical fibers, portable compact disc read-only memories (CD-ROMs), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0224] To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0225] The systems and techniques described here can be implemented in a computing system that includes a back end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front end component (e.g., a user computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0226] The computer system can include clients and servers. This relationship can be. The servers are typically remote from the clients with the interactions typically taking place over a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The servers can be cloud servers, also known as cloud computing servers or cloud hosts, which are a host product in the cloud computing service system to solve the defects of large management difficulty and weak business scalability in traditional physical hosts and VPS services ("Virtual Private Server", or simply "VPS"). The servers can also be servers of a distributed system, or servers combined with a blockchain.

[0227] It should be understood that the various forms of flow shown above can be re-ordered, added to, or deleted from without departing from the scope of the present disclosure. For example, the steps recited in the present disclosure can be performed in parallel, in series, or in a different order, without departing from the desired results of the technical solutions of the present disclosure, and are not limited herein.

[0228] The above detailed description does not constitute a limitation on the protection scope of the present disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements, and improvements within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A sensor data caching method applied in a data caching system, the data caching system comprising a field programmable logic gate array and a preset target memory; the field programmable logic gate array is in communication connection with a plurality of sensors respectively; the field programmable logic gate array comprises a plurality of data caching units, and the data caching units correspond to the plurality of sensors one by one. The data cache unit comprises a preset cache area for storing data in a first-in first-out manner, comprising: acquiring the to-be-cached data collected by any preset sensor, and storing the to-be-cached data into a first cache area associated with the preset sensor in the field programmable logic gate array; in response to a preset data write condition being met, writing the to-be-cached data in the first cache area into a second cache area associated with the preset sensor in a target memory in communication connection with the field programmable logic gate array; writing the update state of the to-be-cached data into the preset cache area in a first-in first-out manner, the update state comprising the data type and operation length of a plurality of data packets corresponding to the current write operation; wherein the writing of the update state of the to-be-cached data into the preset cache area in a first-in first-out manner comprises: performing an encoding operation on the update state in a preset encoding manner to obtain encoded data, wherein the encoded data is used to indicate the data type and operation length of a plurality of data packets corresponding to the current write operation; writing the encoded data into the preset cache area in a first-in first-out manner.

2. The method of claim 1, wherein, The writing of the to-be-cached data in the first cache area into the second cache area associated with the preset sensor in the target memory in communication connection with the field programmable logic gate array in response to the preset data write condition being met comprises: in response to the to-be-cached data in the first cache area meeting a preset trigger condition, determining a first storage state, wherein the first storage state comprises the cache state associated with the first cache area and the cache state associated with the second cache area; in response to the first storage state meeting a preset condition, writing the to-be-cached data into the second cache area.

3. The method of claim 2, wherein, The writing of the to-be-cached data into the second cache area in response to the first storage state meeting a preset condition comprises: if it is determined based on the first storage state that the first cache area and the second cache area are both full and there is overflow data, discarding the to-be-cached data; if it is determined based on the first storage state that the first cache area and the second cache area are both full but there is no overflow data, returning to perform the step of determining the first storage state until there is storage space in the second cache area, and writing the to-be-cached data into the second cache area; if it is determined based on the first storage state that there is storage space in the second cache area, writing the to-be-cached data into the second cache area.

4. The method of claim 2, wherein, The determination of the first storage state in response to the to-be-cached data in the first cache area meeting a preset trigger condition comprises: determining whether the data quantity of the to-be-cached data in the first cache area reaches a preset data quantity threshold; if yes, determining the first storage state.

5. The method of claim 1, wherein, The writing of the to-be-cached data in the first cache area into the second cache area associated with the preset sensor in the target memory in communication connection with the field programmable logic gate array in response to the preset data write condition being met comprises: determining a data amount corresponding to the data to be cached, and determining a transmission parameter set by a user, wherein the transmission parameter comprises a number of bytes transmitted per clock cycle; performing a packetization operation on the data to be cached based on the data amount and the transmission parameter, to obtain a plurality of data packets to be transmitted; writing the plurality of data packets to be transmitted into the second cache area.

6. The method of claim 5, wherein, The packetization operation on the data to be cached based on the data amount and the transmission parameter, to obtain a plurality of data packets to be transmitted, comprises: obtaining valid data matching the transmission parameter from the data to be cached, and constructing the data packets to be transmitted based on the valid data; in response to a data amount of remaining valid data in the data to be cached being less than the transmission parameter, determining a byte amount difference between the remaining valid data and the transmission parameter; inserting padding codes matching the byte amount difference into the remaining data to be cached, to obtain the data packets to be transmitted.

7. The method of any one of claims 1-6, after the writing of the update status of the data to be cached into the preset cache area in the first-in-first-out manner, the method further comprises: in response to a preset data reading condition being met, determining target data to be read currently in the preset cache area in the first-in-first-out manner; reading the target data from the second cache area into a third cache area associated with the preset sensor in the field programmable logic gate array.

8. The method of claim 7, the third cache area is the same as the first cache area.

9. The method of claim 7, wherein, The determining of the target data to be read currently in the preset cache area in the first-in-first-out manner in response to the preset data reading condition being met, comprises: in response to the third cache area having a cache space, determining a second cache state, wherein the second cache state comprises a cache state associated with the second cache area and a cache state associated with the third cache area; if it is determined based on the second cache state that the third cache area has a cache space and there is cache data in the second cache area, determining the target data to be read currently in the preset cache area in the first-in-first-out manner.

10. The method of claim 7, wherein, The determining of the target data to be read currently in the preset cache area in the first-in-first-out manner, comprises: determining a plurality of data packets to be read currently in the preset cache area in the first-in-first-out manner; for each data packet, performing a decoding operation on an update status associated with the data packet in the preset cache area based on a preset decoding manner, to obtain a data type and an operation length corresponding to the data packet; determining a memory space and a memory address of the data type, the operation length corresponding to the data packet, and the transmission parameter set by the user in the second cache area; The reading of the target data from the second cache area into the third cache area associated with the preset sensor in the field programmable logic gate array, comprises: reading the target data from the second cache area into the third cache area based on the memory space and the memory address.

11. The method of claim 7, wherein, The reading of the target data from the second cache area into a third cache area associated with the preset sensor in the field programmable logic gate array comprises: unpacking the target data to obtain valid data corresponding to the target data; reading the valid data into the third cache area.

12. The method of claim 11, wherein, The unpacking of the target data to obtain valid data corresponding to the target data comprises: extracting a first data packet, a last data packet and at least one intermediate segment data packet in the target data; determining the first data packet and the at least one intermediate segment data packet as the valid data; determining whether the last data packet includes padding code; if the padding code exists, deleting the padding code and determining the remaining fields in the last data packet as the valid data.

13. The method of any one of claims 1-6, wherein the target memory comprises a double data rate synchronous dynamic random access memory.

14. The method of any one of claims 1-6, after the obtaining of the to-be-cached data collected by any one of the preset sensors, further comprising: determining a data amount corresponding to the to-be-cached data and a preset transmission parameter; configuring a cache control of the second cache area through a preset configuration interface according to the data amount and the transmission parameter.

15. A data caching system, comprising a field programmable logic gate array and a preset target memory; the field programmable logic gate array is in communication connection with a plurality of sensors respectively; The field programmable logic gate array comprises a plurality of data cache units, which are in one-to-one correspondence with a plurality of preset sensors. a plurality of data caching units are configured to obtain to-be-cached data collected by the plurality of sensors and temporarily store the to-be-cached data; a double data rate synchronous dynamic random access memory comprises a plurality of second cache areas, and the second cache areas correspond to the sensors one by one; the data caching units are configured to write the to-be-cached data sent by the sensors into the second cache area corresponding to the sensors in the target memory when a preset writing condition is met, wherein a cache control of the second cache area is dynamically configured based on a data amount of the to-be-cached data and a preset transmission parameter; the data caching units comprise a preset cache area configured to store data in a first-in-first-out manner, and the preset cache area is configured to store an update state associated with a current writing operation; the update state comprises a data type and an operation length of a plurality of data packets corresponding to the current writing operation; the data caching units are further configured to determine target data to be read in the second cache area in the preset cache area in a first-in-first-out manner when a preset reading condition is met, and read the target data into the data caching units; the preset cache area is specifically configured to encode the update state in a preset encoding manner to obtain encoded data, and store the encoded data in a first-in-first-out manner; wherein the encoded data is configured to indicate the data type and the operation length of the plurality of data packets corresponding to the current writing operation.

16. The data caching system of claim 15, wherein the data caching unit further comprises a cache writing module and a cache reading module; the cache writing module and the cache reading module are in communication connection with the preset cache area; the cache writing module is configured to cache the to-be-cached data sent by the sensor into a preset first cache area, and write the to-be-cached data into a second cache area corresponding to the sensor in the target memory when a preset writing condition is met; the cache reading module is configured to determine target data to be read in the second cache area in the preset cache area in a first-in-first-out manner when a preset reading condition is met, and read the target data into a third cache area in the cache reading module.

17. The data caching system of claim 16, wherein, the cache writing module comprises a first cache area, a packet assembling module and a writing state control module, and the packet assembling module is in communication connection with the first cache area, the writing state control module and the second cache area; the first cache area is configured to cache the to-be-cached data collected by the sensor; the writing state control module is configured to control the packet assembling module to assemble the to-be-cached data when a preset data writing condition is met, and write the assembled to-be-cached data into the second cache area.

18. The data caching system of claim 16, wherein, the cache reading module comprises a third cache area, a packet disassembling module and a reading state control module; the packet disassembling module is in communication connection with the third cache area, the reading state control module and the second cache area; the reading state control module is configured to determine target data to be read in the preset cache area in a first-in-first-out manner when a reading condition is met, and perform a reading operation on the target data from the second cache area; the packet disassembling module is configured to disassemble the target data, and read valid data in the target data into the third cache area.

19. The data caching system of any of claims 16-18, wherein, The storage space of the first cache area and the third cache area is smaller than that of the second cache area.

20. The data caching system of any of claims 16-18, wherein, The first cache area and the third cache area are unified cache areas.

21. The data caching system of any of claims 15-18, wherein, The target memory comprises a double data rate synchronous dynamic random access memory.

22. A sensor data caching apparatus applied in a data caching system, the data caching system comprising a field programmable logic gate array and a preset target memory; the field programmable logic gate array is in communication connection with a plurality of sensors respectively; the field programmable logic gate array comprises a plurality of data caching units, and the data caching units correspond to the plurality of sensors one by one; The data caching unit comprises a preset cache area for storing data in a first-in-first-out manner, comprising: an acquisition module configured to acquire to-be-cached data collected by any preset sensor, and store the to-be-cached data into a first cache area associated with the preset sensor in a field programmable gate array; a writing module configured to write the to-be-cached data in the first cache area into a second cache area associated with the preset sensor in a target memory in communication connection with the field programmable gate array in response to a preset data writing condition being met; an updating module configured to write an updating state of the to-be-cached data into the preset cache area in a first-in-first-out manner, the updating state comprising data types and operation lengths of a plurality of data packets corresponding to the writing operation; wherein the updating module comprises: an encoding unit configured to perform an encoding operation on the updating state in a preset encoding manner to obtain encoded data, wherein the encoded data is used to indicate the data types and the operation lengths of the plurality of data packets corresponding to the writing operation. An updating unit is configured to write the encoded data into the preset buffer area in a first-in first-out manner.

23. The apparatus of claim 22, wherein, The writing module comprises: A determining unit is configured to determine a first storage state in response to the to-be-buffered data in the first buffer area satisfying a preset triggering condition, wherein the first storage state comprises a buffer state associated with the first buffer area and a buffer state associated with the second buffer area. A writing unit is configured to write the to-be-buffered data into the second buffer area in response to the first storage state satisfying a preset condition.

24. The apparatus of claim 23, wherein, The writing unit comprises: A first processing sub-unit is configured to discard the to-be-buffered data if it is determined based on the first storage state that the first buffer area and the second buffer area are both full and there is overflow data. A second processing sub-unit is configured to return to the step of determining the first storage state until there is storage space in the second buffer area, and write the to-be-buffered data into the second buffer area if it is determined based on the first storage state that the first buffer area and the second buffer area are both full but there is no overflow data. A writing sub-unit is configured to write the to-be-buffered data into the second buffer area if it is determined based on the first storage state that there is storage space in the second buffer area.

25. The apparatus of claim 23, wherein, The determining unit comprises: A determining sub-unit is configured to determine whether the data amount of the to-be-buffered data in the first buffer area reaches a preset data amount threshold. The determining sub-unit is configured to determine the first storage state if the data amount of the to-be-buffered data in the first buffer area reaches the preset data amount threshold.

26. The apparatus of claim 22, wherein, The writing module comprises: A determining unit is configured to determine the data amount corresponding to the to-be-buffered data and a transmission parameter set by a user in advance, wherein the transmission parameter comprises the number of bytes transmitted per clock beat. A packetizing unit is configured to perform packetizing operation on the to-be-buffered data based on the data amount and the transmission parameter to obtain a plurality of to-be-transmitted data packets. A writing unit is configured to write the plurality of to-be-transmitted data packets into the second buffer area.

27. The apparatus of claim 26, wherein, The packetizing unit comprises: An obtaining sub-unit is configured to obtain valid data matching the transmission parameter from the to-be-buffered data, and construct the to-be-transmitted data packet based on the valid data. A determining sub-unit is configured to determine the difference in the number of bytes between the remaining valid data and the transmission parameter in response to the data amount of the remaining valid data being less than the transmission parameter. A padding sub-unit is configured to insert padding code matching the difference in the number of bytes into the remaining to-be-buffered data to obtain the to-be-transmitted data packet.

28. The apparatus according to any one of claims 22-27, further comprising: A determining module is configured to determine, in response to a preset data reading condition being satisfied, target data to be read currently in a preset buffer area based on a first-in first-out manner. A reading module is configured to read the target data from the second buffer area to a third buffer area associated with the preset sensor in the field programmable logic gate array.

29. The apparatus according to claim 28, wherein the third buffer area is the same as the first buffer area.

30. The apparatus of claim 28, wherein, The determining module comprises: The determining unit is configured to determine a second cache state in response to the third cache area having cache space, wherein the second cache state comprises a cache state associated with the second cache area and a cache state associated with the third cache area. The reading unit is configured to determine target data to be read in the preset cache area based on a first-in-first-out manner if it is determined based on the second cache state that the third cache area has cache space and there is cache data in the second cache area.

31. The apparatus of claim 28, wherein, The determining unit comprises: A determining sub-unit configured to determine a plurality of data packets to be read in the preset cache area based on the first-in-first-out manner. A decoding sub-unit configured to, for each data packet, perform decoding operation on an update state associated with the data packet in the preset cache area based on a preset decoding manner to obtain a data type and an operation length corresponding to the data packet. A mapping sub-unit configured to determine a memory space and a memory address of the data type, the operation length and a transmission parameter set by a user in the second cache area. The reading unit comprises: A reading sub-unit configured to read the target data from the second cache area to the third cache area based on the memory space and the memory address.

32. The apparatus of claim 28, wherein, The reading module comprises: An unpacking unit configured to perform unpacking operation on the target data to obtain valid data corresponding to the target data. A reading unit configured to read the valid data to the third cache area.

33. The apparatus of claim 32, wherein, The unpacking unit comprises: An extracting sub-unit configured to extract a first data packet, a last data packet and at least one intermediate data packet in the target data. A determining sub-unit configured to determine the first data packet and the at least one intermediate data packet as the valid data. An identifying sub-unit configured to, for the last data packet, determine whether padding code is included in the last data packet. A deleting sub-unit configured to, if the padding code exists, delete the padding code and determine remaining fields in the last data packet as the valid data.

34. The apparatus of any one of claims 22-27, wherein the target memory comprises a double data rate synchronous dynamic random access memory.

35. The apparatus of any one of claims 22-27, further comprising: a determining module configured to determine a data amount corresponding to the data to be cached and a preset transmission parameter; a configuring module configured to perform configuration operation on a cache control of the second cache area through a preset configuration interface according to the data amount and the transmission parameter.

36. An electronic device, comprising: at least one processor; and a memory connected to the at least one processor in communication; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-14.

37. A non-transitory computer readable storage medium having stored thereon computer instructions, wherein, The computer instructions are used to enable the computer to perform the method of any one of claims 1-14.

38. A computer program product comprising a computer program which, when executed by a processor, implements the steps of the method of any of claims 1-14.

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