Chip design method and device, equipment, storage medium and program product

Abstract

The embodiment of the invention provides a method, equipment and device for chip design, a medium and a program product, and relates to the field of chip design tools. The method includes generating a design drawing for a chip in a multi-die design environment, the chip including a first die, a second die, and a third die for coupling the first die and the second die, and the design drawing representing an arrangement of the first die, the second die, and the third die. The method further comprises: in a multi-die design environment, determining a plurality of names of a plurality of interconnected elements of the chip based on a unified naming rule, and generating element connection data using the plurality of interconnected elements according to a current path in the chip; and generating a fusion layout for the at least two dies based on the element connection data. In this manner, with the same design environment, elements, such as power supplies, signals, and 3D components, in a plurality of dies can be placed in the same development environment, thereby achieving a more intuitive, more efficient multi-die design.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to the field of chip design tools. More specifically, embodiments of the present disclosure relate to methods, devices, apparatuses, computer-readable storage media, and computer program products for chip design. Background Art

[0002] Electronic design automation (EDA) software is widely used in chip functional design, synthesis, verification, simulation and other processes. By using EDA software, the chip design process can be easily carried out, such as architecture design and register transfer level (RTL) code design, logic synthesis, design for test (DFT), physical development and signoff.

[0003] At present, as chips become more and more complex, the importance of multi-die design is becoming increasingly prominent. In multi-die design, by splitting a complex chip into multiple dies for design, each die can be manufactured separately using the adapted manufacturing process of one or more factories (fabrication, FAB) and then multiple dies can be integrated into a single package to achieve higher power consumption, performance, and area (PPA) goals. However, due to the complex interconnection relationship between the multiple dies in the chip, such as power network connection and signal connection, the difficulty of multi-die design is greatly increased compared to monolithic design. Therefore, a chip design scheme is needed to efficiently perform multi-die design. Summary of the invention

[0004] Embodiments of the present disclosure provide a solution for chip design.

[0005] In a first aspect of the present disclosure, a method for chip design is provided. The method includes generating a design drawing for a chip in a multi-die design environment, the chip including a first die, a second die, and a third die for coupling the first die and the second die, the design drawing representing the arrangement of the first die, the second die, and the third die. The method also includes: in the multi-die design environment, determining the corresponding multiple names of multiple interconnection elements in the interconnection element set of the chip, wherein the multiple names are based on a unified naming rule, and the interconnection element set includes multiple elements associated with die interconnection in the first die, the second die, and the third die. The method also includes: according to the current path in the chip, using the multiple interconnection elements to generate element connection data corresponding to the current path; and based on the element connection data, generating a fusion layout for at least two dies in the chip.

[0006] In this way, by generating a fusion layout for at least two dies using the component connection data of multiple interconnected elements with unified names in multiple dies in the same design environment, components such as power, signal, and 3D components in multiple dies can be placed in the same development environment, thereby achieving a more intuitive and efficient multi-die design. In some examples, by uniformly naming the fused devices, metals, and vias, naming conflicts between various factories can be eliminated. In some examples, by generating component connection data using interconnected elements with unified names, component interconnection relationships in a unified or standard format can be generated, so that the data of various factories can be linked, which is conducive to the joint optimization of the design and verification process.

[0007] In some embodiments of the first aspect, determining multiple names of multiple interconnection elements in the interconnection element set of the chip includes: determining the interconnection relationship between the multiple elements associated with the die interconnection based on the arrangement of the first die, the second die, and the third die; and selecting the multiple interconnection elements from the interconnection element set based on the interconnection relationship. In this way, one or more target interconnection elements can be selected from the die in the multi-die chip for generating a fusion layout. For example, a user-defined fusion depth for each die can be supported to generate a fusion layout, thereby reducing the layout volume. In addition, suitable interconnection elements in multiple dies can be selected based on the arrangement of the die to generate a fusion layout. For example, a minimum circuit that embodies the interconnection relationship between dies can be determined based on the arrangement of multiple dies, and elements in the minimum circuit are selected to generate a fusion layout, thereby reducing the layout volume.

[0008] In some embodiments of the first aspect, a first name in the plurality of names corresponding to a first element in the plurality of interconnected elements identifies the first element and the first die including the first element; a second name in the plurality of names corresponding to a second element in the plurality of interconnected elements identifies the second element and the second die including the second element, and each of the plurality of names includes at least one of a text description or a numerical number. In this way, a specific element in a specific die can be identified from the level of the element and the level of the die, so that corresponding elements from multiple dies can be uniformly processed in the same design environment.

[0009] In some embodiments of the first aspect, determining multiple names of multiple interconnection elements in the interconnection element set of the chip includes: mapping the original name of the first element associated with the first die manufacturing process to the first name; and mapping the original name of the second element associated with the second die manufacturing process to the second name. In this way, a mapping process from a single die to multiple dies can be established, so that the names associated with a specific die manufacturing process are mapped to the names based on the unified naming rule in the multi-die design environment.

[0010] In some embodiments of the first aspect, generating a fused layout for at least two dies in the chip further comprises: updating at least one of a first layout corresponding to the first die or a second layout corresponding to the second die based on the multiple names of the multiple interconnected elements and the element connection data; and generating the fused layout based on the updated at least one layout. In this way, the fused layout can be generated with reference to the layout corresponding to a single die, thereby improving the efficiency of generating the fused layout by using existing layout information.

[0011] In some embodiments of the first aspect, the method further includes: mapping a portion of the first die in the fused layout to a first verification layout corresponding to the first die, the first verification layout being associated with a first die manufacturing process; and mapping a portion of the second die in the fused layout to a second verification layout corresponding to the second die, the second verification layout being associated with a second die manufacturing process. In this way, a mapping process from multiple die to a single die can be established, so that the fused layout is mapped to multiple separate layouts for producing corresponding dies using an adapted die manufacturing process. By using the mapping process between a single die and multiple die, the association and rapid conversion between a multi-die design environment and a production and manufacturing environment of each factory can be achieved.

[0012] In some embodiments of the first aspect, the current path includes at least one of a power path or a signal path. In some embodiments of the first aspect, at least two of the first die, the second die, or the third die are associated with different die manufacturing processes. In some embodiments of the first aspect, the arrangement includes at least one of horizontal stacking or vertical stacking. In this way, the present solution can be applicable to various forms of multi-die designs and to one or more die manufacturing processes of one or more FABs.

[0013] In some embodiments of the first aspect, selecting the plurality of interconnection elements from the set of interconnection elements includes: selecting all metal layers and vias in the third die as a first portion of the plurality of interconnection elements; and selecting at least one device, metal layer or via in the first die and the second die as a second portion of the plurality of interconnection elements based on power paths and signal paths between the third die and the first die and the second die, respectively. In this way, suitable interconnection elements can be selected for generating a fusion layout in consideration of the coupling relationship between the dies.

[0014] In a second aspect of the present disclosure, a device for chip design is provided. The device includes: a layout determination unit configured to generate a design drawing for a chip in a multi-die design environment, the chip including a first die, a second die, and a third die for coupling the first die and the second die, the design drawing representing the layout of the first die, the second die, and the third die; a naming determination unit configured to determine the corresponding multiple names of multiple interconnection elements in the interconnection element set of the chip in the multi-die design environment, wherein the multiple names are based on a unified naming rule, the interconnection element set including multiple elements associated with die interconnection in the first die, the second die, and the third die; a connection determination unit configured to generate element connection data corresponding to the current path using the multiple interconnection elements according to the current path in the chip; and a layout generation unit configured to generate a fusion layout for at least two dies in the chip based on the element connection data.

[0015] In this way, by uniformly naming multiple interconnected elements in multiple dies in the same design environment and generating a fused layout for at least two dies based on the current paths in the chip, physical units such as power, signals, and 3D components in multiple dies can be placed in the same development environment, thereby achieving more intuitive and efficient multi-die design.

[0016] In some embodiments of the second aspect, the naming determination unit is further configured to: determine the interconnection relationship between the multiple elements associated with the die interconnection based on the arrangement of the first die, the second die and the third die; and select the multiple interconnection elements from the interconnection element set based on the interconnection relationship.

[0017] In some embodiments of the second aspect, a first name among the multiple names corresponding to a first element among the multiple interconnected elements identifies the first element and the first bare die including the first element; a second name among the multiple names corresponding to a second element among the multiple interconnected elements identifies the second element and the second bare die including the second element, and each name among the multiple names includes at least one of a text description or a digital number.

[0018] In some embodiments of the second aspect, the naming determination unit is configured to: map the original naming of the first element associated with the first die manufacturing process to the first naming; and map the original naming of the second element associated with the second die manufacturing process to the second naming.

[0019] In some embodiments of the second aspect, the layout generation unit is further configured to: update at least one of the first layout corresponding to the first die or the second layout corresponding to the second die based on the multiple names of the multiple interconnected elements and the element connection data; and generate the fused layout based on the updated at least one layout.

[0020] In some embodiments of the second aspect, the device also includes a mapping unit, which is configured to: map a portion of the first die in the fusion layout to a first verification layout corresponding to the first die, and the first verification layout is associated with a first die manufacturing process; and map a portion of the second die in the fusion layout to a second verification layout corresponding to the second die, and the second verification layout is associated with a second die manufacturing process.

[0021] In some embodiments of the second aspect, the current path includes at least one of a power path or a signal path. In some embodiments of the second aspect, at least two of the first die, the second die, or the third die are associated with different die manufacturing processes. In some embodiments of the second aspect, the arrangement includes at least one of horizontal stacking or vertical stacking.

[0022] In some embodiments of the second aspect, the naming determination unit is further configured to: select all metal layers and through-holes in the third die as a first part of the multiple interconnection elements; and select at least one device, metal layer or through-hole in the first die and the second die as a second part of the multiple interconnection elements based on the power path and signal path of the third die with the first die and the second die respectively.

[0023] In a third aspect of the present disclosure, an electronic device is provided, comprising: at least one computing unit; and at least one memory, wherein the at least one memory is coupled to the at least one computing unit and stores instructions for execution by the at least one computing unit, and when the instructions are executed by the at least one computing unit, the device implements the method provided in the first aspect.

[0024] In a fourth aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored, wherein the computer program is executed by a processor to implement the method provided in the first aspect.

[0025] In a fifth aspect of the present disclosure, a computer program product is provided, comprising computer executable instructions, which implement part or all of the steps of the method of the first aspect when the instructions are executed by a processor.

[0026] It can be understood that the electronic device of the third aspect, the computer storage medium of the fourth aspect, or the computer program product of the fifth aspect provided above are all used to execute the method provided in the first aspect. Therefore, the explanation or description of the first aspect is also applicable to the second aspect, the third aspect, the fourth aspect, and the fifth aspect. In addition, the beneficial effects that can be achieved in the second aspect, the third aspect, the fourth aspect, and the fifth aspect can refer to the beneficial effects in the corresponding method, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, wherein:

[0028] Figure 1 A flowchart showing the chip design and manufacturing process;

[0029] Figure 2 A flowchart showing an example process for chip design according to some embodiments of the present disclosure is shown;

[0030] Figure 3 A schematic diagram showing the interconnection relationship of multiple dies in a multi-die design environment according to some embodiments of the present disclosure;

[0031] Figure 4A schematic diagram showing example nomenclature of interconnect elements in coupled dies according to some embodiments of the present disclosure;

[0032] Figure 5 A schematic diagram showing example nomenclature of interconnect elements in a coupled die according to some embodiments of the present disclosure;

[0033] Figure 6 A schematic diagram showing example identification of multiple elements in multiple dies according to some embodiments of the present disclosure;

[0034] Figure 7 A schematic diagram showing an example connection relationship between elements according to some embodiments of the present disclosure;

[0035] Figure 8 A schematic diagram showing an example mapping file for single-die to multi-die mapping according to some embodiments of the present disclosure;

[0036] Fig. 9 A schematic diagram showing another example mapping file for mapping of single die to multiple die according to some embodiments of the present disclosure;

[0037] Fig.10 A flowchart illustrating an example process of chip design in a multi-die design environment according to some embodiments of the present disclosure;

[0038] Fig.11 A schematic block diagram showing an apparatus for chip design according to some embodiments of the present disclosure; and

[0039] Fig.12 A block diagram of a computing device capable of implementing various embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0040] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein, which are instead provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.

[0041] In the description of the embodiments of the present disclosure, the term "including" and similar terms should be understood as open inclusion, that is, "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0042] As briefly mentioned above, multi-die design involves complex interconnections between multiple dies, so the design difficulty is greatly increased compared to monolithic design. For example, in large-scale three-dimensional integrated circuit (3DIC) or 2.5D IC design, multiple dies can be stacked vertically, placed side by side, or placed vertically and horizontally. Die 1 and die 2 in the multiple dies can be produced by FAB 1 and FAB 2 respectively, and finally stacked in FAB 3. In this scenario, when the number of dies increases, when the sizes of the dies are different, and / or there are mirroring or flipping during the stacking process, the difficulty of chip design such as aligning the power supply, signal, and 3D components between the dies increases dramatically.

[0043] In some solutions, each die can be designed independently and then stitched together. However, designing each die separately is not intuitive from the system level of 3DIC and has low design efficiency. For example, traditional physical design methods cannot integrate the design elements of multiple dies to intuitively observe the alignment and placement of 3D components in multiple dies, and therefore cannot meet the design requirements of multi-die design.

[0044] In other solutions, the die and the corresponding layout can be generated in separate design environments and the layouts can be verified separately. Then, the interface part to be fused can be extracted from the layout that has passed the separate verification to form a new fusion layout for verification. The independent design environment can include independent EDA tools or independent inputs of the same EDA tool, such as the definition and connection relationship of each component in the corresponding die. For example, a layout corresponding to the first die (die 1) can be generated in design environment 1. Figure 1 And check the version Figure 1 A version corresponding to the second die (die 2) can be generated in design environment 2. Figure 2 And check the version Figure 2 Verify. Figure 1 Japanese version Figure 2 After passing the verification, you can Figure 1 Japanese version Figure 2 Adjacent interface layers are extracted separately to form a new fusion layout for verification. In this way, the design and verification of multi-die chips can be achieved.

[0045] However, the design environments in this solution are independent of each other, so the design and verification based on the layout need to be performed independently. If the connection relationship at the interface to be fused is complex, such as one driving many or many driving many, the connection relationship of the generated fused layout will be unpredictable, making verification impossible. For example, the interface part directly extracted from the layout cannot accurately reflect the logical connection relationship between the components in the interface part and other components that have not been extracted. Therefore, this solution is only applicable to scenarios with a single connection relationship at the interface.

[0046] In addition, the segmented verification method of first verifying the layout of each die separately and then verifying the fused layout is only applicable to multi-die design scenarios with a small number of dies. If the number of dies increases, the number of independent design environments required increases, and the fused layout generated from the interface between each two dies needs to be verified one by one, resulting in reduced development efficiency. Therefore, for multi-die design scenarios with complex interconnections, such as scenarios where multiple dies are stacked vertically, a complete and efficient multi-die design solution is required.

[0047] In order to at least partially solve the above problems and other potential problems, various embodiments of the present disclosure provide a solution for chip design. According to various embodiments described herein, a method for chip design is provided. The method includes: generating a design drawing for a chip in a multi-die design environment, the chip including a first die, a second die, and a third die for coupling the first die and the second die, and the design drawing represents the arrangement of the first die, the second die, and the third die. The method also includes: in the multi-die design environment, determining the corresponding multiple names of multiple interconnection elements in the interconnection element set of the chip, the multiple names are based on a unified naming rule, and the interconnection element set includes a first die, a second die, and a third die, and multiple elements associated with die interconnection. The method also includes: according to the current path in the chip, using the multiple interconnection elements to generate element connection data corresponding to the current path; and based on the element connection data, generating a fusion layout for at least two dies in the chip.

[0048] In this way, by generating a fused layout for at least two dies using component connection data of multiple interconnected components with unified names in multiple dies in the same design environment, components such as power, signals, and 3D components in multiple dies can be placed in the same development environment, thereby achieving more intuitive and efficient multi-die design.

[0049] Various exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings. Figure 1A flow chart of a chip design and manufacturing process 100 is shown. The design and manufacturing process 100 begins with specification formulation 110. At the stage of specification formulation 110, the requirements for the functions and performances that the integrated circuit needs to achieve are determined. At the stage of chip design 120, circuit design is performed with the aid of EDA software to obtain, for example, a layout file for chip manufacturing. Based on the difference in circuits (e.g., digital circuits or analog circuits), the design 120 may include different design links. At the stage of manufacturing 140, integrated circuits are formed on wafers through processes such as photolithography, etching, ion implantation, thin film deposition, and polishing. At the stage of packaging 150, the wafer is cut to obtain a bare die, and the bare die is packaged to obtain a chip through processes such as pasting, welding, and mold sealing. The resulting chip is tested at the stage of testing 160 to ensure that the performance of the finished chip meets the requirements determined in the specification formulation 110. The chip 170 that has passed the test can be delivered to the customer. It can be understood that the above process is only illustrative and does not limit the scope of the present disclosure. In some cases, the design and manufacturing process of the chip may be different. For example, tape-out may be performed before manufacturing 140. A small number of chips obtained from the tape-out may be used for testing to verify whether the chip design meets expectations. If it does not meet expectations, this indicates that the tape-out has failed and the chip design may need to be adjusted or redesigned.

[0050] In some embodiments, the design 120 of the digital circuit may exemplarily include an architecture design 121, an RTL design 123, a functional simulation 125, a synthesis 127, a timing analysis 129, a DFT 131, a verification check 133, a layout 135, a design rule check (DRC) 137, and a layout 139. The architecture design 121 includes, for example, designing the architecture of the chip. For example, EDA software may be used to determine the categories and quantities of components or subcircuits included in the chip system, as well as the functions, connections, and interactions of each component or subcircuit. In the stage of RTL design 123, a hardware programming language such as Verilog or VHDL may be used to describe the determined chip architecture in code at the RTL level. Functional simulation 125 is also referred to as RTL-level behavioral simulation or front-end simulation. The purpose of functional simulation is to analyze the correctness of the logical relationship of the design circuit. Synthesis 127 may convert RTL into a gate-level netlist. Synthesis 127 may include, for example, translation, optimization, and mapping. In one embodiment, the EDA software used for synthesis may first convert the RTL code into a general Boolean equation and compile it. The netlist may be optimized according to the constraints imposed by the designer, such as delay and area, and then the RTL netlist may be mapped to the process library to generate a gate-level netlist.

[0051] Timing analysis 129 is usually static timing analysis, which mainly involves timing calculation and prediction of digital circuits. Timing analysis is performed on the paths in the digital circuit to determine whether timing convergence is achieved, thereby ensuring whether the timing of various circuits meets various timing requirements. The verification of such digital circuits is usually completed statically and does not require simulation of digital logic. At the stage of DFT 131, various hardware logics for improving chip testability (including controllability and observability) can be embedded in the design. By using this part of logic, test vectors can be generated to achieve the purpose of testing large-scale digital circuits. DFT can, for example, include a test method based on a scan chain or a built-in self-test circuit (BIST). At the stage of verification check 133, the circuit can be formally verified and / or equivalence checked. Formal verification can use mathematical methods to prove its correctness or incorrectness based on one or more formal specifications or attributes. Formal verification can, for example, include abstract interpretation, formal model checking (also known as characteristic checking) and theorem proving. Equivalence checking can be used to verify whether the register transfer level design is consistent with the gate-level netlist, and between the gate-level netlist and the gate-level netlist.

[0052] In the stage of layout and routing 135, the chip circuit can be laid out (placement) and routed (routing). The layout can reasonably arrange the gate-level netlist generated by logic synthesis 127 in a rectangular area corresponding to the chip based on considerations such as area, critical path delay length, and power consumption. After this, the various components or sub-circuits that have been laid out can be routed to connect them. Routing generally expects the total routing to be short, the routing delay to meet the timing requirements, and to comply with the routing rules in the process (such as routing density). Although layout and routing are described separately here, this is only illustrative and does not limit the scope of the present disclosure. In some cases, layout and routing can be performed simultaneously or alternately to achieve optimization of layout and routing.

[0053] At the DRC 137 stage, the layout can be checked for potential open circuits, short circuits or adverse effects caused by violations of design rules. After passing the DRC, a file representing the layout, such as a GDSII file, can be generated 139 by the EDA software. It can be understood that the above steps are only exemplary and not intended to limit the scope of the present disclosure. In the actual design process, the above steps can be added, deleted or modified according to design needs. In addition, some of the above steps can be implemented by different EDA software or integrated in one or more EDA software. The present disclosure does not limit this.

[0054] Figure 2 A flow chart of an example process 200 for chip design according to some embodiments of the present disclosure is shown. Process 200 can be implemented by any suitable computing unit. For example, it can be performed by a computer or other electronic device with computing or circuit design capabilities. Specifically, for example, an EDA tool can be implemented by a processor of a computer according to data and / or instructions stored in a memory to perform process 200. The example process 200 for chip design will be described below.

[0055] In block 210, the processor generates a design drawing for a chip in a multi-die design environment, the chip including a first die, a second die, and a third die for coupling the first die and the second die, the design drawing representing the arrangement of the first die, the second die, and the third die. In a multi-die design, a multi-die chip may include coupled dies and coupling dies for coupling the dies. In some embodiments, multiple dies in a chip may be made by different die manufacturing processes, and different die manufacturing processes may involve different technology nodes, specific process flows of a factory, etc. For example, at least two of the first die, the second die, or the third die may be associated with different die manufacturing processes.

[0056] In some embodiments, the arrangement of multiple dies may include vertical stacking. Alternatively or additionally, the arrangement of multiple dies may include horizontal stacking. For example, the scheme of the present disclosure may be applicable to 2.5D or 3DIC scenarios. In some embodiments, the design drawing representing the arrangement of multiple dies may be an architecture diagram or a model diagram drawn by a designer based on design requirements, which may reflect the arrangement of multiple dies in a real chip product. Additionally, the design drawing may at least partially reflect the arrangement of elements inside a single die. For example, in the case where the layout of the die is already known, the designer may refer to the layout of a single die to further draw a design drawing representing the arrangement of multiple dies.

[0057] In this article, a multi-die design environment may also be referred to as a fusion design environment. The multi-die design environment may include a user interface, and a design diagram representing the arrangement of multiple dies may be provided in the user interface. Unlike conventional design environments, in a multi-die design environment according to the scheme of the present disclosure, a real arrangement form of multiple dies, such as a three-dimensional vertical stacking form, may be provided. Additionally or alternatively, in a multi-die design environment according to the scheme of the present disclosure, a layer involving multiple dies may be provided at the same time. For example, element 1 in die 1 and element 2 in die 2 may be displayed in the same layer of the design environment. Additionally or alternatively, in a multi-die design environment according to the scheme of the present disclosure, a function of optimizing based on the connection relationship of multiple dies may be provided. For example, an option may be provided in the user interface of the multi-die design environment so that a user can view the connection relationship of multiple dies to accelerate the layout and routing process. In this way, components such as power supplies, signals, and 3D components in multiple dies may be placed in the same development environment, thereby achieving a more intuitive and efficient multi-die design.

[0058] In box 220, the processor determines the corresponding multiple names of multiple interconnection elements in the interconnection element set of the chip in a multi-die design environment, wherein the multiple names are based on a unified naming rule. The interconnection element set includes multiple elements associated with the interconnection of the die in the first die, the second die, and the third die. In other words, in a multi-die design environment, multiple interconnection elements associated with the interconnection of the die are uniformly named. It should be noted that in conventional schemes, each factory usually defines the elements in the die according to their own independent naming rules. In this case, when fusing multiple dies from different factories, the problem of naming conflicts may be faced. In contrast, using the scheme of the present disclosure, the elements in each die can be uniformly named, thereby facilitating the fusion of multiple dies in a multi-die design environment and eliminating the problem of naming conflicts.

[0059] In some embodiments, a unified naming rule may specify both the naming identification element of the element and the die to which the element belongs. For example, a first naming corresponding to a first element may identify the first element and a first die including the first element, and a second naming corresponding to a second element may identify the second element and a second die including the second element. In some embodiments, each naming may include at least one of a text description or a digital number. The digital number may be indicated by a GDS code. For example, a metal layer element may be identified by a text description "M". For another example, a digital number "5,0" may be used to identify an element numbered 0 of layer 5. In this way, a specific element in a specific die may be identified from the hierarchy of the element and the hierarchy of the die, so that corresponding elements from multiple die may be uniformly processed in the same design environment.

[0060] In some embodiments, the naming of the components in the die by each factory can be mapped to the naming based on the unified naming rules in the multi-die design environment. In some embodiments, the original naming of the first component associated with the first die manufacturing process can be mapped to the first naming identifying the first component and the first die. The original naming of the second component associated with the second die manufacturing process can be mapped to the second naming identifying the second component and the second die. In this way, a mapping process from a single die to multiple dies can be established, thereby facilitating the conversion between the manufacturing process and the design environment.

[0061] In some embodiments, a target interconnection element can be selected from the interconnection element set of multiple dies of a chip for generating a fusion layout. In some embodiments, the target interconnection element may include a user-defined element of interest. Alternatively or additionally, the target interconnection element may include all elements of a specific layer related to the element of interest. Alternatively or additionally, the target interconnection element may include an element that embodies a specific circuit function. In some embodiments, interconnection elements may be selected for the corresponding fusion depth (also referred to as integration depth) of each die to generate a fusion layout. The fusion depth may be indicated by one or more layers of a manufacturing process. For example, the fusion depth may be determined based on the total number of layers of a manufacturing process.

[0062] In some embodiments, a target interconnection element can be selected based on the interconnection relationship between multiple dies for generating a fusion layout. Specifically, the interconnection relationship between multiple elements associated with die interconnection can be determined based on the arrangement of the first die, the second die, and the third die. The interconnection relationship may include at least a logical connection relationship between the elements. The interconnection relationship may be associated with at least one of a power path or a signal path. Based on the interconnection relationship, multiple interconnection elements can be selected from the interconnection element set for generating a fusion layout. For example, if it is determined that the third die is a die for coupling, all metal layers and vias in the third die can be selected as the first part of the target interconnection element. It is also possible to select at least one device, metal layer or via in the first die and the second die as the second part of the target interconnection element based on the power path and signal path of the third die with the first die and the second die respectively. Additionally or alternatively, the minimum circuit that embodies the interconnection relationship between the dies can be determined based on the arrangement of multiple dies, and the element in the minimum circuit is selected as the target interconnection element for generating a fusion layout. In this way, one or more target interconnect elements can be selected from each die in a multi-die chip to generate a fused layout, thereby reducing the layout size and improving the efficiency of chip design.

[0063] In block 230, the processor generates component connection data corresponding to the current path using multiple interconnection elements according to the current path in the chip. In some embodiments, the current path includes at least one of a power path or a signal path. In other words, the component connection data is generated based on the connection relationship between multiple interconnection elements named uniformly. The component connection data can indicate the interconnection relationship of the devices, metals and vias in the fused multiple dies in a standard format or a uniform format. In some embodiments, the component connection data can include the connection relationship between the elements represented in any suitable form, such as a netlist, a table, etc.

[0064] In block 240, the processor generates a fusion layout for at least two dies in the chip based on the component connection data. In some embodiments, the fusion layout may correspond to an interface portion between the two dies. For example, the fusion layout may correspond to an interface portion between the first die and the coupled die, or may correspond to an interface portion between the second die and the coupled die. In other embodiments, the fusion layout may correspond to a first die, a second die, and a third die coupling the first die and the second die. For example, the fusion layout may correspond to a plurality of dies that are completely stacked. In other embodiments, the fusion layout may correspond to a portion of the elements in the plurality of stacked dies.

[0065] In some embodiments, the Figure 1 The layout generation process shown generates a fusion layout in a multi-die design environment, and the process is not repeated here. In addition, the fusion layout can be generated with reference to the layout corresponding to a single die, and the process can be referred to as a single die to multi-die mapping or a single die to fusion die process. In some embodiments, in the multi-die design process, at least one of the first layout corresponding to the first die or the second layout corresponding to the second die can be updated based on a plurality of interconnected elements with unified names and the element connection data of the plurality of interconnected elements. For example, the element naming in the first layout and the second layout can be mapped to the naming based on the unified naming rules, and the element connection data can be mapped to the element connection data in a unified format. Then, based on the updated first layout and / or the second layout, a fusion layout is generated. In this way, the existing layout information can be used to improve the efficiency of generating a fusion layout.

[0066] In some embodiments, based on the generated fusion layout, the fusion layout can be mapped to multiple separate layouts for manufacturing corresponding dies by an adapted manufacturing process. This process can be referred to as mapping of multiple dies to a single die or a fusion die to single die process. In some embodiments, a portion of the first die in the fusion layout can be mapped to a first verification layout corresponding to the first die. The first verification layout can be associated with the first die manufacturing process, for example, the first die can be produced by the first factory according to the first die manufacturing process. A portion of the second die in the fusion layout can also be mapped to a second verification layout corresponding to the second die. The second verification layout can be associated with the second die manufacturing process, for example, the second die can be produced by the first factory or another factory according to the second die manufacturing process. In this way, by mapping multiple dies to a single die, rapid conversion between a multi-die design environment and the production and manufacturing environment of each factory can be achieved.

[0067] References Figure 2 An example process 200 of multi-die design according to an embodiment of the present disclosure is described. According to an embodiment of the present disclosure, a multi-die design environment, i.e., a fusion design environment, can be provided for multi-die design. In some embodiments, the whole process from architecture design to layout generation can be implemented in the fusion design environment. In the architecture design stage, the arrangement of multiple dies, the naming of components in each die, and the connection relationship between components can be determined based on the initial product planning, and then the target components to be fused are determined based on this information, and component connection data such as a netlist is generated for the target components to be fused, and then a fusion layout is generated. In this case, a separate layout corresponding to a single die may not be required, nor is a design file for a separate die, i.e., the definition and connection relationship of the components in the die.

[0068] In other embodiments, in the fusion design environment, the arrangement of multiple dies and the connection relationship between components can be determined based on the initial product planning and the design file 1 of the separate die 1 and the design file 2 of the die 2 provided. Then, the target components to be fused can be determined based on this information, the target components in the design file 1 and the design file 2 can be renamed based on the unified naming rules, and component connection data such as a netlist can be generated for the target components to be fused, and then a fusion layout can be generated. In this case, the component naming and connection relationship in the original design file can be used to generate the fusion layout.

[0069] In other embodiments, in the fusion design environment, the product initial planning and the provided design files 1 and version Figure 1 and design files 2 and version Figure 2, determine the layout of multiple dies and the connection relationship between components. Then, based on this information, the target components to be merged can be determined, the target components in design files 1 and 2 can be renamed based on the unified naming rules, a netlist can be generated for the target components to be merged, and then a fusion layout can be generated (refer to the layout Figure 1 Japanese version Figure 2 In this case, the component naming and connection relationship and layout information in the original design file can be used.

[0070] It should be understood that the multi-die design environment provided by the scheme of the present disclosure can be applicable to various application scenarios. Using the scheme of the present disclosure, by using the component connection data of multiple interconnected elements with unified names in multiple dies in the same design environment to generate a fusion layout for at least two dies, components such as power, signals, and 3D components in multiple dies can be placed in the same development environment, thereby achieving a more intuitive and efficient multi-die design. In some examples, by uniformly naming the fused devices, metals, and through-holes, naming conflicts between various factories can be eliminated. In some examples, by generating component connection data using interconnected elements with unified names, a unified or standard format of component interconnection relationships can be generated, so that the data of each factory can be linked, which is conducive to the joint optimization of the design and verification process.

[0071] Figure 3 A schematic diagram of the interconnection relationship of multiple bare chips in a multi-bare chip design environment according to some embodiments of the present disclosure is shown. As shown in schematic diagram 310, a design diagram representing the vertical stacking of multiple bare chips can be provided in a multi-bare chip design environment. The design diagram can be determined by modeling according to the connection relationship between power and signal in the actual stacking form of the chip. For example, the models of each die can be imported into the EDA design tool in sequence according to the actual product form. The perspective of the multi-bare chip design environment can be consistent with the perspective after the stacking of multiple bare chips. As shown in schematic diagram 310, the bare chips of the first factory FAB1 and the second factory FAB2 are stacked vertically after production is completed, and the bonding can be completed by the third factory FAB3. After the stacking of multiple bare chips is completed, the interconnection relationship between the multiple bare chips can be reflected by the power path and the signal path during the operation of the device, as shown in schematic diagram 320. A complete circuit is formed by the flow of current between multiple bare chips.

[0072] In some embodiments, the integration depth of a single die can be selected, and then all or part of the layers of each die can be placed in a unified multi-die design environment. Referring to schematic diagram 330, the minimum circuit that reflects the interconnection relationship between the dies can be extracted for fusion design. For example, for the 3DIC elements of the die (e.g., CHIP1) from FAB1 and the die (e.g., CHIP2) from FAB2, all or part of the devices, metal layers, and through holes can be placed in a fusion design environment according to the minimum data requirements of the power path and signal path when the chips are actually working after stacking. For the 3DIC elements of the die (e.g., CHIP12 and CHIP23) from FAB3, all metal layers and through holes can be placed in a fusion environment.

[0073] In some embodiments, multiple dies in a multi-die design environment may be individually identified. Each die may be numbered in sequence according to the stacking order, and an identification name may be assigned to each die in sequence. For example, Figure 3 As shown in the schematic diagram 340 , CHIP1 is identified as C1 , CHIP12 is identified as C12 , CHIP2 is identified as C2 , CHIP23 is identified as C23 , and CHIP3 is identified as C34 .

[0074] Figure 4 Schematic diagram showing example nomenclature of interconnect elements in coupled dies according to some embodiments of the present disclosure. Figure 4A naming schematic diagram 410 for interconnection elements in coupled die C1, a naming schematic diagram 420 for interconnection elements in coupled die C2, and a naming schematic diagram 430 for interconnection elements in coupled die C3 are shown. As shown in the naming schematic diagram 410, the original naming of the elements in die C1 (including the text description represented by FAB1_NAME and the digital number represented by FAB1_LAYER_NUMBER) can be mapped to the naming based on the unified naming rule (including the text description represented by NEW_NAME and the digital number represented by NEW_LAYER_NUM). Similarly, as shown in the naming schematic diagram 420, the original naming of the elements in die C2 (including the text description represented by FAB2_NAME and the digital number represented by FAB2_LAYER_NUMBER) can be mapped to the naming based on the unified naming rule (including the text description represented by NEW_NAME and the digital number represented by NEW_LAYER_NUM). As shown in the naming diagram 430 , the original naming of the components in die C3 (including the text description represented by FAB2_NAME and the numerical number represented by FAB2_LAYER_NUMBER) can be mapped to the naming based on the unified naming rule (including the text description represented by NEW_NAME and the numerical number represented by NEW_LAYER_NUM).

[0075] Figure 5 A schematic diagram showing example nomenclature of interconnect elements in a coupled die according to some embodiments of the present disclosure. Figure 5 A naming diagram 500 for interconnected elements in coupled die C12 and coupled die C23 is shown. As shown in the naming diagram 500, the original naming of elements in dies C12 and C23 (including text descriptions represented by FAB3_NAME and digital numbers represented by FAB3_LAYER_NUMBER) can be mapped to naming based on a unified naming rule (including text descriptions represented by New_NAME and digital numbers represented by New_LAYER_NUM).

[0076] Figure 6 A schematic diagram of example identification of multiple components in multiple dies according to some embodiments of the present disclosure is shown. As shown in schematic diagram 600, multiple discrete dies can be integrated together and multiple components in multiple dies can be uniformly colored to identify each component. As shown in schematic diagram 600, separate components in separate dies (identified by the value of the CHIP_ID column) can be named (identified by the value of the NAME column) and colored (identified by the value of the COLOR column). Reference Figure 4 , Figure 5 and Figure 6,After unified naming, each component in each die can be identified at the die level and the ,component level, and naming conflicts can be avoided.

[0077] Figure 7 A schematic diagram of an example connection relationship 700 between elements according to some embodiments of the present disclosure is shown. In some embodiments, a new connection relationship can be given to interconnected elements that have been uniformly named. For example, in the physical design stage of a 3DIC chip, for elements that have been uniformly named in a fusion design environment, the connection relationship between elements can be established by analyzing the power path and the signal path. Additionally or alternatively, the connection relationship between elements that conform to the uniform naming rules can be determined by modifying the previously determined connection relationship. The example connection relationship 700 can be represented by the arrows in the table. Figure 7 As shown, the component C1_M3 in the die C1 can be connected to the component C12_TSV in the die CXX. The component C12_TSV in the die C12 can be connected to the component C23_Mb in the die C23 through C12_Ma, C12_VIAa, C12_Mb, C33_TSV, C23_Ma, C23_VIAa. The component C12_Mb in the die C12 can be connected to the component C2_M3 in the die C2 through C12_VIAb. The component C23_Mb in the die C23 can be connected to the component C2_M1 in the die C2 through C23_VIAb, C3_M3.

[0078] Figure 8 A schematic diagram of an example mapping file 800 for single-die to multi-die mapping according to some embodiments of the present disclosure is shown. Fig. 9 A schematic diagram of another example mapping file 900 for mapping a single die to multiple dies according to some embodiments of the present disclosure is shown. As described above, a process of converting a single die to a fused die and a process of converting a fused die to a single die can be established. In some embodiments, in the process of converting a single die to a fused die, a mapping file from a single die to multiple dies can be used to convert the layer numbers of each die to the layer numbers in the fused design environment, and then a fused layout is generated based on the uniformly named components. In the process of converting a fused die to a single die, the fused die can be split according to the requirements of each factory, and then the mapping file can be used to convert the layer numbers in the fused design environment to the layer numbers applicable to the factory.

[0079] like Figure 8 and Fig. 9As shown, mapping files 800 and 900 can be represented by a table. Mapping file 800 can be applicable to coupled dies. In mapping file 800, the original layer number (identified by the value of the FAB1_NUM column and the FAB2_NUM column) of each die (identified by the value of the CHIP_ID column) can be associated with the corresponding layer number (identified by the value of the NEW_NUM column) in the fusion design environment for conversion between the layer number of each die and the layer number in the fusion design environment. Figure 8 The mapping file 800 in the example, the mapping file 900 may be applicable to a coupled die, for example Figure 3 In the mapping file 900, the original layer number (identified by the value of the FAB3_NUM column) of each die (identified by the value of the CHIP_ID column) can be associated with the corresponding layer number (identified by the value of the New_NUM column) in the fusion design environment for conversion between the layer number of each die and the layer number in the fusion design environment.

[0080] Fig.10 FIG. 1 is a flowchart showing an example process 1000 of chip design in a multi-die design environment according to some embodiments of the present disclosure. Process 1000 may be considered as a specific example of process 200. Fig.10 As shown, according to an embodiment of the present disclosure, a fusion design environment, i.e., a multi-die design environment, may be established at block 1010. Establishing the fusion design environment may include analyzing the interconnection relationship between dies (i.e., the interconnection relationship between the dies) at block 1012, selecting a single die integration depth at block 1014, assigning a new name to the component that complies with the unified naming rule at block 1016, and assigning a new connection relationship to the renamed component at block 1018.

[0081] At block 1020, a fusion layout may be generated in the fusion design environment. At block 1030, the generated fusion layout may be verified. If it is determined that the verification is passed, process 1000 may end. If it is determined that the verification fails, process 1000 may continue to iterate, adjusting the chip design in the fusion design environment and regenerating the fusion layout. In addition, as described above, a fusion die to single die flow may be established at block 1040, and a single die to fusion die flow may be established at block 1050 to achieve conversion between the fusion design environment and the production manufacturing environment of the factory.

[0082] References Figures 1 to 10The principles and details of the scheme for chip design according to the embodiment of the present disclosure are described. It should be understood that the above processes 200 and 1000 are only exemplary and do not constitute a limitation on the scope of the present disclosure. The scheme of the present disclosure can be applied in a multi-die design scenario to realize the whole process of chip design, verification, and manufacturing in the same design environment. The scheme of the present disclosure proposes a fusion physical design method, by redefining multiple dies and their connection layers in the same design environment, so as to place the physical units such as power supply, signal, 3D components in each die into the same set of development environment. In addition, the scheme of the present disclosure supports data conversion between the fusion design environment and a single die. Using the scheme of the present disclosure, the design requirements of multi-die chips can be solved, the verification accuracy and efficiency can be improved, and the factory manufacturing requirements can be met. In some embodiments, the present solution can be applicable to 3DIC or 2.5D chip design, can be applicable to vertical or horizontal stacking scenarios of chips, and can be applicable to the interconnection of multiple dies of the same FAB or the interconnection of multiple dies of multiple FABs.

[0083] Example devices and equipment

[0084] Fig.11 1 shows a block diagram of an apparatus 1100 for chip design according to an embodiment of the present disclosure. Specifically, the apparatus 1100 may be an EDA software apparatus. The apparatus 1100 may include multiple modules for executing the following steps: Figure 2 and Fig.10 The corresponding steps in the process discussed. Fig.10 As shown, the device 1100 includes: a layout determination unit 1110, which is configured to generate a design drawing for a chip in a multi-die design environment, wherein the chip includes a first die, a second die, and a third die for coupling the first die and the second die, and the design drawing represents the layout of the first die, the second die, and the third die. The device 1100 also includes a naming determination unit 1120, which is configured to determine a plurality of corresponding names of a plurality of interconnection elements in an interconnection element set of the chip in the multi-die design environment, wherein the plurality of names are based on a unified naming rule, and the interconnection element set includes a plurality of elements associated with die interconnection in the first die, the second die, and the third die. The device 1100 also includes a connection determination unit 1130, which is configured to generate element connection data corresponding to the current path using the plurality of interconnection elements according to the current path in the chip. The device 1100 also includes a layout generation unit 1140, which is configured to generate a fusion layout for at least two dies in the chip based on the element connection data.

[0085] In this way, by uniformly naming multiple interconnected elements in multiple dies in the same design environment and generating a fused layout for at least two dies based on the current paths in the chip, physical units such as power, signals, and 3D components in multiple dies can be placed in the same development environment, thereby achieving more intuitive and efficient multi-die design.

[0086] In some embodiments, the naming determination unit 1120 is further configured to: determine the interconnection relationship between the multiple elements associated with the die interconnection based on the arrangement of the first die, the second die and the third die; and select the multiple interconnection elements from the interconnection element set based on the interconnection relationship.

[0087] In some embodiments, a first name among the multiple names corresponding to a first element among the multiple interconnected elements identifies the first element and the first bare die including the first element; a second name among the multiple names corresponding to a second element among the multiple interconnected elements identifies the second element and the second bare die including the second element, and each name among the multiple names includes at least one of a text description or a digital number.

[0088] In some embodiments, the naming determination unit 1120 is configured to: map the original naming of the first element associated with the first die manufacturing process to the first naming; and map the original naming of the second element associated with the second die manufacturing process to the second naming.

[0089] In some embodiments, the layout generation unit 1140 is also configured to: update at least one of the first layout corresponding to the first die or the second layout corresponding to the second die based on the multiple names of the multiple interconnected elements and the element connection data; and generate the fused layout based on the updated at least one layout.

[0090] In some embodiments, the device 1100 also includes a mapping unit, which is configured to: map a portion of the first die in the fusion layout to a first verification layout corresponding to the first die, and the first verification layout is associated with a first die manufacturing process; and map a portion of the second die in the fusion layout to a second verification layout corresponding to the second die, and the second verification layout is associated with a second die manufacturing process.

[0091] In some embodiments, the current path includes at least one of a power path and a signal path. In some embodiments, at least two of the first die, the second die, or the third die are associated with different die manufacturing processes. In some embodiments, the arrangement includes at least one of horizontal stacking and vertical stacking.

[0092] In some embodiments, the naming determination unit 1120 is further configured to: select all metal layers and vias in the third die as a first part of the multiple interconnection elements; and select at least one device, metal layer or via in the first die and the second die as a second part of the multiple interconnection elements based on the power path and signal path of the third die with the first die and the second die respectively.

[0093] Fig.12 A schematic block diagram of an example device 1200 that can be used to implement an embodiment of the present disclosure is shown. As shown, the device 1200 includes a computing unit 1201, which can perform various appropriate actions and processes according to computer program instructions stored in a random access memory (RAM) 1203 and / or a read-only memory (ROM) 1202 or computer program instructions loaded from a storage unit 1208 into the RAM 1203 and / or ROM 1202. In the RAM 1203 and / or ROM 1202, various programs and data required for the operation of the device 1200 can also be stored. The computing unit 1201 and the RAM 1203 and / or ROM 1202 are connected to each other via a bus 1204. An input / output (I / O) interface 1205 is also connected to the bus 1204.

[0094] A number of components in the device 1200 are connected to the I / O interface 1205, including: an input unit 1206, such as a keyboard, a mouse, etc.; an output unit 1207, such as various types of displays, speakers, etc.; a storage unit 1208, such as a disk, an optical disk, etc.; and a communication unit 1209, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 1209 allows the device 1200 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0095] The computing unit 1201 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 1201 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 1201 performs the various methods and processes described above, such as processes 200 and 1000. For example, in some embodiments, processes 200 and 1000 may be implemented as computer software programs, specifically EDA programs, which are tangibly contained in machine-readable media, such as storage unit 1208. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 1200 via RAM and / or ROM and / or communication unit 1209. When the computer program is loaded into RAM and / or ROM and executed by the computing unit 1201, one or more steps of the processes 200 and 1000 described above may be performed. Alternatively, in other embodiments, the computing unit 1201 may be configured to perform processes 200 and 1000 in any other suitable manner (eg, by means of firmware).

[0096] In the above embodiments, the method flow can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a server or terminal, the process or function described in the embodiment of the present application is generated in whole or in part. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a server or terminal or a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (such as a floppy disk, a hard disk and a tape, etc.), an optical medium (such as a digital video disk (digital video disk, DVD), etc.), or a semiconductor medium (such as a solid-state hard disk, etc.).

[0097] In addition, although each operation is described in a specific order, this should be understood as requiring such operation to be performed in the specific order shown or in a sequential order, or requiring that all illustrated operations should be performed to obtain desired results. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although some specific implementation details are included in the above discussion, these should not be interpreted as limiting the scope of the present disclosure. Some features described in the context of a separate embodiment can also be implemented in a single implementation in combination. On the contrary, the various features described in the context of a single implementation can also be implemented in multiple implementations individually or in any suitable sub-combination mode.

[0098] Although the subject matter has been described in language specific to structural features and / or methodological logical actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. On the contrary, the specific features and actions described above are merely example forms of implementing the claims.

Claims

1. A method for chip design, characterized in that: include: generating a design drawing for a chip in a multi-die design environment, the chip comprising a first die, a second die, and a third die for coupling the first die and the second die, the design drawing representing an arrangement of the first die, the second die, and the third die; In the multi-die design environment, determining a corresponding plurality of names for a plurality of interconnection elements in an interconnection element set of the chip, wherein the plurality of names are based on a unified naming rule, the interconnection element set comprising a plurality of elements associated with die interconnection in the first die, the second die, and the third die; generating, according to the current path in the chip, element connection data corresponding to the current path using the plurality of interconnection elements; as well as Based on the component connection data, a fused layout for at least two dies in the chip is generated.

2. The method according to claim 1, characterized in that Determining multiple names of multiple interconnection elements in the interconnection element set of the chip includes: determining an interconnection relationship between the plurality of elements associated with the die interconnect based on the arrangement of the first die, the second die, and the third die; and Based on the interconnection relationship, the plurality of interconnection elements are selected from the set of interconnection elements.

3. The method according to any one of claims 1 to 2, characterized in that A first nomenclature of the plurality of nomenclatures corresponding to a first element of the plurality of interconnect elements identifies the first element and the first die including the first element; A second name in the plurality of names corresponding to a second element in the plurality of interconnected elements identifies the second element and a second die including the second element, and Each of the multiple names includes at least one of a text description or a digital number.

4. The method according to claim 3, characterized in that Determining multiple names of multiple interconnection elements in the interconnection element set of the chip includes: mapping an original nomenclature of the first element associated with a first die manufacturing process to the first nomenclature; and An original nomenclature of the second element associated with a second die manufacturing process is mapped to the second nomenclature.

5. The method according to any one of claims 1 to 4, characterized in that Generating a fused layout for at least two dies in the chip further includes: Based on the plurality of names of the plurality of interconnected elements and the element connection data, updating at least one of a first layout corresponding to the first die or a second layout corresponding to the second die; and The fused layout is generated based on the updated at least one layout.

6. The method according to any one of claims 1 to 5, characterized in that The method further comprises: mapping a portion of the first die in the fused layout to a first verification layout corresponding to the first die, the first verification layout being associated with a first die manufacturing process; and A portion of the second die in the fused layout is mapped to a second verification layout corresponding to the second die, the second verification layout being associated with a second die manufacturing process.

7. The method according to any one of claims 1 to 6, characterized in that The current path includes at least one of a power path and a signal path.

8. The method according to any one of claims 1 to 7, characterized in that At least two of the first die, the second die, or the third die are associated with different die manufacturing processes.

9. A device for chip design, characterized in that: include: an arrangement determining unit configured to generate a design drawing for a chip in a multi-die design environment, the chip comprising a first die, a second die, and a third die for coupling the first die and the second die, the design drawing representing an arrangement of the first die, the second die, and the third die; a naming determination unit configured to determine, in the multi-die design environment, a plurality of corresponding names of a plurality of interconnection elements in an interconnection element set of the chip, wherein the plurality of names are based on a unified naming rule, the interconnection element set comprising a plurality of elements associated with die interconnection in the first die, the second die, and the third die; a connection determination unit configured to generate element connection data corresponding to the current path using the plurality of interconnection elements according to the current path in the chip; as well as The layout generation unit is configured to generate a fusion layout for at least two dies in the chip based on the component connection data.

10. The device according to claim 9, characterized in that The naming determination unit is further configured to: determining an interconnection relationship between the plurality of elements associated with the die interconnect based on the arrangement of the first die, the second die, and the third die; as well as Based on the interconnection relationship, the plurality of interconnection elements are selected from the set of interconnection elements.

11. The device according to any one of claims 9 to 10, characterized in that A first nomenclature of the plurality of nomenclatures corresponding to a first element of the plurality of interconnect elements identifies the first element and the first die including the first element; A second name in the plurality of names corresponding to a second element in the plurality of interconnected elements identifies the second element and a second die including the second element, and Each of the multiple names includes at least one of a text description or a digital number.

12. The device according to claim 11, characterized in that The naming determination unit is configured to: mapping an original nomenclature of the first element associated with a first die manufacturing process to the first nomenclature; and An original nomenclature of the second element associated with a second die manufacturing process is mapped to the second nomenclature.

13. The device according to any one of claims 9 to 12, characterized in that The layout generation unit is further configured to: updating at least one of a first layout corresponding to the first die or a second layout corresponding to the second die based on the plurality of names of the plurality of interconnected elements and the element connection data; as well as The fused layout is generated based on the updated at least one layout.

14. The device according to any one of claims 9 to 13, characterized in that The apparatus further comprises a mapping unit, wherein the mapping unit is configured to: Mapping a portion of the first die in the fused layout to a first verification layout corresponding to the first die, the first verification layout being associated with a first die manufacturing process; as well as A portion of the second die in the fused layout is mapped to a second verification layout corresponding to the second die, the second verification layout being associated with a second die manufacturing process.

15. The device according to any one of claims 9 to 14, characterized in that The current path includes at least one of a power path and a signal path.

16. The device according to any one of claims 9 to 15, characterized in that At least two of the first die, the second die, or the third die are associated with different die manufacturing processes.

17. An electronic device comprising: at least one computing unit; At least one memory, the at least one memory is coupled to the at least one computing unit and stores instructions for execution by the at least one computing unit, the instructions, when executed by the at least one computing unit, causing the electronic device to perform the method according to any one of claims 1-8.

18. A computer-readable storage medium having a computer program stored thereon, wherein the program, when executed by a processor, implements the method according to any one of claims 1 to 8.

19. A computer program product comprising computer executable instructions, wherein the computer executable instructions, when executed by a processor, implement the method according to any one of claims 1 to 8.

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