A method for automatically placing capacitors in electronic design software

Abstract

The present invention relates to the field of electronic design automation technology, and specifically discloses a method for automatically placing capacitors in an electronic design software, including: placing a chip in a board of an EDA software, and performing fanout processing on each non-Dummy pin of the chip; inputting the refdes of the chips that need to automatically place capacitors in the user interface of an automation tool, and separating multiple refdes with ","; the system automatically calls and executes relevant EDA programs; searching for the chips in the board according to the input refdes, and reporting an error if not found; if the chips are found, determining whether all non-Dummy pins of the chips have been fanout, and reporting an error if there are pins that have not been fanout. The present invention saves the time required for manually placing capacitors, improves the work efficiency of electronic design, and reduces the design cost.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic design automation (EDA), and particularly to a method for automatically placing capacitors in an electronic design software. Background Art

[0002] In the field of electronic design, connecting decoupling capacitors to the power pins of a chip is a key step to ensure the stable operation of the circuit. With the continuous increase in the complexity of electronic circuits, the number of decoupling capacitors required by the chip is increasing day by day. During the circuit board design process, manually placing these capacitors has become an extremely cumbersome and time-consuming task. In some complex designs, it even takes more than a whole day to complete the capacitor placement, greatly reducing the design efficiency and increasing the design cost.

[0003] Currently, although most EDA design software is equipped with secondary development tools, and some design automation functions can be achieved using their built-in languages, when dealing with complex design tasks, relying solely on the built-in language for development is restricted by the EDA software itself and is prone to running jams. This makes it an urgent problem to develop an efficient and stable automatic capacitor placement tool. So far, there is no customized tool that can achieve the function of automatic capacitor placement. The present invention aims to fill this gap and provide an efficient solution for electronic design work. Summary of the Invention

[0004] The purpose of the present invention is to provide a method for automatically placing capacitors in an electronic design software, and solve the following technical problems:

[0005] The low efficiency of manually placing capacitors and the problem of jams when developing complex applications using the built-in language of EDA software are solved, and the automatic placement of capacitors in the electronic design software is realized quickly and accurately, improving the efficiency of electronic design work.

[0006] The purpose of the present invention can be achieved by the following technical solutions:

[0007] A method for automatically placing capacitors in an electronic design software includes the following steps:

[0008] Preparation step: Place the chip on the board of the EDA software, and perform fanout processing on each non-Dummy pin of the chip;

[0009] Input chip identification step: Input the chip refdes for which automatic capacitor placement is required in the user interface of the automation tool, and separate multiple refdes with ",";

[0010] EDA program execution step: The system automatically calls and executes relevant EDA programs;

[0011] Chip Search and Status Judgment Steps: Search for the chip in the board according to the input refdes. If not found, report an error. If the chip is found, judge whether all non-Dummy pins of the chip have been fanout. If there are pins that have not been fanout, report an error.

[0012] As a further solution of the present invention: It further includes an information extraction step, and the information extraction step includes:

[0013] Power Nets Search Sub-step: Search for the pin information belonging to power according to the attributes of the chip pins and store it in a temporary list;

[0014] Power_cap_net.txt File Output Sub-step: Traverse the temporary list, search for the capacitors connected to the powernet, and output the Power_cap_net.txt file containing the information of IC_name, Power_net, Cap_name, Cap_power_pin_number, and Cap_size;

[0015] ic_information.txt File Output Sub-step: Search for the shape of the specified chip in the EDA software packagegeometryclass to obtain the chip package size, export the information of IC_neme, Via_net_name, Via_location, and Via_size of all vias within the chip package area, and output it as the ic_information.txt file.

[0016] As a further solution of the present invention: The capacitor parameter calculation step includes:

[0017] Capacitor Size Calculation Sub-step: According to the Via_location and Via_size information in the ic_information.txt file, simulate the via positions and sizes, calculate the distances between vias and count them into a distance array, and determine the available capacitor sizes based on the distance array;

[0018] Capacitor Quantity Calculation Sub-step: Count the cap quantities of different powernets according to the Power_cap_net.txt, denoted as Q_cap; Combine the Power_cap_net.txt and ic_information.txt to count the via quantities and position information of the powernet, search whether the adjacent vianet is GND, and define the vias in pairs as Gp_via; If Q_cap ≤ Gp_via, the calculated quantity is the actual cap quantity; If Q_cap > Gp_via, offset the caps to increase the cap quantity.

[0019] As a further solution of the present invention: It further includes the step of generating a clip file: According to the calculated capacitance size and quantity information, generate a clip file that can be imported into EDA software. The clip file defines the origin coordinate of the board as the location of the via in the upper left corner of the chip. Place capacitors of appropriate size in the via area inside the chip, and place the remaining capacitors evenly around the chip according to the power position, and arrange the spacing between caps according to different sizes.

[0020] As a further solution of the present invention: It further includes the step of wire connection: Import the clip file into the board. Generate flying wires between the power and ground pins of the cap and the pins of the adjacent same net. Use commands to call the wire routing mode and connect the flying wire coordinate points with cline.

[0021] As a further solution of the present invention: In the step of executing the EDA program, the main program is embedded in the EDA software and starts to execute after opening the board that needs to automatically place capacitors, without the need to additionally open a specified board.

[0022] As a further solution of the present invention: In the sub-step of calculating the capacitance size, when simulating the position and size of the via, it is actually achieved by building a two-dimensional array instead of constructing an actual model.

[0023] As a further solution of the present invention: When performing offset placement of the cap, assume that the power via coordinate is (x, y), the via spacing is D, and the offset position coordinate is (x - D / 2, y - D / 2).

[0024] As a further solution of the present invention: In the step of generating the clip file, usually, the capacitance size placed around the chip is slightly larger than the capacitance size placed in the via area inside the chip.

[0025] Advantages of the present invention: By combining the built-in development language of EDA with external development tools (such as Python), the present invention gives full play to the advantages of both, avoiding the lag phenomenon when only using the built-in language of EDA to develop complex applications. This automatic capacitor placement method can quickly and accurately complete the capacitor placement work, greatly saving the time required for manual capacitor placement, improving the work efficiency of electronic design, and reducing the design cost. At the same time, this method has good versatility and can be applied to a variety of EDA software, providing an efficient and convenient design means for the electronic design industry. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The following further describes the present invention with reference to the accompanying drawings.

[0027] Figure 1 It is a schematic flow chart of inputting chip information before executing the EDA program in the present invention;

[0028] Figure 2 It is a schematic flow chart of executing the EDA program in the present invention;

[0029] Figure 3 It is a schematic flow chart of capacitance calculation after executing the EDA program in the present invention;

[0030] Figure 4 It is a schematic diagram of the via position and size in the present invention;

[0031] Figure 5 It is a schematic diagram of the final placement of capacitors in the present invention. Detailed implementation manners

[0032] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present invention.

[0033] The present invention is a method for automatically pasting capacitors in an electronic design software, including the following steps:

[0034] Preparation work: Before starting the operation, the designer needs to place the chip in the board of the EDA software and perform fanout processing on each non-Dummy (virtual or empty) pin.

[0035] Input chip information: As Figure 1 shown, in the user interface, input the chip refdes (Reference Designator, the reference identifier, which is also the unique name of the device defined in the figure) that needs to automatically paste capacitors. One or more can be input, and multiple refdes are separated by ",", such as U1, U2, U3.

[0036] Execute the EDA program: As Figure 2 shown, when the refdes input is completed, the system automatically calls and executes the relevant EDA program. Since the main program is embedded in the EDA software, it starts to execute after opening the board that needs to automatically paste capacitors, and there is no need to open a specified board additionally.

[0037] Select the chip and check the status: According to the refdes input by the user, search for the corresponding chip on the board. If the chip is not found, pop up an error window to prompt "Chip not found on the board"; if the chip is found, further check whether all non-Dummy pins of the chip have completed fanout. If there are pins that have not been fanout, pop up an error window, such as "Pin A1 of chip U1 has not been fanout".

[0038] Extract chip and capacitor information: When the chip status is normal, extract chip and capacitor information.

[0039] Search for Power Nets: According to the different attributes of the chip pins, judge the type of signal pins, search for the information related to the pins belonging to power, and store it in a temporary list.

[0040] Output the Power_cap_net.txt file: Use foreach to traverse the temporary list containing power net, search for the capacitors connected to it, and the output Power_cap_net.txt file is as follows:

[0041] IC_neme;Power_net;Cap_name;Cap_power_pin_number; Cap_size;

[0042] U1; VDD_I; C1; 1; 0402;

[0043] U1; VDD_I; C2; 1; 0402;

[0044] U1; VDD_I; C3; 1; 0402;

[0045] U1; VDD_I; C4; 1; 0402;

[0046] U1; VDD_I; C5; 1; 0402;

[0047] U1; VDD I; C6; 1; 0402;

[0048] U1; VDD_II; C7; 1; 0402;

[0049] U1; VDD II; C8; 1; 0402;

[0050] U1; VDD_II; C9; 1; 0402;

[0051] U1; VDD_II; C10; 1; 0402;

[0052] U1; VDD_II; C11; 1; 0402;

[0053] Contains information such as IC_name (Integrated Circuit Name), Power_net (Power Network), Cap_name (Capacitor Name), Cap_power_pin_number (capacitor power pin number), Cap_size (Capacitor Size), etc.;

[0054] foreach is a loop structure used in programming to iterate over elements in a collection or array. Its main purpose is to simplify the operation of iterating over iterable objects, making the code more concise and readable. The specific implementation and syntax of foreach vary in different programming languages.

[0055] Output the ic_information.txt file: Since the capacitor is attached to the back of the chip, only the via (via, a hole used to achieve electrical connection between different layers in a multi-layer printed circuit board (PCB)) information of the pin fan-out needs to be considered. Obtain the chip package size by looking up the shape (package style) of the specified chip in the EDA software packagegeometryclass, and then export the basic information of all vias within the chip package area, including IC_name, Via_net_name (Via Network Name), Via_location (Via Location), and Via_size, and output it as the ic_information.txt file as follows:

[0056] IC_neme;Via_net_name;Via_location; Via_size;

[0057] U1; GND; (-42.0000 134.2244); 012PO20RND;

[0058] U1;TGO_A_DSEL6;(-41.0000 134.2244); 012PO20RND;

[0059] U1;TGO_A_I021;(-40.0000 134.2244); 012P020RND;

[0060] U1; TGO_A_IO5; (-39.0000 134.2244); 012PO20RND;

[0061] U1; TGO_A_IO23; (-38.0000 134.2244); 012PO20RND;

[0062] U1; GND; (-37.0000 134.2244); 012PO2ORND;

[0063] U1; TGO_A_IO25; (-36.0000 134.2244); 012PO20RND;

[0064] U1; TGO_Al09; (-35.0000 134.2244); 012PO2ORND;

[0065] As Figure 3 shown, calculate the capacitance size and quantity:

[0066] Calculate the capacitance size: According to the Via_location and Via_size in the ic_information.txt file, simulate the via position and size schematic diagram as Figure 4 shown (only a two-dimensional array actually needs to be built);

[0067] According to the summarized coordinate array, from left to right and top to bottom, the distance between each via can be calculated. Count according to different distances and summarize them into another distance array. For example, there are 1400 vias with a distance of 1mm between vias, 200 vias with a distance of 2mm between vias, and 30 vias with a distance of 3mm between vias;

[0068] According to the above distance array, we can calculate the capacitance size information that can be placed.

[0069] Distance ≤ 0.6mm: 0201;

[0070] 0.6mm < Distance ≤ 1mm: 0201, 0402;

[0071] 1mm < Distance ≤ 1.6mm: 0402, 0603;

[0072] 1.6mm < Distance ≤ 2mm: 0402, 0603, 0805;

[0073] Generally, the size of capacitors within the chip should not be too large. Try not to select capacitors larger than the 0805 size. For areas where the distance exceeds 2 mm, also try to choose capacitors smaller than the 0805 size. After all the capacitors are placed, then consider whether capacitors larger than the 0805 size can be placed.

[0074] Calculate the number of capacitors:

[0075] First, count the number of caps (capacitors) for different power nets according to the Power_net in Power_cap_net.txt (denoted as Q_cap);

[0076] Then, obtain all the power nets of the required chip according to the Power_net in Power_cap_net.txt, and combine the Via_net_name and Via_location in ic_information.txt to count the via number and location information of these power nets. Since each cap has two pins, one connected to the power net and the other connected to the ground net, it is necessary to check whether the adjacent via net is GND (Ground, indicating grounding), and define the vias in pairs as Gp_via.

[0077] Compare the number of caps and vias:

[0078] If Q_cap ≤ Gp_via, it means that it is sufficient to directly attach the caps on the vias. In this case, the calculated number is the actual number of caps corresponding to this power net; if

[0079] Q_cap > Gp_via, it means that there are still some caps that do not have suitable vias to attach after the caps are attached to the vias, and the caps need to be offset to be placed. The offset method is as follows: Assume that the coordinates of the power via are (x, y), and the distance between vias is D, then the position coordinates that need to be offset are (x - D / 2, y - D / 2). According to this offset method, the number of caps obtained can increase the maximum value of the number of vias of this power net on the horizontal or vertical axis;

[0080] In electronic circuit design, offset placement refers to placing capacitors not in the conventional neat arrangement manner, but with a certain offset.

[0081] Output clip file: Generate a clip file that can be imported into EDA software based on the calculated capacitor size and quantity information. The clip file needs to define the origin coordinates of the board (which is the location of the via in the upper left corner of the chip), place capacitors of appropriate size in the via area inside the chip, evenly place the remaining capacitors around the chip according to the power position, and arrange the spacing between caps according to different sizes. Usually, the capacitors around the perimeter are slightly larger than those in the middle.

[0082] In EDA software, sometimes it is necessary to transfer similar information between different boards, and the file used is the clip file.

[0083] For example, the same board A has many signal layers. Engineer A needs to complete the routing of the sig01 layer, and Engineer B needs to complete the routing of the sig02 layer. When they finish their work, they need to combine these lines. So they use the tool built in EDA to export these lines into the clip format for combination.

[0084] Of course, not only routing, but any designable part of the board can be imported and exported.

[0085] Routing connection: After importing the generated clip file into the board, the power and ground pins of the caps will generate flying wires with the pins of the same net adjacent to them. Use the command to call and open the routing mode, and connect the coordinate points of the generated flying wires with cline (routing) to complete the final placement of the capacitors, as Figure 5 shown.

[0086] The above has described a specific embodiment of the present invention in detail, but the content described is only the preferred embodiment of the present invention and cannot be considered as limiting the scope of implementation of the present invention. Any equivalent changes and improvements made within the scope of the application of the present invention should still fall within the scope covered by the patent of the present invention.

Claims

1. A method for automatically attaching capacitors in electronic design software, characterized in that: The following steps are involved: Preparation steps: Place the chip in the board of the EDA software and perform fanout processing on each non-dummy pin of the chip; Steps for inputting chip identification: input the chip refdes that needs to be automatically attached with capacitors in the user interface of the automation tool, and separate multiple refdes with ","; EDA program execution steps: The system automatically calls and executes related EDA programs; The EDA program includes: Chip search and status judgment steps: Search the chip in the board according to the input refdes, and report an error if it is not found; If the chip is found, check whether all non-dummy pins of the chip have fanout. If there are pins that have not fanout, an error is reported.

2. A method for automatically attaching capacitors in electronic design software according to claim 1, characterized in that: The EDA program further includes an information extraction step, which is performed after the chip search and status determination steps, and includes: Find Power Nets sub-step: Find the pin information belonging to the power according to the attributes of the chip pin and store it in a temporary list; Output Power_cap_net.txt file sub-step: traverse the temporary list, find the capacitor connected to the powernet, and output the Power_cap_net.txt file containing the integrated circuit name, power network, capacitor name, capacitor power pin number, and capacitor size information; Output ic_information.txt file sub-steps: Find the shape of the specified chip in the EDA software packagegeometryclass to obtain the chip package size, export the integrated circuit name, power network, capacitor name, capacitor power pin number, capacitor size information of all vias in the chip package area, and output it as ic_information.txt file.

3. A method for automatically attaching capacitors in electronic design software according to claim 2, characterized in that: After the EDA program is finished, a capacitance parameter calculation step is executed, and the capacitance parameter calculation step includes: Calculate capacitor size sub-steps: According to the Via_location and Via_size information in the ic_information.txt file, simulate the via location and size, calculate the distance between vias and count them into a distance array, and determine the capacitor size that can be placed based on the distance array; Sub-steps for calculating the number of capacitors: Count the number of caps of different powernets according to Power_cap_net.txt, recorded as Q_cap; count the number and location information of vias of powernet in combination with Power_cap_net.txt and ic_information.txt, find out whether the adjacent vianet is GND, and define the vias in groups of two as Gp_via; if Q_cap≤Gp_via, the calculated number is the actual number of caps; if Q_cap>Gp_via, offset the caps to increase the number of caps.

4. The method for automatically attaching capacitors in electronic design software according to claim 3, characterized in that: It also includes the step of generating a clip file: based on the calculated capacitor size and quantity information, a clip file that can be imported by the EDA software is generated. The clip file defines the origin coordinates of the board as the location of the via in the upper left corner of the chip. Capacitors of appropriate sizes are placed in the via area inside the chip. The remaining capacitors are evenly placed around the chip according to the power position, and the spacing between caps is arranged according to different sizes.

5. The method for automatically attaching capacitors in electronic design software according to claim 4, characterized in that: It also includes the wiring connection steps: import the clip file into the board, generate flying wires between the power and ground pins of the cap and the adjacent pins of the same net, use the command to call the wiring mode, and connect the flying wire coordinate points with cline.

6. The method for automatically attaching capacitors in electronic design software according to claim 1, characterized in that: In the EDA program execution step, the main program is embedded in the EDA software and starts to execute after the board card that needs to automatically attach capacitors is opened, without the need to open the specified board card additionally.

7. The method for automatically attaching capacitors in electronic design software according to claim 3, characterized in that: In the sub-step of calculating the capacitor size, when simulating the via position and size, it is actually achieved by building a two-dimensional array instead of constructing an actual model.

8. The method for automatically attaching capacitors in electronic design software according to claim 3, characterized in that: When the cap is offset, assuming that the power via coordinates are (x, y), the via spacing is D, the position coordinates after offset placement are (xD / 2, yD / 2).

9. The method for automatically attaching capacitors in electronic design software according to claim 4, characterized in that: In the step of generating a clip file, generally, the size of the capacitors placed around the chip is slightly larger than the size of the capacitors placed in the via area inside the chip.

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