Register verification method, device and equipment, readable storage medium and program product

Abstract

The invention relates to a register verification method and device, equipment, a readable storage medium and a program product. The method comprises the following steps: determining an address range to be scanned and tested; starting a test sequence for the register which is indicated by the address range and participates in the test through an instantiated universal verification methodology UVM register model to complete verification of the register; wherein the test executed by the test sequence comprises at least one of the following items: performing security access detection on the register through a non-secure type bus, and the non-secure type bus is an unauthorized non-secure type bus; when the result of the security access detection is passing, performing default value detection on the register; if the register has the read-write attribute, performing a read-write attribute test on the register; performing adhesion test on addresses between the register and other registers; and performing a bit adhesion test on the register. Therefore, various potential risks in the register can be fully covered, and specific verification requirements are met.

Description

Technical Field

[0001] The present application relates to the field of testing technology, and in particular to a register verification method, apparatus, computer equipment, computer-readable storage medium, and computer program product. Background Art

[0002] In the Register-Transfer Level (RTL) verification, it is an important task to test and scan the registers in the Device Under Test (DUT) to ensure that the behavior of the registers is as expected. All configuration spaces allocated to registers, including the explicitly listed registers and the remaining space, are tested, and the test requires that the full space of the register address is scanned without hanging, and the verification of the register default value and read and write properties must meet expectations.

[0003] In traditional technology, the Universal Verification Methodology Manual (UVM) register model provides a built-in test sequence to check registers, which can check the reset value of the register, check the read and write functions of the register, etc. When using it, you only need to start the test sequence to automatically complete the check of all registers.

[0004] However, the built-in test sequence has a single test mode and is not sufficient to cover all edge cases or special situations. Especially in large-scale self-developed system-on-a-chip (SOC) designs, the built-in test sequence cannot fully meet the specific verification requirements due to its limitations. Summary of the invention

[0005] Based on this, it is necessary to provide a register verification method, device, computer equipment, computer-readable storage medium and computer program product that can comprehensively cover various potential risks in the register and meet specific verification requirements in response to the above technical problems.

[0006] In a first aspect, the present application provides a register verification method, comprising:

[0007] Determine the address range to be scanned and tested;

[0008] For the registers involved in the test indicated by the address range, a test sequence is started by instantiating a universal verification methodology UVM register model to complete the verification of the registers; wherein the test sequence performs at least one of the following tests:

[0009] Performing security access detection on registers via a non-secure type bus, wherein the non-secure type bus is an unauthorized non-secure bus;

[0010] When the result of the security access detection is passed, performing a default value detection on the register;

[0011] If the register has read-write properties, performing a read-write property test on the register;

[0012] Performing a sticky test on addresses between the register and other registers;

[0013] The register is tested for bit sticking.

[0014] In one embodiment, the secure access detection of the register through the non-secure type bus includes:

[0015] Accessing a register through a non-secure type bus and detecting a return state or return value of the register;

[0016] If the return status of the register is a correct response, or the return value is 0, the result of the security access detection is determined to be passed;

[0017] If the return status of the register is an error response, or the return value is not 0, the result of the security access detection is determined to be a failure, and the test ends.

[0018] In one embodiment, the performing a default value detection on the register includes:

[0019] Perform the first round of reset on the registers and read the register values ​​twice;

[0020] Compare the register value with the default value for the first time;

[0021] If the first comparison fails, the default value test result is determined to be failed;

[0022] If the first comparison passes, write 1 to the register;

[0023] Perform a second round of reset on the registers and read the register values ​​twice;

[0024] Compare the register value with the default value for a second time;

[0025] If the second comparison fails, the default value test result is determined to be failed;

[0026] If the second comparison passes, write 0 to the register;

[0027] Perform a third round of reset on the registers and read the register values ​​twice;

[0028] Compare the register value with the default value for the third time;

[0029] If the third comparison fails, the default value test result is determined to be failed;

[0030] If the third comparison passes, a random value is written to the register;

[0031] Perform the fourth round of register reset and read the register value twice;

[0032] Compare the register value with the default value for the fourth time;

[0033] If the fourth comparison fails, the default value test result is determined to be failed;

[0034] If the fourth comparison passes, the result of the default value detection is determined to be passed.

[0035] In one embodiment, the performing read and write property test on the register includes:

[0036] Write the first string to the register to verify whether the even bits of the register have any reading or writing errors;

[0037] Write the second string to the register to verify whether the even bits of the register have any reading or writing errors;

[0038] If the string is written twice and no error occurs in the even-numbered bits of the register, all 1s are written to the register for the first time after the register is reset;

[0039] Read the register value twice to determine whether the results of the two reads are correct;

[0040] If there is at least one error in the results of the two reads, the result of the read-write attribute test is determined to be failed;

[0041] If the results of both reads are correct, write all 0s to the register;

[0042] Read the register value twice to determine whether the results of the two reads are correct;

[0043] If there is at least one error in the results of the two reads, the result of the read-write attribute test is determined to be failed;

[0044] If the results of both reads are correct, write all 1s to the register the second time;

[0045] Read the register value twice to determine whether the results of the two reads are correct;

[0046] If there is at least one error in the results of the two reads, the result of the read-write attribute test is determined to be failed;

[0047] If the results of both reads are correct, the result of the read-write attribute test is determined to be passed.

[0048] In one embodiment, performing a sticky test on the address between the register and other registers includes:

[0049] First, write 1 to the odd-numbered bits of the register address in sequence, and read the register value back in reverse order;

[0050] If the register value read back in reverse order of the address is incorrect, the result of the address sticking test is determined to be failed;

[0051] If the register value read back in reverse order is correct, write 1 to the even-numbered bits of the register address in reverse order, and read back the register value in address order;

[0052] If the register value read back in address sequence is incorrect, the result of the address sticking test is judged as failed;

[0053] If the register value read back in address order is correct, write 1 to the odd bits of the register address in sequence for the second time, and read back the register value in reverse address order;

[0054] If the register value read back in reverse order of the address is incorrect, the result of the address sticking test is determined to be failed;

[0055] If the register value read back in reverse order is correct, then write a random value to the register in random order, and read back the register value in random order;

[0056] If the register value read back by the address out of order is incorrect, the result of the address sticking test is determined to be failed;

[0057] If the register value read back by the address out of order is correct, the result of the address sticky test is determined to be passed.

[0058] In one embodiment, performing a bit sticking test on the register includes:

[0059] Traversing each bit of the register, and performing a sticky test on one bit at a time until the sticky test of all bits in the register is completed; wherein the performing a sticky test on one bit includes:

[0060] Write 1 to the bit being tested and 0 to the rest of the bits;

[0061] Read the register value twice;

[0062] If there is at least one error in the register values ​​read twice, the bit sticky test result of the register is determined to be failed;

[0063] If the register values ​​read twice are both correct, write 0 to the tested bit and 1 to the other bits;

[0064] Read the register value twice;

[0065] If there is at least one error in the register values ​​read twice, the bit sticky test result of the register is determined to be failed;

[0066] If the register values ​​read twice are both correct, the bit sticky test result of the register is determined to be passed.

[0067] In one embodiment, before determining the register address range to be scanned and tested, the method further includes:

[0068] Integrate the instantiated UVM register model in the verification environment, and establish a connection between the adapter and the sequencer, wherein the adapter bridges the register level and the hardware bus level, and the sequencer is a bus-side excitation driver;

[0069] The front door access method is used to simulate the bus behavior of a real DUT during the read and write operations on the register, and the DUT is the unit under test.

[0070] In a second aspect, the present application also provides a register verification device, including:

[0071] A determination module is used to determine the address range to be scanned and tested;

[0072] A verification module is used to start a test sequence for the registers involved in the test indicated by the address range through an instantiated universal verification methodology UVM register model to complete the verification of the registers; wherein the test sequence performs at least one of the following tests:

[0073] Performing security access detection on registers via a non-secure type bus, wherein the non-secure type bus is an unauthorized non-secure bus;

[0074] When the result of the security access detection is passed, performing a default value detection on the register;

[0075] If the register has read-write properties, performing a read-write property test on the register;

[0076] Performing a sticky test on addresses between the register and other registers;

[0077] The register is tested for bit stickiness.

[0078] In a third aspect, the present application further provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0079] Determine the address range to be scanned and tested;

[0080] For the registers involved in the test indicated by the address range, a test sequence is started by instantiating a universal verification methodology UVM register model to complete the verification of the registers; wherein the test sequence performs at least one of the following tests:

[0081] Performing security access detection on registers via a non-secure type bus, wherein the non-secure type bus is an unauthorized non-secure bus;

[0082] When the result of the security access detection is passed, performing a default value detection on the register;

[0083] If the register has read-write properties, performing a read-write property test on the register;

[0084] Performing a sticky test on addresses between the register and other registers;

[0085] The register is tested for bit sticking.

[0086] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the following steps are implemented:

[0087] Determine the address range to be scanned and tested;

[0088] For the registers involved in the test indicated by the address range, a test sequence is started by instantiating a universal verification methodology UVM register model to complete the verification of the registers; wherein the test sequence performs at least one of the following tests:

[0089] Performing security access detection on registers via a non-secure type bus, wherein the non-secure type bus is an unauthorized non-secure bus;

[0090] When the result of the security access detection is passed, performing a default value detection on the register;

[0091] If the register has read-write properties, performing a read-write property test on the register;

[0092] Performing a sticky test on addresses between the register and other registers;

[0093] The register is tested for bit sticking.

[0094] In a fifth aspect, the present application further provides a computer program product, including a computer program, which implements the following steps when executed by a processor:

[0095] Determine the address range to be scanned and tested;

[0096] For the registers involved in the test indicated by the address range, a test sequence is started by instantiating a universal verification methodology UVM register model to complete the verification of the registers; wherein the test sequence performs at least one of the following tests:

[0097] Performing security access detection on registers via a non-secure type bus, wherein the non-secure type bus is an unauthorized non-secure bus;

[0098] When the result of the security access detection is passed, performing a default value detection on the register;

[0099] If the register has read-write properties, performing a read-write property test on the register;

[0100] Performing a sticky test on addresses between the register and other registers;

[0101] The register is tested for bit sticking.

[0102] The register verification method, device, computer equipment, computer readable storage medium and computer program product are described above. The address range to be scanned and tested is determined. For the registers involved in the test indicated by the address range, the test sequence is started through the instantiated universal verification methodology UVM register model to complete the verification of the registers. Thus, basic test cases can be established based on the UVM register model, and the advantages of the UVM register model can be fully utilized to realize automatic testing of the registers. Among them, the test sequence performs the following tests: security access detection of the registers through a non-secure type bus, and the non-secure type bus is an unauthorized non-safety bus. Thus, access checks on security registers can be realized to meet specific test requirements in SOC design. When the result of the security access detection is passed, the register is tested for default values. Thus, it is fully verified whether the register can be reset to the default value after writing 0 or writing 1, so as to evaluate the robustness of the register under different conditions. If the register has read-write properties, the register is tested for read-write properties. Thus, the read-write properties of various types of registers are fully verified to prevent design type errors. Perform a stickiness test on the addresses between the register and other registers; thereby, it is easier to detect stickiness problems between registers. Perform a bit stickiness test on the register; thereby, by reading the number of 0 or 1 of the register mirror value, the influence on other bits when writing a single bit is determined, and the independence between bits is verified. The method in the embodiment of the present application can adopt a standardized register verification process, and all register tests can be completed using a unified test case; it can accurately point to a certain register address space in the SOC, flexibly control the registers within its range for scanning through front-door access, and comprehensively cover various potential risks in the registers to meet specific verification requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0103] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0104] Figure 1 A schematic diagram of a UVM register model performing register testing in one embodiment;

[0105] Figure 2 A schematic diagram of a flow chart of a register verification method in an embodiment;

[0106] Figure 3 is a flow chart of step 202 in one embodiment;

[0107] Figure 4 is a flow chart of a register verification method in another embodiment;

[0108] Figure 5 A schematic diagram of a test flow of a UVM register in one embodiment;

[0109] FIG6 (a) is a schematic diagram of a secure access detection process in one embodiment;

[0110] FIG6( b ) is a schematic diagram of a flow chart of register default value detection in one embodiment;

[0111] FIG6 (c) is a schematic diagram of a flow chart of a register read / write property test in one embodiment;

[0112] FIG6( d ) is a schematic diagram of a flow chart of an address sticking test in one embodiment;

[0113] FIG6( e ) is a schematic diagram of a flow chart of register bit sticking test in one embodiment;

[0114] Figure 7 is a structural block diagram of a register verification device in an embodiment;

[0115] Figure 8 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0116] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0117] For example, Figure 1 FIG. 1 is a schematic diagram showing a UVM register model performing register testing in an embodiment, as shown in FIG. Figure 1As shown, the UVM register model is instantiated in the verification environment, and the connection between the adapter (bridge between the register level and the hardware bus level) and the sequencer (bus side stimulus driver) is established. The register test sequence is essentially a sequence generated by calling the read and write tasks of the register model. The role of the adapter is to realize the conversion between "uvm_reg_item" and "bus item". The reg2bus function in the adapter generates the task (transaction) type "bus_seq" that can be accepted by the sequencer and the driver, and is driven to the bus by the driver. When the driver reads the bus, the driver will also get the read "bus_seq", which is passed back to the register model through the bus2reg function of the adapter, thereby verifying whether the value read by the register meets the expectations.

[0118] In this embodiment, the steps of traversing the register address and verifying whether the properties and functions of the register meet the expectations are encapsulated as virtual functions in uvm_reg_test, so that it can be flexibly applied to various project scenarios.

[0119] In an exemplary embodiment, Figure 2 As shown, a register verification method is provided, and the method in this embodiment may include the following steps 201 to 202. Among them:

[0120] Step 201, determine the address range to be scanned and tested.

[0121] In this embodiment, the address boundary of the register to be scanned and tested is first determined, so as to facilitate subsequent verification of the registers within the address range.

[0122] Step 202 , for the registers involved in the test indicated by the address range, a test sequence is started through an instantiated universal verification methodology UVM register model to complete verification of the registers.

[0123] In the present embodiment, based on the good reusability of the UVM register model, the register model is integrated into the verification environment, and by establishing a test case "uvm_reg_test", and opening the case to the public directory, for other verification projects to reuse. Wherein, the test case can adopt a unified, standardized register test process and method, so that the verification personnel only need to inherit the test case, pass in the UVM register model and address range, and can complete the verification of the respective register parts.

[0124] For example, Figure 3As shown, the test process performed by the test sequence in step 202 may include the following steps:

[0125] Step 2021, performing security access detection on the register via a non-secure type bus.

[0126] The non-secure type bus is an unauthorized non-secure bus.

[0127] In this embodiment, in the SOC design, there are some secure registers that are only allowed to be accessed by specific hosts or authorized buses. When such secure registers are accessed by unauthorized non-secure type buses, the correct response is to give an error return or the read register value is 0. If the non-secure type bus successfully accesses the secure register, this error will cause a major security vulnerability in the SOC design. Therefore, verifying access to the secure register is particularly important in the SOC design.

[0128] Exemplarily, a register can be accessed through a non-secure type bus, and the return status or return value of the register can be detected; if the return status of the register is a correct response, or the return value is 0, the result of the security access test is determined to be passed; if the return status of the register is an error response, or the return value is not 0, the result of the security access test is determined to be failed, and the test is terminated.

[0129] Step 2022: When the result of the security access detection is passed, a default value detection is performed on the register.

[0130] In this embodiment, four rounds of reset detection can be used: the first round resets the register model, resets the DUT, then reads the register value and compares it with the default value given in the table; the second round writes 1 to all registers, resets the register model, resets the DUT, and reads the register value; the third round writes 0 to all registers, resets the register model, resets the DUT, and reads the register value; the fourth round writes random values ​​to all registers, resets the register model, resets the DUT, and reads the register value.

[0131] Exemplarily, the register is reset for the first time, and the register value is read twice; the register value is compared with the default value for the first time; if the first comparison fails, the result of the default value detection is determined to be failed; if the first comparison passes, 1 is written to the register.

[0132] Exemplarily, the register is reset for the second round, and the register value is read twice; the register value is compared with the default value for the second time; if the second comparison fails, the result of the default value detection is determined to be failed; if the second comparison passes, 0 is written to the register.

[0133] Exemplarily, the register is reset for the third time, and the register value is read twice; the register value is compared with the default value for the third time; if the third comparison fails, the result of the default value detection is determined to be failed; if the third comparison passes, a random value is written to the register.

[0134] Exemplarily, the register is reset for the fourth time, and the register value is read twice; the register value is compared with the default value for the fourth time; if the fourth comparison fails, the result of the default value test is determined to be failed; if the fourth comparison passes, the result of the default value test is determined to be passed.

[0135] In this embodiment, four rounds of checks are used to fully verify the correctness of the register reset function. Compared with the traditional method of only checking the default value after the register model is reset, this embodiment fully verifies whether the register can be reset to the default value after writing 0 or writing 1, so as to evaluate the robustness of the register under different conditions.

[0136] Step 2023: If the register has read-write attributes, the register is tested for read-write attributes.

[0137] In this embodiment, for some special access type registers that will have an impact when writing or reading, such as WC (cleared when writing), RC (cleared when reading), W1T (flipped when writing 1), W0T (flipped when writing 0), etc., a bit flip scan test is added to further ensure the register properties.

[0138] Exemplarily, a bit-flip scan test can be performed after the register is reset. First, all 1s are written to the register, and the register value is read twice to ensure that the register is not cleared when read. Then, the register is flipped and all 0s are written, the register value is read, and the register is flipped again and all 1s are written, and the register value is read to ensure that the register is not affected by writing 0 or 1.

[0139] Exemplarily, a first string is written to a register to verify whether any reading or writing errors occur in the even-numbered bits of the register; a second string is written to the register to verify whether any reading or writing errors occur in the even-numbered bits of the register; if no reading or writing errors occur in the even-numbered bits of the register after the strings are written twice, then after resetting the register, all 1s are written to the register for the first time; the register value is read twice to determine whether the results of the two reads are correct; if there is at least one error in the results of the two reads, the result of the read-write attribute test is determined to be failed; if the results of the two reads are both correct, all 0s are written to the register; the register value is read twice to determine whether the results of the two reads are correct; if there is at least one error in the results of the two reads, the result of the read-write attribute test is determined to be failed; if the results of the two reads are both correct, all 1s are written to the register for the second time; the register value is read twice to determine whether the results of the two reads are correct; if there is at least one error in the results of the two reads, the result of the read-write attribute test is determined to be failed; if the results of the two reads are both correct, the result of the read-write attribute test is determined to be passed.

[0140] In this embodiment, the double reading method is used when reading registers. For registers with read and write properties, it can prevent designers from mistakenly designing them as RC type registers (that is, they will be cleared when read). The double reading method can fully verify its read properties.

[0141] Step 2024, performing a sticky test on the addresses between the register and other registers.

[0142] In this embodiment, by writing 1 to the address bits crosswise, it is detected whether the registers at other addresses (usually the registers at adjacent addresses) will be affected when a specific register is read or written. For example, for the sake of safety, after "sequential writing" and "reverse reading", a reverse test is performed again, so that the situation where A affects B but B does not affect A can be prevented, and the adhesion problem between registers can be detected more easily.

[0143] Exemplarily, the odd-numbered bits of the register address are sequentially written with 1 for the first time, and the register value is read back in reverse address order; if the register value read back in reverse address order is incorrect, the result of the address sticking test is determined to be failed; if the register value read back in reverse address order is correct, the even-numbered bits of the register address are written with 1 in reverse address order, and the register value is read back in sequential address order; if the register value read back in sequential address order is incorrect, the result of the address sticking test is determined to be failed; if the register value read back in sequential address order is correct, the odd-numbered bits of the register address are sequentially written with 1 for the second time, and the register value is read back in reverse address order; if the register value read back in reverse address order is incorrect, the result of the address sticking test is determined to be failed; if the register value read back in reverse address order is correct, random values ​​are written to the register in random order, and the register value is read back in random address order; if the register value read back in random address order is incorrect, the result of the address sticking test is determined to be failed; if the register value read back in random address order is correct, the result of the address sticking test is determined to be passed.

[0144] Step 2025, performing a bit sticky test on the register.

[0145] In this embodiment, for the bit sticking test in the same register, one bit of the register can be written as 1 each time and the remaining bits can be written as 0, and the mirror value of the register model can be read twice, and then written again after flipping, that is, only 0 is written to the bit and 1 is written to the remaining bits, and the mirror value of the register model is read twice; the above verification operation is performed on all bits in the register in sequence until all bits of the register are tested.

[0146] Exemplarily, each bit of the register is traversed, and a adhesion test is performed on one bit each time until the adhesion test of all bits in the register is completed; wherein, the adhesion test for one bit includes: writing 1 to the tested bit and writing 0 to the remaining bits; reading the register value twice; if there is at least one error in the register values ​​read twice, the bit adhesion test result of the register is determined to be failed; if the register values ​​read twice are both correct, writing 0 to the tested bit and writing 1 to the remaining bits; reading the register value twice; if there is at least one error in the register values ​​read twice, the bit adhesion test result of the register is determined to be failed; if the register values ​​read twice are both correct, the bit adhesion test result of the register is determined to be passed.

[0147] This embodiment can determine the influence of writing a single bit on other bits by reading the number of 0 or 1 of the register mirror value, thereby verifying the independence between the bits.

[0148] The register verification method is to determine the address range to be scanned and tested; for the registers involved in the test indicated by the address range, start the test sequence through the instantiated universal verification methodology UVM register model to complete the verification of the register; thereby, it is possible to establish a basic test case based on the UVM register model, make full use of the advantages of the UVM register model, and realize automatic testing of the register. Among them, the test sequence performs the test including: performing a security access detection on the register through a non-secure type bus, and the non-secure type bus is an unauthorized non-safety bus; thereby, it is possible to realize the access check of the security register and meet the specific test requirements in the SOC design. When the result of the security access detection is passed, the register is tested for the default value; thereby, it is fully verified whether the register can be reset to the default value after the operation of writing 0 or writing 1, so as to evaluate the robustness of the register under different conditions. If the register has read-write properties, the register is tested for read-write properties; thereby, the read-write properties of various types of registers are fully verified to prevent design type errors. The address between the register and other registers is tested for adhesion; thereby, it is easier to detect the adhesion problem between registers. The register is subjected to a bit adhesion test; thereby, the influence of writing a single bit on other bits is determined by reading the number of 0 or 1 of the register mirror value, and the independence between bits is verified. The method in the embodiment of the present application can adopt a standardized register verification process, and all register tests can be completed using a unified test case; it accurately points to a certain register address space in the SOC, flexibly controls the registers within its range for scanning through front door access, and comprehensively covers various potential risks in the register to meet specific verification requirements.

[0149] In another exemplary embodiment, Figure 4 As shown, a register verification method is provided, and the method in this embodiment may include the following steps 401 to 404. Among them:

[0150] Step 401, integrating the instantiated UVM register model into the verification environment, and establishing a connection between the adapter and the sequencer.

[0151] The adapter is a bridge between the register level and the hardware bus level, and the sequencer is a bus-side excitation driver.

[0152] In this embodiment, based on the good reusability of the UVM register model, the UVM register model can be integrated into the verification environment, and a test case "uvm_reg_test" is established, and then the test case is opened to the public directory for reuse by other verification projects. For example, see Figure 1The UVM register model shown in the figure establishes a connection between the adapter and the sequencer, so that the adapter converts the "uvm_reg_item" and the "bus item", and generates the task type "bus_seq" that can be accepted by the sequencer and the driver through the reg2bus function in the adapter, and is driven to the bus by the driver. When the driver reads the bus, the driver will also get the read "bus_seq", and finally pass it back to the register model through the bus2reg function of the adapter to verify whether the value read by the register meets the expectations.

[0153] Step 402: Use the front door access method to simulate the bus behavior of the real DUT when performing read and write operations on the register.

[0154] The DUT is a unit under test.

[0155] In this embodiment, using the front door access method helps to simulate real usage scenarios and ensure the behavior of registers in actual applications.

[0156] Step 403, determine the address range to be scanned and tested.

[0157] Step 404 , for the registers involved in the test indicated by the address range, a test sequence is started through the instantiated universal verification methodology UVM register model to complete the verification of the registers.

[0158] In this embodiment, the specific implementation process and technical effects of steps 403 to 404 are shown in Figure 2 The descriptions of steps 201 to 202 in the illustrated method embodiment will not be repeated here.

[0159] In an exemplary embodiment, Figure 5 As shown, the test process of the UVM register is given, which may include the following steps:

[0160] 1) Determine the address boundaries of the registers to be scanned and tested.

[0161] 2) Set exclude regs. If some registers are not involved in this test, set them to "excluderegs[$]". Exclude regs means excluding registers that are not involved in the test.

[0162] 3) Confirm the registers that need to be tested and classify the access types (RW / RO / RC / WC) of the registers.

[0163] 4) Operations before register scanning: such as setting reg sequencer. reg sequencer means register sequence generator.

[0164] 5) Secure register access detection: Check and confirm that the secure registers cannot be accessed by the non-secure bus.

[0165] 6) Register reset function test: Test whether the default value of the register meets the expectation and whether the reset function of the register is correct.

[0166] 7) Register read and write property test: Perform read and write operations and verify data accuracy.

[0167] 8) Register address adhesion test: Check whether there is interference between adjacent register addresses, such as whether adjacent registers are read or written at the same time when reading or writing a register.

[0168] 9) Register bit adhesion test: Check whether the bits inside the register interfere with each other.

[0169] In another exemplary embodiment, as shown in FIG. 6 (a) to FIG. 6 (e), a test flow of a UVM register is provided, which may include: secure access detection, register default value detection, register read and write property test, address sticky test, and register bit sticky test.

[0170] In this embodiment, referring to FIG. 6 (a), a non-secure access register is detected, and the return state or return value of the register is detected; if the return state of the register is a correct response, or the return value is 0, the result of the secure access detection is determined to be passed, and the next step of register default value detection is performed. If the return state of the register is an error response, or the return value is not 0, the result of the secure access detection is determined to be failed, and the test is terminated.

[0171] In this embodiment, referring to FIG. 6 (b), the register is reset for the first time, and the register value is read twice; 1 is written to the register; the register is reset for the second time, and the register value is read twice; 0 is written to the register; the register is reset for the third time, and the register value is read twice; a random value is written to the register; the register is reset for the fourth time, and the register value is read twice; if the register values ​​read four times are correct, the next step of register read and write property test is performed.

[0172] In this embodiment, referring to FIG6 (c), "haa" is written to the register to verify whether an even-numbered bit of the register is incorrectly read or written; "h55" is written to the register to verify whether an even-numbered bit of the register is incorrectly read or written; the register is reset and all 1s are written to the register for the first time; the register is reset and the register value is read twice; all 0s are written to the register; the register value is read twice; all 1s are written to the register for the second time; the register value is read twice; if all the read register values ​​are correct, the next step of address sticking test is performed.

[0173] In this embodiment, referring to FIG. 6 (d), the odd-numbered bits of the register address are sequentially written with 1 for the first time, and the register value is read back in reverse order; the even-numbered bits of the register address are sequentially written with 1, and the register value is read back in sequential order; the odd-numbered bits of the register address are sequentially written with 1 for the second time, and the register value is read back in reverse order; random values ​​are written to the register in random order, and the register value is read back in random order; if the register value read back in reverse order is correct, the register value read back in sequential order is correct, and the register value read back in random order is correct, the next step of register bit adhesion test is performed.

[0174] In this embodiment, as shown in FIG6 (e), the register is first scanned according to the bit position, and the initial value of i is set to 0, and it is determined whether i is less than the register bit width. If so, 1 is written to the bit, and 0 is written to the remaining bits, and the register value is read twice; 0 is written to the bit, and 1 is written to the remaining bits, and the register value is read twice; then i is incremented by 1, and the same operation is performed on the next bit position until the test of all register bits is completed.

[0175] In this embodiment, a security access check is performed on the register through a non-secure type bus, and the non-secure type bus is an unauthorized non-security type bus; thereby, access checks on security registers can be implemented to meet specific test requirements in SOC design. When the result of the security access check is passed, the register is tested for default values; thereby, it is fully verified whether the register can be reset to the default value after the operation of writing 0 or writing 1, so as to evaluate the robustness of the register under different conditions. If the register has read and write properties, the register is tested for read and write properties; thereby, the read and write properties of various types of registers are fully verified to prevent design type errors. The addresses between the register and other registers are tested for adhesion; thereby, adhesion problems between registers are more easily detected. The register is tested for bit adhesion; thereby, the number of 0 or 1 in the register mirror value is read to determine the impact of writing a single bit on other bits, and the independence between bits is verified. The method in the embodiment of the present application can adopt a standardized register verification process and complete all register tests using a unified test case; it can accurately point to a certain register address space in the SOC, flexibly control the registers within its range for scanning through front-door access, and comprehensively cover various potential risks in the registers to meet specific verification requirements.

[0176] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0177] Based on the same inventive concept, the embodiment of the present application also provides a register verification device for implementing the register verification method involved above. The implementation solution provided by the device to solve the problem is similar to the implementation solution recorded in the above method, so the specific limitations in one or more register verification device embodiments provided below can refer to the limitations of the register verification method above, and will not be repeated here.

[0178] In an exemplary embodiment, Figure 7 As shown, a register verification device is provided, including: a determination module 701 and a verification module 702, wherein:

[0179] A determination module 701 is used to determine an address range to be scanned and tested;

[0180] The verification module 702 is used to start a test sequence for the registers involved in the test indicated by the address range through the instantiated universal verification methodology UVM register model to complete the verification of the registers; wherein the test sequence performs at least one of the following tests:

[0181] Performing security access detection on registers via a non-secure type bus, wherein the non-secure type bus is an unauthorized non-secure bus;

[0182] When the result of the security access detection is passed, performing a default value detection on the register;

[0183] If the register has read-write properties, performing a read-write property test on the register;

[0184] Performing a sticky test on addresses between the register and other registers;

[0185] The register is tested for bit stickiness.

[0186] Exemplarily, the security access detection on the register through the non-secure type bus includes: accessing the register through the non-secure type bus, and detecting the return status or return value of the register; if the return status of the register is a correct response, or the return value is 0, then the result of the security access detection is determined to be passed; if the return status of the register is an error response, or the return value is not 0, then the result of the security access detection is determined to be failed, and the test is terminated.

[0187] Exemplarily, the default value detection of the register includes: resetting the register for the first round and reading the register value twice; comparing the register value with the default value for the first time; if the first comparison fails, the result of the default value detection is determined to be failed; if the first comparison passes, writing 1 to the register; resetting the register for the second round and reading the register value twice; comparing the register value with the default value for the second time; if the second comparison fails, the result of the default value detection is determined to be failed; if the second comparison passes, writing 0 to the register; resetting the register for the third round and reading the register value twice; comparing the register value with the default value for the third time; if the third comparison fails, the result of the default value detection is determined to be failed; if the third comparison passes, writing a random value to the register; resetting the register for the fourth round and reading the register value twice; comparing the register value with the default value for the fourth time; if the fourth comparison fails, the result of the default value detection is determined to be failed; if the fourth comparison passes, the result of the default value detection is determined to be passed.

[0188] Exemplarily, the read-write property test of the register includes: writing a first string to the register to verify whether an erroneous read or write occurs in the even-numbered bits of the register; writing a second string to the register to verify whether an erroneous read or write occurs in the even-numbered bits of the register; if no erroneous read or write occurs in the even-numbered bits of the register after the strings are written twice, then after resetting the register, writing all 1s to the register for the first time; reading the register value twice to determine whether the results of the two reads are correct; if there is at least one error in the results of the two reads, then determining that the result of the read-write property test is failed; if the results of the two reads are both correct, writing all 0s to the register; reading the register value twice to determine whether the results of the two reads are correct; if there is at least one error in the results of the two reads, then determining that the result of the read-write property test is failed; if the results of the two reads are both correct, then writing all 1s to the register for the second time; reading the register value twice to determine whether the results of the two reads are correct; if there is at least one error in the results of the two reads, then determining that the result of the read-write property test is failed; if the results of the two reads are both correct, then writing all 1s to the register for the second time; reading the register value twice to determine whether the results of the two reads are correct; if there is at least one error in the results of the two reads, then determining that the result of the read-write property test is failed; if the results of the two reads are both correct, then determining that the result of the read-write property test is passed.

[0189] Exemplarily, a stickiness test is performed on the address between the register and other registers, including: writing 1 sequentially to the odd bits of the register address for the first time, and reading back the register value in reverse order; if the register value read back in reverse order is incorrect, the result of the address stickiness test is determined to be failed; if the register value read back in reverse order is correct, writing 1 to the even bits of the register address in reverse order, and reading back the register value in sequence; if the register value read back in sequence is incorrect, the result of the address stickiness test is determined to be failed; if the register value read back in sequence is correct, writing 1 sequentially to the odd bits of the register address for the second time, and reading back the register value in reverse order; if the register value read back in reverse order is incorrect, the result of the address stickiness test is determined to be failed; if the register value read back in reverse order is correct, writing random values ​​to the register in random order, and reading back the register value in random order; if the register value read back in random order is incorrect, the result of the address stickiness test is determined to be failed; if the register value read back in random order is correct, the result of the address stickiness test is determined to be passed.

[0190] Exemplarily, performing a bit adhesion test on the register includes: traversing each bit of the register, and performing a adhesion test on one bit each time until the adhesion test of all bits in the register is completed; wherein, performing a adhesion test on one bit includes: writing 1 to the tested bit and writing 0 to the remaining bits; reading the register value twice; if there is at least one error in the register values ​​read twice, then the bit adhesion test result of the register is determined to be failed; if the register values ​​read twice are both correct, then writing 0 to the tested bit and writing 1 to the remaining bits; reading the register value twice; if there is at least one error in the register values ​​read twice, then the bit adhesion test result of the register is determined to be failed; if the register values ​​read twice are both correct, then the bit adhesion test result of the register is determined to be passed.

[0191] Exemplarily, the above-mentioned device may also include a model integration module 703, which is used to integrate the instantiated UVM register model into the verification environment and establish a connection between the adapter and the sequencer, wherein the adapter bridges the register level and the hardware bus level, and the sequencer is a bus-side excitation driver; a front-door access method is used to simulate the bus behavior of a real DUT during register read and write operations, wherein the DUT is a unit under test.

[0192] Each module in the register verification device can be implemented in whole or in part by software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module.

[0193] In an exemplary embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as shown in FIG. Figure 8 As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. The processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a register verification method is implemented.

[0194] Those skilled in the art will understand that Figure 8 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0195] In an exemplary embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above-mentioned method embodiments when executing the computer program.

[0196] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0197] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0198] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0199] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0200] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0201] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A register verification method, characterized in that: The method comprises: Determine the address range to be scanned and tested; For the registers involved in the test indicated by the address range, a test sequence is started by instantiating a universal verification methodology UVM register model to complete the verification of the registers; wherein the test sequence performs at least one of the following tests: Performing security access detection on registers via a non-secure type bus, wherein the non-secure type bus is an unauthorized non-secure bus; When the result of the security access detection is passed, performing a default value detection on the register; If the register has read-write properties, performing a read-write property test on the register; Performing a sticky test on addresses between the register and other registers; The register is tested for bit stickiness.

2. The method according to claim 1, characterized in that The secure access detection of the register through the non-secure type bus includes: Accessing a register through a non-secure type bus and detecting a return state or return value of the register; If the return status of the register is a correct response, or the return value is 0, the result of the security access detection is determined to be passed; If the return status of the register is an error response, or the return value is not 0, the result of the security access detection is determined to be a failure, and the test ends.

3. The method according to claim 1, characterized in that The performing default value detection on the register includes: Perform the first round of reset on the registers and read the register values ​​twice; Compare the register value with the default value for the first time; If the first comparison fails, the default value test result is determined to be failed; If the first comparison passes, write 1 to the register; Perform a second round of reset on the registers and read the register values ​​twice; Compare the register value with the default value for a second time; If the second comparison fails, the default value test result is determined to be failed; If the second comparison passes, write 0 to the register; Perform a third round of reset on the registers and read the register values ​​twice; Compare the register value with the default value for the third time; If the third comparison fails, the default value test result is determined to be failed; If the third comparison passes, a random value is written to the register; Perform the fourth round of register reset and read the register value twice; Compare the register value with the default value for the fourth time; If the fourth comparison fails, the default value test result is determined to be failed; If the fourth comparison passes, the result of the default value detection is determined to be passed.

4. The method according to claim 1, characterized in that: The performing a read-write property test on the register includes: Write the first string to the register to verify whether the even bits of the register have any reading or writing errors; Write the second string to the register to verify whether the even bits of the register are read or written incorrectly; If the string is written twice and no error occurs in the even-numbered bits of the register, all 1s are written to the register for the first time after the register is reset; Read the register value twice to determine whether the results of the two reads are correct; If there is at least one error in the results of the two reads, the result of the read-write attribute test is determined to be failed; If the results of both reads are correct, write all 0s to the register; Read the register value twice to determine whether the results of the two reads are correct; If there is at least one error in the results of the two reads, the result of the read-write attribute test is determined to be failed; If the results of both reads are correct, write all 1s to the register the second time; Read the register value twice to determine whether the results of the two reads are correct; If there is at least one error in the results of the two reads, the result of the read-write attribute test is determined to be failed; If the results of both reads are correct, the result of the read-write attribute test is determined to be passed.

5. The method according to claim 1, characterized in that Performing a sticky test on the address between the register and other registers, including: First, write 1 to the odd-numbered bits of the register address in sequence, and read the register value back in reverse order; If the register value read back in reverse order of the address is incorrect, the result of the address sticking test is determined to be failed; If the register value read back in reverse order is correct, write 1 to the even-numbered bits of the register address in reverse order, and read back the register value in address order; If the register value read back in address sequence is incorrect, the result of the address sticking test is judged as failed; If the register value read back in address order is correct, write 1 to the odd bits of the register address in sequence for the second time, and read back the register value in reverse address order; If the register value read back in reverse order of the address is incorrect, the result of the address sticking test is determined to be failed; If the register value read back in reverse order is correct, then write a random value to the register in random order, and read back the register value in random order; If the register value read back by the address out of order is incorrect, the result of the address sticking test is determined to be failed; If the register value read back by the address out of order is correct, the result of the address sticky test is determined to be passed.

6. The method according to claim 1, characterized in that A bit sticking test is performed on the register, comprising: Traversing each bit of the register, and performing a sticky test on one bit at a time until the sticky test of all bits in the register is completed; wherein the performing a sticky test on one bit includes: Write 1 to the bit being tested and 0 to the rest of the bits; Read the register value twice; If there is at least one error in the register values ​​read twice, the bit sticky test result of the register is determined to be failed; If the register values ​​read twice are both correct, write 0 to the tested bit and 1 to the other bits; Read the register value twice; If there is at least one error in the register values ​​read twice, the bit sticky test result of the register is determined to be failed; If the register values ​​read twice are both correct, the bit sticky test result of the register is determined to be passed.

7. The method according to any one of claims 1 to 6, characterized in that: Before determining the register address range to be scanned and tested, the method further includes: Integrate the instantiated UVM register model in the verification environment, and establish a connection between the adapter and the sequencer, wherein the adapter bridges the register level and the hardware bus level, and the sequencer is a bus-side excitation driver; The front door access method is used to simulate the bus behavior of a real DUT during the read and write operations on the register, and the DUT is the unit under test.

8. A register verification device, characterized in that: The device comprises: A determination module is used to determine the address range to be scanned and tested; A verification module is used to start a test sequence for the registers involved in the test indicated by the address range through an instantiated universal verification methodology UVM register model to complete the verification of the registers; wherein the test sequence performs at least one of the following tests: Performing security access detection on registers via a non-secure type bus, wherein the non-secure type bus is an unauthorized non-secure bus; When the result of the security access detection is passed, performing a default value detection on the register; If the register has read-write properties, performing a read-write property test on the register; Performing a sticky test on addresses between the register and other registers; The register is tested for bit stickiness.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

11. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

Images