State tracking and positioning method and system in processor core FPGA (Field Programmable Gate Array) simulation process

Abstract

The invention discloses a state tracking and positioning method and system in the FPGA simulation process of a processor core, and belongs to the technical field of computers. The method comprises the steps that the key state of the processor core to be verified is monitored to obtain tracking data; and restoring the tracking data into a tracking data frame, and processing and analyzing the tracking data frame to obtain a change sequence of the abnormal state of the processor core. The system comprises a target to-be-tested system which is internally provided with a to-be-verified processor core and a key state tracker realized by an FPGA (Field Programmable Gate Array) and is connected with a host machine, and a program receiving module and a positioning analysis module run on the host machine; the key state tracker monitors the key state of the processor core to obtain tracking data and then outputs the tracking data to the host machine; the receiving program module restores the tracking data into a tracking data frame, and the positioning analysis module processes and analyzes the tracking data frame to obtain a change sequence of the abnormal state of the processor core. The method does not need to track a program execution stream, and greatly reduces the tracking data volume.

Description

Technical Field

[0001] The invention belongs to the field of computer technology, and in particular relates to a state tracking and positioning method and system in a processor core FPGA simulation process. Background Art

[0002] Processor cores, especially high-performance processor cores, have a huge number of logic gates. In order to avoid design defects, they must undergo a large number of tests before tape-out. These tests include directional tests in a bare metal environment and tests based on some benchmark data sets under the operating system, such as SPEC CPU 2006. Since the number of logic gates of the processor is extremely large, complex tests are almost impossible to complete in a software simulation environment. In addition to software simulation, simulation can also be performed through FPGA (Field-Programmable Gate Array) or using a dedicated hardware simulation accelerator. Generally, a dedicated hardware simulation accelerator can achieve a simulation speed of about 0.5~10MHz, which is a huge improvement in simulation speed compared to software simulation. However, hardware simulation accelerators are extremely expensive, and the waveform window for observation is limited. For complex use cases, it takes several days to run to get simulation results.

[0003] Compared with simulation accelerators, FPGA simulation is low-cost and runs faster, usually reaching around 50~100MHz. Using FPGA to debug processor cores can be done through the software path of GDB (GNU Debugger) + OpenOCD (Open On-Chip Debugger) + JTAG (Joint Test Action Group) + Debug (debugging) kernel, or through waveform debugging. Using software path debugging faces the problem of slow debugging response and the inability to grasp the overall picture of the entire program flow, which makes it difficult for debuggers to track and analyze the program execution flow based on GDB. Using waveform debugging, it is impossible to track signals for a long time. At the same time, when changing the debug signal, the FPGA layout and wiring needs to be re-performed, which is a very time-consuming process. These two problems make it difficult to debug complex problems when using FPGA to simulate processor cores.

[0004] Tracing the program execution flow is a very effective method to grasp the overall picture of the operation. Currently, many tracing methods are based on tracing the program counter (PC). The branch instructions and the number of instructions executed continuously after the jump are tracked, and then these information flows are compressed by hardware in real time and sent to the host through the output port. There are two main problems with this method: First, the amount of data traced based on branches far exceeds the communication speed of general low-speed peripherals, such as JTAG and UART (Universal Asynchronous Receiver Transmitter). If additional information is to be provided, such as changes in the value of general registers, this problem will be more serious. Second, in order to solve this large amount of data tracing information, a large amount of complex compression logic must be introduced or a more complex high-speed communication port must be used, such as a network port and a PCIE (Peripheral Component Interconnect Express) interface. Therefore, due to the problem of data volume, tracing based on branches will inevitably lead to a large amount of complex logic.

[0005] In summary, the existing technology of using FPGA to debug processor cores has technical defects such as large amount of tracking data and difficulty in tracking and debugging. Summary of the invention

[0006] In view of this, the present invention proposes a state tracking and positioning method and system during the FPGA simulation of a processor core, which tracks and restores the key state changes of the processor core by adding a key state tracker in the processor core, so as to solve the technical defects of the existing method of using FPGA to debug the processor core, such as large amount of tracking data, difficulty in tracking and debugging, etc.

[0007] In a first aspect, the present invention provides a state tracking and positioning method in a processor core FPGA simulation process, comprising: Monitor the key state of the processor core to be verified on the target system to be tested to obtain tracking data, and transmit it to the host machine through the simulation debugging interface, wherein the key state of the processor core at least includes the abnormal state entered by the processor core when the program execution is interrupted, the execution is abnormal, the system is called, and the internal abnormality defined by the micro-architecture; The tracing data is restored into tracing data frames, and the tracing data frames are processed and analyzed to obtain a change sequence of the abnormal state of the processor core.

[0008] Furthermore, the method further comprises: Reliability encoding of the tracking data is performed and then transmitted to the host machine; The tracking data is decoded using a decoding method corresponding to the reliability coding to obtain a data frame stream, and the key state of each abnormal point on the processor core is restored through the obtained data frame.

[0009] In a second aspect, the present invention provides a state tracking and positioning system in a processor core FPGA simulation process, comprising: A target system to be tested, wherein the target system to be tested is connected to a host machine via a simulation debugging interface, wherein a processor core to be verified and a key state tracker implemented by FPGA are arranged in the target system to be tested, and a receiving program module and a positioning analysis module are running on the host machine; The key state tracker monitors the key state of the processor core to obtain tracking data and then outputs it to the host machine through the simulation debugging interface, wherein the key state of the processor core at least includes the abnormal state entered by the processor core when program execution is interrupted, execution is abnormal, system call, or internal abnormality defined by the micro-architecture; The receiving program module restores the tracking data output by the key state tracker into a tracking data frame, and the positioning analysis module processes and analyzes the tracking data frame to obtain a change sequence of the abnormal state of the processor core.

[0010] Further, the key state tracker also includes an encoder; The encoder is used for performing reliability encoding on the tracking data to enhance the reliability of the tracking data transmission.

[0011] Further, the key state tracker also includes an output controller; The output controller is used to select whether to temporarily store the tracking data in a DDR memory or directly output the tracking data to the host machine.

[0012] Furthermore, the key state tracker further includes a core tracker, which is used to monitor the key state of the processor core to obtain tracking data; the core tracker includes: A general register traverser is used to read and save data saved to the general register when the operating system handles an exception; the general register traverser maintains a state machine for saving the value of each general register read for the first time after the exception occurs to a first-in-first-out queue memory, and the general register traverser gradually obtains the value of the general register through multiple cycles; A special purpose register reader for reading and saving data saved to special purpose registers when the operating system handles an exception; A custom register reader, used to read and save data saved to the custom register when the operating system handles an exception, wherein the custom register includes at least a count value each time an exception is triggered and a process number of the currently running task; The first-in-first-out queue memory is used to store the values ​​saved by the general register walker, the special purpose register reader and the custom register reader; The frame packing module is used to pack the data stored in the first-in-first-out queue memory into data frames according to a fixed-order frame format.

[0013] Furthermore, the positioning analysis module is also used to read the clock cycle interval between two adjacent tracking data, and when the clock cycle interval is greater than a specified cycle threshold, output a prompt message of a software error that may cause a long-term lock interruption.

[0014] Furthermore, the positioning analysis module is also used to count the time when a specific interruption occurs. If the specific interruption does not appear in the tracking data stream for more than a specified time, a prompt message that the specific interruption may be lost is output; or, to count the number of times a specific interruption occurs. If the occurrence of the specific interruption in the tracking data stream does not exceed a specified number of times, a prompt message that the specific interruption may be lost is output.

[0015] Furthermore, the positioning analysis module is also used to read the process number and address space identifier in the tracking data, and if it is determined that the values ​​of two adjacent tracking data are different, output prompt information of the context switch and the process number of the new task.

[0016] Furthermore, the operating system running on the processor core reads the exception count register before entering exception processing, interrupt processing or system call.

[0017] In a third aspect, the present invention provides an electronic device comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus; the memory is used to store computer programs; and when the processor is used to execute the program stored in the memory, the state tracking and positioning method in the above-mentioned processor core FPGA simulation process is implemented.

[0018] In a fourth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a computer, implements the state tracking and positioning method in the above-mentioned processor core FPGA simulation process.

[0019] The state tracking and positioning method and system in the processor core FPGA simulation process provided by the present invention have the following advantages and beneficial effects: The present invention aims at the problem of difficulty in emulation debugging of processor core on existing FPGA, and adds a key state tracker in the processor core. The key state tracker uses the exceptions of the processor core, such as interrupts, exceptions in the usual sense and system calls, and internal exceptions defined by the micro-architecture as tracking points, and cooperates with the analysis and processing of the operating system kernel and the host machine to realize the tracking and restoration of the key state transition of the processor core. Since the present invention tracks the exceptions of the processor core through the key state tracker in the processor core, it is not necessary to track the program execution flow, which greatly reduces the amount of tracking data. Therefore, the amount of tracking data is much lower than the existing tracking method based on branch instructions, and the difficulty of tracking implementation is also reduced.

[0020] The present invention abandons the complex branch instruction-based tracking method in the prior art, tracks the key states within the processor core, constructs the state change process of the processor core through the analysis software on the host machine, restores the key change sequence in the program execution process on each hardware thread, and corresponds to the software log of the operating system. It can effectively assist in locating problems in complex programs and provide analysis data for complex problems. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings described herein are used to provide a further understanding of the embodiments of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings: Figure 1 A flowchart of a state tracking and positioning method in a processor core FPGA simulation process provided by an embodiment of the present invention; Figure 2 A block diagram of a state tracking and positioning system in a processor core FPGA simulation process provided by an embodiment of the present invention; Figure 3 A block diagram of a state tracking and positioning system in a processor core FPGA simulation process provided by an embodiment of the present invention; Figure 4 The embodiment of the present invention provides Figure 3 A structural block diagram of a key state tracker in FIG. Figure 5 The embodiment of the present invention provides Figure 4 A structural block diagram of the core tracker; Figure 6 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The technical solution provided by the present invention is further described below with reference to the accompanying drawings and examples. It should be understood that the system structure and business scenarios provided in the embodiments of the present invention are mainly to illustrate possible implementation methods of the technical solution of the present invention and should not be interpreted as the sole limitation of the technical solution of the present invention. It is known to those skilled in the art that with the evolution of the system structure and the emergence of new business scenarios, the technical solution provided by the present invention is also applicable to similar technical problems.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. In the event of any inconsistency, the meanings described in this specification or derived from the contents recorded in this specification shall prevail. In addition, the terms used herein are only for the purpose of describing the embodiments of the present invention and are not intended to limit the present invention.

[0024] like Figure 1 As shown, Figure 1 A flow chart of a state tracking and positioning method in a processor core FPGA simulation process provided by an embodiment of the present invention is shown. The method comprises the following steps: Step S1, monitoring the key status of the processor core to be verified on the target system to be tested to obtain tracking data, and transmitting the tracking data to the host machine through the simulation debugging interface.

[0025] Among them, the key state of the processor core includes at least the exception state that the processor core enters when the program execution is interrupted, the execution is abnormal, the system call, and the internal exception defined by the microarchitecture. The key state of the processor core can be the program counter (PC) value when the exception occurs, the system status value, the general register, the exception cause, the process number (ProcessIdentifier, PID) of the current running task, the address space identifier (Address Space Identifier, ASID) and the count value (evcounter) when each exception is triggered. For example, in the RISCV processor, the registers corresponding to these values ​​are mepc (Machine Exception Program Counter, Machine Exception Program Counter), mstatus (Machine Status Register, Machine Status Register), GPR (General Purpose Registers, General Purpose Register), mcause (Machine Cause Register, Machine Exception Cause Register), satp (Supervisor Address Translation and Protection, Supervisor Address Translation and Protection Register), and for the process number, a separate register is added.

[0026] Optionally, the emulation debugging interface may be UART, JTAG or Ethernet (Ethernet interface).

[0027] Step S2, restoring the trace data into a trace data frame, and obtaining a change sequence of the abnormal state of the processor core after processing and analyzing the trace data frame.

[0028] Optionally, in order to maintain high reliability of data transmission when using unreliable low-speed communication interfaces such as UART, JTAG or Ethernet to transmit trace data to the host, the trace data can be encoded for reliability before being transmitted to the host. Coding schemes such as error correction codes, redundant codes or simple check codes can be used to encode the trace data from the perspective of the bit stream.

[0029] After receiving the tracking data, the host machine restores the tracking data into a tracking data frame, and uses a decoding method corresponding to the tracking data encoding method to decode the tracking data frame to obtain a data frame stream, and restores the key state of each abnormal point on the processor core through the obtained data frame.

[0030] The embodiment of the present invention encodes the tracking data in order to reduce the probability of bit errors occurring in data transmission and to increase the reliability of the transmission process of the present invention.

[0031] Furthermore, in order to better locate the problem, the operating system running on the target system to be tested reads the value of the exception count (evcounter) register before entering exception handling, interrupt handling, and system calls. In this way, the hardware tracking information can be aligned with some log information of the software. In addition, the operating system running on the target system to be tested also needs to write the currently running process number to the process number register when the context is switched. When monitoring the processor core exception, these exception-related information can be read from the exception count register and the process number register.

[0032] Furthermore, the state tracking and positioning method in a processor core FPGA simulation process provided by an embodiment of the present invention may also include the following steps: Reading a clock cycle interval between two adjacent tracking data, when the clock cycle interval is greater than a specified cycle threshold, outputting a prompt message indicating a software error that a long-term lock interruption may occur, such as through a human-computer interaction method such as a graphical user interface; Counting the time when a specific interruption occurs, if the specific interruption does not occur in the tracking data stream for more than a specified time, outputting a prompt message that the specific interruption may be lost, such as through a human-computer interaction method such as a graphical user interface; or, counting the number of times a specific interruption occurs, if the number of times a specific interruption occurs in the tracking data stream does not exceed a specified number, outputting a prompt message that the specific interruption may be lost, such as through a human-computer interaction method such as a graphical user interface; The process number and the address space identifier in the tracking data are read, and if it is determined that the values ​​of two adjacent tracking data are different, prompt information of the process number of the context switch and the new task is outputted through a human-computer interaction method such as a graphical user interface.

[0033] like Figure 2 and Figure 3 As shown, in order to implement the state tracking and positioning method in the processor core FPGA simulation process provided by the embodiment of the present invention, the embodiment of the present invention provides a state tracking and positioning system in the processor core FPGA simulation process, the state tracking and positioning system includes a target system to be tested 101, the target system to be tested 101 is connected to a host machine 102 through a simulation debugging interface, and a processor core 1011 to be verified and a key state tracker 1012 implemented by FPGA are set in the target system to be tested 101. A receiving program module 1021 and a positioning analysis module 1022 are running on the host machine 102.

[0034] Optionally, the target system under test 101 may have one or more processor cores 1011. When there are multiple processor cores 1011 in the target system under test 101, a key state tracker 1012 may be set in the target system under test 101 to monitor the key states of multiple processor cores 1011 at the same time, or the same number of key state trackers 1012 as the number of processor cores 1011 may be set, and one processor core 1011 corresponds to one key state tracker 1012 to monitor the key state of the corresponding processor core 1011.

[0035] The critical state of the processor core 1011 may be an abnormal state entered by the processor core when program execution is interrupted, execution is abnormal under normal circumstances, system calls, or internal exceptions defined by the microarchitecture. The critical state tracker 1012 monitors the critical state of the processor core 1011 to obtain tracking data.

[0036] The key state tracker 1012 outputs the tracking data to the host machine 102 through the simulation debugging interface. Optionally, the simulation debugging interface may be UART, JTAG or Ethernet.

[0037] The host machine 102 runs a receiving program module 1021, which restores the received data stream into tracking data frames. These tracking data frames can be handed over to the positioning analysis module 1022 for processing. After processing and analysis, the change sequence of the abnormal state of each processor core 1011 in the system is obtained. The positioning analysis module 1022 constructs the state change process of the processor, restores the key change sequence in the program execution process on each hardware thread, and corresponds to the software log of the operating system, which can effectively assist in locating problems of complex programs.

[0038] Further, in order to better locate the problem, the operating system running on the target system to be tested 101 reads the value of the exception count register before entering exception handling, interrupt handling, and system call. In this way, the tracking information of the hardware can be aligned with some log information of the software. In addition, the operating system running on the target system to be tested 101 also needs to write the currently running process number into the process number register when the context is switched. When monitoring the processor core exception, the key state tracker 1012 can read these exception-related information from the exception count register and the process number register.

[0039] Optionally, in order to maintain high reliability of data transmission when using an unreliable low-speed communication interface such as UART, JTAG or Ethernet to transmit trace data to the host machine 102, such as Figure 4 As shown, an encoder is added to the key state tracker 1012, and the encoder is used to perform reliability encoding on the tracking data to enhance the reliability of the tracking data transmission. The encoder can use coding schemes such as error correction code, redundant code or simple check code to encode the tracking data from the perspective of the bit stream, reduce the probability of bit errors in data transmission, and increase the reliability of the transmission process of the present invention.

[0040] Alternatively, if Figure 4 As shown, an output controller may be further added to the key state tracker 1012 , and the output controller is used to select whether to temporarily store the tracking data in a DDR memory (Double Data Rate Synchronous Dynamic RandomAccess Memory) or directly output the tracking data to the host machine 102 .

[0041] like Figure 4 As shown, the key state tracker 1012 is composed of a core tracker, an encoder, and an output controller. The core tracker completes the tracking of the key state of each processor core 1011 in the system on chip (SoC). The key state may include the program counter value, system status value, general register, exception reason, process number, address space identifier, etc. when an exception occurs. For example, in a RISCV processor, the registers corresponding to these values ​​are mepc, mstatus, GPR, mcause, satp, and for the process number, a separate register is added.

[0042] like Figure 5 As shown, the core tracker is the core component for tracking key states on each processor core 1011, and the core tracker consists of a general register traverser, a special purpose register reader, a custom register reader, a first-in-first-out queue memory, and a frame packing module.

[0043] Among them, the general register traverser is used to read and save the data saved to the general register when the operating system handles an exception. The general register traverser maintains a state machine for saving the value of each general register read for the first time after the exception occurs to the first-in-first-out queue memory, and the general register traverser gradually obtains the value of the general register through multiple cycles.

[0044] General registers are indispensable in the process of program flow control and are usually an important part of the context in a computer operating system. However, in a high-performance processor, due to the presence of multiple execution pipelines, register files are read and written simultaneously. If all general registers are read in one cycle, too many reading ports are required, which is almost impossible to achieve. Therefore, the present invention adopts a traversal method, that is, gradually obtaining the values ​​of general registers through multiple cycles, rather than reading the values ​​of general registers at one time.

[0045] Considering that when exceptions defined by the instruction set architecture occur, the operating system generally saves the general registers when handling these exceptions, and there must be a process of reading the general registers. Therefore, after receiving the architecture-defined exception event, the general register traverser monitors the reading port of the general register, and maintains a state machine in the general register traverser to save the value of each general register read for the first time after the exception occurs to the first-in-first-out queue memory. When all the general register values ​​are saved, the traversal is completed.

[0046] Among them, the special purpose register reader is used to read and save the data saved to the special purpose register (SPR) when the operating system handles an exception. These registers include the program counter value, system status, exception cause, clock cycle count, address space identifier value, etc. when the exception occurs. For example, in the RISCV processor, the registers corresponding to these values ​​are mepc, mstatus, mcause, satp, etc. The read values ​​are saved in the first-in-first-out queue memory.

[0047] The custom register reader is used to read and save the data saved to the custom register when the operating system handles an exception. The custom register includes at least a count value each time an exception is triggered and the process number of the currently running task. The exception count register counts each time an exception is triggered, and the process number register is used to save the process number of the currently running task.

[0048] The first-in-first-out queue memory is used to store the values ​​saved by the general register traverser, the special purpose register reader and the custom register reader.

[0049] The write port of the FIFO queue memory is controlled by the general register traverser, the special purpose register reader, and the custom register reader, and the read port is controlled by the frame packing module. That is, the general register traverser, the special purpose register reader, and the custom register reader write the value of the general register, the value of the special purpose register, and the custom register value to the FIFO queue memory through the write port of the FIFO queue memory, and these values ​​are read out by the frame packing module through the read port of the FIFO queue memory in a FIFO manner.

[0050] Preferably, in order to enable the first-in-first-out queue memory to provide more read and write ports to avoid read and write conflicts, in an embodiment of the present invention, multiple random access memories (RAMs) are used to splice into a large-bit-width first-in-first-out queue memory. The random access memory can adopt a simple dual-port random access memory, and the depth of the first-in-first-out queue memory can be relatively shallow, that is, the first-in-first-out queue memory can store a smaller number of data items.

[0051] The frame packing module is used to pack the data stored in the first-in-first-out queue memory into a data frame according to a fixed-order frame format. The data in the data frame is arranged in a fixed order, preferably in the order of the hardware thread number where the exception occurs, the clock cycle count value, the custom register value, the address space identifier value, the exception reason, the general register value, etc.

[0052] like Figure 3 As shown, the processing and analysis tool of the host machine 102 provided in the embodiment of the present invention is divided into two parts: a receiving program module 1021 and a positioning and analysis module 1022. The receiving program module 1021 receives the tracking data packet from UART / JTAG / Ethernet. Optionally, the data packet is sent according to Figure 4 The decoding method corresponding to the encoding method used by the encoder in the key state tracker is decoded. After decoding, the tracked data frame can be obtained. The positioning analysis module 1022 recovers the key state of each abnormal point on the processor core through the obtained data frame stream.

[0053] Furthermore, the positioning analysis module 1022 can also implement the following functions: The positioning analysis module 1022 reads the clock cycle interval between two adjacent tracking data, and when the clock cycle interval is greater than a specified cycle threshold, a prompt message indicating a software error that a long-term lock interruption may occur is outputted through a human-computer interaction method such as a graphical user interface.

[0054] The positioning analysis module 1022 counts the time when a specific interruption occurs. If the specific interruption does not occur in the tracking data stream for more than a specified time, a prompt message indicating that the specific interruption may be lost is outputted through a human-machine interaction method such as a graphical user interface; or, counts the number of times a specific interruption occurs. If the occurrence of the specific interruption in the tracking data stream does not exceed a specified number of times, a prompt message indicating that the specific interruption may be lost is outputted through a human-machine interaction method such as a graphical user interface.

[0055] Specifically, each interrupt has a type identifier to distinguish different interrupt sources or causes. The type identifier of a specific interrupt can be used to identify the time and number of times the specific interrupt occurs. If an interrupt does not occur for a long time, it may be because the interrupt was accidentally masked, there is a problem with the interrupt handler, or the interrupt processing process is blocked due to hardware failure.

[0056] The location analysis module 1022 reads the process ID and address space identifier in the tracking data, and if it is determined that the values ​​of two adjacent tracking data are different, a prompt message of the process ID of the context switch and the new task is outputted through a human-computer interaction method such as a graphical user interface.

[0057] like Figure 6 As shown, an embodiment of the present invention further provides an electronic device, including a processor 201, a communication interface 202, a memory 203 and a communication bus 204, wherein the processor 201, the communication interface 202 and the memory 203 communicate with each other through the communication bus 204. The memory 203 is used to store computer programs. When the processor 201 is used to execute the program stored in the memory 203, the state tracking and positioning method in the processor core FPGA simulation process provided by the embodiment of the present invention is implemented.

[0058] In addition, an embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a computer, the state tracking and positioning method in the processor core FPGA simulation process provided by the embodiment of the present invention is implemented.

[0059] The computer storage medium of the embodiment of the present invention can adopt any combination of one or more computer-readable media. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium can be, for example, but not limited to, a system, device or component of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of computer-readable storage media include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this article, a computer-readable storage medium can be any tangible medium containing or storing a program, which can be used by an instruction execution system, a device or a device or used in combination with it.

[0060] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, which carry computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0061] The program code embodied on the computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, radio frequency (RF), etc., or any suitable combination of the foregoing.

[0062] Computer program code for performing the operations of the present invention may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0063] The embodiment of the present invention aims at the problem that the simulation debugging of the processor core on the existing FPGA is difficult. A key state tracker is added in the processor core. The key state tracker uses the exceptions of the processor core, such as interrupts, exceptions in the usual sense and system calls, and internal exceptions defined by the micro-architecture as tracking points, and cooperates with the analysis and processing of the operating system kernel and the host machine to achieve tracking and restoration of the key state changes of the processor core. Since the present invention tracks the exceptions of the processor core through the key state tracker in the processor core, it is not necessary to track the program execution flow, which greatly reduces the amount of tracking data. Therefore, the amount of tracking data is much lower than the existing tracking method based on branch instructions, and the difficulty of tracking implementation is also reduced.

[0064] The embodiment of the present invention abandons the complex branch instruction-based tracking method in the prior art, tracks the key states within the processor core, constructs the state change process of the processor core through the analysis software on the host machine, restores the key change sequence in the program execution process on each hardware thread, and corresponds to the software log of the operating system. It can effectively assist in locating problems in complex programs and provide analysis data for complex problems.

[0065] It should be noted that the embodiments described in the present invention are only some embodiments of the present invention, rather than all embodiments. The components of the embodiments of the present invention generally described and shown in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the above detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present invention.

[0066] The words "first, second, third, etc." or module A, module B, module C and the like in the specification and claims are used only to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that the specific order or sequence can be interchanged where permitted so that the embodiments of the invention described herein can be implemented in an order other than that illustrated or described herein.

[0067] In the above description, the numbers representing the steps involved do not necessarily mean that the steps will be executed. Intermediate steps may be included or replaced by other steps. The order of the previous and next steps may be interchanged or executed simultaneously if permitted.

[0068] The term "comprising" as used in the description and claims should not be interpreted as being limited to what is listed thereafter; it does not exclude other elements or steps. Therefore, it should be interpreted as specifying the presence of the features, integers, steps or components mentioned, but does not exclude the presence or addition of one or more other features, integers, steps or components and groups thereof. Therefore, the expression "a device comprising means A and B" should not be limited to a device consisting of components A and B only.

[0069] The "one embodiment" or "embodiment" mentioned in this specification means that the specific features, structures or characteristics described in conjunction with the embodiment are included in at least one embodiment of the present invention. Therefore, the terms "in one embodiment" or "in an embodiment" appearing in various places in this specification do not necessarily refer to the same embodiment, but may refer to the same embodiment. In addition, in various embodiments of the present invention, if there is no special explanation and logical conflict, the terms and / or descriptions between different embodiments are consistent and can be referenced to each other, and the technical features in different embodiments can be combined to form a new embodiment according to their internal logical relationship.

[0070] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may also include more other equivalent embodiments without departing from the concept of the present invention, all of which belong to the scope of protection of the present invention.

Claims

1. A state tracking and positioning method in a processor core FPGA simulation process, characterized in that: include: Monitor the key state of the processor core to be verified on the target system to be tested to obtain tracking data, and transmit it to the host machine through the simulation debugging interface, wherein the key state of the processor core at least includes the abnormal state entered by the processor core when the program execution is interrupted, the execution is abnormal, the system is called, and the internal abnormality defined by the micro-architecture; The tracing data is restored into tracing data frames, and the tracing data frames are processed and analyzed to obtain a change sequence of the abnormal state of the processor core.

2. The state tracking and positioning method in the processor core FPGA simulation process according to claim 1 is characterized in that: The method further comprises: Reliability encoding of the tracking data is performed and then transmitted to the host machine; The tracking data is decoded using a decoding method corresponding to the reliability coding to obtain a data frame stream, and the key state of each abnormal point on the processor core is restored through the obtained data frame.

3. A state tracking and positioning system in a processor core FPGA simulation process, characterized in that: include: A target system to be tested, wherein the target system to be tested is connected to a host machine via a simulation debugging interface, wherein a processor core to be verified and a key state tracker implemented by FPGA are arranged in the target system to be tested, and a receiving program module and a positioning analysis module are running on the host machine; The key state tracker monitors the key state of the processor core to obtain tracking data and then outputs it to the host machine through the simulation debugging interface, wherein the key state of the processor core at least includes the abnormal state entered by the processor core when program execution is interrupted, execution is abnormal, system call, or internal abnormality defined by the micro-architecture; The receiving program module restores the tracking data output by the key state tracker into a tracking data frame, and the positioning analysis module processes and analyzes the tracking data frame to obtain a change sequence of the abnormal state of the processor core.

4. The state tracking and positioning system in the processor core FPGA simulation process according to claim 3, characterized in that: The key state tracker also includes an encoder; The encoder is used for performing reliability encoding on the tracking data to enhance the reliability of the tracking data transmission.

5. The state tracking and positioning system in the processor core FPGA simulation process according to claim 3, characterized in that: The critical state tracker also includes an output controller; The output controller is used to select whether to temporarily store the tracking data in a DDR memory or directly output the tracking data to the host machine.

6. The state tracking and positioning system in the process of processor core FPGA simulation according to any one of claims 3 to 5, characterized in that: The key state tracker further includes a core tracker, which is used to monitor the key state of the processor core to obtain tracking data; the core tracker includes: A general register traverser is used to read and save data saved to the general register when the operating system handles an exception; the general register traverser maintains a state machine for saving the value of each general register read for the first time after the exception occurs to a first-in-first-out queue memory, and the general register traverser gradually obtains the value of the general register through multiple cycles; A special purpose register reader for reading and saving data saved to special purpose registers when the operating system handles an exception; A custom register reader, used to read and save data saved to the custom register when the operating system handles an exception, wherein the custom register includes at least a count value each time an exception is triggered and a process number of the currently running task; The first-in-first-out queue memory is used to store the values ​​saved by the general register walker, the special purpose register reader and the custom register reader; The frame packing module is used to pack the data stored in the first-in-first-out queue memory into data frames according to a fixed-order frame format.

7. The state tracking and positioning system in the processor core FPGA simulation process according to claim 3, characterized in that: The positioning analysis module is also used to read the clock cycle interval between two adjacent tracking data, and when the clock cycle interval is greater than a specified cycle threshold, output a prompt message of a software error that may occur during a long lock interruption.

8. The state tracking and positioning system in the processor core FPGA simulation process according to claim 3, characterized in that: The positioning analysis module is also used to count the time when a specific interruption occurs. If the specific interruption does not appear in the tracking data stream for more than a specified time, a prompt message that the specific interruption may be lost is output; or, to count the number of times a specific interruption occurs. If the number of times the specific interruption appears in the tracking data stream does not exceed a specified number, a prompt message that the specific interruption may be lost is output.

9. The state tracking and positioning system in the processor core FPGA simulation process according to claim 3, characterized in that: The positioning analysis module is also used to read the process number and address space identifier in the tracking data, and if it is determined that the values ​​of two adjacent tracking data are different, output prompt information of the context switch and the process number of the new task.

10. The state tracking and positioning system in the processor core FPGA simulation process according to claim 3, characterized in that: The operating system running on the processor core reads the exception count register before entering exception processing, interrupt processing or system call.

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