Modeling method, system and device for bus capacitor

Abstract

The invention discloses a modeling method, system and device of a bus capacitor, and relates to the field of electromagnetic compatibility simulation, an equivalent circuit model of the bus capacitor is established, the equivalent circuit model comprises a plurality of devices, each device is correspondingly provided with an unknown parasitic parameter, characteristic information representing impedance characteristic conditions between ports of the bus capacitor is obtained, and the characteristic information is used for calculating the impedance characteristic conditions of the ports of the bus capacitor. Modeling parasitic parameters corresponding to the unknown parasitic parameters are obtained based on the feature information and a preset parameter determination strategy, and the equivalent circuit model after the corresponding modeling parasitic parameters are set for the devices is determined as a modeling result of the bus capacitor. Therefore, the characteristic information corresponding to the impedance characteristic condition between the ports is introduced, and the modeling parasitic parameters can be reliably determined in combination with the equivalent circuit model, so that the modeling accuracy of the bus capacitor is improved, the electromagnetic compatibility of an electrical device including the bus capacitor can be better determined subsequently, and practical application is facilitated.

Description

Technical Field

[0001] The present invention relates to the technical field of electromagnetic compatibility simulation, and in particular to a modeling method, system and device for a busbar capacitor. Background Art

[0002] Bus capacitors are usually installed on power buses. They balance the reactive power in the system by storing and releasing electrical energy to improve voltage stability, reduce power losses, suppress voltage fluctuations and harmonics, and improve power supply reliability. They are currently widely used in substations, distribution networks, electric vehicles, and industrial power systems.

[0003] Electromagnetic compatibility simulation can analyze the performance of electrical devices including bus capacitors in an electromagnetic environment by simulating electromagnetic interference and electromagnetic sensitivity, and predict the electromagnetic compatibility performance of electrical devices to help technicians identify and solve potential problems in the design stage. Specifically, when performing electromagnetic compatibility simulation, it is necessary to first model various devices. The accuracy of device modeling will affect the accuracy of the simulation. As an important component of electrical devices, bus capacitors need to be reliably modeled during electromagnetic compatibility simulation. However, due to process reasons, there are parasitic parameters at each port of the bus capacitor, which brings difficulties to effective modeling. If the parasitic parameters are not accurately determined, the modeling of the bus capacitor is naturally inaccurate, resulting in inaccurate modeling of subsequent electrical devices including bus capacitors. Therefore, how to provide an effective modeling solution for bus capacitors is a problem that needs to be solved urgently. Summary of the invention

[0004] In view of this, the present invention provides a bus capacitor modeling method, system and device, which can reliably determine the modeling parasitic parameters, thereby improving the accuracy of the bus capacitor modeling.

[0005] In order to solve the above technical problems, the present application provides a busbar capacitance modeling method, including:

[0006] Establishing an equivalent circuit model of the bus capacitor; the equivalent circuit model includes a plurality of devices, and each of the devices is correspondingly provided with an unknown parasitic parameter;

[0007] Acquire characteristic information representing impedance characteristics between ports of the bus capacitor;

[0008] Based on the characteristic information and the preset parameter determination strategy, the modeling parasitic parameters corresponding to each of the unknown parasitic parameters are obtained to determine that the equivalent circuit model after setting the corresponding modeling parasitic parameters for each of the devices is the modeling result of the bus capacitor.

[0009] Further, the equivalent circuit model includes a first parasitic resistor, a second parasitic resistor, a third parasitic resistor, a first parasitic inductance, a second parasitic inductance, a third parasitic inductance, a first parasitic capacitor, a second parasitic capacitor and a third parasitic capacitor;

[0010] The first parasitic resistor, the first parasitic inductor and the first parasitic capacitor are connected in series to obtain a first circuit; the second parasitic resistor, the second parasitic inductor and the second parasitic capacitor are connected in series to obtain a second circuit; the third parasitic resistor, the third parasitic inductor and the third parasitic capacitor are connected in series to obtain a third circuit;

[0011] One end of the first circuit is connected to the positive bus, the other end of the first circuit is connected to one end of the second circuit, and the common end of the connections serves as the equivalent grounding end of the bus capacitor, the other end of the second circuit is connected to the negative bus, one end of the third circuit is connected to the positive bus, and the other end of the third circuit is connected to the negative bus;

[0012] The first end of the positive busbar close to the first circuit serves as the equivalent input positive terminal of the busbar capacitor, and the second end of the positive busbar close to the third circuit serves as the equivalent output positive terminal of the busbar capacitor; the first end of the negative busbar close to the second circuit serves as the equivalent output negative terminal of the busbar capacitor, and the second end of the negative busbar close to the third circuit serves as the equivalent output negative terminal of the busbar capacitor.

[0013] Furthermore, the characteristic information includes first characteristic information characterizing the pole-to-ground impedance characteristics of the bus capacitor, and second characteristic information characterizing the inter-pole impedance characteristics of the bus capacitor.

[0014] Further, the characteristic information includes a first impedance test curve of the input positive terminal of the bus capacitor to the ground terminal, and a second impedance test curve of the input positive terminal to the input negative terminal;

[0015] Before obtaining the modeling parasitic parameters corresponding to each of the unknown parasitic parameters based on the characteristic information and the preset parameter determination strategy, the method further includes:

[0016] Determine, according to the first impedance test curve, a first frequency value when the phase angle is -90°, a first impedance amplitude corresponding to the first frequency value, a second frequency value when the phase angle is 0°, and a second impedance amplitude corresponding to the second frequency value;

[0017] Determine, according to the second impedance test curve, a third frequency value when the phase angle is -90°, a third impedance amplitude corresponding to the third frequency value, a fourth frequency value when the phase angle is 0°, and a fourth impedance amplitude corresponding to the fourth frequency value;

[0018] Based on the characteristic information and the preset parameter determination strategy, the modeling parasitic parameters corresponding to each of the unknown parasitic parameters are obtained, including:

[0019] Determine a first resistance value, a first inductance value, and a first capacitance value of the input positive terminal to the ground terminal according to the first frequency value, the first impedance amplitude, the second frequency value, and the second impedance amplitude;

[0020] Determine a second resistance value, a second inductance value, and a second capacitance value of the input positive terminal to the input negative terminal according to the third frequency value, the third impedance amplitude, the fourth frequency value, and the fourth impedance amplitude;

[0021] Based on the first resistance value, the first inductance value, the first capacitance value, the second resistance value, the second inductance value and the second capacitance value, modeling parasitic parameters corresponding to the unknown parasitic parameters of each device in the equivalent circuit model are determined.

[0022] Furthermore, the step of obtaining the first impedance test curve and the second impedance test curve includes:

[0023] The first impedance test curve and the second impedance test curve are respectively obtained by an impedance analyzer.

[0024] Further, determining a first resistance value, a first inductance value, and a first capacitance value of the input positive terminal to the ground terminal according to the first frequency value, the first impedance amplitude, the second frequency value, and the second impedance amplitude includes:

[0025] The first capacitance value of the input positive terminal to the ground terminal is determined according to the first frequency value, the first impedance amplitude and a first preset relationship; the first preset relationship is:

[0026]

[0027] Among them, C P-GND is the first capacitance value, f 1 is the first frequency value, Z 1 is the first impedance amplitude;

[0028] Determine that a first resistance value of the input positive terminal to the ground terminal is equal to the second impedance amplitude;

[0029] The first inductance value of the input positive terminal to the ground terminal is determined according to the first capacitance value, the second frequency value and a second preset relationship; the second preset relationship is:

[0030]

[0031] Among them, L P-GNDis the first inductance value, f 2 is the second frequency value.

[0032] Further, determining a second resistance value, a second inductance value, and a second capacitance value of the input positive terminal to the input negative terminal according to the third frequency value, the third impedance amplitude, the fourth frequency value, and the fourth impedance amplitude includes:

[0033] The second capacitance value of the input positive terminal to the input negative terminal is determined according to the third frequency value, the third impedance amplitude and a third preset relationship; the third preset relationship is:

[0034]

[0035] Among them, C P-N is the second capacitance value, f 3 is the third frequency value, Z 3 is the third impedance amplitude;

[0036] Determine that a second resistance value of the input positive terminal to the input negative terminal is equal to the fourth impedance amplitude;

[0037] The second inductance value of the input positive terminal to the input negative terminal is determined according to the second capacitance value, the fourth frequency value and a fourth preset relationship; the fourth preset relationship is:

[0038]

[0039] Among them, L P-N is the second inductance value, f 4 is the fourth frequency value.

[0040] Further, based on the first resistance value, the first inductance value, the first capacitance value, the second resistance value, the second inductance value and the second capacitance value, determining the modeling parasitic parameters corresponding to the unknown parasitic parameters of each device in the equivalent circuit model includes:

[0041] According to the first resistance value, the first inductance value, the first capacitance value, the second resistance value, the second inductance value, the second capacitance value and a fifth preset relationship, a first resistance parameter, a second resistance parameter, a first capacitance parameter, a second capacitance parameter, a first inductance parameter and a second inductance parameter are determined; the fifth preset relationship is:

[0042]

[0043] Among them, C P-GND is the first capacitance value, R P-GND is the first resistance value, L P-GNDis the first inductance value, C P-N For the second capacitance value, R P-N is the second resistance value, L P-N For the second inductor value, R X is the first resistance parameter, R Y is the second resistance parameter, C X is the first capacitance parameter, C Y is the second capacitance parameter, L X is the first inductance parameter, L Y is the second inductance parameter;

[0044] Determine the modeling parasitic parameter corresponding to the first parasitic resistance as R Y , determine the modeling parasitic parameter corresponding to the first parasitic capacitor as C Y , determine the modeling parasitic parameter corresponding to the first parasitic inductance as L Y ;

[0045] Determine the modeling parasitic parameter corresponding to the second parasitic resistance as R Y , determine the modeling parasitic parameter corresponding to the second parasitic capacitor as C Y , determine the modeling parasitic parameter corresponding to the second parasitic inductance as L Y ;

[0046] Determine the modeling parasitic parameter corresponding to the third parasitic resistor as R X , determine the modeling parasitic parameter corresponding to the third parasitic capacitor as C X , determine the modeling parasitic parameter corresponding to the third parasitic inductance as L X .

[0047] In order to solve the above technical problems, the present application also provides a busbar capacitor modeling system, including:

[0048] A model building unit, used to build an equivalent circuit model of the bus capacitor; the equivalent circuit model includes a plurality of devices, and each of the devices is correspondingly provided with an unknown parasitic parameter;

[0049] An acquisition unit, used to acquire characteristic information representing the impedance characteristics between ports of the bus capacitor;

[0050] A parameter determination unit is used to obtain modeling parasitic parameters corresponding to each of the unknown parasitic parameters based on the characteristic information and a preset parameter determination strategy, so as to determine that the equivalent circuit model after setting the corresponding modeling parasitic parameters for each of the devices is the modeling result of the bus capacitor.

[0051] In order to solve the above technical problems, the present application also provides a busbar capacitance modeling device, comprising:

[0052] Memory for storing computer programs;

[0053] A processor is used to implement the steps of the bus capacitance modeling method as described above when executing the computer program.

[0054] The present application provides a modeling method, system and device for bus capacitors, establishes an equivalent circuit model of bus capacitors, includes multiple devices in the equivalent circuit model and each device is set with unknown parasitic parameters, obtains characteristic information that characterizes the impedance characteristics between ports of the bus capacitor, so as to obtain the modeling parasitic parameters corresponding to each unknown parasitic parameter based on the characteristic information and the preset parameter determination strategy, so as to determine that the equivalent circuit model after setting the corresponding modeling parasitic parameters for each device is the modeling result of the bus capacitor. It can be seen that the application introduces characteristic information corresponding to the impedance characteristics between ports, and the modeling parasitic parameters can be reliably determined in combination with the equivalent circuit model, thereby improving the accuracy of the modeling of the bus capacitor, facilitating the subsequent better determination of the electromagnetic compatibility performance of electrical devices including bus capacitors, ensuring the accuracy of electromagnetic compatibility simulation analysis, and facilitating better improvement of the research and development efficiency of electrical devices and shortening the research and development cycle, which is beneficial to practical application.

[0055] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0057] Figure 1 A flow chart of a busbar capacitor modeling method provided by the present invention;

[0058] Figure 2 A schematic structural diagram of an equivalent circuit model of a busbar capacitor provided by the present invention;

[0059] Figure 3 A schematic diagram of a first impedance test curve provided by the present invention;

[0060] Figure 4 A schematic diagram of a second impedance test curve provided by the present invention;

[0061] Figure 5 A comparison diagram of an impedance amplitude characteristic curve between an input positive terminal and an input negative terminal provided by the present invention;

[0062] Figure 6 A comparison diagram of a phase characteristic curve between a positive input terminal and a negative input terminal provided by the present invention;

[0063] Figure 7 A comparison diagram of an impedance amplitude characteristic curve between an input positive terminal and a ground terminal provided by the present invention;

[0064] Figure 8 A comparison diagram of a phase characteristic curve between an input positive terminal and a ground terminal provided by the present invention;

[0065] Fig. 9 A schematic structural diagram of a busbar capacitor modeling system provided by the present invention;

[0066] Fig.10 A schematic structural diagram of a busbar capacitor modeling device provided by the present invention. DETAILED DESCRIPTION

[0067] The core of the present invention is to provide a bus capacitor modeling method, system and device, which can reliably determine the modeling parasitic parameters, thereby improving the accuracy of the bus capacitor modeling.

[0068] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0069] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0070] Please refer to Figure 1 , Figure 1 A flow chart of a busbar capacitance modeling method provided in the present application.

[0071] The busbar capacitance modeling method includes:

[0072] S11: establishing an equivalent circuit model of the bus capacitor; the equivalent circuit model includes a plurality of devices, and each device is correspondingly provided with an unknown parasitic parameter;

[0073] S12: Acquire characteristic information representing impedance characteristics between ports of bus capacitors;

[0074] S13: obtaining modeling parasitic parameters corresponding to each unknown parasitic parameter based on the characteristic information and the preset parameter determination strategy, so as to determine that the equivalent circuit model after setting the corresponding modeling parasitic parameters for each device is the modeling result of the bus capacitor.

[0075] In this embodiment, considering that the bus capacitor has parasitic parameters at its ports due to process and other reasons, which brings difficulties to the accurate modeling of the bus capacitor, the present application provides a modeling method for the bus capacitor, which introduces characteristic information corresponding to the impedance characteristics between the ports, and combines with the equivalent circuit model to reliably determine the modeling parasitic parameters, thereby improving the modeling accuracy of the bus capacitor.

[0076] First, an equivalent circuit model of the bus capacitor is established, which includes multiple devices. Specifically, considering that under ideal conditions, the circuit model of the bus capacitor only includes capacitors, but due to process manufacturing and other reasons, parasitic resistance and parasitic inductance are inevitably introduced into the circuit model. Therefore, the equivalent circuit model in the present application is essentially obtained by connecting multiple parasitic resistors, parasitic inductors and parasitic capacitors. The specific circuit structure is described in the following embodiments and will not be repeated here.

[0077] Secondly, according to step S12, the characteristic information corresponding to the bus capacitor can be obtained. Specifically, the port-to-port information of the bus capacitor here refers to the area between the input positive terminal and the ground terminal or between the input negative terminal and the ground terminal, and between the input positive terminal and the input negative terminal of the bus capacitor. Finally, based on step S13, the modeling result of the bus capacitor can be obtained, wherein the preset parameter determination strategy is essentially obtained based on the circuit structure design of the equivalent circuit model.

[0078] It is understandable that after obtaining the modeling result of the bus capacitor, other components of the electrical device including the bus capacitor may be further modeled to achieve electromagnetic compatibility simulation modeling of the entire electrical device.

[0079] It should also be noted that, usually, the bus capacitor includes a ground terminal (also known as the GND terminal), an input positive terminal (also known as the P terminal), an input negative terminal (also known as the N terminal) and at least one group of output terminals (any group of output terminals here includes an output positive terminal and an output negative terminal). Depending on the actual application situation, multiple groups of output terminals can be set, such as three groups. The present application does not make any special limitation on the number of groups of output terminals that the bus capacitor includes, that is, the scheme is applicable to bus capacitors of various specifications.

[0080] In summary, the present application provides a modeling method for bus capacitance, which introduces characteristic information corresponding to the impedance characteristics between ports, and combined with the equivalent circuit model, can reliably determine the modeling parasitic parameters, thereby improving the modeling accuracy of the bus capacitance, facilitating the subsequent better determination of the electromagnetic compatibility performance of electrical devices including the bus capacitance, ensuring the accuracy of electromagnetic compatibility simulation analysis, and facilitating better improvement of the R&D efficiency of electrical devices and shortening the R&D cycle, which is conducive to practical application.

[0081] Based on the above embodiments:

[0082] In some embodiments, the equivalent circuit model includes a first parasitic resistor R1, a second parasitic resistor R2, a third parasitic resistor R3, a first parasitic inductor L1, a second parasitic inductor L2, a third parasitic inductor L3, a first parasitic capacitor C1, a second parasitic capacitor C2, and a third parasitic capacitor C3;

[0083] The first parasitic resistor R1, the first parasitic inductor L1 and the first parasitic capacitor C1 are connected in series to obtain a first circuit; the second parasitic resistor R2, the second parasitic inductor L2 and the second parasitic capacitor C2 are connected in series to obtain a second circuit; the third parasitic resistor R3, the third parasitic inductor L3 and the third parasitic capacitor C3 are connected in series to obtain a third circuit;

[0084] One end of the first circuit is connected to the positive bus, the other end of the first circuit is connected to one end of the second circuit and the common end of the connections serves as the equivalent grounding end of the bus capacitor, the other end of the second circuit is connected to the negative bus, one end of the third circuit is connected to the positive bus, and the other end of the third circuit is connected to the negative bus;

[0085] The first end of the positive bus close to the first circuit serves as the equivalent input positive terminal of the bus capacitor, and the second end of the positive bus close to the third circuit serves as the equivalent output positive terminal of the bus capacitor; the first end of the negative bus close to the second circuit serves as the equivalent output negative terminal of the bus capacitor, and the second end of the negative bus close to the third circuit serves as the equivalent output negative terminal of the bus capacitor.

[0086] For details, please refer to Figure 2 , Figure 2 A structural schematic diagram of an equivalent circuit model of a bus capacitor provided by the present invention, wherein, for the convenience of clear illustration, the first end of the positive bus, that is, the equivalent input positive end, is marked as +in, the second end of the positive bus, that is, the equivalent output positive end, is marked as +out, the first end of the negative bus, that is, the equivalent input negative end, is marked as -in, and the second end of the negative bus, that is, the equivalent output negative end, is marked as -out.

[0087] In some embodiments, the characteristic information includes first characteristic information characterizing the pole-to-ground impedance characteristic of the bus capacitor, and second characteristic information characterizing the pole-to-pole impedance characteristic of the bus capacitor.

[0088] In this embodiment, considering that under the structure of the above-mentioned equivalent circuit model, the input positive terminal of the bus capacitor is essentially symmetrical to the ground terminal, and the input negative terminal is essentially symmetrical to the ground terminal, therefore, the first characteristic information here may include information characterizing the impedance characteristics of the input positive terminal of the bus capacitor to the ground terminal, such as a first impedance test curve of the input positive terminal to the ground terminal, or the first impedance test curve is obtained by measuring in advance and then analyzed, so that the processor executing the modeling method directly obtains the first frequency value, the first impedance amplitude, the second frequency value and the second impedance amplitude as the first characteristic information from the processor analyzing the curve, which is not particularly limited here; the first characteristic information may also be information characterizing the input of the bus capacitor. Information on the impedance characteristics of the negative input terminal to the ground terminal, such as a third impedance test curve of the negative input terminal to the ground terminal, or analyzing the curve after obtaining the third impedance test curve by measuring in advance, so that the processor executing the modeling method directly obtains the fifth frequency value when the phase angle is -90°, the fifth impedance amplitude corresponding to the fifth frequency value, the sixth frequency value when the phase angle is 0°, and the sixth impedance amplitude corresponding to the sixth frequency value from the processor that analyzes the curve, and it can be understood that due to the symmetrical structure, from a numerical point of view, the fifth frequency value here is equal to the first frequency value, the fifth impedance amplitude is equal to the first impedance amplitude, the sixth frequency value is equal to the second frequency value, and the sixth impedance amplitude is equal to the second impedance amplitude.

[0089] In some embodiments, the characteristic information includes a first impedance test curve of the input positive terminal of the bus capacitor to the ground terminal, and a second impedance test curve of the input positive terminal to the input negative terminal;

[0090] Before obtaining the modeling parasitic parameters corresponding to each unknown parasitic parameter based on the characteristic information and the preset parameter determination strategy, it also includes:

[0091] Determine, according to the first impedance test curve, a first frequency value when the phase angle is -90°, a first impedance amplitude corresponding to the first frequency value, a second frequency value when the phase angle is 0°, and a second impedance amplitude corresponding to the second frequency value;

[0092] Determine, according to the second impedance test curve, a third frequency value when the phase angle is -90°, a third impedance amplitude corresponding to the third frequency value, a fourth frequency value when the phase angle is 0°, and a fourth impedance amplitude corresponding to the fourth frequency value;

[0093] Based on the characteristic information and the preset parameter determination strategy, the modeling parasitic parameters corresponding to each unknown parasitic parameter are obtained, including:

[0094] Determine a first resistance value, a first inductance value, and a first capacitance value from the input positive terminal to the ground terminal according to the first frequency value, the first impedance amplitude, the second frequency value, and the second impedance amplitude;

[0095] Determine a second resistance value, a second inductance value, and a second capacitance value of the input positive terminal to the input negative terminal according to the third frequency value, the third impedance amplitude, the fourth frequency value, and the fourth impedance amplitude;

[0096] Based on the first resistance value, the first inductance value, the first capacitance value, the second resistance value, the second inductance value and the second capacitance value, modeling parasitic parameters corresponding to the unknown parasitic parameters of each device in the equivalent circuit model are determined.

[0097] Specifically, the above settings can reliably determine the modeling parasitic parameters of each device in the equivalent circuit model, and then determine that the equivalent circuit model after setting the corresponding modeling parasitic parameters for each device is the modeling result of the bus capacitor.

[0098] In some embodiments, the steps of obtaining the first impedance test curve and the second impedance test curve include:

[0099] The first impedance test curve and the second impedance test curve are respectively obtained by an impedance analyzer.

[0100] Specifically, the first impedance test curve and the second impedance test curve can be reliably measured by the impedance analyzer. Please refer to Figure 3 , Figure 3 This is a schematic diagram of a first impedance test curve provided by the present invention. It should be noted that: Figure 3 The blue line is the impedance amplitude characteristic curve between the input positive terminal and the ground terminal, and the yellow line is the phase characteristic curve; please refer to Figure 4 , Figure 4 A schematic diagram of a second impedance test curve provided by the present invention, Figure 4 The blue line in the middle is the impedance amplitude characteristic curve between the positive input terminal and the negative input terminal and the yellow line is the phase characteristic curve.

[0101] In some embodiments, determining a first resistance value, a first inductance value, and a first capacitance value from the input positive terminal to the ground terminal according to the first frequency value, the first impedance amplitude, the second frequency value, and the second impedance amplitude includes:

[0102] The first capacitance value between the input positive terminal and the ground terminal is determined according to the first frequency value, the first impedance amplitude and the first preset relationship; the first preset relationship is:

[0103]

[0104] Among them, C P-GND is the first capacitance value, f 1 is the first frequency value, Z1 is the first impedance amplitude;

[0105] Determine that a first resistance value of the input positive terminal to the ground terminal is equal to a second impedance amplitude;

[0106] The first inductance value between the input positive terminal and the ground terminal is determined according to the first capacitance value, the second frequency value and the second preset relationship; the second preset relationship is:

[0107]

[0108] Among them, L P-GND is the first inductance value, f 2 is the second frequency value.

[0109] It should also be noted that the second preset relationship is designed based on the RLC resonance principle.

[0110] In some embodiments, determining a second resistance value, a second inductance value, and a second capacitance value of the input positive terminal to the input negative terminal according to the third frequency value, the third impedance amplitude, the fourth frequency value, and the fourth impedance amplitude includes:

[0111] The second capacitance value between the input positive terminal and the input negative terminal is determined according to the third frequency value, the third impedance amplitude and the third preset relationship; the third preset relationship is:

[0112]

[0113] Among them, C P-N is the second capacitance value, f 3 is the third frequency value, Z 3 is the third impedance amplitude;

[0114] Determine that a second resistance value of the input positive terminal to the input negative terminal is equal to a fourth impedance amplitude;

[0115] The second inductance value of the input positive terminal to the input negative terminal is determined according to the second capacitance value, the fourth frequency value and the fourth preset relationship; the fourth preset relationship is:

[0116]

[0117] Among them, L P-N is the second inductance value, f 4 is the fourth frequency value.

[0118] It should also be noted that the fourth preset relationship is designed based on the RLC resonance principle.

[0119] In some embodiments, based on the first resistance value, the first inductance value, the first capacitance value, the second resistance value, the second inductance value, and the second capacitance value, determining the modeling parasitic parameters corresponding to the unknown parasitic parameters of each device in the equivalent circuit model includes:

[0120] According to the first resistance value, the first inductance value, the first capacitance value, the second resistance value, the second inductance value, the second capacitance value and the fifth preset relationship, the first resistance parameter, the second resistance parameter, the first capacitance parameter, the second capacitance parameter, the first inductance parameter and the second inductance parameter are determined; the fifth preset relationship is:

[0121]

[0122] Among them, C P-GND is the first capacitance value, R P-GND is the first resistance, L P-GND is the first inductance value, C P-N is the second capacitance value, R P-N is the second resistance, L P-N is the second inductance value, R X is the first resistance parameter, R Y is the second resistance parameter, C X is the first capacitance parameter, C Y is the second capacitance parameter, L X is the first inductance parameter, L Y is the second inductance parameter;

[0123] Determine the modeling parasitic parameter corresponding to the first parasitic resistor R1 as R Y , determine the modeling parasitic parameter corresponding to the first parasitic capacitor C1 as C Y , determine the modeling parasitic parameter corresponding to the first parasitic inductance L1 as L Y ;

[0124] Determine the modeling parasitic parameter corresponding to the second parasitic resistor R2 as R Y , determine the modeling parasitic parameter corresponding to the second parasitic capacitor C2 as C Y , determine the modeling parasitic parameter corresponding to the second parasitic inductance L2 as L Y ;

[0125] Determine the modeling parasitic parameter corresponding to the third parasitic resistor R3 as R X , determine the modeling parasitic parameter corresponding to the third parasitic capacitor C3 as C X , determine the modeling parasitic parameter corresponding to the third parasitic inductance L3 as L X .

[0126] Specifically, as an explanation of the accuracy of the modeling results of the bus capacitance obtained in the present application, a simulation is performed for the modeling results of the bus capacitance obtained in the present application to respectively determine the fourth impedance characteristic curve (including the impedance amplitude characteristic curve and the phase characteristic curve) between the equivalent input positive terminal and the equivalent ground terminal, and the fifth impedance characteristic curve (including the impedance amplitude characteristic curve and the phase characteristic curve) between the equivalent input positive terminal and the equivalent input negative terminal; please first refer to Figure 5 , Figure 5 A comparison diagram of the impedance amplitude characteristic curve between the input positive terminal and the input negative terminal provided by the present invention, wherein the blue line is the impedance amplitude characteristic curve between the input positive terminal and the input negative terminal obtained by simulation according to the modeling result of the bus capacitor, and the red line is the impedance amplitude characteristic curve obtained after actual measurement of the input positive terminal and the input negative terminal of the bus capacitor; please refer to Figure 6 , Figure 6 A comparison diagram of a phase characteristic curve between an input positive terminal and an input negative terminal provided by the present invention, wherein the blue line is a phase characteristic curve between the input positive terminal and the input negative terminal obtained by simulation according to the modeling result of the bus capacitor, and the red line is a phase characteristic curve obtained after actual measurement of the input positive terminal and the input negative terminal of the bus capacitor;

[0127] Please refer to Figure 7 , Figure 7 A comparison diagram of the impedance amplitude characteristic curve between the input positive terminal and the ground terminal provided by the present invention, wherein the blue line is the impedance amplitude characteristic curve between the equivalent input positive terminal and the equivalent ground terminal obtained by simulation according to the modeling result of the bus capacitor, and the red line is the impedance amplitude characteristic curve obtained after actual measurement of the input positive terminal and the ground terminal of the bus capacitor; please refer to Figure 8 , Figure 8 A comparison diagram of the phase characteristic curve between the input positive terminal and the ground terminal provided by the present invention, wherein the blue line is the phase characteristic curve between the equivalent input positive terminal and the equivalent ground terminal simulated according to the modeling result of the bus capacitor, and the red line is the phase characteristic curve obtained after actual measurement of the input positive terminal and the ground terminal of the bus capacitor.

[0128] Combination Figures 5 to 8 It can be seen from the comparison diagram that the characteristic curve obtained according to the modeling result of the bus capacitor is highly consistent with the characteristic curve obtained by actual measurement, which proves the effectiveness of the modeling scheme of the bus capacitor provided in this application.

[0129] Please refer to Fig. 9 , Fig. 9 A schematic structural diagram of a busbar capacitor modeling system provided by the present invention.

[0130] The bus capacitor modeling system includes:

[0131] The model building unit 21 is used to build an equivalent circuit model of the bus capacitor; the equivalent circuit model includes multiple devices, and each device is correspondingly provided with unknown parasitic parameters;

[0132] An acquisition unit 22 is used to acquire characteristic information representing the impedance characteristics between ports of the bus capacitor;

[0133] The parameter determination unit 23 is used to obtain the modeling parasitic parameters corresponding to each unknown parasitic parameter based on the characteristic information and the preset parameter determination strategy, so as to determine that the equivalent circuit model after setting the corresponding modeling parasitic parameters for each device is the modeling result of the bus capacitor.

[0134] For an introduction to the bus capacitor modeling system provided in the present application, please refer to the above-mentioned embodiment of the bus capacitor modeling method, which will not be repeated here.

[0135] In some embodiments, the characteristic information includes a first impedance test curve of the input positive terminal of the bus capacitor to the ground terminal, and a second impedance test curve of the input positive terminal to the input negative terminal;

[0136] The busbar capacitance modeling system further includes:

[0137] A first determination unit, used for determining, before the parameter determination unit 23, according to the first impedance test curve, a first frequency value when the phase angle is -90°, a first impedance amplitude corresponding to the first frequency value, a second frequency value when the phase angle is 0°, and a second impedance amplitude corresponding to the second frequency value;

[0138] A second determination unit is used to determine, according to the second impedance test curve, a third frequency value when the phase angle is -90°, a third impedance amplitude corresponding to the third frequency value, a fourth frequency value when the phase angle is 0°, and a fourth impedance amplitude corresponding to the fourth frequency value;

[0139] The parameter determination unit 23 comprises:

[0140] A first intermediate value determining unit, configured to determine a first resistance value, a first inductance value, and a first capacitance value of the input positive terminal to the ground terminal according to the first frequency value, the first impedance amplitude, the second frequency value, and the second impedance amplitude;

[0141] A second intermediate value determining unit, configured to determine a second resistance value, a second inductance value, and a second capacitance value of the input positive terminal to the input negative terminal according to the third frequency value, the third impedance amplitude, the fourth frequency value, and the fourth impedance amplitude;

[0142] A modeling parasitic parameter determination unit is used to determine the modeling parasitic parameters corresponding to the unknown parasitic parameters of each device in the equivalent circuit model based on the first resistance value, the first inductance value, the first capacitance value, the second resistance value, the second inductance value and the second capacitance value.

[0143] In some embodiments, the first intermediate value determining unit includes:

[0144] The first capacitance value determining unit is used to determine a first capacitance value of the input positive terminal to the ground terminal according to the first frequency value, the first impedance amplitude and a first preset relationship; the first preset relationship is:

[0145]

[0146] Among them, C P-GND is the first capacitance value, f 1 is the first frequency value, Z 1 is the first impedance amplitude;

[0147] A first resistance determination unit, used for determining that a first resistance of the input positive terminal to the ground terminal is equal to the second impedance amplitude;

[0148] The first inductance value determining unit is used to determine a first inductance value of the input positive terminal to the ground terminal according to the first capacitance value, the second frequency value and a second preset relationship; the second preset relationship is:

[0149]

[0150] Among them, L P-GND is the first inductance value, f 2 is the second frequency value.

[0151] In some embodiments, the second intermediate value determining unit includes:

[0152] The second capacitance value determining unit is used to determine a second capacitance value of the input positive terminal to the input negative terminal according to the third frequency value, the third impedance amplitude and a third preset relationship; the third preset relationship is:

[0153]

[0154] Among them, C P-N is the second capacitance value, f 3 is the third frequency value, Z 3 is the third impedance amplitude;

[0155] A second resistance determination unit, used for determining that a second resistance of the input positive terminal to the input negative terminal is equal to the fourth impedance amplitude;

[0156] The second inductance value determining unit is used to determine the second inductance value of the input positive terminal to the input negative terminal according to the second capacitance value, the fourth frequency value and a fourth preset relationship; the fourth preset relationship is:

[0157]

[0158] Among them, L P-N is the second inductance value, f 4 is the fourth frequency value.

[0159] In some embodiments, the modeling parasitic parameter determination unit includes:

[0160] a parameter determination reference unit, configured to determine a first resistance parameter, a second resistance parameter, a first capacitance parameter, a second capacitance parameter, a first inductance parameter, and a second inductance parameter according to the first resistance value, the first inductance value, the first capacitance value, the second resistance value, the second inductance value, the second capacitance value, and a fifth preset relationship; the fifth preset relationship is:

[0161]

[0162] Among them, C P-GND is the first capacitance value, R P-GND is the first resistance value, L P-GND is the first inductance value, C P-N For the second capacitance value, R P-N is the second resistance value, L P-N For the second inductor value, R X is the first resistance parameter, R Y is the second resistance parameter, C X is the first capacitance parameter, C Y is the second capacitance parameter, L X is the first inductance parameter, L Y is the second inductance parameter;

[0163] The first parasitic parameter determination subunit is used to determine the modeling parasitic parameter corresponding to the first parasitic resistor R1 as R Y , determine the modeling parasitic parameter corresponding to the first parasitic capacitor C1 as C Y , determine the modeling parasitic parameter corresponding to the first parasitic inductance L1 as L Y ;

[0164] The second parasitic parameter determination subunit is used to determine the modeling parasitic parameter corresponding to the second parasitic resistor R2 as R Y , determine the modeling parasitic parameter corresponding to the second parasitic capacitor C2 as C Y , determine the modeling parasitic parameter corresponding to the second parasitic inductance L2 as L Y ;

[0165] The third parasitic parameter determination subunit is used to determine the modeling parasitic parameter corresponding to the third parasitic resistor R3 as R X , determine the modeling parasitic parameter corresponding to the third parasitic capacitor C3 as C X , determine the modeling parasitic parameter corresponding to the third parasitic inductance L3 as L X .

[0166] Please refer to Fig.10 , Fig.10 A schematic structural diagram of a busbar capacitor modeling device provided by the present invention.

[0167] The busbar capacitor modeling device includes:

[0168] A memory 31, used for storing computer programs;

[0169] The processor 32 is used to implement the steps of the bus capacitance modeling method as described above when executing the computer program.

[0170] For an introduction to the bus capacitor modeling device provided in the present application, please refer to the above-mentioned embodiment of the bus capacitor modeling method, which will not be repeated here.

[0171] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts refer to the method part description. Relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements that are not clearly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements limited by the sentence "including one" do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.

[0172] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A busbar capacitance modeling method, characterized in that: include: Establishing an equivalent circuit model of the bus capacitor; the equivalent circuit model includes a plurality of devices, and each of the devices is correspondingly provided with an unknown parasitic parameter; Acquire characteristic information representing impedance characteristics between ports of the bus capacitor; Based on the characteristic information and the preset parameter determination strategy, the modeling parasitic parameters corresponding to each of the unknown parasitic parameters are obtained to determine that the equivalent circuit model after setting the corresponding modeling parasitic parameters for each of the devices is the modeling result of the bus capacitor.

2. The busbar capacitance modeling method according to claim 1, characterized in that: The equivalent circuit model includes a first parasitic resistor, a second parasitic resistor, a third parasitic resistor, a first parasitic inductance, a second parasitic inductance, a third parasitic inductance, a first parasitic capacitor, a second parasitic capacitor and a third parasitic capacitor; The first parasitic resistor, the first parasitic inductor and the first parasitic capacitor are connected in series to obtain a first circuit; the second parasitic resistor, the second parasitic inductor and the second parasitic capacitor are connected in series to obtain a second circuit; the third parasitic resistor, the third parasitic inductor and the third parasitic capacitor are connected in series to obtain a third circuit; One end of the first circuit is connected to the positive bus, the other end of the first circuit is connected to one end of the second circuit, and the common end of the connections serves as the equivalent grounding end of the bus capacitor, the other end of the second circuit is connected to the negative bus, one end of the third circuit is connected to the positive bus, and the other end of the third circuit is connected to the negative bus; The first end of the positive busbar close to the first circuit serves as the equivalent input positive terminal of the busbar capacitor, and the second end of the positive busbar close to the third circuit serves as the equivalent output positive terminal of the busbar capacitor; the first end of the negative busbar close to the second circuit serves as the equivalent output negative terminal of the busbar capacitor, and the second end of the negative busbar close to the third circuit serves as the equivalent output negative terminal of the busbar capacitor.

3. The busbar capacitance modeling method according to claim 2, characterized in that: The characteristic information includes first characteristic information characterizing the pole-to-ground impedance characteristic of the bus capacitor, and second characteristic information characterizing the inter-pole impedance characteristic of the bus capacitor.

4. The busbar capacitance modeling method according to claim 2, characterized in that: The characteristic information includes a first impedance test curve of the input positive terminal of the bus capacitor to the ground terminal, and a second impedance test curve of the input positive terminal to the input negative terminal; Before obtaining the modeling parasitic parameters corresponding to each of the unknown parasitic parameters based on the characteristic information and the preset parameter determination strategy, the method further includes: Determine, according to the first impedance test curve, a first frequency value when the phase angle is -90°, a first impedance amplitude corresponding to the first frequency value, a second frequency value when the phase angle is 0°, and a second impedance amplitude corresponding to the second frequency value; Determine, according to the second impedance test curve, a third frequency value when the phase angle is -90°, a third impedance amplitude corresponding to the third frequency value, a fourth frequency value when the phase angle is 0°, and a fourth impedance amplitude corresponding to the fourth frequency value; Based on the characteristic information and the preset parameter determination strategy, the modeling parasitic parameters corresponding to each of the unknown parasitic parameters are obtained, including: Determine a first resistance value, a first inductance value, and a first capacitance value of the input positive terminal to the ground terminal according to the first frequency value, the first impedance amplitude, the second frequency value, and the second impedance amplitude; Determine a second resistance value, a second inductance value, and a second capacitance value of the input positive terminal to the input negative terminal according to the third frequency value, the third impedance amplitude, the fourth frequency value, and the fourth impedance amplitude; Based on the first resistance value, the first inductance value, the first capacitance value, the second resistance value, the second inductance value and the second capacitance value, modeling parasitic parameters corresponding to the unknown parasitic parameters of each device in the equivalent circuit model are determined.

5. The busbar capacitance modeling method according to claim 4, characterized in that: The step of obtaining the first impedance test curve and the second impedance test curve includes: The first impedance test curve and the second impedance test curve are respectively obtained by an impedance analyzer.

6. The busbar capacitance modeling method according to claim 4, characterized in that: Determining a first resistance value, a first inductance value, and a first capacitance value of the input positive terminal to the ground terminal according to the first frequency value, the first impedance amplitude, the second frequency value, and the second impedance amplitude, comprising: The first capacitance value of the input positive terminal to the ground terminal is determined according to the first frequency value, the first impedance amplitude and a first preset relationship; the first preset relationship is: Among them, C P-GND is the first capacitance value, f1 is the first frequency value, and Z1 is the first impedance amplitude; Determine that a first resistance value of the input positive terminal to the ground terminal is equal to the second impedance amplitude; The first inductance value of the input positive terminal to the ground terminal is determined according to the first capacitance value, the second frequency value and a second preset relationship; the second preset relationship is: Among them, L P-GND is the first inductance value, and f2 is the second frequency value.

7. The busbar capacitance modeling method according to claim 4, characterized in that: Determining a second resistance value, a second inductance value, and a second capacitance value of the input positive terminal to the input negative terminal according to the third frequency value, the third impedance amplitude, the fourth frequency value, and the fourth impedance amplitude, including: The second capacitance value of the input positive terminal to the input negative terminal is determined according to the third frequency value, the third impedance amplitude and a third preset relationship; the third preset relationship is: Among them, C P-N is the second capacitance value, f3 is the third frequency value, and Z3 is the third impedance amplitude; Determine that a second resistance value of the input positive terminal to the input negative terminal is equal to the fourth impedance amplitude; The second inductance value of the input positive terminal to the input negative terminal is determined according to the second capacitance value, the fourth frequency value and a fourth preset relationship; the fourth preset relationship is: Among them, L P-N is the second inductance value, and f4 is the fourth frequency value.

8. The busbar capacitance modeling method according to claim 4, characterized in that: Determining modeling parasitic parameters corresponding to unknown parasitic parameters of each device in the equivalent circuit model based on the first resistance value, the first inductance value, the first capacitance value, the second resistance value, the second inductance value, and the second capacitance value, including: According to the first resistance value, the first inductance value, the first capacitance value, the second resistance value, the second inductance value, the second capacitance value and a fifth preset relationship, a first resistance parameter, a second resistance parameter, a first capacitance parameter, a second capacitance parameter, a first inductance parameter and a second inductance parameter are determined; the fifth preset relationship is: Among them, C P-GND is the first capacitance value, R P-GND is the first resistance value, L P-GND is the first inductance value, C P-N For the second capacitance value, R P-N is the second resistance value, L P-N For the second inductor value, R X is the first resistance parameter, R Y is the second resistance parameter, C X is the first capacitance value parameter, C Y is the second capacitance parameter, L X is the first inductance parameter, L Y is the second inductance parameter; Determine the modeling parasitic parameter corresponding to the first parasitic resistance as R Y , determine the modeling parasitic parameter corresponding to the first parasitic capacitor as C Y , determine the modeling parasitic parameter corresponding to the first parasitic inductance as L Y ; Determine the modeling parasitic parameter corresponding to the second parasitic resistance as R Y , determine the modeling parasitic parameter corresponding to the second parasitic capacitor as C Y , determine the modeling parasitic parameter corresponding to the second parasitic inductance as L Y ; Determine the modeling parasitic parameter corresponding to the third parasitic resistor as R X , determine the modeling parasitic parameter corresponding to the third parasitic capacitor as C X , determine the modeling parasitic parameter corresponding to the third parasitic inductance as L X .

9. A busbar capacitance modeling system, characterized in that: include: A model building unit, used to build an equivalent circuit model of the bus capacitor; the equivalent circuit model includes a plurality of devices, and each of the devices is correspondingly provided with an unknown parasitic parameter; An acquisition unit, used to acquire characteristic information representing the impedance characteristics between ports of the bus capacitor; A parameter determination unit is used to obtain modeling parasitic parameters corresponding to each of the unknown parasitic parameters based on the characteristic information and a preset parameter determination strategy, so as to determine that the equivalent circuit model after setting the corresponding modeling parasitic parameters for each of the devices is the modeling result of the bus capacitor.

10. A busbar capacitance modeling device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the bus capacitance modeling method as described in any one of claims 1 to 8 when executing the computer program.

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