Isolation device layout design method and device, electronic equipment and storage medium

Abstract

The invention provides an isolation device layout design method and device, electronic equipment and a storage medium, and the method comprises the steps: in a front-end design stage, in response to an isolation ring type selection instruction for a current isolation device, selecting a target isolation ring type of the current isolation device from a plurality of candidate isolation ring types; obtaining a device simulation netlist based on the target isolating ring type, and performing circuit simulation by using the device simulation netlist to obtain a circuit simulation result; and when the circuit simulation result does not meet the design specification requirement, re-selecting the target isolation ring type, and returning to execute the step of obtaining the device simulation netlist based on the target isolation ring type by using the re-selected target isolation ring type. By adopting the isolation device layout design method and device, the electronic equipment and the storage medium, the problems of long design period and low design efficiency of the isolation device layout are solved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design and manufacturing, and in particular to a method, device, electronic device and storage medium for designing an isolation device layout. Background Art

[0002] PDK (Process Design Kit) is a process design toolkit necessary for integrated circuit design. It is a bridge of communication between foundries and design houses. Foundries pass process parameters to design houses through PDK, so that they can understand process information and related process limits. Design houses design products according to the content and product specifications in PDK, and provide final data of process design confirmation stage to foundries for production. In the entire manufacturing process, PDK content and ease of use are crucial.

[0003] At present, most traditional PDKs only describe basic device properties, such as width W, length L, number of fingers (gate) structures NF (Number of Fingers) of transistors, unit repetition multiple related parameters M (Multiplier) and the connection method of Source, Drain and Gate. In order to avoid violating design rules, designers usually set the maximum process parameters according to the design rule file when setting layout data, and only optimize the layout dependency effect properties of the withstand voltage value in the back-end layout verification stage, resulting in long design cycle and low design efficiency of isolation device layout. Summary of the invention

[0004] In view of this, the purpose of the present application is to provide an isolation device layout design method, device, electronic device and storage medium to solve the problems of long design cycle and low design efficiency of isolation device layout.

[0005] In a first aspect, an embodiment of the present application provides an isolation device layout design method, which is applied to a process design tool, including: In the front-end design stage, in response to an isolation ring type selection instruction for the current isolation device, a target isolation ring type of the current isolation device is selected from a plurality of candidate isolation ring types; Acquire a device simulation netlist based on the target isolation ring type, and perform circuit simulation using the device simulation netlist to obtain a circuit simulation result; When the circuit simulation result does not meet the design specification requirements, the target isolation ring type is reselected, and the reselected target isolation ring type is used to return to the step of obtaining the device simulation netlist based on the target isolation ring type.

[0006] Optionally, a plurality of candidate isolation ring types are preset in the process design tool, each candidate isolation ring type is used to reflect the corresponding relationship between the withstand voltage value and the layout-dependent attribute, and the layout-dependent attribute is used to characterize the width of the oxidation-resistant layer groove of the isolation device.

[0007] Optionally, the process design tool includes a physical layout view, and after selecting a target isolation ring type for the current isolation device from multiple candidate isolation ring types, further includes: displaying the device physical layout of the current isolation device under the target isolation ring type in the physical layout view.

[0008] Optionally, the device physical layout of the current isolation device under the target isolation ring type is displayed in the physical layout view, including: displaying the device physical layout in the physical layout view according to the value of the layout dependency attribute corresponding to the target isolation ring type.

[0009] Optionally, the method also includes: when the circuit simulation results meet the design specification requirements, performing netlist extraction processing on the device physical layout to obtain a layout netlist; comparing the layout netlist with the circuit description language netlist to determine whether the consistency requirements are met based on the comparison results.

[0010] Optionally, comparing the layout netlist with the circuit description language netlist includes: comparing the isolation ring type in the layout netlist with the isolation ring type in the circuit description language netlist; comparing the size parameters in the layout netlist with the size parameters in the circuit description language netlist.

[0011] Optionally, circuit simulation is performed using a device simulation netlist to obtain a circuit simulation result, including: inputting the device simulation netlist and a device simulation model of the current isolation device into a simulator to perform circuit simulation to obtain a circuit simulation result.

[0012] In a second aspect, an embodiment of the present application further provides an isolation device layout design device, which is applied to a process design tool, and the device includes: An isolation ring selection module is used to select a target isolation ring type of the current isolation device from a plurality of candidate isolation ring types in response to an isolation ring type selection instruction for the current isolation device during the front-end design stage; A circuit simulation module, used for obtaining a device simulation netlist based on a target isolation ring type, and performing circuit simulation using the device simulation netlist to obtain a circuit simulation result; The design iteration module is used to reselect the target isolation ring type when the circuit simulation result does not meet the design specification requirements, and use the reselected target isolation ring type to return to the step of obtaining the device simulation netlist based on the target isolation ring type.

[0013] In a third aspect, an embodiment of the present application further provides an electronic device, comprising: a processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate through the bus, and when the machine-readable instructions are executed by the processor, the steps of the isolation device layout design method as described above are performed.

[0014] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the isolation device layout design method as described above are executed.

[0015] The embodiments of the present application bring the following beneficial effects: An isolation device layout design method, apparatus, electronic device and storage medium provided in the embodiments of the present application can select a target isolation ring type in the front-end design stage, and reselect the target isolation ring type when the circuit simulation result does not meet the design specification requirements, thereby realizing the optimization of the layout-dependent effect property of the withstand voltage value in the front-end design stage, avoiding the problem of optimizing the layout-dependent effect property of the withstand voltage value in the back-end layout verification stage of the entire isolation device layout design process. Compared with the isolation device layout design method in the prior art, the problems of long design cycle and low design efficiency of the isolation device layout are solved.

[0016] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 A flow chart showing a method for designing a layout of an isolation device provided in an embodiment of the present application is shown; Figure 2 A schematic diagram showing an integrated circuit design process provided by an embodiment of the present application; Figure 3 A schematic diagram showing the location of layout dependency attributes provided in an embodiment of the present application is shown; Figure 4 A schematic diagram showing the structure of an isolation device layout design apparatus provided in an embodiment of the present application is shown; Figure 5A schematic diagram of the structure of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0019] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application usually described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, each other embodiment obtained by those skilled in the art without making creative work belongs to the scope of protection of the present application.

[0020] It is worth noting that before this application was filed, PDK (Process Design Kit) was a necessary process design toolkit for integrated circuit design. It was a communication bridge between the foundry and the design house. The foundry passed the process parameters to the design house through the PDK, so that they could understand the process information and its related process limits and other related contents. The design house designs the product according to the content and product specifications in the PDK, and provides the final data of the process design confirmation stage to the foundry for production. In the entire manufacturing process, the content and ease of use of the PDK are crucial. At present, most traditional PDKs only describe the basic properties of the device, such as: width W, length L, number of finger (gate) structures NF (Number of Fingers) of the transistor, unit repetition multiple related parameters M (Multiplier) and the connection method of Source, Drain and Gate. In order to avoid violating design rules, designers usually set the maximum process parameters according to the design rule file when setting layout data. There is little description of layout-dependent effect properties in the front-end design stage, and the layout-dependent effect properties of the withstand voltage value of the isolation device are not described. In addition, the layout-dependent effect properties of the withstand voltage value are only optimized in the back-end layout verification stage, resulting in long design cycle and low design efficiency for the isolation device layout.

[0021] The following is an explanation of the terms used in the embodiments of the present application.

[0022] PDK (Process Design Kit): PDK is a necessary process design toolkit for integrated circuit design. It is a communication bridge between foundry and design house. It can complete integrated circuit product design and provide strong support for bringing products to market. In the industry design ecosystem, the contents of PDK mainly include PCell, Model, DRC, LVS and PEX, which are process design toolkit components in the entire design process.

[0023] PCell (Parameter Cell, adjustable parameter unit): The adjustable parameter unit serves as the core to provide design services for other design components, provide device Spice simulation netlist for Model (device simulation model), provide device verification layout for DRC, provide device CDL netlist for LVS, and provide device back-end parasitic back-labeling for PEX.

[0024] Model (Device Spice Model, device simulation model): The device simulation model is a mathematical expression that describes the device performance and provides the necessary device data support for the SPICE simulator.

[0025] DRC (Design Rule Check): DRC is a process design rule check file used to verify the correctness of the device backend layout in the PCell library.

[0026] LVS (Layout Versus Schematic, layout and principle Figure 1 consistency check): LVS for layout and principle Figure 1 Conformance check file to verify the back-end layout and front-end principle of the device in the PCell library Figure 1 Consistency.

[0027] PEX (Parasitic Extraction): PEX is a parasitic parameter extraction technology that reveals the impact of parasitic parameters in circuits on circuit performance by modeling and simulating circuits, thereby providing a basis for optimizing circuit design.

[0028] Based on this, an embodiment of the present application provides an isolation device layout design method to shorten the design cycle of the isolation device layout and improve the design efficiency of the isolation device layout.

[0029] See also Figure 1 , Figure 1 This is a flow chart of a method for designing a layout of an isolation device provided in an embodiment of the present application. Figure 1As shown, the isolation device layout design method provided in the embodiment of the present application includes: Step S101, in the front-end design stage, in response to an isolation ring type selection instruction for a current isolation device, selecting a target isolation ring type for the current isolation device from a plurality of candidate isolation ring types; Step S102, obtaining a device simulation netlist based on the target isolation ring type, and performing circuit simulation using the device simulation netlist to obtain a circuit simulation result; Step S103, when the circuit simulation result does not meet the design specification requirements, reselect the target isolation ring type, and use the reselected target isolation ring type to return to the step of obtaining the device simulation netlist based on the target isolation ring type.

[0030] The isolation device layout design method provided in the embodiment of the present application can select the target isolation ring type in the front-end design stage, and re-select the target isolation ring type when the circuit simulation result does not meet the design specification requirements, thereby realizing the optimization of the layout-dependent effect property of the withstand voltage value in the front-end design stage, avoiding the problem of optimizing the layout-dependent effect property of the withstand voltage value in the back-end layout verification stage of the entire isolation device layout design process, and solving the problems of long design cycle and low design efficiency of the isolation device layout.

[0031] To facilitate understanding of this embodiment, the following takes the application of the isolation device layout design method to the process design tool as an example to illustrate the above exemplary steps provided in the embodiment of the present application. The process design tool refers to the PDK (Process Design Kit), which includes a physical layout view.

[0032] Refer to the following Figure 2 To introduce the entire integrated circuit design process.

[0033] Figure 2 A schematic diagram of the integrated circuit design process provided by the embodiment of the present application is shown, such as Figure 2 As shown, the entire integrated circuit design process includes the front-end design stage and the back-end design stage. The front-end design is also called the analog design front-end, and the back-end design is also called the analog design back-end.

[0034] The front-end design stage may refer to the stage of designing the front end in the entire integrated circuit design process. In the front-end design stage, step S201 and step S202 are first performed. Step S201 is used to determine the product specifications, and step S202 is used to determine whether the function implementation meets the specifications. If it is determined that the function implementation does not meet the specifications, return to step S201 to reset the product specifications; if it is determined that the function implementation meets the specifications, step S203 is performed.

[0035] Step S203, module design.

[0036] Here, each module in the integrated circuit can be designed, and CDF parameters can be set for the devices in the module. The current isolation device is a device under a module in the integrated circuit.

[0037] In one example, when executing step S203, the PCell component of the prior art includes CDF (Component Description Format) parameter settings, but the CDF parameters do not include candidate isolation ring types. In an embodiment of the present application, a candidate isolation ring type parameter is added to the CDF parameters of the PCell, and the candidate isolation ring type parameter is used to characterize the corresponding relationship between the withstand voltage value of the isolation device and the layout dependency attribute, and the candidate isolation ring type is recorded as: isolation Ring Type.

[0038] In an embodiment of the present application, when using PDK for integrated circuit design, in response to an isolation ring type selection instruction for a current isolation device, an isolation ring type can be set for the current isolation device in the integrated circuit in the PCell component, that is, one is selected from multiple candidate isolation ring types as the target isolation ring type. After the target isolation ring type is set for the current isolation device, the target isolation ring type will be passed to each component in the entire PDK toolkit, and each component of the PDK will perform corresponding operations according to the target isolation ring type.

[0039] The isolation ring type selection instruction may refer to an instruction for selecting an isolation ring type.

[0040] The candidate isolation ring type is used to characterize the correspondence between the withstand voltage value of the isolation device and the layout dependency attribute, and the layout dependency attribute is used to characterize the width of the oxidation-resistant layer groove of the isolation device. As an example, the candidate isolation ring types include but are not limited to: ISO16, ISO24, ISO35, where ISO16 represents the isolation ring type corresponding to the withstand voltage value of 16V, and ISO24 represents the isolation ring type corresponding to the withstand voltage value of 24V.

[0041] If the target isolation ring type of the current isolation device is ISO16, it is equivalent to setting the withstand voltage value of the current isolation device to 16V. Correspondingly, the layout dependency attribute is the width of the oxidation-resistant layer groove of the current isolation device when the withstand voltage value is 16V. The groove width can be determined according to the correspondence between the withstand voltage value and the layout dependency attribute. For example: when the withstand voltage value is 16V, the layout dependency attribute is 2um.

[0042] The current isolation device may refer to an electrical isolation device. The current isolation device is an isolation device located on a target module in an integrated circuit. As an example, the current isolation device may refer to a MOS isolation device.

[0043] In one example, in order to be able to set the isolation ring type of the current isolation device when using the PDK, multiple candidate isolation ring types can be added to the PCell component of the PDK, and each candidate isolation ring type is used to reflect the correspondence between the withstand voltage value and the layout dependency attribute. For example: ISO16 represents the value of the layout dependency attribute when the withstand voltage value is 16V, and the withstand voltage value may refer to the maximum voltage value that the P-Sub area of ​​the current isolation device can withstand. The withstand voltage value is crucial to product design, which not only affects the manufacturing cost of the product, but also affects the reliability of the product. The layout dependency attributes need to be integrated into the entire PDK using CAD (Computer Aided Design) and applied in the product design process. To this end, this application places the layout dependency attributes in the front-end circuit design stage in the product design process, rather than in the PEX verification stage, or there is no corresponding verification process at all.

[0044] The layout-dependent attribute may refer to the distance d between PW (PWell) and NW (NWell) in the isolation device, i.e., the width of the oxidation-resistant layer groove, where PW is called P-well and NW is called N-well.

[0045] Refer to the following Figure 3 Let's introduce layout dependency properties.

[0046] Figure 3 A schematic diagram showing the location of the layout dependency attributes provided in the embodiment of the present application is shown. Figure 3As shown, the current isolation device is a MOS isolation device, and the current MOS isolation device includes a PMOS transistor 311 and an NMOS transistor 312. Among them, the PMOS transistor 311 and the NMOS transistor 312 share an isolation well 320 (Deep NWell, DNW), and the P-Sub region 330 is the substrate of the wafer. The P+ region 341 in the P well 313 and the P+ region 348 in the P well 315 are connected to VSS, the N+ region 342 in the N well 314 and the N+ region 347 in the N well 316 are connected to VDD, and the distance between the P well 313 and the N well 314 and the distance between the P well 315 and the N well 316 are both the width of the voltage-resistant oxide layer groove 350. In addition, the isolation well 320 is connected to VDD through the N+ region 342 in the N well 314 and the N+ region 347 in the N well 316. Meanwhile, the N+ region 343 of the N well 317 in the PMOS transistor 311 is a PMOS Bulk N well connection terminal connected to VDD, and the N well 317 further includes a P+ region 344. The P+ region 345 of the P well 318 in the NMOS transistor 312 is an NMOS Bulk P well connection terminal connected to VSS, and the P well 318 further includes an N+ region 346. The PMOS transistor 311 further includes a GATE region 361, and the NMOS transistor 312 further includes a GATE region 362.

[0047] In one example, a physical layout view (PCell Layout View) and a device circuit schematic (PCell Schematic View) are provided in the Pcell component. After determining the target isolation ring type of the current chip module, the device physical layout of the current isolation device under the target isolation ring type is displayed in the physical layout view, that is, the device physical layout is displayed in the physical layout view according to the value of the layout dependency attribute corresponding to the target isolation ring type. For example: the larger the value of the layout dependency attribute corresponding to the target isolation ring type, the higher the withstand voltage value, and the larger the width of the oxidation-resistant layer groove of the device physical layout displayed in the physical layout view; the smaller the value of the layout dependency attribute corresponding to the target isolation ring type, the lower the withstand voltage value, and the smaller the width of the oxidation-resistant layer groove of the device physical layout displayed in the physical layout view. At the same time, the circuit schematic is displayed in the device circuit schematic, and the circuit schematic can be a circuit schematic of a single device or a circuit schematic of multiple different devices.

[0048] In one example, based on the target isolation ring type, the device simulation netlist and CDL netlist corresponding to the current isolation device can be obtained by using an electronic design automation (EDA) tool. The device simulation netlist can refer to a device Spice (Simulation Program with Integrated Circuit Emphasis) simulation netlist. The collection of multiple device simulation netlists under the designed module constitutes a circuit simulation netlist. The circuit simulation netlist can refer to a circuit Spice simulation netlist. Then, the circuit simulation is performed using the circuit simulation netlist and the device simulation models of each device in the module.

[0049] In one example, during circuit simulation, the circuit simulation netlist and the device simulation models of each device in the target module can be input into the simulator together for circuit simulation to obtain circuit simulation results. For example, if the target isolation ring type set for the current isolation device is ISO35 and the identifier of the current isolation device is "NM1", the generated device simulation netlist of the integrated circuit includes the following content: "NM1 (DGSB ISO PSUB) nv50_iso w=280n l=600n nf=1 sa=520n sb=520n sd=0 sca=0 scb=0 scc=0 nrd=1.10714 nrs=1.10714 multi=1 as=204.4fad=204.4f ps=1.88u pd=1.88u mismod=1 post=0 isoType=ISO35", and the isoType=ISO35 displayed in the content is the target isolation ring type selected when the CDF parameters are set.

[0050] At this point, the module design is complete and step S204 is executed.

[0051] Step S204, determining whether the module design meets the specifications.

[0052] Here, the circuit simulation results include the values ​​of parameters such as voltage and current of the design module. Based on the values ​​of these circuit parameters, it can be determined whether the module design of the integrated circuit meets the design specification requirements. For example, when the current exceeds the set current threshold or the voltage exceeds the set voltage threshold, it can be determined that the module design of the integrated circuit does not meet the design specification requirements.

[0053] If it is determined that the module design meets the specifications, step S205 is executed. If it is determined that the module design does not meet the specifications, step S208 is executed.

[0054] Step S205: module integration.

[0055] Here, the various modules of the integrated circuit can be integrated together to form a completed integrated circuit.

[0056] Step S206, determining whether the module integration meets the specification.

[0057] The integrated circuit is compared with the preset standard to determine whether it meets the preset standard. If it meets the preset standard, it is determined that the module integration meets the specification, and step S209 is executed to enter the back-end design stage. Otherwise, it is determined that the module integration does not meet the specification, and step S207 is executed.

[0058] Step S207, determining whether the product specifications need to be updated.

[0059] When it is determined that the module integration does not meet the specifications, it may be due to various reasons. If it is due to unreasonable product specification design, the product specification needs to be updated, that is, return to step S201; if it is not due to unreasonable product specification design, the module integration needs to be re-performed, that is, return to step S205.

[0060] Step S208, determining whether the product specifications need to be updated.

[0061] Similarly, when it is determined that the module design does not meet the specifications, it may be due to various reasons. If it is due to unreasonable product specification design, the product specification needs to be updated and the process returns to step S201; if it is not due to unreasonable product specification design, the module design needs to be redesigned and the process returns to step S203.

[0062] Step S209, reading the circuit.

[0063] After the modules of the integrated circuit are integrated and meet the specifications, the back-end design phase begins. In the back-end design phase, the integrated circuit is first read to perform layout design, that is, step S210 is executed.

[0064] Step S210: layout design.

[0065] At this time, the layout design can be performed for the integrated circuit, and this step includes performing the layout design for the current isolation device. In the process of performing the layout design for the current isolation device, it is necessary to consider the target isolation ring type configured for the current isolation device during module design, so as to design a layout that meets the layout dependency attributes. Then, step S211, step S212 and step S213 are performed in sequence.

[0066] Step S211, determine whether the layout design meets the requirements.

[0067] Whether the layout design meets the requirements belongs to the prior art and will not be described in detail here. If it is determined that the layout design meets the requirements, step S212 is executed; if it is determined that the layout design does not meet the requirements, the process returns to step S210.

[0068] Step S212, determining whether the process rule check is passed.

[0069] Here, the process rule check may refer to DRC check, i.e. Design Rule Check, which belongs to the prior art and will not be described in detail here. If it is determined that the process rule check has passed, step S213 is executed; if it is determined that the process rule check has not passed, the process returns to step S210.

[0070] Step S213, determining whether the consistency check passes.

[0071] Here, consistency check can refer to LVS check, and LVS check can refer to Layout Versus Schematic (Layout and Schematic Figure 1 consistency check).

[0072] Specifically, the physical layout of the device may be subjected to netlist extraction to obtain a layout netlist, and the extracted layout netlist may be compared with the circuit description language netlist to determine whether the consistency requirement is met based on the comparison result. The circuit description language netlist may refer to a CDL (Circuit Description Language) netlist.

[0073] Taking the above example, the following content is included in the CDL netlist: "XNM1 DGSB ISO PSUB nv50_iso W=280n L=600n NF=1 MULTI=1 isoType=ISO35". Then, the isolation ring type in the layout netlist is compared with the isolation ring type in the circuit description language netlist, that is, the isoType in the layout netlist is compared with the isoType in the CDL netlist. If the two are equal, it indicates that the layout in the back-end design stage is correct. If the two are not equal, it indicates that the layout in the back-end design stage is wrong. At the same time, the size parameters in the layout netlist are compared with the size parameters in the circuit description language netlist, that is, the W and L in the layout netlist are compared with the W and L in the CDL netlist respectively. If the W in the layout netlist and the W in the CDL netlist are equal and the L in the layout netlist and the L in the CDL netlist are also equal, it indicates that the layout size design in the back-end design stage is correct. If the W in the layout netlist and the W in the CDL netlist are not equal or the L in the layout netlist and the L in the CDL netlist are not equal, it indicates that there is an error in the layout size design in the back-end design stage.

[0074] If the comparison result between the extracted layout netlist and the circuit description language netlist is consistent, it is determined that the consistency requirement is met, the consistency LVS check is passed, and step S214 is executed; otherwise, it is determined that the consistency requirement is not met, the consistency LVS check is not passed, and the process returns to step S210.

[0075] Step S214, determining whether the parasitic extraction is confirmed.

[0076] Here, parasitic extraction confirmation may refer to PEX confirmation, and PEX confirmation may refer to Parasitic Extraction (parasitic parameter extraction). Parasitic extraction confirmation belongs to the prior art and will not be described in detail here.

[0077] It should be noted that in order to enable PDK to achieve the above functions, the existing PDK needs to be modified. For example: it is necessary to determine the correspondence between the layout dependency attribute and the withstand voltage value, and add CDF parameter configuration in PDK according to the correspondence to add multiple candidate isolation ring types, each candidate isolation ring type represents a set of correspondence between the layout dependency attribute and the withstand voltage value. Then, in the PCell component in PDK, according to the CDF parameter setting, modify the functions of each view to reflect the influence of different withstand voltage values ​​on the device layout in the view, for example: for symbol view, provide the function of selecting and setting the layout dependency attribute in the circuit schematic; for layout view, provide the function of adjusting the distance d according to the layout dependency attribute to generate the corresponding physical layout; for spectre view, provide the function of adding the corresponding CDF mark according to the layout dependency attribute and outputting the circuit spectre simulation netlist; for hspiceD view, provide the function of adding the corresponding CDF mark according to the layout dependency attribute and outputting the circuit hspice simulation netlist; for auCdl view, provide the function of adding the corresponding CDF mark according to the layout dependency attribute to output the circuit CDL netlist. For auLvs view, the function of adding corresponding CDF tags according to layout dependency attributes to output the embedded LVS netlist is provided; for ivpcell view, the function of back-labeling parasitic netlist devices is provided. Among them, the CDF tag can refer to a specific isoType.

[0078] In addition, for the Model component in the PDK, based on the CDF parameter settings and device model test data, define different devices under different CDF tags to develop device models.

[0079] For the DRC components in the PDK, different devices under different CDF tags are defined according to the CDF parameter settings, and corresponding inspection rules are developed according to the correspondence between different withstand voltage values ​​and layout dependency attributes. For example, the layout dependency attribute corresponding to the 45V withstand voltage value is 5um.

[0080] For the LVS components in the PDK, define different devices under different CDF tags according to the CDF parameter settings, and develop consistency checks between schematics and layouts according to different device identifications (for example, identifying the isoType of different isolated devices).

[0081] For the PEX components in PDK, extract the corresponding layout parasitic netlist according to the CDF parameter settings and LVS check files, and develop the PEX parasitic parameter documents according to the devices in LVS.

[0082] Based on the same inventive concept, an isolation device layout design apparatus corresponding to the isolation device layout design method is also provided in the embodiment of the present application. Since the principle of solving the problem by the apparatus in the embodiment of the present application is similar to the above-mentioned isolation device layout design method in the embodiment of the present application, the implementation of the apparatus can refer to the implementation of the method, and the repeated parts will not be repeated.

[0083] See also Figure 4 , Figure 4 This is a schematic diagram of the structure of an isolation device layout design device provided in an embodiment of the present application. Figure 4 As shown in , the isolation device layout design device 400 includes: The isolation ring selection module 401 is used to select a target isolation ring type of the current isolation device from multiple candidate isolation ring types in response to an isolation ring type selection instruction for the current isolation device during the front-end design stage; A circuit simulation module 402 is used to obtain a device simulation netlist based on the target isolation ring type, and perform circuit simulation using the device simulation netlist to obtain a circuit simulation result; The design iteration module 403 is used to reselect the target isolation ring type when the circuit simulation result does not meet the design specification requirements, and use the reselected target isolation ring type to return to the step of obtaining the device simulation netlist based on the target isolation ring type.

[0084] See also Figure 5 , Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Figure 5 As shown in , the electronic device 500 includes a processor 510 , a memory 520 and a bus 530 .

[0085] The memory 520 stores machine-readable instructions executable by the processor 510. When the electronic device 500 is running, the processor 510 communicates with the memory 520 via the bus 530. When the machine-readable instructions are executed by the processor 510, the above-mentioned Figure 1 The specific implementation of the steps of the isolation device layout design method in the method embodiment shown can be found in the method embodiment, which will not be repeated here.

[0086] The present application also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the computer program can execute the above-mentioned Figure 1 The specific implementation of the steps of the isolation device layout design method in the method embodiment shown can be found in the method embodiment, which will not be repeated here.

[0087] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0088] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of devices or units can be electrical, mechanical or other forms.

[0089] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0090] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0091] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

[0092] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-mentioned embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-mentioned embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A method for designing a layout of an isolation device, characterized in that: Applications in process design tools include: In the front-end design stage, in response to an isolation ring type selection instruction for a current isolation device, a target isolation ring type of the current isolation device is selected from a plurality of candidate isolation ring types; Acquire a device simulation netlist based on the target isolation ring type, and perform circuit simulation using the device simulation netlist to obtain a circuit simulation result; When the circuit simulation result does not meet the design specification requirements, the target isolation ring type is reselected, and the step of obtaining the device simulation netlist based on the target isolation ring type is returned using the reselected target isolation ring type.

2. The method according to claim 1, characterized in that The process design tool has a plurality of candidate isolation ring types preset, each candidate isolation ring type is used to reflect the corresponding relationship between the withstand voltage value and the layout-dependent attribute, and the layout-dependent attribute is used to characterize the width of the oxidation-resistant layer groove of the isolation device.

3. The method according to claim 2, characterized in that The process design tool includes a physical layout view, and after selecting the target isolation ring type of the current isolation device from a plurality of candidate isolation ring types, further includes: The device physical layout of the current isolation device under the target isolation ring type is displayed in the physical layout view.

4. The method according to claim 3, characterized in that The displaying of the device physical layout of the current isolation device under the target isolation ring type in the physical layout view includes: The physical layout of the device is displayed in the physical layout view according to the value of the layout dependency attribute corresponding to the target isolation ring type.

5. The method according to claim 3, characterized in that: The method further comprises: When the circuit simulation result meets the design specification requirements, performing netlist extraction processing on the physical layout of the device to obtain a layout netlist; The layout netlist is compared with the circuit description language netlist to determine whether the consistency requirement is met according to the comparison result.

6. The method according to claim 5, characterized in that The comparing the layout netlist with the circuit description language netlist comprises: comparing the isolating ring type in the layout netlist with the isolating ring type in the circuit description language netlist; The size parameters in the layout netlist are compared with the size parameters in the circuit description language netlist.

7. The method according to claim 1, characterized in that The circuit simulation is performed using the device simulation netlist to obtain a circuit simulation result, including: The device simulation netlist and the device simulation model of the current isolation device are input into a simulator to perform circuit simulation to obtain a circuit simulation result.

8. An isolation device layout design device, characterized in that: Applications in process design tools include: An isolation ring selection module is used to select a target isolation ring type of the current isolation device from a plurality of candidate isolation ring types in response to an isolation ring type selection instruction for the current isolation device during the front-end design stage; A circuit simulation module, used for obtaining a device simulation netlist based on the target isolation ring type, and performing circuit simulation using the device simulation netlist to obtain a circuit simulation result; The design iteration module is used to reselect the target isolation ring type when the circuit simulation result does not meet the design specification requirements, and use the reselected target isolation ring type to return to the step of obtaining the device simulation netlist based on the target isolation ring type.

9. An electronic device, characterized in that: include: A processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor communicates with the memory via the bus, and the processor executes the machine-readable instructions to perform the steps of the isolation device layout design method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the isolation device layout design method according to any one of claims 1 to 7 are executed.

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