Packaging Optimization Method and System for UHV MOSFET

Abstract

The present application provides a packaging optimization method and system for ultra-high voltage MOSFETs, which relates to the field of semiconductor manufacturing technology. By determining the preset packaging layout of ultra-high voltage MOSFET components; analyzing the parasitic capacitance and its influence on the switching speed, as well as the parasitic inductance and its influence on the voltage overshoot, and combining the correlation analysis of energy loss, a parasitic capacitance optimization network and a parasitic inductance optimization network are established; multiple equivalent RC circuits are formulated and equivalently combined, and a performance optimization model is established according to the optimization network; based on the performance optimization model, combined with the packaging requirement information, a compromise backtracking iteration is carried out. At the same time, the preset packaging layout is adjusted to obtain the optimal packaging layout. The present application solves the technical problem that the prior art lacks systematic optimization of parasitic effects during the packaging process, resulting in difficulty in improving the overall packaging performance, and achieves the technical effect of significantly improving the performance and reliability of ultra-high voltage MOSFETs.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and specifically relates to a packaging optimization method and system for ultra-high voltage MOSFETs. Background Art

[0002] Ultra-high voltage MOSFETs are key power electronic components, widely used in fields such as high-voltage power transmission, frequency converters, and electric vehicle drive systems. Existing ultra-high voltage MOSFET packaging optimization methods mainly focus on improving the packaging process. By improving the packaging materials, layout, and structure, the impact of parasitic effects is reduced, and the performance of power modules is enhanced. However, in existing ultra-high voltage MOSFET packaging technologies, the optimization of parasitic parameters mainly focuses on the adjustment of single or partial parasitic parameters, lacking consideration of the systematic relationship between parasitic parameters and other important factors. For example, when optimizing parasitic capacitance and parasitic inductance, independent methods are often used. For instance, the parasitic capacitance is improved through a specific ceramic substrate design, and the parasitic inductance is optimized by changing the layout structure. These optimization methods only focus on the optimization of parasitic parameters in local areas and do not consider the impact of optimization measures on the surrounding circuits, which may result in the ineffective control of parasitic effects in the entire circuit, limiting the improvement of the overall performance of ultra-high voltage MOSFETs. Summary of the Invention

[0003] This application provides a packaging optimization method and system for ultra-high voltage MOSFETs, solving the technical problem that the existing technology lacks systematic optimization of parasitic effects during the packaging process of ultra-high voltage MOSFETs, resulting in difficulty in improving the overall packaging performance, and achieving the technical effect of significantly improving the performance and reliability of ultra-high voltage MOSFETs.

[0004] In view of the above problems, on the one hand, the present application provides a packaging optimization method for ultra-high voltage MOSFETs, and the method includes: determining a preset packaging layout according to the ultra-high voltage MOSFET components, where the ultra-high voltage MOSFET components include a high-side MOSFET source pin, a motor winding, and a low-side MOSFET drain pin; analyzing the parasitic capacitance and the influence of the parasitic capacitance on the switching speed according to the preset packaging layout, obtaining a first influence evaluation combination, and performing energy loss correlation analysis according to the first influence evaluation combination, and establishing a parasitic capacitance optimization network by using the first energy loss correlation analysis result; analyzing the parasitic inductance and the influence of the parasitic inductance on the voltage overshoot according to the preset packaging layout, obtaining a second influence evaluation combination, and performing energy loss correlation analysis according to the second influence evaluation combination, and establishing a parasitic inductance optimization network by using the second energy loss correlation analysis result; formulating a plurality of equivalent RC circuits through the high-side MOSFET source pin, the motor winding, and the low-side MOSFET drain pin in the ultra-high voltage MOSFET components, where the plurality of equivalent RC circuits include a series-equivalent RC circuit and a parallel-equivalent RC circuit; performing equivalent combination on the series-equivalent RC circuit and the parallel-equivalent RC circuit in the plurality of equivalent RC circuits, and establishing a performance optimization model according to the parasitic capacitance optimization network and the parasitic inductance optimization network; based on the performance optimization model, performing compromise backtracking iteration in combination with the packaging requirement information of the ultra-high voltage MOSFET components, and at the same time, adjusting the preset packaging layout to obtain an optimal packaging layout.

[0005] On the other hand, the present application also provides a packaging optimization system for extra-high voltage MOSFETs. The system includes: a preset packaging layout module for determining a preset packaging layout according to an extra-high voltage MOSFET component, where the extra-high voltage MOSFET component includes a high-side MOSFET source pin, a motor winding, and a low-side MOSFET drain pin; a parasitic capacitance analysis module for analyzing the parasitic capacitance and the influence of the parasitic capacitance on the switching speed according to the preset packaging layout, obtaining a first influence evaluation combination, and performing energy loss correlation analysis according to the first influence evaluation combination, and establishing a parasitic capacitance optimization network by using the first energy loss correlation analysis result; a parasitic inductance analysis module for analyzing the parasitic inductance and the influence of the parasitic inductance on the voltage overshoot according to the preset packaging layout, obtaining a second influence evaluation combination, and performing energy loss correlation analysis according to the second influence evaluation combination, and establishing a parasitic inductance optimization network by using the second energy loss correlation analysis result; an equivalent RC circuit module for formulating a plurality of equivalent RC circuits through the high-side MOSFET source pin, the motor winding, and the low-side MOSFET drain pin in the extra-high voltage MOSFET component, where the plurality of equivalent RC circuits include a series-equivalent RC circuit and a parallel-equivalent RC circuit; a circuit equivalent combination module for performing equivalent combination on the series-equivalent RC circuit and the parallel-equivalent RC circuit in the plurality of equivalent RC circuits, and establishing a performance optimization model according to the parasitic capacitance optimization network and the parasitic inductance optimization network; a packaging layout optimization module for performing trade-off backtracking iteration based on the performance optimization model and combining the packaging requirement information of the extra-high voltage MOSFET component, and at the same time, adjusting the preset packaging layout to obtain an optimal packaging layout.

[0006] One or more technical solutions provided in the present application have at least the following technical effects or advantages:

[0007] Based on the UHV MOSFET device, a preset packaging layout is determined, clarifying the initial positional relationship and electrical connection methods of each part of the UHV MOSFET device, providing a reference framework for subsequent parasitic effect analysis and optimization. By analyzing the parasitic capacitance and its impact on the switching speed, and constructing a parasitic capacitance optimization network, it provides an optimization direction and basis for subsequent comprehensive performance optimization in terms of parasitic capacitance. By analyzing the parasitic inductance and its impact on voltage overshoot, and constructing a parasitic inductance optimization network, it provides an optimization direction and basis for subsequent comprehensive performance optimization in terms of parasitic inductance. Using the key components of the UHV MOSFET device, multiple equivalent RC circuits are formulated, transforming the actual circuit structure into an equivalent circuit model convenient for analysis, providing basic circuit model units for subsequent establishment of a performance optimization model, enabling unified performance analysis of complex actual circuits through these equivalent circuits. The equivalent RC circuits are equivalently combined and combined with the established parasitic capacitance and parasitic inductance optimization networks to construct a mathematical model that can comprehensively describe the packaging performance optimization relationship. Based on the performance optimization model and combined with packaging requirements, a compromise backtracking iteration is carried out, comprehensively considering the mutual restraint relationships of various factors, and continuously adjusting the preset packaging layout to achieve comprehensive performance optimization in multiple aspects such as electrical, thermal, and mechanical while meeting the packaging requirements.

[0008] In summary, through a series of steps including determining the preset packaging layout, gradually and deeply analyzing the impacts of parasitic capacitance and parasitic inductance on the performance of the UHV MOSFET device, constructing corresponding optimization networks, formulating equivalent RC circuits and establishing a performance optimization model, and finally obtaining the optimal packaging layout through compromise backtracking iteration, this application realizes comprehensive performance optimization of the UHV MOSFET packaging in multiple aspects such as electrical, thermal, and mechanical. It can not only effectively reduce the adverse impacts of parasitic capacitance on the switching speed and parasitic inductance on voltage overshoot, thereby reducing energy loss, but also comprehensively improve the overall performance of the UHV MOSFET device by optimizing the packaging layout on the premise of meeting the packaging requirements, enabling the UHV MOSFET to operate more efficiently and stably in complex working environments.

[0009] The above description is only an overview of the technical solution of this application. In order to be able to understand the technical means of this application more clearly, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features, and advantages of this application more obvious and understandable, the following specifically gives the specific implementation manners of this application. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a schematic flowchart of a packaging optimization method for UHV MOSFET provided by an embodiment of this application.

[0011] Figure 2Schematic diagram of the process for obtaining the optimal packaging layout in the packaging optimization method for ultra-high voltage MOSFETs provided by the embodiments of the present application.

[0012] Figure 3 Schematic diagram of the process for determining the thermal resistance constraint conditions in the packaging optimization method for ultra-high voltage MOSFETs provided by the embodiments of the present application.

[0013] Figure 4 Schematic diagram of the structure of the packaging optimization system for ultra-high voltage MOSFETs provided by the embodiments of the present application.

[0014] Description of reference numerals: preset packaging layout module 10, parasitic capacitance analysis module 20, parasitic inductance analysis module 30, equivalent RC circuit module 40, circuit equivalent combination module 50, packaging layout optimization module 60. Detailed implementation manners

[0015] By providing a packaging optimization method and system for ultra-high voltage MOSFETs, the embodiments of the present application solve the technical problem in the prior art that the lack of systematic optimization of parasitic effects during the packaging process of ultra-high voltage MOSFETs makes it difficult to improve the overall packaging performance, and achieve the technical effect of significantly improving the performance and reliability of ultra-high voltage MOSFETs.

[0016] Embodiment 1, as Figure 1 shown, the embodiments of the present application provide a packaging optimization method for ultra-high voltage MOSFETs, and the method includes:

[0017] Step S1: Determine a preset packaging layout according to the ultra-high voltage MOSFET component, where the ultra-high voltage MOSFET component includes a high-side MOSFET source pin, a motor winding, and a low-side MOSFET drain pin.

[0018] Specifically, the ultra-high voltage MOSFET is a semiconductor device used to handle high voltages. Its main components include the high-side MOSFET source pin, the motor winding, and the low-side MOSFET drain pin. The high-side MOSFET source pin, which is the pin on the MOSFET device connected to the source and at the higher potential side in the circuit, is the input terminal of the current in the MOSFET, controlling the inflow of current and acting as a current switch. The low-side MOSFET drain pin, which is the pin on the MOSFET device connected to the drain and at the lower potential side in the circuit, is the output terminal of the current in the MOSFET, controlling the outflow of current and affecting the on / off of the current. The motor winding is the electromagnetic coil part in the motor, associated with the MOSFET component, and controls the operation of the motor by controlling the current flow direction. The preset package layout is a preliminary package structure arrangement preset according to the characteristics and requirements of the ultra-high voltage MOSFET component before package optimization, including the layout methods such as the relative positions and connection methods of each pin, component, etc.

[0019] According to the characteristics of the ultra-high voltage MOSFET component itself, such as the functions and electrical connection requirements of the high-side MOSFET source pin, the motor winding, and the low-side MOSFET drain pin, referring to the electrical parameter manual of the ultra-high voltage MOSFET and the historical packaging experience of similar products, determine an initial preset package layout. Exemplarily, if the ultra-high voltage MOSFET is applied to a motor drive circuit, according to the power requirements and working voltage range of the motor, layout the high-side MOSFET source pin close to the power input side, layout the low-side MOSFET drain pin close to the motor winding side, and layout the motor winding in the best way for electromagnetic coupling. The preset package layout provides a basic framework for subsequent performance analysis and optimization, determines the relative position relationship of each component, and preliminarily plans the electrical connection path.

[0020] Step S2: According to the preset package layout, analyze the parasitic capacitance and the influence of the parasitic capacitance on the switching speed, obtain the first influence evaluation combination, and perform an energy loss correlation analysis based on the first influence evaluation combination. Using the result of the first energy loss correlation analysis, establish a parasitic capacitance optimization network.

[0021] Specifically, parasitic capacitance refers to the unintended capacitance that occurs in electronic components or circuits due to physical proximity or electric field effects between conductors, pins, chips, etc. Parasitic capacitance usually affects high-frequency signals and switching processes, which may lead to signal delay, energy loss, and interference. Switching speed refers to the speed at which a MOSFET turns on and off or vice versa. Switching speed is one of the important performance indicators of a MOSFET and directly affects the response speed and working efficiency of the circuit. The parasitic capacitance optimization network is an optimization network model established through the first influence evaluation combination and the energy loss correlation analysis results, which is used to optimize the switching speed and energy loss by adjusting capacitance values, layouts, and component configurations.

[0022] Based on the preset package layout, analyze the existing parasitic capacitance situation. Calculate the magnitude of the parasitic capacitance through electromagnetic simulation software (such as Ansys Maxwell) or based on circuit theory formulas. Then study the influence of parasitic capacitance on the switching speed. For example, when the parasitic capacitance is large, it will slow down the switching speed. According to the results of this influence evaluation, form the first influence evaluation combination. Next, use circuit analysis methods (such as Kirchhoff's laws) to conduct energy loss correlation analysis, relating the parasitic capacitance to the energy loss, and generate the first energy loss correlation analysis result. Finally, based on these analysis results, establish an optimization network for parasitic capacitance. This network can be a structure based on mathematical relationships, which is used to describe how to optimize the parasitic capacitance to reduce its impact on the switching speed.

[0023] By analyzing the parasitic capacitance and its influence on the switching speed, an optimization network is established, providing a theoretical basis for reducing the adverse effects of parasitic capacitance on the switching speed and reducing energy loss.

[0024] Step S3: According to the preset package layout, analyze the parasitic inductance and the influence of the parasitic inductance on the voltage overshoot, obtain the second influence evaluation combination, and conduct energy loss correlation analysis based on the second influence evaluation combination. Use the second energy loss correlation analysis result to establish a parasitic inductance optimization network.

[0025] Specifically, parasitic inductance refers to the unintended inductance generated in a circuit due to the physical structure between wires, pins, circuits or components and the change of current. Parasitic inductance can affect the high-frequency response of the circuit and may cause voltage fluctuations or overshoot phenomena. Among them, voltage overshoot refers to the phenomenon that the voltage exceeds the target value during the switching process. The second impact assessment combination refers to the combination of all key impact factors obtained by analyzing the impact of parasitic inductance on voltage overshoot, including the amplitude and duration of the voltage overshoot caused by parasitic inductance and its impact on the overall circuit performance. The parasitic inductance optimization network is an optimization model established through the second impact assessment combination and the results of energy loss correlation analysis, which is used to reduce the impact of parasitic inductance by adjusting factors such as package layout and pin configuration, and optimize the voltage overshoot and energy loss during the switching process.

[0026] Similar to step S2, based on the preset package layout, the magnitude of the parasitic inductance is determined through a magnetic field simulation software (such as Ansys HFSS) or an inductance calculation formula, and the impact of the parasitic inductance on voltage overshoot is studied. For example, when the parasitic inductance is large, it will cause a large voltage overshoot at the moment of switching. The second impact assessment combination is obtained through the analysis of the parasitic inductance, and then the energy loss correlation analysis is carried out. The parasitic inductance optimization network is established using the analysis results.

[0027] By analyzing the parasitic inductance and its impact on voltage overshoot, establishing an optimization network helps to reduce the impact of parasitic inductance on voltage overshoot, thereby reducing energy loss.

[0028] Step S4: Multiple equivalent RC circuits are formulated through the high-side MOSFET source pin, motor winding, and low-side MOSFET drain pin in the UHV MOSFET component. The multiple equivalent RC circuits include a series-equivalent RC circuit and a parallel-equivalent RC circuit.

[0029] Specifically, an equivalent RC circuit is a circuit model composed of a resistor (R) and a capacitor (C), which is used to equivalently represent some electrical characteristics in an actual circuit, including a series-equivalent RC circuit and a parallel-equivalent RC circuit. Among them, a series-equivalent RC circuit is an equivalent circuit in which a resistor and a capacitor are connected in series, and a parallel-equivalent RC circuit is an equivalent circuit in which a resistor and a capacitor are connected in parallel.

[0030] Using components such as the high-side MOSFET source pin, motor winding, and low-side MOSFET drain pin in the extra-high voltage MOSFET component, multiple equivalent RC circuits are formulated according to circuit principles. For example, the resistance of the motor winding and the associated parasitic capacitance form a series-equivalent RC circuit, or the parasitic capacitance near the high-side MOSFET source pin and the equivalent resistance form a parallel-equivalent RC circuit. By constructing the equivalent RC circuits, the analysis of complex circuits is simplified, and it is more convenient to study the electrical characteristics of the extra-high voltage MOSFET component.

[0031] Step S5: Perform equivalent combination on the series-equivalent RC circuit and the parallel-equivalent RC circuit among the multiple equivalent RC circuits, and establish a performance optimization model based on the parasitic capacitance optimization network and the parasitic inductance optimization network.

[0032] Specifically, the performance optimization model is a mathematical model established for optimizing the packaging performance of the extra-high voltage MOSFET based on the analysis results of factors such as parasitic capacitance and parasitic inductance, comprehensively considering various influencing relationships.

[0033] Perform equivalent combination on the series-equivalent RC circuit and the parallel-equivalent RC circuit among the multiple equivalent RC circuits according to the circuit connection relationship. Then, incorporate the relevant parameter relationships in the previously established parasitic capacitance optimization network and parasitic inductance optimization network into the equivalently combined circuit to establish a performance optimization model. This model can be a mathematical expression containing multiple variables and constraint conditions, used to describe the relationship between circuit performance and each optimization network.

[0034] By establishing the performance optimization model, the optimization relationship between parasitic capacitance and parasitic inductance can be comprehensively considered, providing a unified mathematical framework for comprehensively optimizing the packaging performance of the extra-high voltage MOSFET.

[0035] Step S6: Based on the performance optimization model, perform trade-off backtracking iteration in combination with the packaging requirement information of the extra-high voltage MOSFET component. At the same time, adjust the preset packaging layout to obtain the optimal packaging layout.

[0036] Specifically, during the optimization process, since there may be contradictions between different performance metrics, for example, reducing parasitic capacitance may increase parasitic inductance, it is necessary to conduct a compromise backtracking iteration based on the performance optimization model, combined with the packaging requirement information of the UHV MOSFET components, such as packaging size limitations, heat dissipation requirements, electrical insulation requirements, etc. By adjusting various parameters in the preset packaging layout, such as component spacing, wiring direction, etc., and then recalculating the relevant parameters in the performance optimization model, comparing the results before and after adjustment, and continuously repeating this process until the optimal packaging layout that meets the packaging requirements is obtained. Exemplarily, if the packaging requirement is to achieve the lowest energy loss within a limited space while meeting certain voltage overshoot limitations. During the iteration process, it may be found that reducing the parasitic capacitance in a certain area will cause the parasitic inductance in another area to increase, exceeding the voltage overshoot limitation. At this time, it is necessary to backtrack to the previous step of adjusting the layout, readjust the layout of the components, and recalculate the performance optimization model until an optimal packaging layout that can meet both the voltage overshoot requirement and achieve a lower energy loss within a limited space is found.

[0037] Through the compromise backtracking iteration, the mutual restraint relationships between various packaging requirements and performance metrics can be comprehensively considered, and the optimal packaging layout can be obtained, thereby realizing the comprehensive performance optimization of the UHV MOSFET packaging in multiple aspects such as electrical, thermal, and mechanical.

[0038] Furthermore, as Figure 2 shown, step S6 includes:

[0039] Step S61: Introduce peripheral electronic components and draw up a set of peripheral circuits.

[0040] Step S62: Based on the set of peripheral circuits and the power distribution network, conduct layout compactness guidance and set a layout guidance vector.

[0041] Step S63: Use the layout guidance vector to optimize the relative positions and connection paths between components to obtain the optimal packaging layout.

[0042] Specifically, peripheral electronic components refer to other electronic components that are directly connected to or cooperate with the extra-high voltage MOSFET but do not belong to the MOSFET itself, such as resistors, capacitors, inductors, diodes, sensors, drivers, etc. The peripheral circuit set refers to the circuit set formed by combining all the peripheral electronic components connected to the extra-high voltage MOSFET according to the design requirements and functional relationships. These circuits work together with the MOSFET to form the circuit framework of a system. The power distribution network refers to the power supply system in the circuit, which is responsible for distributing the power from the battery, power adapter or other power sources to each component. The layout guiding vector is a vector representation used to guide the optimization direction and degree of the layout of circuit components, and contains multiple parameters, such as the moving direction of components, the direction of spacing adjustment, etc.

[0043] Based on the extra-high voltage MOSFET components, analyze the entire circuit system to determine all the peripheral electronic components that work in cooperation with the extra-high voltage MOSFET. Such as power filters, drivers, voltage regulators, temperature sensors, etc. Then, according to the electrical connection relationships between these components, draw up a peripheral circuit set that includes all the peripheral electronic components and their connection relationships. Exemplarily, in a circuit where an extra-high voltage MOSFET is used for motor drive, in addition to the MOSFET itself, there are also peripheral electronic components such as capacitors for filtering, resistors for current limiting, and diodes for protection. Draw up the peripheral circuit set according to the connection relationships of these components in the circuit. For example, the capacitor is connected to the source and ground of the MOSFET, the resistor is connected in series in the gate circuit of the MOSFET, and the diode is connected in parallel with the drain of the MOSFET, etc. These peripheral circuit sets provide more comprehensive circuit structure information for subsequent layout optimization, making the layout optimization no longer limited to the extra-high voltage MOSFET components themselves, but considering the collaborative optimization of the entire circuit system.

[0044] Based on the drawn-up peripheral circuit set and power distribution network, analyze the electrical relationships between the peripheral electronic components and the extra-high voltage MOSFET components, and set the layout guiding vector with the goal of layout compactness. That is, in the subsequent package optimization process, set the corresponding layout rules to make the components in the circuit arranged as compactly as possible, thereby reducing the floor area of the circuit and reducing the influence of factors such as parasitic capacitance and inductance in the current path. Mark these layout rules in the form of a vector to obtain the layout guiding vector.

[0045] Adjust the relative positions and connection paths between the UHV MOSFET components and the peripheral electronic components according to the layout guiding vector. For example, if the layout guiding vector indicates that a certain component needs to be moved to the left, adjust the position of the component according to this indication, and at the same time optimize the connection path to reduce unnecessary wiring length and bending, and finally obtain the optimal package layout. The optimal package layout is a layout scheme with the most optimized relative positions and connection paths between components on the premise of meeting the circuit performance requirements. The layout adjustment process can use an automatic placement and routing tool to optimize the placement and routing under the constraint of the layout guiding vector. Exemplarily, in a preset package layout, the connection path between a resistor and the UHV MOSFET component is long and passes through multiple bends. According to the indication of the layout guiding vector, the resistor is moved to a position closer to the MOSFET, and the connection path is re-planned to make it a straight connection, reducing parasitic inductance and resistance and improving the circuit performance.

[0046] By optimizing the relative positions and connection paths between components, the optimal package layout is obtained, improving the electrical performance (such as reducing parasitic parameters) and space utilization rate of the circuit.

[0047] Further, step S62 includes:

[0048] Step S621: Collect circuit interconnection parameters through the circuit interconnection method between the UHV MOSFET component and the peripheral electronic components.

[0049] Step S622: Based on the peripheral circuit set, collect signal recognition parameters through the signal recognition method between the UHV MOSFET component and the peripheral electronic components.

[0050] Step S623: Taking the power distribution network as the direction, combine the circuit interconnection parameters and signal recognition parameters to conduct layout compactness guidance and configure the layout guiding vector.

[0051] Specifically, the circuit interconnection method refers to the electrical connection form between the UHV MOSFET component and the peripheral electronic components, including series connection, parallel connection, direct connection, connection through a specific circuit structure (such as a bridge circuit), etc. The circuit interconnection method determines the transmission paths and directions of current, voltage, and signals, and affects the working performance and stability of the circuit. The circuit interconnection parameters are parameters describing the circuit interconnection characteristics between the UHV MOSFET component and the peripheral electronic components, including the length, width, thickness of the interconnecting wire, the resistivity of the interconnecting wire material, the spacing between the interconnecting wires, etc. These parameters will affect the electrical properties such as parasitic resistance, parasitic inductance, and capacitance of the circuit.

[0052] The signal mutual recognition method represents the way of identifying and processing signals when the UHV MOSFET component exchanges signals with the peripheral electronic components. For example, in digital circuits, it includes methods such as level matching, signal encoding and decoding; in analog circuits, it includes operations such as signal amplification, filtering, modulation and demodulation. Signal mutual recognition parameters are used to describe the characteristic parameters of signal transmission, including signal frequency, amplitude, phase, rise time, fall time, signal noise tolerance, etc. These parameters reflect the characteristics of the signal when it is transmitted between components.

[0053] According to the circuit schematic diagram in the peripheral circuit set, identify the circuit interconnection method between the UHV MOSFET component and each peripheral electronic component. For different connection situations, measure or calculate the relevant circuit interconnection parameters. For example, if it is connected through the wires on a printed circuit board (PCB), it is necessary to measure the length and width of the wires and query the resistivity of the wire material, etc., so as to obtain circuit interconnection parameters such as the resistance of the interconnection line. Collecting the circuit interconnection parameters can accurately quantify the electrical characteristics of the circuit connection between the UHV MOSFET component and the peripheral electronic components, providing key information about the physical circuit connection for the subsequent layout compactness guidance, and helping to optimize the layout to reduce unnecessary electrical losses.

[0054] Based on the already formulated peripheral circuit set, determine the signal mutual recognition method between the UHV MOSFET component and the peripheral electronic components. In digital circuits, it is necessary to check the level conversion relationship between logic gate circuits; in analog circuits, it is necessary to analyze the amplification, filtering and other processing processes of the signal when it passes through different components. Then, measure the signal frequency, amplitude, etc. through instruments such as oscilloscopes, and analyze the logical state conversion of the signal through a logic analyzer, etc., so as to collect signal mutual recognition parameters. Exemplarily, in an amplification circuit containing a UHV MOSFET, the peripheral electronic component is an amplifier. The signal is output from the drain of the MOSFET and amplified by the amplifier. Using an oscilloscope to measure the amplitude of the signal at the drain of the MOSFET is 1V, and the output amplitude after being amplified by the amplifier is 5V. These 1V and 5V are part of the signal mutual recognition parameters, and at the same time measure other relevant parameters such as the signal frequency of 1kHz. Collecting the signal mutual recognition parameters helps to comprehensively understand the characteristics of signal transmission between the UHV MOSFET component and the peripheral electronic components, ensuring that the accuracy and stability of signal transmission can be taken into account during the layout optimization process, and avoiding signal transmission errors or performance degradation caused by layout adjustment.

[0055] Regarding the power distribution network as the main direction of layout compactification guidance, comprehensively consider the collected circuit interconnection parameters (such as the resistance and inductance of interconnecting wires, etc.) and signal mutual recognition parameters (such as the frequency and amplitude of signals, etc.). For example, if the resistance of the interconnecting wire in the circuit interconnection parameters is large, and the signal amplitude in the signal mutual recognition parameters is sensitive to the resistance, then when guiding the layout compactification, it is necessary to minimize the length of the interconnecting wire as much as possible. Based on these comprehensive factors, through the circuit layout optimization algorithm software, configure the layout guidance vector, which contains information such as the direction and degree of component layout adjustment. The circuit layout optimization algorithm software can calculate the layout guidance vector according to the input circuit interconnection parameters and signal mutual recognition parameters. Exemplarily, the power distribution network is concentrated on one side of the circuit board, and the circuit interconnection parameters between a peripheral electronic component and a UHV MOSFET component show that the relatively long interconnecting wire results in a large parasitic inductance, and at the same time, the signal mutual recognition parameters show that there is a large attenuation when the signal is transmitted on this interconnecting wire. According to these situations, configure the layout guidance vector to indicate that this peripheral electronic component is moved a certain distance in the direction close to the power distribution network and the UHV MOSFET component to reduce the parasitic inductance and signal attenuation.

[0056] By taking the power distribution network as the direction, combining the circuit interconnection parameters and signal mutual recognition parameters to conduct layout compactification guidance and configure the layout guidance vector, it is possible to comprehensively consider various factors such as the electrical performance of the circuit and signal transmission, provide comprehensive and accurate guidance for component layout optimization, and contribute to improving the overall performance of the circuit and the rationality of the layout.

[0057] Furthermore, as Figure 3 shown, step S6 further includes:

[0058] Step S64: Obtain the thermal loss characteristics of the UHV MOSFET component.

[0059] Step S65: Based on the preset package layout, determine an integrated heat pipe cooling structure, which has a combination of various specifications of heat pipes and various specifications of heat sinks.

[0060] Step S66: According to the thermal loss characteristics, combined with the integrated heat pipe cooling structure, determine the thermal resistance constraint condition, which is used to determine whether the heat dissipation requirement standard in the package requirement information is met.

[0061] Specifically, the thermal loss characteristic refers to the characteristic of the UHV MOSFET component generating heat during operation due to factors such as current passing through and internal electron movement, including the rate of heat generation, the distribution of heat within the component, etc. The thermal loss characteristic is closely related to factors such as the operating current, voltage, operating frequency, and internal structure of the component. The integrated heat pipe cooling structure is a structure composed of a combination of heat pipes of various specifications and heat sinks of various specifications for heat dissipation. Among them, the heat pipe is an efficient heat conduction component that uses the phase change of the internal working medium to transfer heat; the heat sink speeds up the dissipation of heat by increasing the heat dissipation area. Thermal resistance is an important parameter in the process of heat transfer. The smaller the thermal resistance, the easier it is for heat to be transferred. The thermal resistance constraint condition refers to the thermal resistance limit that the cooling structure needs to meet to ensure that the MOSFET operates at a safe working temperature, and is used to determine whether the current cooling structure can meet the heat dissipation requirement standard in the package requirement information, that is, whether heat can be effectively dissipated from the MOSFET component through the cooling structure to prevent the component temperature from being too high.

[0062] The thermal loss characteristic of the UHV MOSFET component is obtained by analyzing various factors such as its electrical characteristics, physical structure, and operating conditions. For example, thermal simulation software (such as ANSYS Icepak or Flotherm) can be used to simulate the thermal behavior of the MOSFET under different operating conditions, and a thermal imager or temperature sensor can be used to measure the actual junction temperature and surface temperature, or the power loss under different operating states can be calculated according to the power loss formula of the component (such as P = I 2 R, where P is the power loss, I is the operating current, and R is the equivalent resistance), and the power loss is converted into heat loss. Obtaining the thermal loss characteristic can accurately understand the heat generation situation of the UHV MOSFET component during operation, providing basic data for subsequent determination of a suitable cooling structure and judgment of whether the heat dissipation meets the requirements.

[0063] Based on the obtained preset packaging layout, considering factors such as the position of the UHV MOSFET component in the package and the spacing from other components, an integrated heat pipe cooling structure is determined. This process requires analyzing the heat dissipation capabilities of heat pipes and heat sinks of different specifications, and selecting appropriate heat pipes and heat sinks for combination according to the size of the packaging space, the heat dissipation requirements of the components, etc. For example, if the packaging space is limited but the heat dissipation requirement is high, heat pipes with a smaller diameter but a high thermal conductivity coefficient and heat sinks with a larger heat dissipation area but a thinner thickness can be selected for combination. Exemplarily, in a compact UHV MOSFET packaging layout, there are certain space limitations around the MOSFET components in the preset packaging layout. By simulating different combinations of heat pipes and heat sinks through heat dissipation simulation software, it is found that an integrated heat pipe cooling structure composed of a heat pipe with a diameter of 3 mm and a length of 50 mm and a heat sink with an area of 10 cm² and a thickness of 2 mm can provide good heat dissipation effect in this space, so this combination is determined as the integrated heat pipe cooling structure. Determining the appropriate integrated heat pipe cooling structure can effectively improve the heat dissipation efficiency of the UHV MOSFET component, ensure that the temperature of the component is within a reasonable range during operation, and improve the reliability and service life of the component.

[0064] According to the obtained heat loss characteristics of the UHV MOSFET component and the determined integrated heat pipe cooling structure, the thermal resistance constraint conditions are determined through the heat conduction formula (such as Q = ΔT / R, where Q is the heat transfer rate, ΔT is the temperature difference, and R is the thermal resistance). The calculated thermal resistance is compared with the heat dissipation requirement standard (such as the maximum allowable thermal resistance) in the packaging requirement information to determine whether the heat dissipation requirement is met. Determining the thermal resistance constraint conditions can effectively evaluate whether the current cooling structure can meet the heat dissipation requirements of the UHV MOSFET component, so as to ensure that the packaged component meets the requirements in terms of heat dissipation and avoid performance degradation or damage of the component caused by insufficient heat dissipation.

[0065] Further, step S65 includes:

[0066] Step S651: Perform thermal stress analysis according to the preset packaging layout to obtain the first combination of expansion coefficients.

[0067] Step S652: Perform thermal stress analysis according to the integrated heat pipe cooling structure to obtain the second combination of expansion coefficients.

[0068] Step S653: Based on the first combination of expansion coefficients and the second combination of expansion coefficients, perform a two-way balance analysis of heat dissipation requirements and packaging reliability, determine the structural compatibility constraint standard, and verify it during the process of adjusting the preset packaging layout.

[0069] Specifically, in circuit packaging, due to the different coefficients of thermal expansion (CTEs) of different materials, thermal stress will be generated when the temperature changes. Thermal stress analysis calculates and analyzes the stress distribution inside an object by considering factors such as the thermal expansion characteristics of materials, temperature distribution, and structural constraints. The combination of CTEs refers to a set of CTEs related to a specific structure (such as a preset packaging layout or an integrated heat pipe cooling structure) in thermal stress analysis. The coefficient of thermal expansion represents the degree of expansion or contraction of a material when the temperature changes. A combination of CTEs may include the CTEs of multiple materials, and these coefficients interact to affect the stress state of the entire structure when the temperature changes. The structural compatibility constraint criteria refer to the specific requirements for material selection, design parameters, etc. to ensure the reliability and heat dissipation performance of the packaging structure.

[0070] For a preset packaging layout, first determine all the materials involved in the layout, such as packaging materials, chip materials, connection materials, etc. Then, based on the CTE characteristics of these materials and the structural relationships in the preset packaging layout, consider the expansion and contraction of these materials under different operating temperature conditions, and use the relevant theories and methods of thermal stress analysis to calculate the stress distribution generated inside the structure due to temperature changes, thereby obtaining the first combination of CTEs related to the preset packaging layout. For example, finite element analysis software (such as ANSYS, etc.) can be used for thermal stress analysis. Finite element analysis software can accurately simulate the stress state of the structure under thermal load according to the input information such as material properties, geometric structure, and boundary conditions.

[0071] For an integrated heat pipe cooling structure, also determine all the materials in the structure, such as heat pipe materials, heat sink materials, etc. Analyze the thermal expansion behavior of these materials when the temperature changes and their interaction relationships. Using the thermal stress analysis method, consider factors such as the operating temperature range of the heat pipe and the temperature changes during the heat dissipation process of the heat sink, calculate the stress distribution inside the integrated heat pipe cooling structure, and then obtain the second combination of CTEs. This thermal stress analysis process can also be completed with the help of finite element analysis software.

[0072] Take the first coefficient of thermal expansion combination and the second coefficient of thermal expansion combination as key data, and conduct a two-way balance analysis of heat dissipation requirements and packaging reliability. During the analysis, in terms of heat dissipation requirements, it is necessary to ensure that the integrated heat pipe heat dissipation structure can effectively dissipate the heat generated by the UHV MOSFET components; in terms of packaging reliability, it is necessary to ensure that the preset packaging layout and the integrated heat pipe heat dissipation structure will not cause structural damage or performance degradation due to excessive thermal stress when the temperature changes. Through this two-way analysis, determine the structural compatibility constraint criteria, which include constraint conditions for material selection, structural dimensions, component layout, etc. When adjusting the preset packaging layout, it is necessary to verify according to this standard to ensure that each adjustment can meet the heat dissipation requirements while ensuring the reliability of the packaging.

[0073] Determining the structural compatibility constraint criteria and verifying them during the adjustment process of the preset packaging layout can effectively balance the heat dissipation requirements and packaging reliability, avoid ignoring the stability of the packaging structure due to excessive pursuit of heat dissipation, or affecting the heat dissipation effect due to emphasizing packaging reliability, thereby improving the comprehensive performance of the entire packaging structure.

[0074] Further, step S653 includes:

[0075] Step S653-1: Match according to the first coefficient of thermal expansion combination and the second coefficient of thermal expansion combination, collect expansion difference parameters when the temperature changes, and determine the first difference index and the stress concentration risk.

[0076] Step S653-2: Match according to the first coefficient of thermal expansion combination and the second coefficient of thermal expansion combination, collect shrinkage difference parameters when the temperature changes, and determine the second difference index and the packaging failure risk.

[0077] Step S653-3: Formulate the structural compatibility constraint criteria through the first difference index and the stress concentration risk, and the second difference index and the packaging failure risk.

[0078] Specifically, the expansion difference parameter is a quantitative index of the difference in expansion degree generated due to the different thermal expansion characteristics of materials in different structures (preset packaging layout and integrated heat pipe heat dissipation structure) represented by the first coefficient of thermal expansion combination and the second coefficient of thermal expansion combination when the temperature rises. The expansion difference parameter reflects the inconsistency of the expansion behavior of different structures when the temperature changes. The first difference index is an index calculated based on the expansion difference parameter, which is used to more intuitively represent the degree of expansion difference between different structures. This index can be used as an important basis for judging the stress concentration risk. The stress concentration risk is that when there is an expansion difference between different structures, stress concentration may occur at the connection parts or stress-sensitive areas of the structure, resulting in excessive local stress, thereby increasing the risk of structural damage or performance degradation.

[0079] The shrinkage difference parameter is similar to the expansion difference parameter. It is a quantitative index of the shrinkage degree difference generated due to the different thermal shrinkage characteristics of materials in different structures when the temperature decreases. The second difference index is an index determined based on the shrinkage difference parameter, used to represent the degree of shrinkage difference, and is an important basis for judging the risk of package failure. The risk of package failure is the risk that problems such as cracks, looseness, or poor electrical connection may occur in the package structure due to the shrinkage difference between different structures.

[0080] First, according to the preset package layout, the corresponding coefficients in the first expansion coefficient combination and the second expansion coefficient combination are matched. When the temperature rises, the expansion amount differences of each corresponding part are calculated according to the thermal expansion coefficients of different materials, and the set of these differences is the expansion difference parameter. According to the expansion difference parameter, the first difference index can be calculated, which can be the weighted average of the expansion difference parameter or other statistical calculation methods. Then, the stress concentration risk is evaluated according to the first difference index. If the first difference index is large, it means that the expansion difference is large, and the stress concentration risk at the structural connection part is high. For example, when the first difference index exceeds a certain empirical threshold, it is determined that the stress concentration risk is high, and measures may need to be taken to adjust the structure or materials. Exemplarily, in a package structure, the expansion coefficient of the chip bonding material in the preset package layout is α, and the expansion coefficient of the material near the chip bonding part in the integrated heat pipe heat dissipation structure is β. When the temperature changes by ΔT, the expansion difference parameter ΔL = L α -L β =(α - β)×L×ΔT (where L is the length of the bonding part). By determining the expansion difference parameter and the first difference index, it is possible to quantitatively evaluate the stress concentration risk caused by the expansion difference between different structures when the temperature rises, providing data support for formulating the structural compatibility constraint standard in terms of expansion difference.

[0081] Using a method similar to determining the first difference index and the stress concentration risk, the second difference index and the risk of package failure are determined. The first expansion coefficient combination and the second expansion coefficient combination are matched, and the shrinkage difference parameter is calculated according to the thermal shrinkage coefficients of different materials. The second difference index is calculated according to the shrinkage difference parameter, and algorithms such as weighted average can also be used. The risk of package failure is evaluated according to the second difference index. If the second difference index is large, it means that the shrinkage difference is large, and the risk of package failure is high. For example, problems such as package cracks and electrical connection disconnection may occur. Determining the shrinkage difference parameter and the second difference index can quantitatively evaluate the risk of package failure caused by the shrinkage difference between different structures when the temperature decreases, providing data support for formulating the structural compatibility constraint standard in terms of shrinkage difference.

[0082] The structural compatibility constraint criteria are formulated by comprehensively considering the first difference index and the stress concentration risk, as well as the second difference index and the package failure risk. If the stress concentration risk and the package failure risk are high (i.e., the first difference index and the second difference index are large), the structural compatibility constraint criteria will impose more stringent requirements on the material selection and structural design (such as component spacing, the layout of heat pipes and heat sinks, etc.). For example, if the stress concentration risk is high, the structural compatibility constraint criteria may stipulate the use of a more elastic bonding material at certain key connection parts or increase the buffer structure at the connection parts; if the package failure risk is high, it may be required to adjust the relative positions of the heat pipes and other components to reduce the impact of shrinkage differences during temperature changes.

[0083] Formulating the structural compatibility constraint criteria can ensure that the preset package layout and the integrated heat pipe heat dissipation structure have good compatibility during temperature changes, balance the heat dissipation requirements and package reliability, and reduce the risks of structural problems and performance degradation caused by thermal expansion and contraction differences.

[0084] Furthermore, step S4 further includes:

[0085] Step S41: For the connection between the source pin of the high-side MOSFET and the drain pin of the low-side MOSFET, collect a type of sensitive circuit behavior and add a first marking instruction.

[0086] Step S42: For the connection between the source pin of the high-side MOSFET and the motor winding, collect a second type of sensitive circuit behavior and add a second marking instruction.

[0087] Step S43: Obtain the compatible constraint supplementary conditions through the first type of sensitive circuit behavior and the first marking instruction, and the second type of sensitive circuit behavior and the second marking instruction.

[0088] Step S44: Based on the compatible constraint supplementary conditions, identify and proofread the conflict points of the structural compatibility constraint criteria.

[0089] Specifically, sensitive circuit behaviors occur at specific connection parts of the circuit (such as between the source pin of the high-side MOSFET and the drain pin of the low-side MOSFET, between the source pin of the high-side MOSFET and the motor winding), which are circuit operating states or phenomena that have an important impact on circuit performance, stability, or reliability, including situations such as sudden changes in current, voltage fluctuations, signal interference, etc. The marking instruction is an instruction code used to identify and distinguish different types of sensitive circuit behaviors. The first marking instruction is used to mark one type of sensitive circuit behavior, and the second marking instruction is used to mark another type of sensitive circuit behavior, facilitating subsequent processing and analysis of these behaviors. The compatible constraint supplementary conditions are obtained by analyzing and organizing different types of sensitive circuit behaviors with marking instructions. These conditions supplement the previously existing structural compatibility constraint standards, making them more comprehensive and better able to adapt to various special situations in the circuit.

[0090] Use circuit test equipment (such as oscilloscopes, current probes, etc.) to monitor the connection line between the source pin of the high-side MOSFET and the drain pin of the low-side MOSFET. Observe and record the sensitive circuit behaviors that occur (recorded as one type of sensitive circuit behavior) under normal circuit operation and various simulated abnormal operating states. For example, it may be found that when the circuit switches states, there is a short current spike on the connection line between these two points, which is one type of sensitive circuit behavior. Add the first marking instruction for one type of sensitive circuit behavior. This instruction can be a specific code or symbol used to uniquely identify one type of sensitive circuit behavior.

[0091] Similarly, use circuit test equipment to monitor the connection between the source pin of the high-side MOSFET and the motor winding. Collect the second type of sensitive circuit behaviors that occur under different operating conditions, such as different motor speeds, load changes, etc. For example, when the motor load suddenly increases, it may be found that there is a short voltage drop and fluctuation on this connection line, which is one type of the second type of sensitive circuit behavior. Add the second marking instruction for this sensitive circuit behavior.

[0092] Comprehensively analyze a type of sensitive circuit behavior with a first marking instruction and a second type of sensitive circuit behavior with a second marking instruction. For example, consider the possible impact of current spikes in a type of sensitive circuit behavior on other components in the circuit, and the chain reaction that may be triggered by a voltage drop in a second type of sensitive circuit behavior. Based on these analysis results, obtain supplementary compatibility constraint conditions. These supplementary compatibility constraint conditions include the adjustment range of component parameters, special requirements for circuit wiring, etc. For example, if a current spike may shorten the lifespan of a certain capacitor, the supplementary compatibility constraint conditions will stipulate that the voltage withstand value of this capacitor needs to be increased by a certain percentage; if a voltage drop may affect the performance of a motor, the supplementary compatibility constraint conditions will require adding a voltage stabilizing circuit on the connection line. This analysis process can use circuit analysis software (such as SPICE software) to simulate and analyze the circuit after comprehensively considering sensitive circuit behaviors to determine the supplementary compatibility constraint conditions.

[0093] Compare and analyze the supplementary compatibility constraint conditions with the existing structural compatibility constraint standards, identify points that may be mutually contradictory or inconsistent with the actual situation in the standards (i.e., conflict points), and make corrections and adjustments to ensure the accuracy and effectiveness of the structural compatibility constraint standards. For example, check whether there is a conflict between the requirements for the voltage stabilizing circuit in the supplementary conditions and the power distribution network layout in the structural compatibility constraint standards. If the addition of the voltage stabilizing circuit changes the original characteristics of the power distribution network, it is marked as a conflict point. Circuit design rule checking tools can be used to assist in identifying conflict points. For the identified conflict points, proofread according to the actual requirements and performance requirements of the circuit. For example, if the addition of the voltage stabilizing circuit does indeed affect the optimized layout of the power distribution network but is very necessary to ensure the stable operation of the motor, then it may be necessary to make fine-tuning to the layout of the power distribution network or re-evaluate the relevant clauses in the structural compatibility constraint standards.

[0094] Through conflict point identification and proofreading, it is possible to ensure that the structural compatibility constraint standards are coordinated and consistent with the newly obtained supplementary compatibility constraint conditions, improving the rationality and feasibility of the entire circuit design.

[0095] In summary, the packaging optimization method for UHV MOSFETs provided by the embodiments of this application has the following technical effects:

[0096] By determining the preset packaging layout and analyzing the influence of parasitic capacitance and inductance, the switching speed and voltage overshoot of the UHV MOSFET are optimized, the energy loss is reduced, and the stability and reliability of the circuit are improved. Secondly, by formulating an equivalent RC circuit and establishing a performance optimization model, the circuit behavior can be accurately simulated, providing a theoretical basis for performance optimization. Further, by introducing the layout compactness guidance of peripheral electronic components and the power distribution network, the maximization of space utilization and the optimization of signal transmission are achieved. In addition, by collecting sensitive circuit behaviors and adding marker instructions, compatible constraint supplementary conditions are obtained, enhancing the robustness of the circuit design. Finally, by combining the thermal loss characteristics and the integrated heat pipe heat dissipation structure, the thermal resistance constraint conditions are determined to ensure that the heat dissipation requirements and the reliability of the packaging structure are met. Generally speaking, the embodiments of the present application comprehensively consider electrical performance, thermal management, structural compatibility and sensitive circuit behaviors, realizing the comprehensive optimization of the UHV MOSFET packaging and improving the overall performance of the UHV MOSFET.

[0097] Embodiment 2, as Figure 4 shown, the embodiment of the present application provides a packaging optimization system for UHV MOSFETs, and the system includes:

[0098] A preset packaging layout module 10, configured to determine a preset packaging layout according to a UHV MOSFET component, where the UHV MOSFET component includes a high-side MOSFET source pin, a motor winding, and a low-side MOSFET drain pin.

[0099] A parasitic capacitance analysis module 20, configured to analyze the parasitic capacitance and the influence of the parasitic capacitance on the switching speed according to the preset packaging layout, obtain a first influence evaluation combination, and perform energy loss correlation analysis according to the first influence evaluation combination, and use the first energy loss correlation analysis result to establish a parasitic capacitance optimization network.

[0100] A parasitic inductance analysis module 30, configured to analyze the parasitic inductance and the influence of the parasitic inductance on the voltage overshoot according to the preset packaging layout, obtain a second influence evaluation combination, and perform energy loss correlation analysis according to the second influence evaluation combination, and use the second energy loss correlation analysis result to establish a parasitic inductance optimization network.

[0101] An equivalent RC circuit module 40, configured to formulate a plurality of equivalent RC circuits through the high-side MOSFET source pin, the motor winding, and the low-side MOSFET drain pin in the UHV MOSFET component, where the plurality of equivalent RC circuits include a series-equivalent RC circuit and a parallel-equivalent RC circuit.

[0102] The circuit equivalent combination module 50 is used to perform equivalent combination on the series-equivalent RC circuits and parallel-equivalent RC circuits in the multiple equivalent RC circuits, and establish a performance optimization model according to the parasitic capacitance optimization network and the parasitic inductance optimization network.

[0103] The package layout optimization module 60 is used to perform trade-off backtracking iteration based on the performance optimization model in combination with the package requirement information of the UHV MOSFET component, and at the same time, adjust the preset package layout to obtain the optimal package layout.

[0104] Furthermore, the execution steps of the package layout optimization module 60 in the embodiment of the present application include:

[0105] Introduce peripheral electronic components and draw up a set of peripheral circuits; perform layout compactness guidance based on the set of peripheral circuits and the power distribution network, and set a layout guidance vector; use the layout guidance vector to optimize the relative positions and connection paths between components to obtain the optimal package layout.

[0106] Furthermore, the execution steps of performing layout compactness guidance based on the set of peripheral circuits and the power distribution network and setting a layout guidance vector include:

[0107] Collect circuit interconnection parameters through the circuit interconnection method between the UHV MOSFET component and the peripheral electronic components; collect signal recognition parameters based on the set of peripheral circuits through the signal recognition method between the UHV MOSFET component and the peripheral electronic components; take the power distribution network as the direction, and perform layout compactness guidance in combination with the circuit interconnection parameters and the signal recognition parameters to configure the layout guidance vector.

[0108] Furthermore, the execution steps of the package layout optimization module 60 in the embodiment of the present application further include:

[0109] Obtain the thermal loss characteristics of the UHV MOSFET component; based on the preset package layout, determine an integrated heat pipe cooling structure, and the integrated heat pipe cooling structure has a combined configuration of various specifications of heat pipes and various specifications of heat sinks; according to the thermal loss characteristics, in combination with the integrated heat pipe cooling structure, determine a thermal resistance constraint condition, and the thermal resistance constraint condition is used to determine whether the heat dissipation requirement standard in the package requirement information is met.

[0110] Furthermore, the execution steps of determining an integrated heat pipe cooling structure based on the preset package layout, and the integrated heat pipe cooling structure has a combined configuration of various specifications of heat pipes and various specifications of heat sinks include:

[0111] Perform thermal stress analysis according to the preset packaging layout to obtain the first combination of expansion coefficients; perform thermal stress analysis according to the integrated heat pipe heat dissipation structure to obtain the second combination of expansion coefficients; based on the first combination of expansion coefficients and the second combination of expansion coefficients, conduct a two-way balance analysis of heat dissipation requirements and packaging reliability, determine the structural compatibility constraint criteria, and verify during the process of adjusting the preset packaging layout.

[0112] Further, based on the first combination of expansion coefficients and the second combination of expansion coefficients, conduct a two-way balance analysis of heat dissipation requirements and packaging reliability, and the steps for determining the structural compatibility constraint criteria include:

[0113] Match according to the first combination of expansion coefficients and the second combination of expansion coefficients, collect expansion difference parameters when the temperature changes, determine the first difference index and the risk of stress concentration; match according to the first combination of expansion coefficients and the second combination of expansion coefficients, collect shrinkage difference parameters when the temperature changes, determine the second difference index and the risk of packaging failure; formulate the structural compatibility constraint criteria through the first difference index and the risk of stress concentration, and the second difference index and the risk of packaging failure.

[0114] Further, the execution steps of the equivalent RC circuit module 40 in the embodiment of the present application further include:

[0115] For the connection between the source pin of the high-side MOSFET and the drain pin of the low-side MOSFET, collect a type of sensitive circuit behavior and add a first marking instruction; for the connection between the source pin of the high-side MOSFET and the motor winding, collect a second type of sensitive circuit behavior and add a second marking instruction; obtain the compatible constraint supplementary conditions through the first type of sensitive circuit behavior and the first marking instruction, and the second type of sensitive circuit behavior and the second marking instruction; based on the compatible constraint supplementary conditions, identify and proofread the conflict points of the structural compatibility constraint criteria.

[0116] Through the foregoing detailed description of the packaging optimization method for UHV MOSFETs in this specification, those skilled in the art can clearly know the packaging optimization system for UHV MOSFETs in this embodiment. For the system disclosed in Embodiment 2, since it corresponds to the method disclosed in Embodiment 1, it has corresponding functional modules and beneficial effects. For the relevant parts, refer to the description in the method part.

[0117] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A packaging optimization method for ultra-high voltage MOSFET, characterized in that: The method comprises: Determining a preset package layout according to an ultra-high voltage MOSFET component, wherein the ultra-high voltage MOSFET component includes a high-side MOSFET source pin, a motor winding, and a low-side MOSFET drain pin; According to the preset package layout, analyzing the parasitic capacitance and the influence of the parasitic capacitance on the switching speed, obtaining a first influence assessment combination, performing an energy loss correlation analysis according to the first influence assessment combination, and establishing a parasitic capacitance optimization network using the first energy loss correlation analysis result; According to the preset package layout, analyze the parasitic inductance and the influence of the parasitic inductance on the voltage overshoot, obtain a second influence assessment combination, perform energy loss correlation analysis according to the second influence assessment combination, and establish a parasitic inductance optimization network using the second energy loss correlation analysis result; By means of the high-side MOSFET source pin, the motor winding, and the low-side MOSFET drain pin in the UHV MOSFET element, a plurality of equivalent RC circuits are proposed, wherein the plurality of equivalent RC circuits include a series equivalent RC circuit and a parallel equivalent RC circuit; Equivalently combining the series equivalent RC circuits and the parallel equivalent RC circuits in the multiple equivalent RC circuits, and establishing a performance optimization model according to the parasitic capacitance optimization network and the parasitic inductance optimization network; Based on the performance optimization model, combined with the packaging requirement information of the UHV MOSFET element, a compromise backtracking iteration is performed, and at the same time, the preset packaging layout is adjusted to obtain an optimal packaging layout. The method includes: Introduce peripheral electronic components and formulate peripheral circuit sets; Performing layout compaction guidance based on the peripheral circuit set and the power distribution network, and setting a layout guidance vector; Using the layout guiding vector, optimizing the relative positions and connection paths between components to obtain the optimal package layout; The preset packaging layout is adjusted to obtain an optimal packaging layout, and the method further includes: Obtaining heat loss characteristics of the UHV MOSFET element; Based on the preset packaging layout, an integrated heat pipe heat dissipation structure is determined, wherein the integrated heat pipe heat dissipation structure has a combination of heat pipes of various specifications and heat sinks of various specifications; According to the heat loss characteristics, in combination with the integrated heat pipe heat dissipation structure, a thermal resistance constraint condition is determined, wherein the thermal resistance constraint condition is used to determine whether the heat dissipation requirement standard in the packaging requirement information is met; Based on the preset packaging layout, an integrated heat pipe heat dissipation structure is determined, wherein the integrated heat pipe heat dissipation structure has a combination of heat pipes of various specifications and heat sinks of various specifications, and the method includes: Performing thermal stress analysis according to the preset packaging layout to obtain a first expansion coefficient combination; Performing thermal stress analysis according to the integrated heat pipe heat dissipation structure to obtain a second expansion coefficient combination; Based on the first expansion coefficient combination and the second expansion coefficient combination, a two-way balance analysis between heat dissipation requirements and packaging reliability is performed to determine a structural compatibility constraint standard, and verification is performed during the adjustment of the preset packaging layout, the method comprising: Matching is performed according to the first expansion coefficient combination and the second expansion coefficient combination, collecting expansion difference parameters when the temperature changes, and determining a first difference index and stress concentration risk; Matching the first expansion coefficient combination and the second expansion coefficient combination, collecting shrinkage difference parameters when the temperature changes, and determining a second difference index and a packaging failure risk; A structural compatibility constraint standard is formulated based on the first difference index and stress concentration risk, the second difference index and packaging failure risk.

2. The packaging optimization method for UHV MOSFET according to claim 1, characterized in that: Based on the peripheral circuit set and the power distribution network, layout compaction guidance is performed, and a layout guidance vector is set. The method includes: Collecting circuit interconnection parameters through the circuit interconnection mode between the UHV MOSFET component and the peripheral electronic component; Based on the peripheral circuit set, signal mutual recognition parameters are collected through a signal mutual recognition method between the UHV MOSFET component and the peripheral electronic component; Taking the power distribution network as a direction, the circuit interconnection parameters and the signal mutual recognition parameters are combined to guide the layout compactness, and the layout guidance vector is configured.

3. The packaging optimization method for UHV MOSFET according to claim 1, characterized in that: By using the high-side MOSFET source pin, the motor winding, and the low-side MOSFET drain pin in the UHV MOSFET element, a plurality of equivalent RC circuits are prepared, and the method further includes: For the connection between the high-side MOSFET source pin and the low-side MOSFET drain pin, collect a class of sensitive circuit behaviors and add a first marking instruction; For the connection between the source pin of the high-side MOSFET and the motor winding, collect the second type of sensitive circuit behavior and add a second marking instruction; Obtaining a compatible constraint supplementary condition through the first type of sensitive circuit behavior and the first marking instruction, the second type of sensitive circuit behavior and the second marking instruction; Based on the compatibility constraint supplementary conditions, conflict points of the structural compatibility constraint standard are identified and proofread.

4. Packaging optimization system for UHV MOSFET, characterized in that: The system is used to execute the packaging optimization method for ultra-high voltage MOSFET according to any one of claims 1 to 3, comprising: A preset package layout module, used to determine a preset package layout according to an ultra-high voltage MOSFET component, wherein the ultra-high voltage MOSFET component includes a high-side MOSFET source pin, a motor winding, and a low-side MOSFET drain pin; A parasitic capacitance analysis module, configured to analyze parasitic capacitance and the influence of parasitic capacitance on switching speed according to the preset package layout, obtain a first influence assessment combination, perform energy loss correlation analysis according to the first influence assessment combination, and establish a parasitic capacitance optimization network using the first energy loss correlation analysis result; A parasitic inductance analysis module, configured to analyze the parasitic inductance and the influence of the parasitic inductance on the voltage overshoot according to the preset package layout, obtain a second influence assessment combination, perform an energy loss correlation analysis according to the second influence assessment combination, and establish a parasitic inductance optimization network using the second energy loss correlation analysis result; An equivalent RC circuit module, used to formulate multiple equivalent RC circuits through the high-side MOSFET source pin, the motor winding, and the low-side MOSFET drain pin in the ultra-high voltage MOSFET element, wherein the multiple equivalent RC circuits include a series equivalent RC circuit and a parallel equivalent RC circuit; A circuit equivalent combination module, used for equivalently combining the series equivalent RC circuits and the parallel equivalent RC circuits in the multiple equivalent RC circuits, and establishing a performance optimization model according to the parasitic capacitance optimization network and the parasitic inductance optimization network; A package layout optimization module, used to perform a compromise backtracking iteration based on the performance optimization model and the package requirement information of the UHV MOSFET component, and at the same time, adjust the preset package layout to obtain an optimal package layout; The execution steps of the package layout optimization module include: Introducing peripheral electronic components and formulating a peripheral circuit set; guiding layout compactness based on the peripheral circuit set and the power distribution network, and setting a layout guiding vector; using the layout guiding vector, optimizing the relative positions and connection paths between components to obtain the optimal packaging layout; Obtain the heat loss characteristics of the UHV MOSFET element; determine an integrated heat pipe heat dissipation structure based on the preset package layout, wherein the integrated heat pipe heat dissipation structure has a combination of heat pipes of various specifications and heat sinks of various specifications; determine a thermal resistance constraint condition according to the heat loss characteristics and in combination with the integrated heat pipe heat dissipation structure, wherein the thermal resistance constraint condition is used to determine whether the heat dissipation requirement standard in the package requirement information is met; Further, based on the preset packaging layout, an integrated heat pipe heat dissipation structure is determined, wherein the integrated heat pipe heat dissipation structure has a combination of heat pipes of various specifications and heat sinks of various specifications, and the execution steps include: Performing a thermal stress analysis according to the preset packaging layout to obtain a first expansion coefficient combination; performing a thermal stress analysis according to the integrated heat pipe heat dissipation structure to obtain a second expansion coefficient combination; performing a two-way balance analysis between heat dissipation requirements and packaging reliability based on the first expansion coefficient combination and the second expansion coefficient combination, determining a structural compatibility constraint standard, and performing verification during the process of adjusting the preset packaging layout; Furthermore, based on the first expansion coefficient combination and the second expansion coefficient combination, a two-way balance analysis between heat dissipation requirements and packaging reliability is performed to determine a structural compatibility constraint standard, and the execution steps include: Matching is performed based on the first expansion coefficient combination and the second expansion coefficient combination, and expansion difference parameters are collected when the temperature changes to determine a first difference index and a stress concentration risk; matching is performed based on the first expansion coefficient combination and the second expansion coefficient combination, and contraction difference parameters are collected when the temperature changes to determine a second difference index and a packaging failure risk; a structural compatibility constraint standard is formulated based on the first difference index and the stress concentration risk, the second difference index and the packaging failure risk.

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