Wiring area determination method and device, electronic equipment and readable storage medium

Abstract

The invention provides a wiring area determination method and device, electronic equipment and a readable storage medium. The method comprises the steps of dividing a top metal layer of a chip into a plurality of areas to be determined; each to-be-determined area comprises at least one pair of complete power supply wires; determining the pressure drop of each region to be determined; and based on the voltage drop of each to-be-determined area, respectively judging whether each to-be-determined area is a target area in which only power supply wiring is allowed. According to the scheme of the application, the target area with relatively large voltage drop can be found from the top metal layer of the chip, so that circuits such as clock routing and analog signal routing are not arranged in the target area during subsequent layout and wiring, the probability of voltage drop violation caused by the routing in the target area can be reduced, and the reliability of the chip is improved. And the risk of voltage drop violation is reduced.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a method, device, electronic device and readable storage medium for determining a routing area. Background Art

[0002] like Figure 1 As shown, Figure 1 The stacking structure of the chip metal layer is shown, including M1, M2, M3, M4, topM1, topM2, and AP (aluminum layer). Among them, topM1 and topM2 are the top metal layers of the chip, which have the characteristics of thick metal and large line width. Therefore, the square resistance of the top metal layer is small, and in some cases it will be used for power routing, clock routing, analog signal routing, etc.

[0003] However, there are only two top metal layers, and the resources are very limited. The routing of clock signals, analog signals, and other signals on the top metal layer will block the bumps they pass through to power the areas below or nearby, so that the power supply of these areas can only be borne by the bumps farther away, resulting in a larger voltage drop in these areas.

[0004] For areas with relatively large voltage drops (referred to as target areas), if these areas need to be powered by bumps farther away, the voltage drops will be further increased, increasing the risk of voltage drop violations. Therefore, it is necessary to determine the target areas in the chip in advance, so as to prohibit the layout of other routing lines except power routing lines in the target areas in advance. Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide a routing area determination method, device, electronic device and readable storage medium, so as to determine the target area in the chip in advance.

[0006] An embodiment of the present application provides a method for determining a routing area within a chip, comprising: dividing the top metal layer of the chip into a plurality of areas to be determined; each of the areas to be determined contains at least one pair of complete power wirings; determining a voltage drop in each of the areas to be determined; and judging whether each of the areas to be determined is a target area where only power routing is allowed based on the voltage drop of each of the areas to be determined.

[0007] In the above implementation scheme, the top metal layer of the chip is divided into multiple to-be-determined areas containing complete power wiring, and the voltage drop of each to-be-determined area is determined, and then based on the voltage drop of each to-be-determined area, it is judged whether each to-be-determined area is a target area where only power wiring is allowed. In this way, the target area with a relatively large voltage drop can be found from the top metal layer of the chip, and when performing subsequent layout and routing, clock wiring, analog signal wiring and other lines can be omitted in these target areas, thereby reducing the probability of voltage drop violations in the target area due to these wirings, and reducing the risk of voltage drop violations.

[0008] Furthermore, determining the pressure drop of each of the to-be-determined areas includes: for each of the to-be-determined areas: obtaining the pressure drop of each sampling point in the to-be-determined area; and determining the pressure drop of the to-be-determined area according to the pressure drops of each of the sampling points.

[0009] In the above implementation, the pressure drop of the entire area to be determined is determined based on the pressure drop of each sampling point in the area to be determined, which makes the pressure drop of the area to be determined more objectively reflect the pressure drop of the entire area to be determined, thereby making the determined pressure drop more representative.

[0010] Further, determining the pressure drop of the to-be-determined area according to the pressure drop of each sampling point includes: calculating the average value and standard deviation of the pressure drop of each sampling point; and calculating the sum of the average value and the standard deviation to obtain the pressure drop of the to-be-determined area.

[0011] In the above implementation, by taking the sum of the average value and the standard deviation of the pressure drop of each sampling point as the pressure drop of the area to be determined, then according to normal distribution, the pressure drop can cover about 84% of the entire area to be determined. In this way, on the one hand, the voltage drop to be determined can cover the value of most areas in the entire area to be determined, so it can be representative, so that the determination of the target area can be more objective, and there will not be a situation where too many areas are determined as target areas, which will make the design of clock signals and analog signals too difficult; on the other hand, when the area to be determined is not determined as the target area, when the clock routing, analog signal routing and other routings are subsequently laid out in the area, the area with risks is about 16% of the entire area, so even if a voltage drop violation occurs, the violation points will not be particularly large, and the clock routing and other routings themselves also have shielding lines, so the probability of violation points will be further reduced, that is, even if a voltage drop violation occurs, the violation points will not be particularly large, and engineers can adjust the violation points more easily later, that is, the sum of the average value and standard deviation of the voltage drop of each sampling point is used as the voltage drop of the area to be determined, and the subsequent voltage drop violation risk will also be acceptable.

[0012] Furthermore, before determining the pressure drop of the to-be-determined area according to the pressure drop of each sampling point, the method further includes: performing noise filtering processing on the pressure drop of each sampling point.

[0013] In the area to be determined, there may be dropped holes, cells (units, such as standard cells, etc.) with large drives, etc. For the sampling points at these locations, it is not necessary to prohibit the layout of other routings except power routing, which are noise points. In the above implementation, by first performing noise filtering on the voltage drop of each sampling point, and then determining the voltage drop of the area to be determined, the determined voltage drop will not be affected by the voltage drop of noise points such as dropped holes and cells with large drives, and thus will be more objective and representative.

[0014] Furthermore, the voltage drop at each of the sampling points is subjected to noise filtering, including: performing Fourier transform on a matrix formed by the voltage drops at the sampling points to obtain a first frequency matrix; performing noise filtering on the first frequency matrix using a preset low-pass filter to obtain a second frequency matrix; and performing inverse Fourier transform on the second frequency matrix to obtain the voltage drops at each of the sampling points after filtering.

[0015] In the above implementation, by converting the voltage drop of each sampling point to the frequency domain and filtering it with a low-pass filter, and then converting it back, the entire implementation process is relatively simple and has a faster processing speed. The top metal layer of the entire chip will be divided into a large number of areas to be determined. The processing speed advantage in each area to be determined will accumulate to form a huge processing speed advantage. Therefore, based on the above implementation, the implementation speed of the entire solution can be improved and the computing overhead can be reduced.

[0016] Further, the voltage drop of the to-be-determined area is represented by a voltage value of the to-be-determined area.

[0017] For the chip, the voltage drop value of a to-be-determined area is equal to the power supply voltage minus the voltage value of the to-be-determined area. And because the power supply voltage provided by the bump in the chip is set and consistent, for the voltage drop of any to-be-determined area, it can be directly represented by the voltage drop value obtained by subtracting the voltage value of the to-be-determined area from the power supply voltage, or it can be indirectly represented by the voltage value of the to-be-determined area. In the above implementation method, the voltage value of the to-be-determined area is used to indirectly represent the voltage drop of the to-be-determined area. Compared with the method of directly representing the calculated voltage drop value, it has one less calculation step, so that the implementation of the solution can have a higher implementation speed and reduce the computing overhead.

[0018] Furthermore, based on the voltage drop of each of the to-be-determined areas, it is judged whether each of the to-be-determined areas is a target area where only power routing is allowed, including: determining the to-be-determined area with a voltage value lower than a preset voltage threshold as the target area; determining the to-be-determined area with a voltage value higher than or equal to the preset voltage threshold as a non-target area; the non-target area is an area where other routing except power routing is allowed.

[0019] In the above implementation, the target area is selected directly by the voltage threshold. Compared with the method of calculating the voltage drop value and setting the voltage drop value threshold for selection, there is one less calculation step, so that the implementation of the solution can have a higher implementation speed and reduce the computing overhead.

[0020] Furthermore, the voltage threshold is determined according to UIr and Udrop; wherein: UIr is the convergence standard voltage of the chip; and Udrop is the increased voltage drop value when the power is supplied by the bump of the adjacent area.

[0021] UIr is the convergence standard voltage of the chip, that is, UIr is the minimum operating voltage set for the unit (standard unit or analog unit, etc.) when the chip is designed to ensure the normal operation of the chip. Udrop is the increased voltage drop value when the power is supplied by the bump of the adjacent area, that is, if the clock routing or analog signal routing is performed in an area to be determined, the voltage drop value that may occur in the area to be determined. Then, in the above implementation method, the voltage threshold is determined based on UIr and Udrop, which comprehensively considers the impact of the chip on the minimum allowable voltage and the possible voltage drop value, so that the setting of the voltage threshold is more in line with the actual chip.

[0022] Furthermore, the voltage threshold is equal to UIr+2*Udrop.

[0023] The voltage of the device set in the chip is Uvdd-Uvss, where Uvdd is the voltage of the VDD of the device, and Uvss is the voltage of the VSS of the device. For any area to be determined, when clock routing or analog signal routing is performed in the area to be determined, both VDD and VSS will be affected. At this time, Uvdd will decrease by Udrop, and Uvss will increase by Udrop. Based on this, in the above implementation method, the voltage threshold is set to be equal to UIr+2*Udrop, so that the voltage of each area to be determined that is not determined as the target area can still be higher than or equal to UIr after the voltage drop is generated even after clock routing or analog signal routing, thereby meeting the chip design requirements.

[0024] Furthermore, the voltage threshold is determined in the following manner: according to the voltage values ​​of each of the to-be-determined areas, a candidate area with the lowest voltage value is determined from each of the to-be-determined areas according to a preset ratio; and the voltage threshold is determined according to the maximum voltage value of each of the to-be-determined areas.

[0025] When the target area is determined according to the voltage threshold determined by the above implementation method, the ratio of the number of determined target areas to the total number of areas to be determined will not exceed the preset ratio, which can reserve sufficient areas for subsequent layout and routing for routing other than power routing, thereby reducing the risk of excessively increasing the difficulty of layout and routing of other routing due to determining too many areas to be determined as target areas.

[0026] Further, the pressure drop of the to-be-determined area is represented by a pressure drop value of the to-be-determined area.

[0027] Furthermore, based on the voltage drop of each of the to-be-determined areas, it is judged whether each of the to-be-determined areas is a target area where only power routing is allowed, including: determining the to-be-determined area whose voltage drop value is higher than a preset voltage drop value threshold as the target area; determining the to-be-determined area whose voltage drop value is lower than or equal to the voltage drop value threshold as a non-target area; the non-target area is an area where other routing except power routing is allowed.

[0028] Furthermore, the voltage drop value threshold is determined according to UIr and Udrop; wherein: UIr is the convergence standard voltage of the chip; and Udrop is the increased voltage drop value when the power is supplied by the bump of the adjacent area.

[0029] In the above implementation, the voltage drop threshold is determined based on UIr and Udrop, and the impact of the chip on the lowest allowable voltage and the possible voltage drop value is comprehensively considered, so that the setting of the voltage drop threshold is more in line with the actual chip.

[0030] Furthermore, the voltage drop value threshold is equal to: power supply voltage - (UIr+2*Udrop).

[0031] In the above implementation, the voltage drop threshold is set equal to the power supply voltage - (UIr+2*Udrop), so that the voltage of each area to be determined that is not determined as the target area can still be higher than or equal to UIr after the voltage drop is generated even after clock routing or analog signal routing, thereby meeting the chip design requirements.

[0032] Furthermore, the pressure drop value threshold is determined according to the following method: according to the pressure drop values ​​of each of the to-be-determined areas, a candidate area with the highest pressure drop value is determined from each of the to-be-determined areas according to a preset ratio; and the pressure drop value threshold is determined according to the maximum pressure drop value in each of the to-be-determined areas.

[0033] Based on the above implementation, sufficient areas for routing other than power routing can be reserved for subsequent layout and routing, thereby reducing the risk of excessively increasing the difficulty of layout and routing of other routing due to determining too many to-be-determined areas as target areas.

[0034] Furthermore, each of the to-be-determined areas includes a pair of complete power wirings.

[0035] In the above implementation, by limiting each area to be determined to contain only one pair of complete power wirings, it is possible to avoid over-dividing the area to be determined while ensuring that each area to be determined is a complete area affected by the power wirings. That is, it is possible to ensure that each area to be determined is a complete area affected by the power wirings while having a smaller division granularity, thereby making the divided target area more accurate.

[0036] Furthermore, each of the areas to be determined is equal to a rectangular area whose width and height are both three times of the power distance; the power distance is: the spacing distance between VDD and VSS constituting the power wiring in the top metal layer.

[0037] In the top metal layer, VDD and VSS are distributed in sequence, and a pair of VDD and VSS can form a pair of complete power wiring (PG, Power Ground). Considering that VDD and VSS have widths, and the distribution positions of VDD and VSS may change during chip design, in the above implementation, the area to be determined is set equal to a rectangular area with a width and height of 3 times the power distance. No matter where the division is performed, it can be ensured that each area to be determined can contain a pair of complete VDD and VSS, that is, it can ensure that each area to be determined is a complete area affected by the power wiring while having a smaller division granularity, thereby making the divided target area more accurate.

[0038] An embodiment of the present application also provides a device for determining a routing area within a chip, comprising: a first acquisition module, used to acquire top-level design information of the chip; a second acquisition module, used to acquire design information of all target modules from the top-level design information to obtain design information to be detected; the target modules include modules to be detected and modules around the modules to be detected; and an analysis module, used to analyze the design information to be detected to obtain a voltage drop detection result of the module to be detected.

[0039] An embodiment of the present application also provides an electronic device, including: a processor and a memory; the processor is used to execute one or more programs stored in the memory to implement any of the above-mentioned methods for determining a routing area within a chip.

[0040] A computer-readable storage medium is also provided in an embodiment of the present application. The computer-readable storage medium stores one or more programs. The one or more programs can be executed by one or more processors to implement any of the above-mentioned methods for determining routing areas within a chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0042] Figure 1 Schematic diagram of the stacking structure of metal layers in a chip;

[0043] Figure 2 A schematic diagram of a basic flow chart of a method for determining a routing area within a chip provided in an embodiment of the present application;

[0044] Figure 3 A schematic diagram of a region division situation when the region to be determined is a rectangular region equal to 3 times the power supply distance provided in an embodiment of the present application;

[0045] Figure 4 A schematic diagram of a region division situation when a region to be determined is a rectangular region with a width less than 3 times the power supply distance and greater than or equal to 2 times the power supply distance provided in an embodiment of the present application;

[0046] Figure 5 A schematic diagram of a power supply structure provided in an embodiment of the present application when no wiring other than the power wiring is arranged in an area;

[0047] Figure 6 A schematic diagram of a power supply structure when other wirings except power wirings are arranged in an area provided in an embodiment of the present application;

[0048] Figure 7 An exemplary schematic diagram of voltage value distribution of each to-be-determined area provided in an embodiment of the present application;

[0049] Figure 8 A method based on the embodiment of the present application is provided Figure 7A diagram showing the determination of the target area in the case shown;

[0050] Fig. 9 A schematic diagram of the structure of a device for determining a routing area within a chip provided in an embodiment of the present application;

[0051] Fig.10 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0052] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0053] In order to determine in advance the target areas in the chip where the voltage drop is relatively large and is not suitable for routing other than the power routing, so as to avoid these target areas for routing clock routing, analog signal routing, etc. other than the power routing during subsequent layout and routing, so as to reduce the risk of voltage drop violations, a method for determining routing areas in a chip is provided in the embodiments of the present application. Figure 2 As shown, Figure 2 A basic flow chart of a method for determining a routing area within a chip provided in an embodiment of the present application includes:

[0054] S201: Divide the top metal layer of the chip into a plurality of areas to be determined.

[0055] In the embodiment of the present application, the top metal layer of the chip refers to a thick metal layer close to the AP layer in the chip, for example Figure 1 The topM1 layer and topM2 layer are shown.

[0056] In the embodiment of the present application, each area to be determined includes at least one complete PG (power supply wiring), so that each area to be determined is a complete area affected by the PG.

[0057] In the embodiment of the present application, the power wiring, namely PG, refers to a combination of one VDD and one VSS.

[0058] See also Figure 3 As shown, in the chip, VDD and VSS are set in the same direction ( Figure 3In the case of setting in vertical spacing, in addition, it can also be set in horizontal spacing). Then, in order to enable the area to contain a pair of complete power wirings, that is, to contain a pair of VDD and VSS, the width of the area to be determined in the same direction as VDD and VSS should not be less than 2 times the power distance when dividing. The so-called power distance refers to the spacing distance (pitch) between VDD and VSS that constitute a pair of complete power wirings in the top metal layer. Among them, the spacing distance refers to the distance between the centers of adjacent VDD and VSS.

[0059] Considering that VDD and VSS have widths, and the distribution positions of VDD and VSS may change during chip design, only when the width in the same direction as VDD and VSS is not less than 3 times the power supply distance can it be ensured that no matter how the distribution positions of VDD and VSS change during the design process, there will be at least one pair of complete VDD and VSS in the to-be-determined area, for example Figure 3 shown.

[0060] For the case where the width in the same direction as VDD and VSS is less than 3 times the power supply distance but not less than 2 times the power supply distance, if the latest VDD and VSS distribution positions can be clearly obtained each time the division is performed, the division can be performed from the edge of VDD or the edge of VSS based on the latest VDD and VSS distribution positions, thereby ensuring that a complete pair of VDD and VSS is located in the area to be determined.

[0061] Accordingly, if the latest VDD and VSS distribution positions cannot be clearly obtained each time the division is performed, if the width in the same direction as VDD and VSS is less than 3 times the power supply distance, but not less than 2 times the power supply distance, then Figure 4 In this case, it cannot be guaranteed that a pair of complete VDD and VSS are located in the area to be determined. That is, if the latest VDD and VSS distribution positions cannot be clearly obtained each time the division is performed, the width in the same direction as VDD and VSS should not be less than 3 times the power supply distance.

[0062] In addition, considering that there are usually two top metal layers in the chip, and the setting methods of VDD and VSS in different top metal layers are different. That is, VDD and VSS in one top metal layer are set according to the vertical interval, while VDD and VSS in another top metal layer are set according to the horizontal interval. Then in order to ensure that the area to be determined divided in any top metal layer based on the same division method can contain at least one pair of complete VDD and VSS, in a feasible implementation of the embodiment of the present application, each area to be determined can be set as a rectangular area with a width and height greater than or equal to 3 times the power supply distance. In this way, regardless of whether the distribution position of VDD and VSS changes during the chip design process, it can be guaranteed that at least one pair of complete VDD and VSS is located in the area to be determined.

[0063] It should be noted that if the distances between the centers of adjacent VDD and VSS in the two top metal layers are different, that is, if the power supply distances in the two top metal layers are different, then: the width of the area to be determined should be set based on the power supply distance of the top metal layer in which VDD and VSS are arranged at intervals in the vertical direction, and the height of the area to be determined should be set based on the power supply distance of the top metal layer in which VDD and VSS are arranged at intervals in the horizontal direction.

[0064] For example, assume that VDD and VSS in the top metal layer topM1 are spaced apart in the vertical direction, and the power supply distance is l1; assume that VDD and VSS in the top metal layer topM1 are spaced apart in the vertical direction, and the power supply distance is l2. Assuming that each area to be determined is a rectangular area with a width and height equal to 3 times the power supply distance, the actual size of the rectangular area is: a rectangular area with a width of 3*l1 and a height of 3*l2.

[0065] In the embodiment of the present application, the length of the rectangular area in the horizontal direction is the width of the rectangular area, and the length of the rectangular area in the vertical direction is the height of the rectangular area.

[0066] In a feasible implementation of the embodiment of the present application, each area to be determined can be configured to contain only one pair of complete power wiring. In this way, while ensuring that each area to be determined is a complete area affected by the power wiring, it is possible to avoid the area to be determined from being divided too large. In other words, while ensuring that each area to be determined is a complete area affected by the power wiring, it is possible to have a smaller division granularity, thereby making the divided target area more accurate.

[0067] For example, in an optional embodiment, the area to be determined can be set equal to a rectangular area with a width and height of 3 times the power supply distance. In this way, as mentioned above, no matter whether the distribution position of VDD and VSS changes during the chip design process, and whether the wiring direction changes, no matter where the area to be determined is divided from the top metal layer, it can be guaranteed that a pair of complete VDD and VSS can fall into the area to be determined. While ensuring that each area to be determined is a complete area affected by power supply wiring, it can have a smaller division granularity, thereby making the divided target area more accurate.

[0068] S202: Determine the pressure drop of each area to be determined.

[0069] In the embodiment of the present application, voltage drop is a parameter that represents the voltage drop degree generated when the power supply voltage VDD of the chip is supplied to a position or an area in the chip. That is, the voltage drop of each to-be-determined area represents the voltage drop degree generated when the power supply voltage is supplied to the to-be-determined area.

[0070] Therefore, for the chip, the voltage drop value of a voltage drop in a to-be-determined region is equal to the power supply voltage minus the voltage value of the to-be-determined region.

[0071] Therefore, in a feasible implementation of the embodiment of the present application, the voltage drop of the to-be-determined area may be directly represented by a voltage drop value obtained by subtracting the voltage value of the to-be-determined area from the power supply voltage.

[0072] In another feasible implementation of the embodiment of the present application, since the power supply voltage provided by the bump in the chip is set and consistent, that is, the power supply voltage VDD is known and is the same for each area to be determined, the voltage value of the area to be determined can also be used to represent the voltage drop of the area to be determined, thereby achieving indirect representation of the voltage drop of the area to be determined. In this way, compared with the feasible implementation of calculating the voltage drop value to directly represent the voltage drop, this feasible implementation has one less calculation step, so that the implementation of the solution can have a higher implementation speed and reduce the calculation overhead.

[0073] In a feasible implementation of the embodiment of the present application, for each area to be determined: the pressure drop of each sampling point in the area to be determined is obtained respectively, and the pressure drop of the area to be determined is determined according to the pressure drop of each sampling point. In this way, the pressure drop of the area to be determined obtained takes into account the pressure drop of each sampling point in the area to be determined, so it can more objectively reflect the pressure drop of the entire area to be determined, so that the determined pressure drop is more representative.

[0074] In an embodiment of the present application, the sampling points can be determined from the area to be determined in sequence according to the set step size. Among them, the step size can be set as needed. It can be understood that the smaller the step size is set, the more sampling points there are, and the more objective and accurate the pressure drop of the area to be determined is, but the corresponding time and calculation costs are also greater; the larger the step size is set, the fewer sampling points there are, and the objectivity of the pressure drop of the area to be determined is worse than that of the case where the step size is set small, but the time and calculation costs are also smaller. Therefore, the step size can be set based on the objective requirements for the pressure drop of the area to be determined and the requirements for time and calculation costs.

[0075] In the embodiment of the present application, for any area to be determined, there may be multiple ways to determine the pressure drop of the area to be determined based on the pressure drops of each sampling point.

[0076] For example, the average value and standard deviation of the pressure drop at each sampling point can be calculated, and the sum of the average value and the standard deviation can be calculated to obtain the pressure drop of the area to be determined. According to the normal distribution, the pressure drop of the area to be determined in this way can cover about 84% of the area in the entire area to be determined. In this way, on the one hand, the voltage drop to be determined can cover the value of most areas in the entire area to be determined, so it can be representative, so that the determination of the target area can be more objective, and there will not be a situation where too many areas are determined as target areas, which will make the design of clock signals and analog signals too difficult; on the other hand, when the area to be determined is not determined as the target area, when the clock routing, analog signal routing and other routings are subsequently laid out in the area, the area with risks is about 16% of the entire area, so even if a voltage drop violation occurs, the violation points will not be particularly large, and the clock routing and other routings themselves also have shielding lines, so the probability of violation points will be further reduced, that is, even if a voltage drop violation occurs, the violation points will not be particularly large, and engineers can adjust the violation points more easily later, that is, the sum of the average value and standard deviation of the voltage drop of each sampling point is used as the voltage drop of the area to be determined, and the subsequent voltage drop violation risk will also be acceptable.

[0077] As another example, only the average value of the pressure drops at the sampling points may be calculated, and the average value may be used as the pressure drop of the area to be determined.

[0078] Alternatively, and again illustratively, the maximum value of the pressure drops at the sampling points may be used as the pressure drop of the area to be determined.

[0079] Alternatively, and again illustratively, the minimum value of the pressure drops at each sampling point may be used as the pressure drop of the area to be determined.

[0080] Considering that in the divided area to be determined, there may be situations such as dropped holes, cells with large drives (such as standard cells, etc.) at the position, etc. For these positions, it is not necessary to prohibit the layout of other routings except power routing. Therefore, once the sampling point is located at these positions, the sampling point can be considered as a noise point. Therefore, in some optional implementations of the embodiments of the present application, before determining the voltage drop of the area to be determined based on the voltage drop of each sampling point, the voltage drop of each sampling point may be subjected to noise filtering. In this way, the voltage drop of the determined area to be determined will not be affected by the voltage drop at noise points such as dropped holes and cells with large drives at the position, so that it can be more objective and more representative. Of course, in other optional implementations, noise filtering may not be performed.

[0081] In order to achieve noise filtering processing for the voltage drop at each sampling point, an optional implementation method is: Fourier transform can be performed on the matrix formed by the voltage drop of the sampling points to obtain a first frequency matrix, and then a preset low-pass filter is used to perform noise filtering on the first frequency matrix to obtain a second frequency matrix, and then the second frequency matrix is ​​inverse Fourier transformed to obtain the voltage drop of each sampling point after filtering.

[0082] Exemplarily, for any region to be determined, the voltage drops of all sampling points in the region to be determined can be recorded as a matrix f(x, y), where x and y are the coordinates of each sampling point in the region to be determined.

[0083] Perform Fourier transform on f(x, y): F(u, v) = FFT(f(x, y)). FFT is Fourier transform, and obtain the first frequency matrix F(u, v). u and v are the coordinates of each element in the first frequency matrix.

[0084] The low pass filter can be set to:

[0085]

[0086] Among them, p and q are the coordinates of the midpoint of the first frequency matrix F(u, v), that is, p = (u max +u min ) / 2,q=(v max +v min ) / 2,u max is the maximum u value in F(u, v), u min is the minimum u value in F(u, v), v max is the maximum v value in F(u, v), v min is the minimum v value in F(u, v), and D0 is the cutoff frequency of the first frequency matrix F(u, v).

[0087] At this time, the method of using the preset low-pass filter to filter the noise of the first frequency matrix F(u, v) is as follows: for each element in F(u, v), the coordinates (u, v) corresponding to the element are substituted into the above low-pass filter, the filter value H(u, v) corresponding to the element is determined, and then the element is multiplied by the filter value corresponding to the element. In this way, when all elements are multiplied by the corresponding filter values, the second frequency matrix K(u, v) can be obtained.

[0088] Then, K(u, v) is subjected to inverse Fourier transform: f2(x, y)=IFFT(K(u, v)). IFFT is an inverse Fourier transform function.

[0089] f2(x, y) is the matrix after f(x, y) filters out the noise points.

[0090] Based on the above optional implementation, noise points can be easily filtered out using a low-pass filter, and the entire implementation process is relatively simple with a faster processing speed. The top metal layer of the entire chip will be divided into a large number of areas to be determined, and the processing speed advantage on each area to be determined will accumulate to form a huge processing speed advantage, thereby improving the implementation speed of the entire solution and reducing computing overhead.

[0091] In the embodiment of the present application, in addition to being implemented by the above-mentioned filter H(u, v), the low-pass filter may also be implemented by other low-pass filters such as a Gaussian filter, which is not limited in the embodiment of the present application.

[0092] In other optional implementations, the voltage drop of each sampling point may be denoised by using, but not limited to, a denoising algorithm such as a wavelet denoising algorithm, a wavelet packet denoising algorithm, or the like; or after learning the features of noise points and normal sampling points using a neural network model, the voltage drop of each sampling point may be denoised by using the trained neural network model; or the voltage drop of each sampling point may be denoised by using a data cleaning method, for example, by removing outliers or outliers to achieve denoising. The determination method of outliers or outliers may be implemented by an existing method, and the embodiments of the present application will not be described in detail.

[0093] In the embodiment of the present application, the voltage drop of each sampling point in the area to be determined can also be directly represented by the voltage drop value of each sampling point, or can be indirectly represented by the voltage value of each sampling point. At this time, there are the following four optional implementations:

[0094] Embodiment 1: When the pressure drop value of each sampling point is used to directly represent the pressure drop, and the pressure drop of the area to be determined is also directly represented by the pressure drop value, the pressure drop value of the area to be determined can be directly determined according to the pressure drop value of each sampling point in the manner described above.

[0095] Implementation method 2: When the voltage drop is directly represented by the voltage drop value of each sampling point, and the voltage drop of the area to be determined is indirectly represented by a voltage value, the voltage drop value of the area to be determined can be determined according to the voltage drop value of each sampling point in the manner described above, and then the voltage drop value is subtracted from the power supply voltage VDD to obtain the voltage value of the area to be determined.

[0096] Embodiment 3: When the voltage value of each sampling point is used to indirectly represent the voltage drop, and the voltage drop of the area to be determined is also indirectly represented by the voltage value, the voltage value of the area to be determined can be directly determined according to the voltage value of each sampling point in the manner described above.

[0097] Embodiment 4: When the voltage value of each sampling point is used to indirectly represent the voltage drop, and the voltage drop of the area to be determined is directly represented by the voltage drop value, the voltage value of the area to be determined can be determined according to the voltage value of each sampling point in the manner described above, and then the voltage value is subtracted from the power supply voltage VDD to obtain the voltage drop value of the area to be determined.

[0098] It can be understood that during the chip design process, what can be directly obtained through the tool is the voltage value of each sampling point. Therefore, when using the above-mentioned implementation mode three and implementation mode four, the calculation required is less than that of implementation mode one and implementation mode two, and implementation mode three is less than implementation mode four. This makes it possible to have a faster processing speed and less processing overhead when using the above-mentioned implementation mode three and implementation mode four.

[0099] S203: Determine whether each of the to-be-determined areas is a target area where only power supply routing is allowed based on the voltage drop of each to-be-determined area.

[0100] In the embodiment of the present application, the target area is an area where only power routing is allowed.

[0101] In the embodiment of the present application, whether each area to be determined is a target area where only power supply routing is allowed can be determined by presetting a voltage drop value threshold or a voltage threshold.

[0102] For example, when the voltage drop of each to-be-determined area is directly represented by a voltage drop value, the to-be-determined area with a voltage drop value higher than a voltage drop value threshold can be determined as a target area, and the to-be-determined area with a voltage drop value lower than or equal to the voltage drop value threshold can be determined as a non-target area. The non-target area refers to an area where other routing except power routing is allowed. It can be understood that power routing can also be laid in the non-target area.

[0103] Exemplarily, when the voltage drop of each to-be-determined area is indirectly represented by a voltage value, the to-be-determined area with a voltage value lower than a preset voltage threshold can be determined as a target area, and the to-be-determined area with a voltage value higher than or equal to the preset voltage threshold can be determined as a non-target area.

[0104] In an optional implementation of the embodiment of the present application, the voltage drop threshold or voltage threshold can be determined based on UIr and Udrop, where UIr is the convergence standard voltage of the chip and Udrop is the voltage drop value added when the bump in the adjacent area supplies power.

[0105] The so-called convergence standard voltage refers to the minimum operating voltage set for a unit (standard unit or analog unit, etc.) during chip design to ensure the normal operation of the chip. This voltage value can be obtained from the design specification information of the chip, but is not a limitation.

[0106] Udrop is the voltage drop value added when the bump of the adjacent area is powered, that is, the voltage drop value that may occur in the undetermined area when clock routing or analog signal routing is performed in the undetermined area.

[0107] See also Figure 5 and Figure 6 As shown. Figure 5 As shown in the figure, when there is no clock routing or analog signal routing in the area, the bump corresponding to the area will directly supply power to the power supply point (the green point in the figure). When there is no clock routing or analog signal routing in the area, the bump in the area will not be able to use the shortest path for power supply, and needs to be powered from the bump in the adjacent area without routing, such as Figure 6 As shown (the blue area in the figure is the area for other signal routing), compared to Figure 5 For the L line, there will be an extra L line distance, that is, an extra voltage drop of the L line length. This extra voltage drop of the L line length is Udrop.

[0108] In the embodiment of the present application, Udrop can be calculated by the following method:

[0109] Udrop=I*R=Is*ρ*L / (W*T); where W is the line width of the power trace, T is the thickness of the top metal layer, Is is the current of each power trace on the top metal layer, and ρ is the resistivity of the power trace.

[0110] Is = Iv*n2, where Iv is the current of each via on the top metal layer, and n2 is the number of vias required for each power trace on the top metal layer, which is determined by the line width of the power trace.

[0111] And Iv = I / n1, where I is the total current of the chip and n1 is the number of vias in the top metal layer of the chip.

[0112] And I = P / U. Among them, P is the total power consumption of the chip, and U is the operating voltage of the chip. P can be calculated by EDA tools.

[0113] Wherein, L is the extra routing distance when power is supplied from the bump of the adjacent unrouted area as mentioned above. This distance can be set by collecting statistics of the extra routing distances when power is supplied from the bump of the adjacent unrouted area in various existing chip designs.

[0114] Then, in the above optional implementation, the voltage threshold is determined based on UIr and Udrop, which comprehensively considers the impact of the chip on the lowest allowable voltage and the possible voltage drop value, so that the setting of the voltage threshold is more in line with the actual chip.

[0115] Since the voltage of the device set in the chip is Uvdd-Uvss, where Uvdd is the voltage of the VDD of the device, and Uvss is the voltage of the VSS of the device. For any area to be determined, when clock routing or analog signal routing is performed in the area to be determined, both VDD and VSS will be affected. At this time, Uvdd will decrease by Udrop, and Uvss will increase by Udrop. Therefore, in some exemplary embodiments, the voltage threshold can be set to be equal to UIr+2*Udrop, or to a value greater than UIr+2*Udrop; or, the voltage drop value threshold is set to be equal to the power supply voltage-(UIr+2*Udrop), or to a value less than the power supply voltage-(UIr+2*Udrop). In this way, the voltage of the area after the voltage drop is generated in each area to be determined that has not been determined as the target area can still be higher than or equal to UIr even after clock routing or analog signal routing is performed, thereby meeting the chip design requirements.

[0116] In another optional implementation of the embodiment of the present application, the voltage drop value threshold or voltage threshold may also be set by an engineer based on experience.

[0117] In another optional implementation of the embodiment of the present application, the voltage drop value threshold or voltage threshold may also be determined based on the voltage drop of each area to be determined, and the area to be determined with the lowest voltage value (or the highest voltage drop value) is determined from each area to be determined according to a preset ratio, and then the voltage threshold is determined based on the maximum voltage value (or the lowest voltage drop value) in each area to be determined.

[0118] For example, assuming that there are 10,000 areas to be determined, and the target area cannot exceed 1 / 100 of the total number of areas to be determined, then 100 areas to be determined with the largest voltage drop (i.e., the largest voltage drop value but the smallest voltage value) are selected, and the voltage drop value threshold or voltage threshold is set according to the minimum voltage drop value or the maximum voltage value in the 100 areas to be determined. For example, the minimum voltage drop value is used as the voltage drop value threshold, and the maximum voltage value is used as the voltage threshold.

[0119] A layout and routing method is also provided in an embodiment of the present application, including: in the top metal layer, laying out clock routing or analog signal routing or digital signal routing in areas other than the target area; and laying out power routing in the target area of ​​the top metal layer.

[0120] During layout and routing, various types of routing including power routing, clock routing, analog signal routing, digital signal routing, etc. can also be arranged in various areas of the top metal layer except the target area.

[0121] Based on the method for determining the routing area within a chip provided by the embodiment of the present application, the top metal layer of the chip is divided into multiple areas to be determined that contain complete power wiring, and the voltage drop of each area to be determined is determined, and then based on the voltage drop of each area to be determined, it is judged whether each area to be determined is a target area that only allows power routing. In this way, the target area with a relatively large voltage drop can be found from the top metal layer of the chip. When performing subsequent layout and routing, clock routing, analog signal routing and other lines can be omitted in these target areas, thereby reducing the probability of voltage drop violations in the target area due to these routings, and reducing the risk of voltage drop violations.

[0122] To facilitate understanding of the solution of the embodiment of the present application, a specific implementation method is taken as an example below to further illustrate the present application.

[0123] For the top metal layer of the chip, the top metal layer is divided into a plurality of non-overlapping areas to be determined using rectangles with a width three times the power supply distance.

[0124] For each area to be determined, the voltage values ​​of each sampling point in the area are collected in sequence according to a preset step size to obtain a matrix f(x, y).

[0125] Perform Fourier transform on f(x, y): F(u, v) = FFT(f(x, y)).

[0126] The low-pass filter H(u, v) is multiplied by F(u, v) to obtain the matrix K(u, v). The specific content of H(u, v) is described above.

[0127] Perform inverse Fourier transform on K(u,v): f2(x,y)=IFFT(K(u,v)). IFFT is the inverse Fourier transform function.

[0128] Convert f2(x, y) into a one-dimensional sequence, calculate their average value u and standard deviation σ, and use the value of u+σ as the voltage value of the area to be determined.

[0129] Calculate UIr+2Udrop to get the voltage threshold Ut.

[0130] All areas with voltage values ​​lower than Ut are identified as target areas.

[0131] Assume that the voltage values ​​of each area to be determined are as follows Figure 7 Assuming Ut is 0.87, see Figure 8 As shown, the area corresponding to each voltage value in the red frame can be determined as the target area.

[0132] Based on the same inventive concept, the present application also provides a device 900 for determining a routing area in a chip. Fig. 9 As shown, Fig. 9 Shows the use of Figure 2 The method of determining the routing area in the chip of the device 900 is shown. It should be understood that the specific functions of the device 900 can be referred to the description above, and the detailed description is appropriately omitted here to avoid repetition. The device 900 includes at least one software function module that can be stored in the memory in the form of software or firmware or fixed in the operating system of the device 900. Specifically:

[0133] See also Fig. 9 As shown, the device 900 includes: a division module 901, a voltage drop determination module 902 and an area determination module 903. Among them:

[0134] A division module 901 is used to divide the top metal layer of the chip into a plurality of to-be-determined regions; each of the to-be-determined regions contains at least one pair of complete power wirings;

[0135] A pressure drop determination module 902, used to determine the pressure drop of each of the to-be-determined areas;

[0136] The area determination module 903 is used to determine whether each of the to-be-determined areas is a target area where only power supply routing is allowed based on the voltage drop of each of the to-be-determined areas.

[0137] In a feasible implementation of the embodiment of the present application, the pressure drop determination module 902 is specifically used to: for each area to be determined: obtain the pressure drop of each sampling point in the area to be determined, and determine the pressure drop of the area to be determined based on the pressure drops of each sampling point.

[0138] In an optional embodiment of this feasible implementation mode, the pressure drop determination module 902 is specifically used to: calculate the average value and standard deviation of the pressure drop of each sampling point, and calculate the sum of the average value and the standard deviation to obtain the pressure drop of the area to be determined.

[0139] In an optional embodiment of this feasible implementation mode, the pressure drop determination module 902 is further used to perform noise filtering on the pressure drop of each sampling point before determining the pressure drop of the to-be-determined area according to the pressure drop of each sampling point.

[0140] In this optional embodiment, the voltage drop determination module 902 is specifically used to: perform Fourier transform on the matrix formed by the voltage drops of the sampling points to obtain a first frequency matrix; use a preset low-pass filter to perform noise filtering on the first frequency matrix to obtain a second frequency matrix; perform inverse Fourier transform on the second frequency matrix to obtain the voltage drops of each of the sampling points after filtering.

[0141] In a feasible implementation manner of the embodiment of the present application, the voltage drop of the to-be-determined area is represented by a voltage value of the to-be-determined area.

[0142] In this feasible implementation manner, the area determination module 903 is specifically used to: determine the to-be-determined area whose voltage value is lower than a preset voltage threshold as the target area; determine the to-be-determined area whose voltage value is higher than or equal to the preset voltage threshold as the non-target area; the non-target area is an area where other routing except power routing is allowed.

[0143] In an optional embodiment of this feasible implementation mode, the voltage threshold is determined according to UIr and Udrop; wherein: UIr is the convergence standard voltage of the chip; and Udrop is the increased voltage drop value when the power is supplied by the bump of the adjacent area.

[0144] In an optional exemplary manner of this optional embodiment, the voltage threshold is equal to UIr+2*Udrop.

[0145] In another optional embodiment of this feasible implementation method, the voltage threshold is determined according to the following method: according to the voltage values ​​of each of the to-be-determined areas, a to-be-determined area with the lowest voltage value is determined from each of the to-be-determined areas according to a preset ratio; and the voltage threshold is determined according to the maximum voltage value of each of the to-be-determined areas.

[0146] In a feasible implementation manner of the embodiment of the present application, the pressure drop of the to-be-determined area is represented by a pressure drop value of the to-be-determined area.

[0147] In this feasible implementation manner, the area determination module 903 is specifically used to: determine the to-be-determined area whose voltage drop value is higher than a preset voltage drop value threshold as the target area; determine the to-be-determined area whose voltage drop value is lower than or equal to the voltage drop value threshold as a non-target area; the non-target area is an area where other routing except power routing is allowed.

[0148] In an optional embodiment of this feasible implementation method, the voltage drop value threshold is determined according to UIr and Udrop; wherein: UIr is the convergence standard voltage of the chip; and Udrop is the increased voltage drop value when the power is supplied by the bump of the adjacent area.

[0149] In an optional exemplary manner of this optional embodiment, the voltage drop value threshold is equal to: power supply voltage-(UIr+2*Udrop).

[0150] In another optional embodiment of this feasible implementation mode, the pressure drop value threshold is determined according to the following method: according to the pressure drop value of each of the to-be-determined areas, a to-be-determined area with the highest pressure drop value is determined from each of the to-be-determined areas according to a preset ratio; and the pressure drop value threshold is determined according to the maximum pressure drop value in each of the to-be-determined areas.

[0151] In a feasible implementation manner of the embodiment of the present application, each of the to-be-determined areas includes a pair of complete power wirings.

[0152] In a feasible implementation manner of the embodiment of the present application, each of the areas to be determined is equal to a rectangular area whose width and height are both 3 times the power distance; the power distance is: the spacing distance between VDD and VSS constituting the power wiring in the top metal layer.

[0153] It should be understood that, for the sake of brevity, some of the contents described in the method embodiments will not be repeated in the device embodiments.

[0154] Based on the same inventive concept, the present application embodiment provides an electronic device, see Fig.10 As shown, it includes a processor 1001 and a memory 1002. Among them:

[0155] The processor 1001 is used to execute one or more programs stored in the memory 1002 to implement the above-mentioned method for determining the routing area in the chip.

[0156] Processor 1001 The processor can be a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), an AI (Artificial Intelligence) processor, an NPU (Neural Network Processing Unit), an ISP (Image Signal Processor), a DPU (Display Processing Unit), a VPU (Video Processing Unit), a DSP (Digital Signal Processor) data processing core, etc., or it can be a processor chip used in some data computing scenarios, such as the CPU, GPU, AI processor, NPU, ISP, DPU, VPU, DSP, etc. mentioned above. Memory 1002 can be RAM (Random Access Memory), ROM (Read-Only Memory), or flash memory. The above is only an example and should not be a limitation to this application.

[0157] Fig.10 The structure shown is for illustration only. The electronic device may also include Fig.10 More or fewer components as shown, or with Fig.10 For example, it may also have an internal communication bus for realizing communication between the processor 1001 and the memory 1002; for another example, it may also have an external communication interface, such as a USB (Universal Serial Bus) interface, a CAN (Controller Area Network) bus interface, etc.; for another example, it may also have an information display component such as a display screen, but this is not a limitation.

[0158] The electronic device may be a server, an intelligent terminal (such as a host, a smart phone, a laptop computer, a desktop computer, a vehicle terminal, an intelligent operating platform, etc.), or other device with data processing capabilities, but this is not a limitation.

[0159] Based on the same inventive concept, this embodiment also provides a computer-readable storage medium, such as a floppy disk, an optical disk, a hard disk, a flash memory, a USB flash disk, an SD (Secure Digital Memory Card) card, an MMC (Multimedia Card) card, etc., in which one or more programs for implementing the above steps are stored, and the one or more programs can be executed by one or more processors to implement the above-mentioned method for determining the routing area in the chip. No further details will be given here.

[0160] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0161] In addition, the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0162] Furthermore, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0163] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0164] As used herein, a plurality refers to two or more than two.

[0165] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for determining a routing area within a chip, characterized in that: include: Dividing the top metal layer of the chip into a plurality of areas to be determined; Each of the to-be-determined areas contains at least one pair of complete power wirings; Determining the pressure drop of each of the to-be-determined areas; Based on the voltage drop of each of the to-be-determined areas, it is determined whether each of the to-be-determined areas is a target area where only power supply routing is allowed.

2. The method for determining a routing area in a chip according to claim 1, wherein: Determining the pressure drop of each of the to-be-determined areas includes: For each of the areas to be determined: Obtaining the pressure drop of each sampling point in the area to be determined; The pressure drop of the to-be-determined area is determined according to the pressure drops of the sampling points.

3. The method for determining a routing area in a chip according to claim 2, wherein: Determining the pressure drop of the to-be-determined area according to the pressure drop of each sampling point includes: Calculate the average value and standard deviation of the pressure drop at each of the sampling points; The sum of the average value and the standard deviation is calculated to obtain the pressure drop of the area to be determined.

4. The method for determining a routing area in a chip according to claim 2, wherein: Before determining the pressure drop of the to-be-determined area according to the pressure drops of the sampling points, the method further includes: A noise filtering process is performed on the voltage drop at each sampling point.

5. The method for determining a routing area in a chip according to claim 4, wherein: The voltage drop at each sampling point is subjected to noise filtering, including: Performing Fourier transform on the matrix formed by the voltage drops at the sampling points to obtain a first frequency matrix; Using a preset low-pass filter to perform noise filtering on the first frequency matrix to obtain a second frequency matrix; Perform an inverse Fourier transform on the second frequency matrix to obtain the voltage drop of each of the sampling points after filtering.

6. The method for determining a routing area in a chip according to claim 1, wherein: The voltage drop of the to-be-determined area is represented by a voltage value of the to-be-determined area.

7. The method for determining a routing area in a chip according to claim 6, wherein: Determining whether each of the to-be-determined areas is a target area where only power supply routing is allowed based on the voltage drop of each of the to-be-determined areas includes: Determine the to-be-determined area whose voltage value is lower than a preset voltage threshold as the target area; The to-be-determined area with a voltage value higher than or equal to a preset voltage threshold is determined as a non-target area; the non-target area is an area where other routing except power routing is allowed.

8. The method for determining a routing area in a chip according to claim 7, wherein: The voltage threshold is determined according to UIr and Udrop; wherein: The UIr is the convergence standard voltage of the chip; the Udrop is the increased voltage drop value when the power is supplied by the bump of the adjacent area.

9. The method for determining a routing area in a chip according to claim 8, wherein: The voltage threshold is equal to UIr+2*Udrop.

10. The method for determining a routing area in a chip according to claim 7, wherein: The voltage threshold is determined according to the following method: According to the voltage values ​​of the to-be-determined regions, a to-be-selected region with the lowest voltage value is determined from the to-be-determined regions according to a preset ratio; The voltage threshold is determined according to the maximum voltage value in each of the to-be-selected areas.

11. The method for determining a routing area in a chip according to claim 1, wherein: The pressure drop of the to-be-determined area is represented by a pressure drop value of the to-be-determined area.

12. The method for determining a routing area in a chip according to claim 11, wherein: Determining whether each of the to-be-determined areas is a target area where only power supply routing is allowed based on the voltage drop of each of the to-be-determined areas includes: Determine the to-be-determined area whose pressure drop value is higher than a preset pressure drop value threshold as the target area; The to-be-determined area whose voltage drop value is lower than or equal to the voltage drop value threshold is determined as a non-target area; the non-target area is an area where other routing except power routing is allowed.

13. The method for determining a routing area in a chip according to claim 12, wherein: The pressure drop value threshold is determined according to UIr and Udrop; wherein: The UIr is the convergence standard voltage of the chip; the Udrop is the increased voltage drop value when the power is supplied by the bump of the adjacent area.

14. The method for determining a routing area in a chip according to claim 13, wherein: The voltage drop value threshold is equal to: power supply voltage - (UIr+2*Udrop).

15. The method for determining a routing area in a chip according to claim 12, wherein: The voltage drop value threshold is determined according to the following method: According to the pressure drop values ​​of the to-be-determined regions, determining the to-be-selected region with the highest pressure drop value from the to-be-determined regions according to a preset ratio; The pressure drop value threshold is determined according to the maximum pressure drop value in each of the to-be-selected areas.

16. The method for determining a routing area in a chip according to any one of claims 1 to 15, characterized in that: Each of the to-be-determined areas includes a pair of complete power wirings.

17. The method for determining a routing area in a chip according to any one of claims 1 to 15, characterized in that: Each of the areas to be determined is equal to a rectangular area whose width and height are both three times the power distance; the power distance is: the spacing distance between VDD and VSS constituting the power wiring in the top metal layer.

18. A device for determining a routing area in a chip, characterized in that: include: A division module, used for dividing the top metal layer of the chip into a plurality of areas to be determined; Each of the to-be-determined areas contains at least one pair of complete power wirings; A pressure drop determination module, used to determine the pressure drop of each of the to-be-determined areas; The area determination module is used to determine whether each of the to-be-determined areas is a target area where only power supply routing is allowed based on the voltage drop of each of the to-be-determined areas.

19. An electronic device, characterized in that: include: Processor and memory; The processor is used to execute one or more programs stored in the memory to implement the method for determining the routing area in a chip as described in any one of claims 1-17.

20. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the method for determining the routing area within a chip as described in any one of claims 1-17.

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