Circuit for generating peak voltage pulse and preparation method of transistor

Abstract

The invention discloses a circuit for generating a peak voltage pulse and a preparation method of a transistor, relates to the field of bionic design of integrated circuits, and aims to solve the problem that complex biological information cannot be stably and efficiently converted into an electric signal in the prior art. The circuit at least comprises a capacitor unit, a transistor unit and an inverter unit which are connected with one another, the transistor unit comprises a first transistor, and the inverter unit comprises a first transistor and a second transistor; the first transistor and the second transistor are an N-type semiconductor IGZO transistor and a P-type semiconductor LTPS transistor which are prepared based on a low-temperature metal oxide and a low-temperature polycrystalline oxide respectively; based on an input current signal, the circuit generates a peak voltage pulse signal for representing biological information collected by a sensor by using a capacitor unit, a transistor unit and an inverter unit; the device can adapt to complex mechanical deformation and irregular structures in a biological environment, is attached to biological tissues, and simulates the transmission process of electric signals in a biological system.

Description

Technical Field

[0001] The invention relates to the field of integrated circuit bionic design, in particular to a circuit for generating peak voltage pulses and a preparation method of a transistor. Background Art

[0002] In biological systems, signal transmission mainly relies on the transmission and regulation of electrical signals. In particular, the change of current in the nervous system is crucial in the process of information transmission and processing. In the field of neuromorphic computing, converting complex biological signals into processable electrical signals is the core challenge for achieving efficient biomimetic computing.

[0003] Although the rigid bionic circuits designed in the prior art can achieve the accuracy requirements in frequency regulation, they cannot adapt to the complex mechanical deformations and irregular structures in the biological environment. Therefore, they cannot stably and efficiently convert complex biological signals into electrical signals and are not suitable for application in neuromorphic computing and bionic sensors.

[0004] Based on this, there is an urgent need to design a circuit structure that can be applied to neuromorphic computing and bionic sensors to solve the problem that the existing technology cannot stably and efficiently convert complex biological signals into electrical signals. Summary of the invention

[0005] The purpose of the present invention is to provide a circuit for generating a spike voltage pulse and a method for preparing a transistor. By using a circuit for generating a spike voltage pulse composed of a capacitor unit, a transistor unit and an inverter unit, a constant current source drive can be realized, and complex biological signals can be stably and efficiently converted into electrical signals to obtain spike voltage pulses similar to physiological signals; the problem that complex biological signals cannot be stably and efficiently converted into electrical signals in the prior art is solved.

[0006] In order to achieve the above object, the present invention provides the following technical solutions:

[0007] In a first aspect, the present invention provides a circuit for generating a peak voltage pulse, the circuit at least comprising:

[0008] A capacitor unit, a transistor unit and an inverter unit;

[0009] The capacitor unit is connected to the transistor unit, and the transistor unit is connected to the inverter unit;

[0010] The transistor unit includes a first transistor, which is an N-type semiconductor IGZO transistor prepared based on low-temperature metal oxide;

[0011] The inverter unit includes the first transistor and the second transistor, wherein the second transistor is a P-type semiconductor LTPS transistor prepared based on low temperature polycrystalline oxide;

[0012] The circuit generates a peak voltage pulse signal based on an input current driving signal by using the capacitor unit, the transistor unit and the inverter unit; the peak voltage pulse signal is used to represent the biological information collected by the sensor.

[0013] Preferably, the first transistor in the transistor unit may be a first NMOS transistor;

[0014] The drain of the first NMOS tube is connected to the input end of the circuit, the gate of the first NMOS tube is connected to the output end of the circuit, and the source of the first NMOS tube is grounded.

[0015] Preferably, the first transistor in the inverter unit may be a second NMOS transistor and a third NMOS transistor, and the second transistor may be a first PMOS transistor and a second PMOS transistor;

[0016] The source of the first PMOS tube is connected to the power supply terminal, the gate of the first PMOS tube is connected to the input terminal of the circuit, the drain of the first PMOS tube is connected to the drain of the second NMOS tube, the drain of the first PMOS tube is connected to the gate of the second PMOS tube; the gate of the second NMOS tube is connected to the gate of the first PMOS tube, and the source of the second NMOS tube is grounded;

[0017] The source of the second PMOS tube is connected to the power supply end, the gate of the second PMOS tube is connected to the gate of the third NMOS tube, and the drain of the second PMOS tube is connected to the output end of the circuit; the drain of the third NMOS tube is connected to the drain of the second PMOS tube, and the source of the third NMOS tube is grounded.

[0018] Preferably, the capacitor unit may include a first capacitor and a second capacitor;

[0019] The first end of the first capacitor is connected to the input end of the circuit, and the second end of the first capacitor is connected to the output end of the circuit; the first end of the second capacitor is connected to the input end of the circuit, and the second end of the second capacitor is grounded.

[0020] In a second aspect, the present invention provides a method for preparing a transistor, wherein the transistor is a transistor in a circuit transistor unit and an inverter unit that generates a spike voltage pulse; the method for preparing the transistor may include: a method for preparing a P-type semiconductor LTPS transistor and a method for preparing an N-type semiconductor IGZO transistor.

[0021] Preferably, the method for preparing the P-type semiconductor LTPS transistor may include:

[0022] providing a first substrate;

[0023] forming an LTPS gate electrode layer on the first substrate;

[0024] forming an LTPS gate dielectric layer on a side of the LTPS gate electrode layer away from the substrate;

[0025] forming an LTPS active layer on a side of the LTPS gate dielectric layer away from the LTPS gate electrode layer;

[0026] Performing patterning on the LTPS active layer to obtain a target LTPS active layer;

[0027] An LTPS drain-source electrode is formed on a side of the target LTPS active layer away from the LTPS gate dielectric layer to obtain the P-type semiconductor LTPS transistor.

[0028] Preferably, the LTPS gate dielectric layer may be made of materials including High-κ, HfO2 and AlO x At least one of the following: the channel material thickness of the LTPS active layer is 30nm-50nm; the material of the first substrate is a mixed material of polyimide and SiN / SiO, with a thickness of 50nm or 100nm.

[0029] Preferably, the method for preparing the N-type semiconductor IGZO transistor may include:

[0030] providing a second substrate;

[0031] forming a first IGZO gate electrode layer on the second substrate;

[0032] forming a first IGZO gate dielectric layer on a side of the first IGZO gate electrode layer away from the second substrate;

[0033] Etching the first IGZO gate dielectric layer to form a through hole penetrating the first IGZO gate dielectric layer to obtain a second IGZO gate dielectric layer;

[0034] Using a plasma enhanced atomic layer deposition process, forming an IGZO active layer on a side of the second IGZO gate dielectric layer away from the IGZO gate electrode layer;

[0035] Performing patterning on the IGZO active layer to obtain a target IGZO active layer;

[0036] forming an IGZO drain-source electrode on a side of the target IGZO active layer away from the second IGZO gate dielectric layer;

[0037] forming a third IGZO gate dielectric layer on a side of the IGZO drain-source electrode away from the target IGZO active layer;

[0038] forming a second IGZO gate electrode on a side of the third IGZO gate dielectric layer away from the IGZO drain-source electrode;

[0039] An IGZO packaging layer is formed on a side of the second IGZO gate electrode away from the third IGZO gate dielectric layer to obtain the NMOS transistor.

[0040] Preferably, the material of the IGZO encapsulation layer is resin with a thickness of 200 nm; the channel material of the IGZO active layer has a thickness of 7 nm-15 nm; and the material of the second substrate is a mixed material of polyimide and SiN / SiO with a thickness of 50 nm or 100 nm.

[0041] Preferably, the thickness of the first IGZO gate dielectric layer is 10nm-30nm; the thickness of the third IGZO gate dielectric layer is less than 50nm; the manufacturing materials of the first IGZO gate dielectric layer and the third IGZO gate dielectric layer include High-κ, HfO2 and AlO x At least one of them.

[0042] Compared with the prior art, the present invention provides a circuit for generating a spike voltage pulse, which connects the capacitor unit with the transistor unit, and the transistor unit with the inverter unit by setting flexible devices such as a capacitor unit, a transistor unit and an inverter unit; wherein the transistor unit includes a first transistor, and the inverter unit includes the first transistor and the second transistor, the first transistor is an N-type semiconductor IGZO transistor prepared based on a low-temperature metal oxide, and the second transistor is a P-type semiconductor LTPS transistor prepared based on a low-temperature polycrystalline oxide; the circuit generates a spike voltage pulse signal based on an input current drive signal by using the capacitor unit, the transistor unit and the inverter unit; the spike voltage pulse signal is used to represent the biological information; based on this, a flexible spike pulse circuit based on LTPO (low-temperature polycrystalline oxide) material was obtained. Since the combination of N-type IGZO and P-type LTPS in the LTPO material can provide the circuit with excellent electron mobility and current regulation ability, it can achieve stable and efficient signal transmission and processing; therefore, the circuit can not only process conventional optical signals, but also can be extended to a variety of different types of sensor signals, such as pressure, temperature, changes in chemical concentration, humidity and mechanical strain, etc., can adapt to complex mechanical deformation and irregular structures in the biological environment, can fit biological tissues, and simulate the transmission process of electrical signals in biological systems; it solves the problem that the existing technology cannot stably and efficiently convert complex biological information into electrical signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0044] Figure 1 A schematic diagram of the main structure of a circuit for generating a peak voltage pulse provided by the present invention;

[0045] Figure 2 A schematic diagram of simulation results of a circuit output for generating a peak voltage pulse provided by the present invention when driven by different current sources;

[0046] Figure 3 A schematic diagram of the main process of a method for preparing a P-type semiconductor LTPS transistor in a method for preparing a transistor provided by the present invention;

[0047] Figure 4 A schematic diagram of the main process of a method for preparing an N-type semiconductor IGZO transistor in a method for preparing a transistor provided by the present invention;

[0048] Figure 5 A schematic diagram of a device transfer curve simulation result of a P-type semiconductor LTPS TFT transistor prepared by a transistor preparation method provided by the present invention;

[0049] Figure 6 A schematic diagram of a device transfer curve simulation result of an N-type semiconductor IGZO TFT transistor prepared by a transistor preparation method provided by the present invention;

[0050] Figure 7 The present invention provides a circuit for generating a spike voltage pulse, and the simulation results of an inverter circuit composed of LTPS TFT and IGZO TFT devices.

[0051] Reference numerals: 100 - circuit, 110 - capacitor unit, 120 - transistor unit, 130 - inverter unit, C1 - first capacitor, C2 - second capacitor. DETAILED DESCRIPTION

[0052] In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same items or similar items with basically the same functions and effects. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and their order is not limited. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit them to be different.

[0053] It should be noted that, in the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0054] In the present invention, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects in the previous time are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b, c can be single or multiple.

[0055] Currently, in the field of neuromorphic computing, converting complex biological signals into processable electrical signals is the core challenge for achieving efficient bionic computing. There is no better way in the prior art to solve the problem of bionic signal processing. Although the rigid circuits in the prior art can achieve frequency adjustment accuracy and the semiconductor devices in the rigid circuits have good mobility, the rigid circuits are difficult to adapt to the complex mechanical deformations and irregular structures in the biological environment, and cannot effectively fit biological tissues, especially flexible bionic devices, such as bionic flexible robotic arms, bionic manta ray flexible submersibles or bionic flexible end clamps.

[0056] It should be noted that flexible bionic devices include the following:

[0057] Bionic flexible robotic arm: This robotic arm is inspired by the octopus and uses liquid metal sensing technology, allowing it to grasp objects as flexibly as an octopus.

[0058] Bionic Manta Ray Flexible Submersible: This submersible is inspired by the marine creature manta ray and is equipped with high-definition cameras, sonar systems and Beidou navigation systems, and can perform a variety of tasks underwater.

[0059] Bionic flexible end fixture: This type of fixture is installed at the end of the industrial robot arm and is made of polymer elastic material. It has extremely high adaptability and safety and is suitable for the handling of special-shaped and fragile workpieces and changing production environments.

[0060] In view of this, in order to solve the problem that the existing technology cannot stably and efficiently convert complex biological information into electrical signals, the present invention designs a flexible spike pulse circuit based on LTPO (low temperature polycrystalline oxide) material, which can efficiently encode a variety of bionic signals into electrical pulse signals. This material system combines N-type semiconductor IGZO (indium gallium zinc oxide) and P-type semiconductor LTPS (low temperature polycrystalline silicon), and has excellent electrical properties, low power consumption characteristics and flexible adaptability; the LTPO-based flexible circuit can adapt to complex mechanical deformations and irregular structures in the biological environment, so that it can fit biological tissues, and is particularly suitable for application in flexible bionic devices.

[0061] Next, the technical solution of the present invention is described in detail with reference to the accompanying drawings:

[0062] See also Figure 1 , Figure 1 A schematic diagram of the main structure of a circuit for generating a peak voltage pulse provided by the present invention.

[0063] exist Figure 1 In the embodiment, the circuit 100 comprises at least:

[0064] The capacitor unit 110 , the transistor unit 120 and the inverter unit 130 ; the capacitor unit 110 is connected to the transistor unit 120 , and the transistor unit 120 is connected to the inverter unit 130 .

[0065] The capacitor unit 110 includes a first capacitor and a second capacitor; the transistor unit 120 includes a first transistor, which is an N-type semiconductor IGZO transistor prepared based on low-temperature metal oxide; the inverter unit 130 includes the first transistor and the second transistor, which is a P-type semiconductor LTPS transistor prepared based on low-temperature polycrystalline oxide.

[0066] The circuit 100 generates a spike voltage pulse signal based on an input current driving signal by using a capacitor unit 110 , a transistor unit 120 and an inverter unit 130 ; the spike voltage pulse signal is used to represent biological information collected by the sensor.

[0067] Based on this, the circuit for generating spike voltage pulses provided by the present invention can provide excellent electron mobility and current regulation capabilities based on the combined circuit structure of N-type IGZO and P-type LTPS in LTPO materials, so that it can achieve stable and efficient signal transmission and processing. For example, when the external pressure or temperature changes, the sensor in the circuit can capture the tiny current fluctuations caused by these changes, and then encode them through the spike pulse mechanism. This design ensures that when the system faces different types of signals, it can be efficiently converted into pulse signals that can be used for neuromorphic computing through a consistent encoding method, thereby improving the overall response speed and adaptability of the system. Therefore, a circuit for generating spike voltage pulses provided by the present invention can not only process a variety of bionic sensor signals, but also build a more complex signal processing network through multi-node neuron connections. This platform is highly scalable and can be expanded to large-scale neural network simulations according to specific needs. This technology plays an important role in promoting the development of bionic computing, intelligent sensors and neuromorphic hardware, and provides a low-power, flexible and efficient solution for biological interfaces and brain-like computing systems.

[0068] Preferably, the capacitor unit 110 includes a first capacitor C1 and a second capacitor C2.

[0069] Specifically, the first end of the first capacitor C1 is connected to the input end of the circuit 100, and the second end of the first capacitor C1 is connected to the output end of the circuit 100; the first end of the second capacitor C2 is connected to the input end of the circuit 100, and the second end of the second capacitor C2 is grounded.

[0070] Preferably, the first transistor in the transistor unit 120 is a first NMOS transistor.

[0071] Specifically, the drain of the first NMOS tube is connected to the input end of the circuit, the gate of the first NMOS tube is connected to the output end of the circuit, and the source of the first NMOS tube is grounded; thereby, a transistor unit 120 with driving capability can be obtained.

[0072] Preferably, the first transistor in the inverter unit is a second NMOS transistor and a third NMOS transistor, and the second transistor is a first PMOS transistor and a second PMOS transistor.

[0073] Specifically, the source of the first PMOS tube is connected to the power supply terminal, the gate of the first PMOS tube is connected to the input terminal of the circuit 100, the drain of the first PMOS tube is connected to the drain of the second NMOS tube, the drain of the first PMOS tube is connected to the gate of the second PMOS tube; the gate of the second NMOS tube is connected to the gate of the first PMOS tube, and the source of the second NMOS tube is grounded; further, the source of the second PMOS tube is connected to the power supply terminal, the gate of the second PMOS tube is connected to the gate of the third NMOS tube, and the drain of the second PMOS tube is connected to the output terminal of the circuit; the drain of the third NMOS tube is connected to the drain of the second PMOS tube, and the source of the third NMOS tube is grounded; thereby, a first inverter composed of the first PMOS tube and the second NMOS tube, and a second inverter composed of the second PMOS tube and the third NMOS tube are obtained.

[0074] It should be noted that the first NMOS tube needs to match the C1 and C2 capacitors to generate a spike pulse, the first inverter composed of the first PMOS tube and the second NMOS tube, and the second inverter composed of the second PMOS tube and the third NMOS tube, the IGZO TFT and the LTPS TFT performance must match to achieve the reverse and delay functions.

[0075] Preferably, the W / L (width-to-length ratio) of the LTPS TFT is equal to the L / W of the IGZO TFT.

[0076] Specifically, the electrical components in the circuit for generating a peak voltage pulse provided by the present invention can be arranged according to the following requirements:

[0077] 1. Input current I at the circuit input in 500nA to 2.6uA.

[0078] 2. The first capacitor C1 is 1nF to 8nF, preferably 5nF; the second capacitor C2 is 1nF to 8nF.

[0079] 3. The W / L ratio of the first NMOS tube is 2:1 to 6:1; the width of the first NMOS tube is preferably 16 μm, and the length is preferably 4 μm.

[0080] 4. The width-to-length ratio of the PMOS tube is greater than that of the NMOS tube, and the width-to-length ratio of the PMOS tube is inversely proportional to that of the NMOS tube; that is, the width-to-length ratio of the second transistor is greater than that of the first transistor, and the width-to-length ratio of the second transistor is inversely proportional to that of the first transistor.

[0081] Based on this, the present invention provides a circuit for generating a spike voltage pulse, which can achieve inversion at 2.5V voltage under Vdd=5V, and use NMOS tube for driving, combined with the delay caused by the first capacitor and the two inverters cascaded, to generate a spike voltage pulse signal from V out Output.

[0082] In order to more clearly demonstrate the technical effect of a circuit for generating a peak voltage pulse provided by the present invention, please refer to 2, Figure 2 A schematic diagram of simulation results of a circuit output for generating a peak voltage pulse provided by the present invention when driven by different current sources.

[0083] exist Figure 2 In the figure, the horizontal axis represents time in seconds; the vertical axis represents the output peak voltage pulse signal in V; the purple curve is the input current I of the circuit in When the current is 600nA, the output voltage V out The peak voltage pulse curve generated over time; the red curve is the input current I of the circuit in When the current is 800nA, the output voltage V out The peak voltage pulse curve generated over time; the green curve is the input current I of the circuit in When the current is 1500nA, the output voltage V out The peak voltage pulse curve generated over time.

[0084] Depend on Figure 2 It can be undoubtedly obtained that the circuit for generating a peak voltage pulse provided by the present invention can generate a peak voltage pulse at different input currents I in (different input currents are generated by other sensors), the output of voltage spike pulses of different frequencies can be achieved; it can provide excellent electron mobility and current regulation capabilities, enabling stable and efficient signal transmission and processing.

[0085] Through this modular design, the circuit for generating spike voltage pulses provided by the present invention can also be called a flexible spike pulse circuit, which can not only process a variety of bionic sensor signals, but also build a more complex signal processing network through multi-node neuron connections. This platform is highly scalable and can be expanded to large-scale neural network simulations according to specific needs. This technology plays an important role in promoting the development of bionic computing, smart sensors and neuromorphic hardware, and provides a low-power, flexible and efficient solution for biological interfaces and brain-like computing systems.

[0086] It should be noted that the input current is the current data generated after the sensor collects the biological information. Generally, common sensors can sense the biological information and convert it into current, and the present invention does not make any specific limitation.

[0087] In a second aspect, the present invention provides a method for preparing a transistor, which is a transistor in a circuit transistor unit and an inverter unit that generates a spike voltage pulse as described in the first aspect; the method for preparing the transistor may include: a method for preparing a P-type semiconductor LTPS transistor and a method for preparing an N-type semiconductor IGZO transistor.

[0088] Preferably, see Figure 3 to Figure 4 , Figure 3 A schematic diagram of the main process of a method for preparing a P-type semiconductor LTPS transistor in a method for preparing a transistor provided by the present invention; Figure 4 A schematic diagram of the main process of a method for preparing an N-type semiconductor IGZO transistor in a method for preparing a transistor provided by the present invention.

[0089] The method for preparing the P-type semiconductor LTPS transistor comprises:

[0090] Step 310: Provide a first substrate; the material of the first substrate is preferably a mixed material of polyimide and SiN / SiO, and the thickness is preferably 50 nm or 100 nm.

[0091] Step 320: forming an LTPS gate electrode layer on the first substrate; wherein the gate electrode material is preferably one or a combination of TiN, Au, Ti, Mo, and Ag, and the thickness of the gate electrode is preferably 30nm-50nm.

[0092] Step 330: forming an LTPS gate dielectric layer on a side of the LTPS gate electrode layer away from the substrate; wherein the LTPS gate dielectric layer is made of materials including High-κ, HfO2 and AlO x At least one of the following; the thickness of the gate dielectric layer is preferably 10-50nm.

[0093] Step 340: forming an LTPS active layer on a side of the LTPS gate dielectric layer away from the LTPS gate electrode layer; wherein the channel material thickness of the LTPS active layer is preferably 30 nm-50 nm.

[0094] Step 350: performing patterning on the LTPS active layer to obtain a target LTPS active layer.

[0095] Step 360: forming LTPS drain-source electrodes on a side of the target LTPS active layer away from the LTPS gate dielectric layer to obtain the P-type semiconductor LTPS transistor; wherein the source-drain electrodes are preferably made of one or more of Au, Ti, and Ni, and the thickness of the source-drain electrodes is preferably 30nm-100nm.

[0096] Based on steps 310 to 360, a P-type semiconductor LTPS (low temperature polycrystalline silicon) in a flexible spike pulse circuit of the LTPO (low temperature polycrystalline oxide) material of the present invention is prepared.

[0097] exist Figure 4 In the present invention, the method for preparing an N-type semiconductor IGZO transistor may include:

[0098] Step 410: Provide a second substrate.

[0099] Step 420: Form a first IGZO gate electrode layer on the second substrate.

[0100] Step 430: forming a first IGZO gate dielectric layer on a side of the first IGZO gate electrode layer away from the second substrate.

[0101] Step 440: etching the first IGZO gate dielectric layer to form a through hole penetrating the first IGZO gate dielectric layer to obtain a second IGZO gate dielectric layer.

[0102] Step 450: using a plasma enhanced atomic layer deposition process to form an IGZO active layer on a side of the second IGZO gate dielectric layer away from the IGZO gate electrode layer.

[0103] Step 460: patterning the IGZO active layer to obtain a target IGZO active layer.

[0104] Step 470: forming an IGZO drain-source electrode on a side of the target IGZO active layer away from the second IGZO gate dielectric layer.

[0105] Step 480: forming a third IGZO gate dielectric layer on a side of the IGZO drain-source electrode away from the target IGZO active layer.

[0106] Step 490: forming a second IGZO gate electrode on a side of the third IGZO gate dielectric layer away from the IGZO drain-source electrode.

[0107] Step 491: forming an IGZO packaging layer on a side of the second IGZO gate electrode away from the third IGZO gate dielectric layer to obtain the NMOS transistor.

[0108] In steps 410 to 419:

[0109] Preferably, the material of the IGZO encapsulation layer can be resin with a thickness of 200 nm. Using resin as the encapsulation layer can isolate external factors, such as water, oxygen, etc., from affecting the active layer, thereby increasing the working life of the thin film transistor.

[0110] Preferably, the channel material thickness of the IGZO active layer may be 7 nm-15 nm; the material of the second substrate may be a mixed material of polyimide and SiN / SiO, and the thickness may be 50 nm or 100 nm.

[0111] Preferably, the thickness of the first IGZO gate dielectric layer may be 10nm-30nm; the thickness of the third IGZO gate dielectric layer is less than 50nm; the manufacturing materials of the first IGZO gate dielectric layer and the third IGZO gate dielectric layer may include High-κ, HfO2 and AlO x At least one of the following: because when forming the first and third IGZO gate dielectric layers, the IGZO channel and HfO2 material are in the same cavity and in one pot method is adopted, so that the interface defects of the grown IGZO and the dielectric layer are reduced, the threshold voltage drift phenomenon between different devices is effectively controlled, and the device uniformity is enhanced.

[0112] Preferably, the gate electrode material may be one or a combination of TiN, Au, Ti, Mo, and Ag, and the thickness of the gate electrode may be 30nm-50nm; the source and drain electrodes may be made of one or a combination of Au, Ti, and Ni, and the thickness of the source and drain electrodes may be 30nm-100nm; the isolation layer may be made of SiOx / SiNx, and the thickness of the isolation layer may be 30nm-100nm.

[0113] According to step 410 to step 419, an N-type semiconductor IGZO (indium gallium zinc oxide) for generating a flexible spike pulse circuit provided by the present invention is prepared based on low-temperature metal oxide.

[0114] More specifically, in steps 310 to 360, and steps 410 to 419, the following technical means are preferably used to prepare the transistor:

[0115] 1. The bottom gate electrode can be grown on the insulating layer substrate (the first substrate or the second substrate) by electron beam evaporation process, and the bottom gate electrode is patterned by photolithography and stripping process. Preferably, the photoresist used in the photolithography is negative photoresist 1500 and positive photoresist 5141; the photolithography exposure method is contact / proximity photolithography.

[0116] 2. A plasma enhanced atomic layer deposition process is used to grow a bottom gate dielectric layer and an IGZO active layer in the same cavity and in one pot on the gate electrode and the insulating layer substrate; and a photolithography and dry and wet etching process is used to pattern the IGZO active layer to obtain the desired IGZO active layer pattern.

[0117] 3. The source and drain electrodes are grown on the active layer by electron beam evaporation process, and the source and drain electrodes are patterned by photolithography and stripping process, so that the channel length between the source and drain electrodes is 2 μm-200 μm.

[0118] 4. A top gate dielectric layer is grown on the source and drain electrodes using a plasma enhanced atomic layer deposition process.

[0119] 5. Growing a top gate electrode on the top gate dielectric layer by electron beam evaporation, and patterning the top gate electrode by photolithography and lift-off processes.

[0120] Further, in order to reflect the electrical performance of a transistor prepared by a method for preparing a transistor provided by the second aspect of the present invention, please refer to Figures 5 and 6 , Figure 5 A schematic diagram of a device transfer curve simulation result of a P-type semiconductor LTPS TFT transistor prepared by a transistor preparation method provided by the present invention; Figure 6 A schematic diagram of the simulation results of the device transfer curve of an N-type semiconductor IGZO TFT transistor prepared by a transistor preparation method provided by the present invention.

[0121] exist Figure 5 In the graph, the horizontal axis represents the gate-source voltage in V (volts); the vertical axis represents the drain current in A (amperes); Figure 6 In the figure, the horizontal axis represents the gate-source voltage in V, and the vertical axis represents the drain current in A. By adjusting the W / L of the two devices, the performance of the N-type semiconductor device and the P-type semiconductor device are matched to facilitate the formation of an inverter.

[0122] pass Figure 5 and Figure 6 The curve shown shows without a doubt that when the width-to-length ratio of the P-type semiconductor LTPS TFT transistor is greater than that of the N-type semiconductor IGZO TFT transistor and they conform to the inverse proportional law, the performance of the N-type semiconductor device and the P-type semiconductor device is best matched, and they have excellent electrical performance, low power consumption characteristics, and flexible adaptability.

[0123] For further information, see Figure 7 , Figure 7 The simulation results of the inverter circuit composed of LTPS TFT and IGZO TFT devices prepared by the transistor preparation method provided by the present invention.

[0124] exist Figure 7 The horizontal axis represents the input voltage V of the inverter. in , in V; the vertical axis represents the input voltage V out , the unit is V; Figure 7The corresponding curve in shows the voltage variation curve at the input and output ends of the inverter after the inverter is obtained by matching the P-type semiconductor LTPS TFT transistor and the N-type semiconductor IGZO TFT transistor.

[0125] pass Figure 7 The curves shown in the figure clearly show that the inverter composed of N-type devices and P-type devices with matching performance can better realize the midpoint voltage reversal and delay functions, and can achieve V out voltage pulse signal.

[0126] Based on this, the transistor manufacturing method provided by the present invention can be used to manufacture P-type LTPS TFT transistors (PMOS tubes) and N-type IGZO TFT transistors (NMOS tubes); and the manufactured transistors are applied to a circuit for generating a spike voltage pulse as described in the first aspect. According to the circuit structure described in the first aspect, five transistors (an N-type IGZO TFT driving tube, an inverter composed of two groups of IGZO TFTs and LTPS TFTs) and two capacitors are connected respectively, and can be driven by a simple constant current source to generate spike voltage pulses similar to physiological signals. Because the circuit uses flexible devices such as P-type LTPS TFT transistors and N-type IGZO TFT transistors, capacitors, etc., the circuit can fit the biological surface and is particularly suitable for application in flexible bionic devices.

[0127] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0128] Although the present invention has been described in conjunction with specific features and embodiments thereof, it is apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present invention. Accordingly, this specification and the accompanying drawings are merely exemplary illustrations of the present invention as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present invention. Obviously, those skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, the present invention is intended to include such modifications and variations if they fall within the scope of the claims of the present invention and their equivalents.

Claims

1. A circuit for generating a peak voltage pulse, characterized in that: The circuit includes at least: A capacitor unit, a transistor unit and an inverter unit; The capacitor unit is connected to the transistor unit, and the transistor unit is connected to the inverter unit; The transistor unit includes a first transistor, which is an N-type semiconductor IGZO transistor prepared based on low-temperature metal oxide; The inverter unit includes the first transistor and the second transistor, wherein the second transistor is a P-type semiconductor LTPS transistor prepared based on low temperature polycrystalline oxide; The circuit generates a peak voltage pulse signal based on an input current driving signal by using the capacitor unit, the transistor unit and the inverter unit; the peak voltage pulse signal is used to represent the biological information collected by the sensor.

2. The circuit according to claim 1, characterized in that The first transistor in the transistor unit is a first NMOS transistor; The drain of the first NMOS tube is connected to the input end of the circuit, the gate of the first NMOS tube is connected to the output end of the circuit, and the source of the first NMOS tube is grounded.

3. The circuit according to claim 1, characterized in that The first transistor in the inverter unit is a second NMOS tube and a third NMOS tube, and the second transistor is a first PMOS tube and a second PMOS tube; The source of the first PMOS tube is connected to the power supply terminal, the gate of the first PMOS tube is connected to the input terminal of the circuit, the drain of the first PMOS tube is connected to the drain of the second NMOS tube, the drain of the first PMOS tube is connected to the gate of the second PMOS tube; the gate of the second NMOS tube is connected to the gate of the first PMOS tube, and the source of the second NMOS tube is grounded; The source of the second PMOS tube is connected to the power supply end, the gate of the second PMOS tube is connected to the gate of the third NMOS tube, and the drain of the second PMOS tube is connected to the output end of the circuit; the drain of the third NMOS tube is connected to the drain of the second PMOS tube, and the source of the third NMOS tube is grounded.

4. The circuit according to claim 1, characterized in that The capacitor unit includes a first capacitor and a second capacitor; The first end of the first capacitor is connected to the input end of the circuit, and the second end of the first capacitor is connected to the output end of the circuit; the first end of the second capacitor is connected to the input end of the circuit, and the second end of the second capacitor is grounded.

5. A method for preparing a transistor, characterized in that: The transistor is a circuit transistor unit that generates a peak voltage pulse and a transistor in an inverter unit; The method for preparing the transistor comprises: A method for preparing a P-type semiconductor LTPS transistor and a method for preparing an N-type semiconductor IGZO transistor.

6. The method according to claim 5, characterized in that The method for preparing the P-type semiconductor LTPS transistor comprises: providing a first substrate; forming an LTPS gate electrode layer on the first substrate; forming an LTPS gate dielectric layer on a side of the LTPS gate electrode layer away from the substrate; forming an LTPS active layer on a side of the LTPS gate dielectric layer away from the LTPS gate electrode layer; Performing patterning on the LTPS active layer to obtain a target LTPS active layer; An LTPS drain-source electrode is formed on a side of the target LTPS active layer away from the LTPS gate dielectric layer to obtain the P-type semiconductor LTPS transistor.

7. The method according to claim 6, characterized in that The LTPS gate dielectric layer is made of materials including High-κ, HfO2 and AlO x At least one of the following; The channel material thickness of the LTPS active layer is 30nm-50nm; The first substrate is made of a mixed material of polyimide and SiN / SiO, and has a thickness of 50 nm or 100 nm.

8. The method according to claim 5, characterized in that The method for preparing the N-type semiconductor IGZO transistor comprises: providing a second substrate; forming a first IGZO gate electrode layer on the second substrate; forming a first IGZO gate dielectric layer on a side of the first IGZO gate electrode layer away from the second substrate; Etching the first IGZO gate dielectric layer to form a through hole penetrating the first IGZO gate dielectric layer to obtain a second IGZO gate dielectric layer; Using a plasma enhanced atomic layer deposition process, forming an IGZO active layer on a side of the second IGZO gate dielectric layer away from the IGZO gate electrode layer; Performing patterning on the IGZO active layer to obtain a target IGZO active layer; forming an IGZO drain-source electrode on a side of the target IGZO active layer away from the second IGZO gate dielectric layer; forming a third IGZO gate dielectric layer on a side of the IGZO drain-source electrode away from the target IGZO active layer; forming a second IGZO gate electrode on a side of the third IGZO gate dielectric layer away from the IGZO drain-source electrode; An IGZO packaging layer is formed on a side of the second IGZO gate electrode away from the third IGZO gate dielectric layer to obtain the NMOS transistor.

9. The method according to claim 8, characterized in that The material of the IGZO encapsulation layer is resin, and the thickness is 200nm; The channel material thickness of the IGZO active layer is 7nm-15nm; The second substrate is made of a mixed material of polyimide and SiN / SiO, and has a thickness of 50 nm or 100 nm.

10. The method according to claim 8, characterized in that The thickness of the first IGZO gate dielectric layer is 10nm-30nm; the thickness of the third IGZO gate dielectric layer is less than 50nm; The first IGZO gate dielectric layer and the third IGZO gate dielectric layer are made of materials including High-κ, HfO2 and AlO x At least one of them.

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