Display module, display panel, source driving circuit and power manager

Abstract

The invention relates to the technical field of display, in particular to a display module, a display panel, a source driving circuit and a power manager. The power manager is used for driving the display module; the display module further comprises a display panel, and the display panel is provided with a source electrode driving circuit. Wherein the power supply manager is configured to be capable of outputting a constant-voltage gate driving low voltage and a constant-voltage gate driving high voltage, and is capable of outputting an analog driving voltage according to an analog driving voltage value sent by the source driving circuit; the analog driving voltages corresponding to the at least two analog driving voltage values are different; the grid driving low voltage and the grid driving high voltage are directly used for driving a grid driving circuit on the display panel, or are used for driving the grid driving circuit after being processed by a source driving circuit on the display panel; an analog driving voltage can be converted into a black state voltage by a source driving circuit to drive a display panel, and the power manager can reduce power consumption of a driving IC.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display module, a display panel, a source driving circuit, and a power manager. Background Art

[0002] The power consumption of the driver IC of the display module has become more and more obvious. Different display brightnesses require different driving voltages. However, in the related art, no matter how the brightness of the display module changes, the same set of voltage settings is used to drive the display module, resulting in a waste of driver IC power consumption.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] The purpose of the present disclosure is to overcome the deficiencies of the above-mentioned prior art and provide a display module, a display panel, a source driving circuit, and a power manager, which can reduce the power consumption of a driving IC.

[0005] According to one aspect of the present disclosure, there is provided a power manager for driving a display module; the display module further comprises a display panel, the display panel having a source driving circuit; wherein the power manager is configured to output a constant voltage gate driving low voltage, a constant voltage gate driving high voltage, and output an analog driving voltage according to an analog driving voltage value sent by the source driving circuit; the analog driving voltages corresponding to at least two of the analog driving voltage values ​​are different;

[0006] The gate driving low voltage and the gate driving high voltage are directly used to drive the gate driving circuit on the display panel, or are used to drive the gate driving circuit after being processed by the source driving circuit on the display panel;

[0007] The analog driving voltage can be converted into a black state voltage by the source driving circuit to drive the display panel.

[0008] In one embodiment of the present disclosure, the voltage difference between the analog driving voltage and the black state voltage is not less than 0.4V.

[0009] In one embodiment of the present disclosure, the voltage difference between the analog driving voltage and the black state voltage is no more than 0.6V.

[0010] According to another aspect of the present disclosure, there is provided a source driving circuit for driving a display module, wherein the display module has a timing controller;

[0011] The source driving circuit is configured to receive a reference brightness value sent by the timing controller, and generate an analog driving voltage value based on the reference brightness value and send it to the power manager; the reference brightness value is generated by the display brightness value in the display picture data received by the timing controller;

[0012] The analog driving voltage values ​​corresponding to at least two of the display brightness values ​​are different.

[0013] In one embodiment of the present disclosure, the source driving circuit includes a voltage determination unit;

[0014] The voltage determination unit is configured to determine the analog driving voltage value according to the reference brightness value and send the value to the power manager.

[0015] In one embodiment of the present disclosure, the voltage determination unit includes a mapping module;

[0016] The mapping module has a plurality of brightness range values ​​of the display module, and each brightness range value corresponds to an analog driving voltage value;

[0017] When the analog driving voltage value is confirmed according to the brightness range value, the analog driving voltage value corresponding to the reference brightness value is determined according to which brightness range value the reference brightness value falls into.

[0018] In one embodiment of the present disclosure, the voltage determination unit includes a mapping module;

[0019] The mapping module has a plurality of binding parameters, each binding parameter including a binding brightness value and a binding analog driving voltage value;

[0020] When determining the analog driving voltage value according to the bound brightness value, the analog driving voltage value corresponding to the reference brightness value is determined by using a linear interpolation method according to at least two binding parameters and the reference brightness value.

[0021] In one embodiment of the present disclosure, the source driving circuit is configured to generate a black state voltage according to an analog driving voltage from the power manager; wherein, when the display brightness value of the display module is different, the voltage difference between the analog driving voltage and the black state voltage is constant.

[0022] In one embodiment of the present disclosure, the source driving circuit is configured to determine the black state voltage according to the reference brightness value of the display module; and determine the analog driving voltage value according to the minimum voltage difference between the black state voltage and the low voltage difference regulator in the source driving circuit.

[0023] According to another aspect of the present disclosure, there is provided a display panel having the above-mentioned source driving circuit and a gate driving circuit;

[0024] The gate driving circuit is configured to receive a gate driving low voltage and a gate driving high voltage output by the power manager.

[0025] According to another aspect of the present disclosure, a display module is provided, comprising the display panel and the power manager.

[0026] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0028] Figure 1 FIG. 1 is a schematic diagram of the structure of a display panel in one embodiment of the present disclosure.

[0029] Figure 2 FIG. 1 is a schematic diagram of the structure of a display panel in one embodiment of the present disclosure.

[0030] Figure 3 FIG. 1 is a schematic diagram of the structure of a display panel in one embodiment of the present disclosure.

[0031] Figure 4 FIG. 1 is a schematic diagram of the structure of a display panel in one embodiment of the present disclosure.

[0032] Figure 5 It is a schematic diagram of circuit connection of a display module in one embodiment of the present disclosure.

[0033] Figure 6 This is a schematic diagram of the output voltage of the power manager in one embodiment of the present disclosure.

[0034] Figure 7 This is a schematic diagram of the output voltage of the power manager in one embodiment of the present disclosure.

[0035] Figure 8 FIG. 1 is a schematic diagram of setting a black state voltage in one embodiment of the present disclosure.

[0036] Fig. 9 The figure is a graph showing the variation of black state voltage with brightness in one embodiment of the present disclosure.

[0037] Fig.10 The figure is a graph showing the variation of black state voltage with brightness in one embodiment of the present disclosure.

[0038] Fig.11 The figure is a curve diagram of the change of the black state voltage and the analog driving voltage in one embodiment of the present disclosure.

[0039] Fig.12 This is a schematic diagram of power consumption benefit in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0041] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0042] The terms "a", "an", "the", and "said" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusion and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second", etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0043] In the present application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0044] In an embodiment of the present disclosure, a thin film transistor (TFT) includes an active layer, a gate organic layer and a gate that are stacked. The active layer is located in the semiconductor layer, and the active layer includes a channel region and a source and a drain located on both sides of the channel region, respectively. The channel region maintains semiconductor properties, and the source and the drain are both conductorized. In an embodiment of the present disclosure, in the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source" and the "drain" are sometimes interchanged, that is, the "drain" and the "source" can be interchanged. In an embodiment of the present disclosure, for any transistor, one of the "source" and the "drain" is referred to as the first pole of the transistor, and the other is referred to as the second pole of the transistor.

[0045] The embodiment of the present disclosure provides a display module, which can be a television, a computer screen, a smart phone, a smart watch screen, or other types of display modules.

[0046] In one example, the display module includes a display panel PNL. Figure 1 The display panel PNL includes a display area AA and a peripheral area BB located at least on one side of the display area AA. In the display area AA, the display panel PNL is provided with display units UU distributed in an array, and the display units UU include sub-pixels PIX and pixel driving circuits PDC driving the sub-pixels PIX. The display panel PNL does not provide display units UU in the peripheral area BB, or the provided display units UU are not used to display images.

[0047] See also Figure 1 The display panel PNL is provided with a plurality of scanning lines GL extending along the row direction DH in the display area AA, and each scanning line GL is provided in one-to-one correspondence with each display unit row. The pixel driving circuit PDC of each display unit UU of the display unit row is electrically connected to the corresponding scanning line GL, and the scanning line GL is used to load the scanning signal to the pixel driving circuit PDC. The display panel PNL is also provided with a plurality of data lines DL extending along the column direction DV in the display area AA, and each data line DL is provided in one-to-one correspondence with each display unit column. The pixel driving circuit PDC of each display unit UU of the display unit column is electrically connected to the corresponding data line DL, and the data line DL is used to load the data voltage to the pixel driving circuit PDC. In this way, the pixel driving circuit PDC of each display unit UU is connected to a scanning line GL and a data line DL. When the scanning signal is loaded on the scanning line GL, the data voltage loaded on the data line DL can be written into the pixel driving circuit PDC, so that the pixel driving circuit PDC can control the brightness of the sub-pixel PIX according to the written data voltage.

[0048] Optionally, the pixel driving circuit PDC includes at least a data write transistor, a driving transistor and a storage capacitor, and the gate of the driving transistor can be electrically connected to an electrode plate of the storage capacitor. The first pole of the data write transistor can be electrically connected to the data line DL, and the gate of the data write transistor can be electrically connected to the scan line GL. The pixel driving circuit PDC is configured so that when a scan signal is loaded on the scan line GL, the data write transistor is turned on, so that the data voltage on the data line DL is written into the gate of the driving transistor and the storage capacitor. When the data write transistor is turned off, the data voltage can be maintained by the storage capacitor. The driving transistor can output a driving current to drive the sub-pixel PIX to emit light under the control of the voltage on its gate.

[0049] It is understandable that the pixel driving circuit PDC of the embodiment of the present disclosure may also include other transistors or capacitors to enable the pixel driving circuit PDC to have better driving performance. For example, the pixel driving circuit PDC may be a 3T1C (3 thin film transistors and a storage capacitor), 7T1C (7 thin film transistors and a storage capacitor), 8T1C (8 thin film transistors and a storage capacitor) or a pixel driving circuit of other architectures.

[0050] See also Figure 2 and Figure 3 The display panel PNL includes a driving backplane and a pixel layer PIXL. The driving backplane includes a stacked substrate SBT and a driving layer DRL, and the pixel layer PIXL is arranged on a side of the driving layer DRL away from the substrate SBT.

[0051] Optionally, the substrate substrate SBT may be a substrate substrate SBT of an inorganic material, a substrate substrate SBT of an organic material, or a substrate substrate SBT in which organic and inorganic materials are alternately stacked. For example, in one embodiment of the present disclosure, the material of the substrate substrate SBT may be glass materials such as soda-lime glass, quartz glass, and sapphire glass. In another embodiment of the present disclosure, the material of the substrate substrate SBT may be polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or a combination thereof. In another embodiment of the present disclosure, the substrate SBT may also be a flexible substrate SBT, for example, the material of the substrate SBT may be polyimide (PI). The substrate SBT may also be a composite of multiple layers of materials, for example, in one embodiment of the present disclosure, the substrate SBT may include a bottom film layer, a pressure-sensitive adhesive layer, a first polyimide layer, and a second polyimide layer stacked in sequence.

[0052] See also Figure 3 The pixel driving circuit PDC is arranged in the driving layer DRL, and the pixel layer PIXL can be provided with a light-emitting element LD electrically connected to the pixel driving circuit PDC. The light-emitting element LD can serve as a sub-pixel PIX of the display panel PNL. In this way, the driving layer DRL is provided with an array-distributed pixel driving circuit PDC, and the pixel layer PIXL is provided with an array-distributed light-emitting element LD, and each light-emitting element LD emits light under the control of the corresponding pixel driving circuit PDC. The pixel driving circuit PDC is used to drive the corresponding sub-pixel PIX (light-emitting element LD) so that the display panel PNL displays the picture.

[0053] In one embodiment of the present disclosure, see Figure 4, the driving layer DRL may include a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source-drain metal layer SD, and a planarization layer PLN, etc., stacked between the substrate SBT and the pixel layer PIXL. Each thin film transistor and storage capacitor may be formed by a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source-drain metal layer SD, and other film layers. Among them, the positional relationship of each film layer can be determined according to the film layer structure of the thin film transistor. Further, the semiconductor layer SCL can be used to form the channel region of the transistor, and the first and second electrodes located on both sides of the channel region, and when necessary, it can also be formed by conductorization to form part of the wiring or conductive structure. The gate layer GT can be used to form one or more of the gate layer wirings such as the scanning wiring, and can also be used to form the gate of the transistor, and can also be used to form part of or all of the electrode plates of the storage capacitor. The source-drain metal layer SD can be used to form the source-drain metal layer wirings such as the data wiring, and can also be used to form part of the electrode plates of the storage capacitor. Of course, in other embodiments of the present disclosure, the driving layer DRL may further include other film layers as needed, for example, it may further include a light shielding layer, an inorganic buffer layer BUF, etc. located between the semiconductor layer SCL and the substrate SBT. As needed, any of the above-mentioned film layers such as the semiconductor layer SCL, the gate layer GT, the source-drain metal layer SD, etc. may also be multilayered, for example, the driving layer DRL may include two different semiconductor layers SCL, or two or three source-drain metal layers SD, or two or three gate layers GT; accordingly, the insulating film layers in the driving layer DRL (such as the gate insulating layer GI, the interlayer dielectric layer ILD, the planarization layer PLN, etc.) may be adaptively increased or decreased, or new insulating film layers may be added as needed.

[0054] As an example, see Figure 4 , the driving layer DRL may include an inorganic buffer layer BUF, a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source-drain metal layer SD, and a planarization layer PLN stacked sequentially on the surface of the substrate SBT, and the thin film transistor formed in this way is a top-gate thin film transistor. In other examples, the driving layer may include an inorganic buffer layer, a gate layer, a gate insulating layer, a semiconductor layer, a source-drain metal layer, and a planarization layer stacked sequentially on the surface of the substrate, and the thin film transistor formed in this way is a bottom-gate thin film transistor. In other examples, the driving layer may also have a dual-gate thin film transistor, etc.

[0055] It is understandable that the above example of the driving backplane is only one possible manner of the driving backplane in the embodiment of the present disclosure. In other embodiments of the present disclosure, the driving backplane may also be of other structures.

[0056] See also Figure 4 , the light emitting element LD in the pixel layer PIXL may include two stacked electrodes and a light emitting functional unit sandwiched between the two electrodes. For example, the pixel layer PIXL may include a pixel electrode layer PEL, a light emitting functional layer EFL and a common electrode layer COML stacked in sequence. Among them, the pixel electrode layer PEL has a plurality of pixel electrodes in the display area AA of the display panel PNL; the portion of the light emitting functional layer EFL connected to the pixel electrode serves as the light emitting functional unit of the light emitting element LD, and the common electrode layer COML serves as a common electrode electrically connected to the light emitting functional units of each light emitting element LD.

[0057] Further, the pixel layer PIXL may also include a pixel definition layer PDL located between the pixel electrode layer PEL and the light-emitting function layer EFL. The pixel definition layer PDL has a plurality of through pixel openings arranged one by one corresponding to the plurality of pixel electrodes, and any pixel opening exposes at least a portion of the corresponding pixel electrode. For example, the pixel definition layer PDL covers the edge of the pixel electrode and exposes at least a portion of the internal area of ​​the pixel electrode, so that the pixel definition layer PDL can effectively define the actual effective area of ​​the pixel electrode (the area directly connected to the light-emitting function unit), and further define the light-emitting area and light-emitting area of ​​the light-emitting element LD. The light-emitting function layer EFL at least covers the pixel electrode exposed by the pixel definition layer PDL. The common electrode layer COML may cover the light-emitting function layer EFL in the display area AA. The pixel electrode and the common electrode layer COML provide carriers such as electrons and holes to the light-emitting function layer EFL, so that the light-emitting function layer EFL emits light. The portion of the light-emitting function layer EFL located between the pixel electrode and the common electrode layer COML may serve as a light-emitting function unit. The pixel electrode, the common electrode layer COML, and the light-emitting function unit form the light-emitting element LD. Among them, one of the pixel electrode and the common electrode layer COML serves as the anode AE ​​of the light emitting element LD, and the other serves as the cathode CE of the light emitting element LD.

[0058] In one example, the pixel electrode serves as the anode AE ​​of the light emitting element LD, and the common electrode layer COML serves as the cathode CE of the light emitting element LD.

[0059] In one embodiment of the present disclosure, the light emitting element LD may be an organic light emitting diode (OLED), a micro light emitting diode (Micro LED), a quantum dot-organic light emitting diode (QD-OLED), a quantum dot light emitting diode (QLED) or other types of light emitting elements. It is understood that the types of light emitting elements are different, and the materials and film layers of the light emitting functional units are different.

[0060] In one embodiment of the present disclosure, see Figure 2 , Figure 3 and Figure 4, the display panel PNL also includes a thin film encapsulation layer TFE, which can be arranged on the surface of the pixel layer PIXL away from the substrate SBT, and can include inorganic encapsulation layers and organic encapsulation layers alternately stacked. The inorganic encapsulation layer can effectively block external moisture and oxygen, and prevent water and oxygen from invading the pixel layer PIXL and causing aging of the materials in the pixel layer PIXL. Optionally, the edge of the inorganic encapsulation layer can be located in the peripheral area BB. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce the stress between the inorganic encapsulation layers. Among them, the edge of the organic encapsulation layer can be located between the edge of the display area AA and the edge of the inorganic encapsulation layer. For example, see Figure 4 The thin film encapsulation layer TFE includes a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2 which are sequentially stacked on the side of the pixel layer PIXL (common electrode layer COML) away from the substrate SBT. Of course, in other embodiments of the present disclosure, the display panel PNL may not be provided with a thin film encapsulation layer TFE, but may use other methods to encapsulate and protect the pixel layer PIXL.

[0061] In one embodiment of the present disclosure, see Figure 1 and Figure 2 The display panel PNL may further include a touch buffer layer TSL, which may be disposed on a surface of the thin film encapsulation layer TFE away from the substrate SBT, so that the display panel PNL has a touch function. Exemplarily, the touch buffer layer TSL includes a touch buffer layer TBUF, a first touch metal layer TMA, a touch dielectric layer TLD, and a second touch metal layer TMB, which are sequentially stacked on a side of the thin film encapsulation layer TFE away from the substrate SBT, and the first touch metal layer TMA and the second touch metal layer TMB overlap each other at least partially to form a touch capacitor.

[0062] In one embodiment of the present disclosure, see Figure 5 The peripheral area BB of the display panel PNL includes a first sub-peripheral area and a second sub-peripheral area. A gate driving circuit GIC is provided in the first sub-peripheral area. The gate driving circuit GIC is electrically connected to the scanning line GL. The gate driving circuit GIC loads a scanning signal to the pixel driving circuit PDC through the scanning line GL. A source driving circuit SIC is provided in the second sub-peripheral area. The source driving circuit SIC is electrically connected to the data line DL. The source driving circuit SIC loads a data voltage to the pixel driving circuit PDC through the data line DL. The source driving circuit SIC is electrically connected to the host computer through the timing controller TCON. The display picture data sent by the host computer is processed by the timing controller TCON and loaded into the source driving circuit SIC. The source driving circuit SIC can drive the sub-pixels PIX on the display panel PNL to display the picture based on the display signal.

[0063] In another embodiment of the present disclosure, the gate driving circuit GIC and the source driving circuit SIC may be integrated to form an integrated driving circuit DDIC.

[0064] In one embodiment of the present disclosure, see Figure 5 The display module also includes a power manager PMIC, which is used to provide a stable power supply for the display panel PNL.

[0065] The power consumption of the driver IC of the display module has become more and more obvious. Different display brightnesses require different driving voltages. However, in related technologies, no matter how the brightness of the display module changes, the same set of driving voltages is used to drive the display module, resulting in a waste of driver IC power consumption.

[0066] It can be known that the analog driving voltage AVDD can drive the gate driving circuit GIC of the display module, and the analog driving voltage AVDD is the highest. If the analog driving voltage AVDD can be reduced significantly, it will inevitably effectively reduce the power consumption of the driving circuit. The gate driving high voltage VGH and the gate driving low voltage VGL of the gate driving circuit GIC driving the display module are provided by the analog driving voltage AVDD, and the black state voltage VGMP is the black state voltage of the display module, which is also provided by the analog driving voltage AVDD.

[0067] Because at different display brightness values ​​DDBV (different brightness), the driving negative voltage ELVSS (ELVSS usually refers to the negative voltage provided to the electrode (especially the cathode electrode) of the OLED display panel) and the initialization voltage Vint of the OLED pixel circuit are different, so the black state voltage VGMP of the OLED display module at different display brightness values ​​DDBV (the picture that makes the OLED display module display grayscale (Gray) as 0, see Figure 8 , and then change the voltage from small to large, and synchronously collect the brightness of the display module after the voltage is changed. When the brightness of the display module is less than 0.0005nits for the first time, the voltage corresponding to the brightness value is the black state voltage VGMP of the OLED display module, which is also different. Fig. 9 and Fig.10 ( Fig. 9 and Fig.10In the figure (where the horizontal axis is brightness and the vertical axis is voltage), it is a voltage value curve diagram of the black state voltage VGMP corresponding to different display brightness values ​​DDBV. It can be seen that the voltage of the black state voltage VGMP under different display brightness values ​​DDBV is different, that is, the black state voltage VGMP under different display brightness values ​​DDBV can be set to be dynamic. However, because the black state voltage VGMP is generated by the analog drive voltage AVDD, if the analog drive voltage AVDD is not affected by other voltage signals, as the black state voltage VGMP changes, the voltage setting of the analog drive voltage AVDD can also be dynamically changed. In this way, power consumption can be reduced under different display brightness values ​​DDBV. However, the size of the gate drive high voltage VGH and the gate drive low voltage VGL does not change with the change of the display brightness value DDBV of the display module. If the analog drive voltage AVDD changes with the change of the black state voltage VGMP, it will inevitably affect the gate drive high voltage VGH and the gate drive low voltage VGL.

[0068] Based on this concept, the display module is optimized in the present disclosure, and the gate drive low voltage VGL and the gate drive high voltage VGH that control the off state and the on state of the sub-pixel PIX are set not to be generated by the analog drive voltage AVDD. In this way, the analog drive voltage AVDD can be free from the restrictions of the gate drive low voltage VGL and the gate drive high voltage VGH, and then the analog drive voltage AVDD can be adjusted according to the display brightness value DDBV of the display module in the present disclosure, thereby saving power consumption. In the present disclosure, when a sub-pixel PIX needs to be turned on, the gate drive high voltage VGH is applied to the gate of the sub-pixel PIX, thereby turning on the drive transistor connected to the sub-pixel PIX, allowing current to pass and charging the storage capacitor of the sub-pixel PIX, which in turn drives the light-emitting element LD to emit light, thereby realizing the lighting of the pixel. When a pixel needs to be turned off, the gate drive low voltage VGL is applied to the gate of the sub-pixel PIX, thereby turning off the drive transistor (thin film transistor (TFT)) connected to the sub-pixel PIX, preventing current from passing, and making the light-emitting element LD not emit light. In this example, a voltage value of the gate driving high voltage VGH is greater than a voltage value of the gate driving low voltage VGL.

[0069] In one embodiment of the present disclosure, see Figure 5-Figure 7 The gate drive low voltage VGL and the gate drive high voltage VGH are both generated by the power manager PMIC and sent to the gate drive circuit GIC. Specifically, the power manager PMIC is configured to output a constant voltage gate drive low voltage VGL and a constant voltage gate drive high voltage VGH. In one example, see Figure 7 , the gate driving low voltage VGL and the gate driving high voltage VGH are directly used to drive the gate driving circuit GIC on the display panel PNL. Figure 6 , the gate drive low voltage VGL and the gate drive high voltage VGH are used to drive the gate drive circuit GIC after being processed by the source drive circuit SIC on the display panel PNL (at this time, the gate drive low voltage VGL and the gate drive high voltage VGH are respectively formed into a sub-gate drive low voltage VGLO and a sub-gate drive high voltage VGHO after being processed by the source drive circuit SIC on the display panel PNL, and the difference between the sub-gate drive high voltage VGHO and the gate drive high voltage VGH is defined as not less than 0.7v in the present disclosure). In other words, the gate drive low voltage VGL and the gate drive high voltage VGH are used to drive the gate drive circuit GIC after being passed through the low voltage difference regulator LDO of the source drive circuit SIC on the display panel PNL. In this way, it is conducive to outputting a stable gate drive low voltage VGL and a gate drive high voltage VGH.

[0070] In this example, both the source driving circuit SIC and the gate driving circuit GIC are electrically connected to the power manager PMIC.

[0071] In one embodiment of the present disclosure, the source driver circuit SIC is configured to receive the display screen data of the display panel PNL sent by the host computer, and dynamically generate an analog driving voltage value SVDV based on the display screen data and send it to the power manager PMIC; the screen data includes a display brightness value DDBV, and in the present disclosure, at least two analog driving voltage values ​​SVDV corresponding to the display brightness values ​​DDBV are different. The source driver circuit SIC can be connected to the host computer through a timing controller TCON, and the timing controller TCON is configured to receive the display picture data sent by the host computer, and convert the display brightness value DDBV in the display picture data into a reference brightness value CDBV and send it to the source driver circuit SIC, and the source driver circuit SIC is configured to generate an analog driving voltage value SVDV based on the reference brightness value CDBV and send it to the power manager PMIC. In this example, the power manager PMIC can output an analog driving voltage AVDD according to the analog driving voltage value SVDV, and it can be understood that the analog driving voltage AVDD corresponding to at least two analog driving voltage values ​​SVDV is different, in other words, the analog driving voltage AVDD corresponding to at least two display brightness values ​​DDBV is different. In the present disclosure, the power manager PMIC is set to directly output the gate drive high voltage VGH and the gate drive low voltage VGL, so that the analog drive voltage AVDD is not limited by the gate drive high voltage VGH and the gate drive low voltage VGL. At the same time, the source drive circuit SIC outputs different analog drive voltage values ​​SVDV corresponding to different display brightness values ​​DDBV to the power manager PMIC, and the power manager PMIC then outputs different analog drive voltages AVDD according to different analog drive voltage values ​​SVDV. With the solution in the present disclosure, the analog drive voltage AVDD can be adaptively adjusted based on the display brightness value DDBV of the display device, so that the power consumption can be reduced by dynamically adjusting the analog drive voltage AVDD along with the display brightness value DDBV.

[0072] In one embodiment of the present disclosure, the source driver circuit SIC includes a voltage determination unit; the voltage determination unit is configured to determine an analog driving voltage value SVDV according to a reference brightness value CDBV, and send it to a power manager PMIC. The voltage determination unit includes a mapping module; the voltage determination unit can determine the analog driving voltage value SVDV according to the reference brightness value CDBV and the mapping module, and send it to the power manager PMIC.

[0073] In one example, the mapping module has a plurality of brightness range values ​​of the display module, each brightness range value corresponds to an analog driving voltage value SVDV; when the analog driving voltage value SVDV is confirmed according to the brightness range value, the analog driving voltage value SVDV corresponding to the reference brightness value CDBV is determined according to which brightness range value the reference brightness value CDBV falls into. For example, the plurality of brightness range values ​​are (50-70), (71-90), (91-110), (111-130), (131-150), (151-170), etc., wherein the analog driving voltage value corresponding to (50-70) is 4.8, the analog driving voltage value corresponding to (71-90) is 6.2, the analog driving voltage value corresponding to (91-110) is 7.8, the analog driving voltage value corresponding to (111-130) is 9.3, the analog driving voltage value corresponding to (131-150) is 11.1, and the analog driving voltage value corresponding to (151-170) is 13. If the reference brightness value CDBV is 63, it is judged that the reference brightness value CDBV is in the range of (50-70), and the analog driving voltage value SVDV corresponding to the reference brightness value CDBV is 4.8. If the reference brightness value CDBV is 131, it is judged that the reference brightness value CDBV is in the range of (131-150), and the analog driving voltage value SVDV corresponding to the reference brightness value CDBV is 11.1. If the reference brightness value CDBV is 151, it is judged that the reference brightness value CDBV is in the range of (151-170), and the analog driving voltage value SVDV corresponding to the reference brightness value CDBV is 13.

[0074] In another example, the mapping module has multiple binding parameters, each of which includes a binding brightness value and a binding analog driving voltage value; when determining the analog driving voltage value according to the binding brightness value, the analog driving voltage value SVDV corresponding to the reference brightness value CDBV is determined by linear interpolation according to at least two binding parameters and the reference brightness value CDBV. For example, the binding brightness value is 50, and its corresponding binding analog driving voltage value is 6.8 (which can be represented by (50, 6.8)), the binding brightness value is 80, and its corresponding binding analog driving voltage value is 9 (which can be represented by (80, 9)), the binding brightness value is 120, and its corresponding binding analog driving voltage value is 12 (which can be represented by (120, 12)), the binding brightness value is 170, and its corresponding binding analog driving voltage value is 14 (which can be represented by (170, 14)), the binding brightness value is 240, and its corresponding binding analog driving voltage value is 17 (which can be represented by (240, 17)), and so on. If the reference brightness value CDBV is 70, first determine that the reference brightness value CDBV is between 50 and 80, and based on the two sets of parameters (50, 6.8) and (80, 9), use linear interpolation to calculate that when the reference brightness value CDBV is 70, the corresponding analog drive voltage value SVDV is 8.27. If the reference brightness value CDBV is 125, first determine that the reference brightness value CDBV is between 120 and 170, and based on the two sets of parameters (120, 12) and (170, 14), use linear interpolation to calculate that when the reference brightness value CDBV is 70, the corresponding analog drive voltage value SVDV is 12.2. If the reference brightness value CDBV is 170, directly output the corresponding analog drive voltage value SVDV as 14.

[0075] In other examples of the present disclosure, other methods not shown may also be used to obtain the corresponding binding analog driving voltage value based on the reference brightness value CDBV.

[0076] In one embodiment of the present disclosure, the source driver circuit SIC is configured to generate a black state voltage VGMP according to an analog drive voltage AVDD from a power manager PMIC (in other words, the analog drive voltage AVDD can be converted by the source driver circuit SIC into a black state voltage VGMP to drive the display panel PNL); based on different display brightness values ​​DDBV, different analog drive voltages AVDD are different. It can be understood that different display brightness values ​​DDBV have different black state voltages VGMP. In the present disclosure, see Fig.11, when the brightness value DBV of the display module is set to be different, the voltage difference between the analog driving voltage AVDD and the black state voltage VGMP is constant. In other words, the analog driving voltage AVDD outputs the black state voltage VGMP after passing through the low voltage dropout regulator LDO of the source driving circuit SIC. In the present disclosure, as long as the voltage difference between the analog driving voltage AVDD and the black state voltage VGMP meets the minimum voltage dropout of the low voltage dropout regulator LDO, the power consumption is greatly reduced. See Fig.12 , the first column is brightness, the second column is black state voltage, the third column is analog driving voltage AVDD after adopting this solution, the fourth column is analog driving voltage AVDD in related technology, and the fifth column is the power consumption ratio reduced by analog driving voltage AVDD. Fig.12 It can be seen that the solution in the present disclosure reduces power consumption.

[0077] In one example, the voltage difference between the analog drive voltage AVDD and the black state voltage VGMP is not less than 0.4v. In one example, the voltage difference between the analog drive voltage AVDD and the black state voltage VGMP is not greater than 0.6v. In the present disclosure, the analog drive voltage AVDD outputs the black state voltage VGMP after passing through the low voltage dropout regulator LDO, which is conducive to achieving a stable output of the black state voltage VGMP and can protect sensitive devices. For example, the voltage difference between the analog drive voltage AVDD and the black state voltage VGMP is 0.4v. For another example, the voltage difference between the analog drive voltage AVDD and the black state voltage VGMP is 0.45v. For another example, the voltage difference between the analog drive voltage AVDD and the black state voltage VGMP is 0.5v. For another example, the voltage difference between the analog drive voltage AVDD and the black state voltage VGMP is 0.55v. For another example, the voltage difference between the analog drive voltage AVDD and the black state voltage VGMP is 0.6v.

[0078] In another embodiment of the present disclosure, the source driver circuit SIC is configured to determine the black state voltage VGMP according to the reference brightness value CDBV of the display module; output the analog drive voltage value SVDV to the power manager PMIC according to the minimum voltage difference between the black state voltage VGMP and the low voltage dropout regulator LDO in the source driver circuit SIC, and the power manager PMIC outputs the analog drive voltage AVDD according to the analog drive voltage value SVDV.

[0079] In this example, the source driving circuit SIC is configured to receive display picture data of the display panel PNL sent by the host computer, determine a reference brightness value CDBV based on the display picture data, and determine a black state voltage VGMP based on the reference brightness value CDBV.

[0080] In this example, when the reference brightness value CDBV is different, the black state voltage VGMP is different.

[0081] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A power manager, characterized in that: Used to drive a display module; the display module also includes a display panel, and the display panel has a source driving circuit; wherein the power manager is configured to be able to output a constant voltage gate driving low voltage, a constant voltage gate driving high voltage, and to be able to output an analog driving voltage according to an analog driving voltage value sent by the source driving circuit; the analog driving voltages corresponding to at least two of the analog driving voltage values ​​are different; The gate driving low voltage and the gate driving high voltage are directly used to drive the gate driving circuit on the display panel, or are used to drive the gate driving circuit after being processed by the source driving circuit on the display panel; The analog driving voltage can be converted into a black state voltage by the source driving circuit to drive the display panel.

2. The power manager according to claim 1, characterized in that: The voltage difference between the analog driving voltage and the black state voltage is not less than 0.4V.

3. The power manager according to claim 2, characterized in that: The voltage difference between the analog driving voltage and the black state voltage is not greater than 0.6V.

4. A source driving circuit, characterized in that: Used to drive a display module, wherein the display module has a timing controller; The source driving circuit is configured to receive a reference brightness value sent by the timing controller, and generate an analog driving voltage value based on the reference brightness value and send it to the power manager; The reference brightness value is generated by the display brightness value in the display picture data received by the timing controller; The analog driving voltage values ​​corresponding to at least two of the display brightness values ​​are different.

5. The source driving circuit according to claim 4, characterized in that: The source driving circuit comprises a voltage determining unit; The voltage determination unit is configured to determine the analog driving voltage value according to the reference brightness value and send the value to the power manager.

6. The source driving circuit according to claim 5, characterized in that: The voltage determination unit includes a mapping module; The mapping module has a plurality of brightness range values ​​of the display module, and each brightness range value corresponds to an analog driving voltage value; When the analog driving voltage value is confirmed according to the brightness range value, the analog driving voltage value corresponding to the reference brightness value is determined according to which brightness range value the reference brightness value falls into.

7. The source driving circuit according to claim 5, characterized in that: The voltage determination unit includes a mapping module; The mapping module has a plurality of binding parameters, each binding parameter including a binding brightness value and a binding analog driving voltage value; When determining the analog driving voltage value according to the bound brightness value, the analog driving voltage value corresponding to the reference brightness value is determined by using a linear interpolation method according to at least two binding parameters and the reference brightness value.

8. The source driving circuit according to claim 5, characterized in that: The source driving circuit is configured to generate a black state voltage according to an analog driving voltage from the power manager; wherein when the display brightness value of the display module is different, the voltage difference between the analog driving voltage and the black state voltage is constant.

9. The source driving circuit according to claim 4, characterized in that: The source driving circuit is configured to determine a black state voltage according to a reference brightness value of a display module; and determine the analog driving voltage value according to a minimum voltage difference between the black state voltage and a low voltage difference regulator in the source driving circuit.

10. A display panel, characterized in that: A source driving circuit as claimed in any one of claims 4 to 9, and a gate driving circuit; The gate driving circuit is configured to receive a gate driving low voltage and a gate driving high voltage output by the power manager according to any one of claims 1 to 3.

11. A display module, characterized in that: A display panel as claimed in claim 10 and a power manager as claimed in any one of claims 1 to 3.

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