Pixel driving circuit, control method of pixel driving circuit and display panel

Abstract

The invention provides a pixel driving circuit, a control method of the pixel driving circuit and a display panel, the pixel driving circuit comprises a driving module, a reset module, a data writing module and a light emitting control module, the data writing module and a first end of the driving module are connected at a first node, and a second end of the driving module is connected at a second node; the data write-in module comprises a first data write-in unit and a second data write-in unit, the first data write-in unit is used for writing a preset amplitude voltage signal into a first node in a bias stage, and the second data write-in unit is used for writing a data signal into the first node in a data write-in stage; and the second end of the driving module is connected with the reset module at a second node. According to the pixel driving circuit, all the pixels are controlled by the first data write-in module and the second data write-in module to write in the same preset amplitude voltage signals in the bias stage, so that the virtual write-in states of all the pixels are the same, and the shining phenomenon below black fonts is eliminated.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a pixel driving circuit, a control method for a pixel driving circuit, and a display panel. Background Art

[0002] Existing small and medium-sized display products use the Ramless+DDL+VSR 4CK design to reduce costs and improve high-frequency, high-resolution, low-grayscale uniformity and IC power consumption. The term "Ramless+DDL+VSR 4CK" describes a specific drive architecture and operating mode in AMOLED (active matrix organic light-emitting diode) display panels. Its components have the following meanings:

[0003] In AMOLED display, Ramless refers to the design that reduces the demand for the number of sources inside the driver IC by adding demux circuits (demultiplexing circuits), thereby reducing costs. The demux circuit is a digital circuit used to distribute an input signal to one of multiple output signals. It usually consists of an input terminal and multiple output terminals. According to the control signal of the input terminal, the input signal is routed to the corresponding output terminal. The source refers to the signal that provides the data voltage (driving voltage) to the panel;

[0004] DDL (Dual Data Line) refers to dual data line design. Dual data line design means that in the source drive circuit of the display panel, each pixel column is equipped with two data lines;

[0005] VSR (Variable Shift Register) refers to the shift register;

[0006] 4CK: CK here usually refers to the clock signal or control signal, and "4CK" means that four clock signals are used to control the writing and refreshing of pixels.

[0007] Ramless+DDL+VSR 4CK is designed to increase the writing speed of AMOLED (active matrix organic light-emitting diode) displays, reduce power consumption, and improve display quality, especially for high-resolution, low-cost application scenarios. However, this design may also bring some side effects. Summary of the invention

[0008] The main purpose of the present application is to provide a pixel driving circuit, a control method of the pixel driving circuit and a display panel, so as to at least solve the problem of light under black fonts in the display panel in the related art.

[0009] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a pixel driving circuit is provided, including a driving module, a reset module, a data writing module and a light-emitting control module, wherein the data writing module is connected to the first end of the driving module at a first node, the data writing module includes a first data writing unit and a second data writing unit, the first data writing unit is used to write a predetermined amplitude voltage signal to the first node in a bias phase, and the second data writing unit is used to write a data signal to the first node in a data writing phase; the second end of the driving module is connected to the reset module at a second node, and the reset module is used to reset the second node and the anode of the light-emitting element.

[0010] According to another aspect of the present application, based on the same inventive concept, a control method for a pixel driving circuit is provided, and the control method is used to control any one of the pixel driving circuits, and the method includes: when the pixel driving circuit is in the bias stage, controlling the light emitting control module and the second data writing unit to be turned off, and controlling the first data writing unit to be turned on to write the predetermined amplitude voltage signal to the first node; after writing the predetermined amplitude voltage signal to the first node, controlling the first data writing unit to be turned off and the second data writing unit to be turned on, so as to control the pixel driving circuit to enter the data writing stage.

[0011] According to another aspect of the present application, based on the same inventive concept, a display panel is provided, comprising: any one of the pixel driving circuits described above.

[0012] Applying the technical solution of the present application, the above-mentioned pixel driving circuit includes a driving module, a reset module, a data writing module and a light-emitting control module. The first end of the data writing module and the driving module are connected at a first node. The data writing module includes a first data writing unit and a second data writing unit. The first data writing unit is used to write a predetermined amplitude voltage signal to the first node in the bias stage, and the second data writing unit is used to write a data signal to the first node in the data writing stage. The second end of the driving module is connected to the reset module at the second node. The pixel driving circuit controls all pixels to write the same predetermined amplitude voltage signal in the bias stage through the first data writing module and the second data writing module, so that all pixels are in the same virtual writing state, eliminating the phenomenon of light under the black font, and solving the problem of light under the black font in the display panel in the related art. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The drawings constituting part of the present application are used to provide a further understanding of the present application. The exemplary embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0014] Figure 1 A schematic diagram showing a phenomenon of light emission below a black display area of ​​a display panel in the related art;

[0015] Figure 2 A schematic structural diagram of a pixel driving circuit of a display panel in the related art is shown;

[0016] Figure 3 A timing diagram of a first scanning signal and a data signal of a partial area of ​​a display panel under a three-pulse signal in the related art is shown;

[0017] Figure 4 A timing diagram of a second scanning signal and a data signal of a partial area of ​​a display panel under a three-pulse signal in the related art is shown;

[0018] Figure 5 A comparison diagram showing voltages at each terminal of a driving transistor of a pixel driving circuit in a partial area of ​​a display panel in the related art;

[0019] Figure 6 A timing diagram of a second scanning signal and a data signal of a partial area of ​​a display panel under a two-pulse signal and a four-pulse signal in the related art is shown;

[0020] Figure 7 A schematic structural diagram of a pixel driving circuit provided in an embodiment of the present application is shown;

[0021] Figure 8 A schematic structural diagram of another pixel driving circuit provided in an embodiment of the present application is shown;

[0022] Fig. 9 A schematic structural diagram of another pixel driving circuit provided in an embodiment of the present application is shown;

[0023] Fig.10 A schematic structural diagram of another pixel driving circuit provided in an embodiment of the present application is shown;

[0024] Fig.11 A schematic structural diagram of another pixel driving circuit provided in an embodiment of the present application is shown;

[0025] Fig.12 A timing diagram of a pixel driving circuit under a three-pulse signal provided in an embodiment of the present application is shown;

[0026] Fig.13 A timing diagram of a multi-row pixel driving circuit under a three-pulse signal provided in an embodiment of the present application is shown;

[0027] Fig.14A schematic flow chart of a control method of a driving circuit provided in an embodiment of the present application is shown;

[0028] Fig.15 A schematic structural diagram of a display panel provided in an embodiment of the present application is shown.

[0029] The above drawings include the following reference numerals:

[0030] 10. driving module; 20. reset module; 21. reset submodule; 30. data writing module; 31. first data writing unit; 32. second data writing unit; 40. light-emitting control module; 50. threshold compensation module; PD1. light-emitting element; M1. first data writing transistor; M2. second data writing transistor; M3. third data writing transistor; M4. fourth data writing transistor; M5. first dual-gate transistor; M51. first transistor; M52. second transistor; M6. reset transistor; M7. second dual-gate transistor; M71. third transistor; M71. fourth transistor; M8. driving transistor; M9. first light-emitting control transistor; M10. second light-emitting control transistor; C. storage capacitor; N1. first node; N2. second node; DVH. voltage signal of predetermined amplitude; Vdata. data signal; EM1. first data writing control signal; EM2. second data writing control signal; EM3. light-emitting control signal; Scan1. second scanning signal; Scan2. first scanning signal. DETAILED DESCRIPTION

[0031] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0032] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0033] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0034] As introduced in the background technology, in the design of the shift register of the related art that is controlled by 4 clock signals, the data writing process is divided into multiple pulses. Therefore, before the data is officially written, a series of pre-writing or virtual writing steps are performed first to reduce power consumption and improve the stability of data writing.

[0035] DTFT NBS negative bias refers to the phenomenon that in OLED display panels, when a transistor (usually a thin film transistor, TFT) is subjected to a negative bias voltage for a long time, its threshold voltage will shift. Here, DTFT (Driver TFT) refers to the driver transistor in the pixel drive circuit, and NBS (Negative Bias Stress) refers to the negative voltage bias stress applied to the TFT.

[0036] Figure 1 FIG. 1 is a schematic diagram of a light-emitting phenomenon below a black display area of ​​a display panel in the related art. Figure 1 As shown in the figure, during the reset / virtual writing process of the edge row below the black display area in the display panel, the DTFT NBS of the reset module of the pixel driving circuit of the edge row below the black display area is more negatively biased, which may cause insufficient data voltage writing to the gate of the driving transistor. When data writing is insufficient, the OLED pixel may emit a brightness different from the expected brightness in the subsequent light-emitting stage due to insufficient driving current, which is manifested as a bright line or a bright phenomenon, that is, Figure 1 Area A is a black display area, and area B is a bright line or a bright area below the black display area, wherein the black display area may be a black font.

[0037] Figure 2 FIG. 1 is a schematic diagram of a pixel driving circuit of a display panel in the related art. Figure 2As shown, the pixel driving circuit includes a first reset transistor M01, a second reset transistor M02, a threshold compensation transistor M03, a data writing transistor M04, a first light-emitting control transistor M05, a second light-emitting control transistor M06, a driving transistor M00 and a capacitor C0, wherein the first reset transistor M01 is used to be turned on under the control of the second scan signal Scan1 and transmit the reset signal Vref to the second node N2, the second reset transistor M02 is used to be turned on under the control of the second scan signal Scan1 and transmit the reset signal Vref to the anode of the light-emitting element, the threshold compensation transistor M03 and the data writing transistor M04 are used to write the data signal Vdata to the second node N2 under the control of the first scan signal Scan2, the first light-emitting control transistor M05 and the second light-emitting control transistor M06 are used to be turned on under the control of the data writing control signal Emit to transmit the signal of the first driving power line PVDD to the anode of the light-emitting element to control the light-emitting element to emit light, and the driving transistor M00 is used to be turned on under the control of the voltage of the second node N2 to drive the light-emitting element to emit light.

[0038] like Figure 2 As shown, each row in the display panel has a corresponding pixel driving circuit to drive the pixel display in the row. In this embodiment, the nth row is the last row of the black display area of ​​the display panel (ie Figure 1 The n+1th, ..., and n+4th rows are the last four rows starting from the nth row and are the bright areas below the black display area, that is, the n+1th, ..., and n+4th rows are all located at Figure 1 The B area in the figure, the n+5th and n+6th rows are the normal display area below the bright area (i.e. Figure 1 Normal display area below area B in the figure).

[0039] Figure 3 is a timing diagram of the first scanning signal and the data signal of a partial area of ​​the display panel under the three-pulse signal in the related art, Figure 4 : is a timing diagram of the second scanning signal and the data signal of a partial area of ​​the display panel under the three-pulse signal in the related art, such as Figure 2 and Figure 3 As shown, the nth row S1 is the second scanning signal Scan1 of the pixel driving circuit of the nth row, and the n+1th row S1, ..., and the n+6th row S1 are the second scanning signals Scan1 of the pixel driving circuit of the n+1th row, ..., and the second scanning signal Scan1 of the pixel driving circuit of the n+6th row respectively; as shown Figure 2 and Figure 4As shown, the nth row S2 is the first scan signal Scan2 of the pixel driving circuit of the nth row, the n+1th row S2, ..., the n+6th row S2 are the first scan signal Scan2 of the pixel driving circuit of the n+1th row, ..., the first scan signal Scan2 of the pixel driving circuit of the n+6th row. Data is the data signal of the display panel. Figure 3 and Figure 4 As shown, the data signal Data in the black display area of ​​the display panel is a higher voltage signal (for example: 6.6V). Under normal circumstances, the data signal Data in the normal display area below the black display area of ​​the display panel is a lower voltage signal (for example: 3V), and the nth row is the last row of the black display area of ​​the display panel. Therefore, after the data signal Data is written into the nth row of the display panel, the data signal Data changes from a high voltage signal (6.6V) to a low voltage signal (3V). That is, after the last pulse of S2 in the nth row of the display panel ends, the data signal Data changes from a high voltage signal (6.6V) to a low voltage signal (3V).

[0040] Since the scanning signal of the display panel in this scheme is a three-pulse signal, the first two pulse times of S2 of the pixel driving circuit of the n+1th row to the n+4th row are the virtual writing period (i.e., the bias stage) of the pixel driving circuit, and in the virtual writing period (i.e., the bias stage) of the pixel driving circuit of the n+1th row to the n+4th row, the data signal Data is still in the state of a high voltage signal (6.6V), that is, the voltage virtually written by the pixel driving circuit of the n+1th row to the n+4th row is a high voltage signal (6.6V), and the real Data voltage required for the written pixel to emit light is a low voltage signal (3V).

[0041] like Figure 3 and Figure 4 As shown, the solid arrow indicates that the voltage of the first node N1 written into the pixel driving circuit is 6.6V, and the dotted arrow indicates that the voltage of the first node N1 written into the pixel driving circuit is 3V. Since S2 is a signal for controlling data writing in the pixel driving circuit, the first two low-level pulses of S2 are the bias stage of the pixel driving circuit, and the Vdata voltage is virtually written into Figure 2 When the driving transistor M0 and S2 in the pixel drive circuit are in the third low level pulse, it is the real data writing stage of the pixel drive circuit, and the real required Vdata voltage is written into Figure 2 The driving transistor M0 in FIG. Figure 3 and Figure 4 As can be seen from the timing diagram, the timing of S1 and S2 in the pixel driving circuit is different, and data is written only when S2 is at a low level. Therefore, S1 in the pixel driving circuit does not write the Vdata voltage in the first pulse. Figure 2The driving transistor M0 in S1 is only in the last two pulses. Figure 2 The Vdata voltage is written into the driving transistor M0.

[0042] Since the pixel driving circuit of the n+1th row to the pixel driving circuit of the n+4th row is written in the bias phase and the data writing phase Figure 2 The Vdata of the driving transistor M0 in the n+5th row is different, that is, the voltage of the first node N1 of the pixel driving circuit in the n+1th row to the n+4th row is insufficient, resulting in the problem of lighting in the n+1th row to the n+4th row area. Figure 2 The Vdata of the driving transistor M0 in is the same, so the display panel starts to display normally after the n+5th row.

[0043] And, if Figure 4 It can be seen that the high level signal (6.6V) of Vdata virtually written by the n+1th row pixel driving circuit and the n+2th row pixel driving circuit lasts longer, so the brightness of the n+1th row and the n+2th row in the display panel is brighter.

[0044] Figure 5 It is a comparison diagram of the voltages at each end of the driving transistor of the pixel driving circuit in a partial area of ​​the display panel in the related art. Figure 5 (a) is the pixel driving circuit input Figure 3 The data voltage Data represented by the solid arrow in the middle is a schematic diagram of the voltages at each end of the driving transistor, as shown in Figure 5 As shown in (a), the gate voltage of the driving transistor is -3.0V. When the pixel driving circuit writes a high voltage (6.6V) data signal Data, the source voltage of the driving transistor is 6.6V, that is, the gate-source voltage difference of the driving transistor is -9.6V. Figure 5 (b) is the pixel driving circuit input Figure 3 The dashed arrow in the middle represents the data voltage Data, which is a schematic diagram of the voltages at each end of the driving transistor. Figure 5 As shown in (b), the gate voltage of the driving transistor is -3.0V. When the pixel driving circuit writes the low voltage (3V) data signal Data, the source voltage of the driving transistor is 3V, that is, the gate-source voltage difference of the driving transistor is -6V.

[0045] It should be noted that in some cases, the driving transistor can be an n-type transistor or a p-type transistor. In this application, the driving transistor is a p-type transistor as an example. In addition, this application uses a low level as the enable level, that is, when the scanning signal is at a low level, the data signal is written.

[0046] In addition, this application takes a three-pulse signal as an example, such as Figure 3As shown, when the scanning signal is a three-pulse signal, the number of rows affected and illuminated below the black display area is 4 rows. In some cases, the number of pulses of the signal of the pixel driving circuit is not the same, so the number of rows affected and illuminated below the black display area will be different accordingly. Figure 6 is a timing diagram of a second scanning signal and a data signal of a partial area of ​​a display panel under a two-pulse signal and a four-pulse signal in the related art, Figure 6 (a) is a timing diagram of a second scanning signal and a data signal of a partial area of ​​a display panel under a two-pulse signal in the related art, Figure 6 (b) is a timing diagram of the second scanning signal and the data signal of a partial area of ​​the display panel under the four-pulse signal in the related art, such as Figure 6 As shown in (a), the signal of the pixel driving circuit is a two-pulse signal, and the number of rows affected and lit below the black display area is 2. Figure 6 As shown in (b), the signal of the pixel driving circuit is a four-pulse signal, and the number of rows affected and illuminated below the black display area is 6, that is, the more pulses the signal has, the more rows are affected and the wider the bright line is.

[0047] In order to solve the problem of light shining underneath black characters in a display panel in the related art, an embodiment of the present application provides a pixel driving circuit, a control method of a pixel driving circuit and a display panel.

[0048] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0049] In this embodiment, a pixel driving circuit is provided. Figure 7 is a schematic diagram of the structure of a pixel driving circuit provided in an embodiment of the present application, such as Figure 7 As shown, it includes a driving module 10, a reset module 20, a data writing module 30 and a light control module 40, wherein the first end of the data writing module 30 and the driving module 10 are connected at the first node N1, the data writing module 30 includes a first data writing unit 31 and a second data writing unit 32, the first data writing unit 31 is used to write a predetermined amplitude voltage signal into the first node in the bias stage, and the second data writing unit 32 is used to write a data signal into the first node N1 in the data writing stage; the second end of the driving module 10 is connected to the reset module 20 at the second node N2, and the reset module 20 is used to reset the second node N2 and the anode of the light emitting element PD1.

[0050] The driving module 10 is used to drive the light emitting element PD1 to emit light. The reset module 20 is used to provide a reset signal Verf to the second node N2 under the control of the first scan signal Scan2 to reset the second node N2, and to provide the reset signal Verf to the anode of the light emitting element PD1 under the control of the second scan signal Scan1 to reset the anode of the light emitting element PD1. The light emitting control module 40 is used to provide a signal of the first driving power line PVDD to the light emitting element PD1 under the control of the light emitting control signal EM3 to control the light emitting time of the light emitting element PD1.

[0051] Among them, firstly, the reset module 20 is controlled to be turned on in the reset stage to reset the second node N2 and the anode of the light-emitting element PD1, and then the first data writing unit 31 is controlled to be turned on and the second data writing unit 32 is turned off in the bias stage (i.e., the virtual writing stage) to write the predetermined amplitude voltage signal DVH into the first node N1. Among them, the predetermined amplitude voltage signal DVH of all pixel driving circuits on the display panel is the same, so that the voltage virtually written into the first node N1 by all pixel driving circuits on the display panel is the same, and the bias state of the transistor is the same, so that the problem of the black part and the white part on the display panel being lit under the black part of the display panel is avoided due to the different voltage signals written in the bias stage (i.e., the virtual writing stage). That is, when the voltage virtually written into the first node N1 by all pixel driving circuits on the display panel is the same, in the data writing stage, the first data writing unit is turned off and the second data writing unit is turned on, and each pixel driving circuit writes the real data voltage required for the corresponding pixel to emit light, which will not be affected by the inconsistency of the virtual voltage writing, and the corresponding row of each pixel driving circuit displays the corresponding normal brightness.

[0052] The above-mentioned pixel driving circuit of the present application includes a driving module, a reset module, a data writing module and a light control module. The first end of the data writing module and the driving module are connected at a first node. The data writing module includes a first data writing unit and a second data writing unit. The first data writing unit is used to write a predetermined amplitude voltage signal to the first node in the bias stage, and the second data writing unit is used to write a data signal to the first node in the data writing stage. The second end of the driving module is connected to the reset module at the second node. The pixel driving circuit controls all pixels to write the same predetermined amplitude voltage signal in the bias stage through the first data writing module and the second data writing module, so that all pixels have the same virtual writing state, eliminates the phenomenon of light under the black font, and solves the problem of light under the black font in the display panel in the related art.

[0053] In some embodiments, Figure 8As shown, the first data writing unit 31 includes: a first data writing transistor M1, a first electrode of the first data writing transistor M1 is electrically connected to the first node N1, and a gate of the first data writing transistor M1 is used to input a first data writing control signal EM1; a second data writing transistor M2, a first electrode of the second data writing transistor M2 is electrically connected to a second electrode of the first data writing transistor M1, a gate of the second data writing transistor M2 is used to input a first scanning signal Scan2, and a second electrode of the second data writing transistor M2 is used to input the predetermined amplitude voltage signal.

[0054] The first data writing control signal EM1 is used to control the conduction and cut-off of the first data writing transistor M1, and the first scanning signal Scan2 is used to control the conduction and cut-off of the second data writing transistor M2. In this embodiment, the first data writing transistor M1 and the second data writing transistor M2 can be P-type transistors, that is, when the first data writing control signal EM1 is a low-level signal, the first data writing transistor M1 is turned on, and when the first data writing control signal EM1 is a high-level signal, the first data writing transistor M1 is turned off, when the first scanning signal Scan2 is a low-level signal, the second data writing transistor M2 is turned on, and when the first scanning signal Scan2 is a high-level signal, the second data writing transistor M2 is turned off.

[0055] Fig.12 is a timing diagram of a pixel driving circuit provided in an embodiment of the present application, such as Figure 8 and Fig.12As shown, in the bias stage of the pixel driving circuit, the first data write control signal EM1 is a low-level signal, controlling the first data write transistor M1 to be turned on, and the second data write control signal EM2 is a high-level signal, controlling the third data write transistor M3 to be turned off. In the bias stage of the pixel driving circuit, when the second scan signal Scan1 is a high-level signal and the first scan signal Scan2 is a low-level signal, the first scan signal Scan2 controls the second data write transistor M2 to be turned on, so as to write the predetermined amplitude voltage signal DVH into the first node N1 through the second data write transistor M2 and the first data write transistor M1. Since the predetermined amplitude voltage signal DVH of all pixel driving circuits on the display panel is the same, the voltage virtually written into the first node N1 by all pixel driving circuits on the display panel is the same, and the bias state of the transistors is the same, thereby avoiding the problem that the black part and the white part of the display panel are written with different voltage signals in the bias stage (i.e., the virtual write stage), resulting in the light phenomenon under the black part of the display panel. In addition, in the bias stage of the pixel driving circuit, the first scan signal Scan2 is a low-level signal, which controls the fourth data writing transistor M4 to be turned on. However, since the second data writing control signal EM2 is a high-level signal at this time, the third data writing transistor M3 is turned off. Therefore, the data signal Vdata cannot be written into the first node N1 through the third data writing transistor M3. Therefore, in the bias stage (i.e., the virtual writing stage), the voltage of the first node N1 is not affected by the data signal Vdata.

[0056] in, Fig.13 is a timing diagram of a multi-row pixel driving circuit provided in an embodiment of the present application, such as Fig.12 and Fig.13 As shown, in the case where the current pixel driving circuit is the n-th row pixel driving circuit, the first data write control signal EM1 of the n-th row pixel driving circuit is the same as the light emitting control signal EM3 of the n+5-th row pixel driving circuit. Therefore, in the display panel, the first data write control signal EM1 of the n-th row pixel driving circuit and the light emitting control signal EM3 of the n+5-th row pixel driving circuit can reuse the same signal.

[0057] Among them, Fig.13As shown, R is a pixel unit that emits red light, G is a pixel unit that emits green light, B is a pixel unit that emits blue light, and the Source signal is a signal that supplies power to the data signal Vdata. In the field of display technology, the signal output by the IC (Integrated Circuit) is transmitted to the data line of the display panel through a specific pin. The Source signal in the figure is responsible for transmitting information such as image data from the IC to the corresponding data line, providing power and data for it. For the display panel design of the present application, a Source signal can correspond to pixels in two adjacent columns in the same row, which is Fig.13 The label corresponding to each pixel unit in Fig.13 The label corresponding to each pixel unit is the row number in the display panel.

[0058] The solid line of Scan1[1] is the waveform of the second scanning signal of the pixel driving circuit of the n+1th row on the display panel, the solid line of Scan1[2] is the waveform of the second scanning signal of the pixel driving circuit of the n+2th row on the display panel, the solid line of Scan1[3] is the waveform of the second scanning signal of the pixel driving circuit of the n+3th row on the display panel, ..., the solid line of Scan1[8] is the waveform of the second scanning signal of the pixel driving circuit of the n+8th row on the display panel, EM[-1] is the light-emitting control signal of the pixel driving circuit of the n-1th row on the display panel, EM[0] is the light-emitting control signal of the pixel driving circuit of the nth row on the display panel, ..., EM[7] is the light-emitting control signal of the pixel driving circuit of the n-7th row on the display panel, and in addition, Fig.13 The middle dotted line is the waveform of the first scanning signal of the corresponding row, and the nth row of pixel driving circuits is the last row of the black area on the display panel.

[0059] In some embodiments, Figure 8 As shown, the second data writing unit 32 includes: a third data writing transistor M3, a first electrode of the third data writing transistor M3 is electrically connected to the first node N1, and a gate of the third data writing transistor M3 is used to input the second data writing control signal EM2; a fourth data writing transistor M4, a first electrode of the fourth data writing transistor M4 is electrically connected to the second electrode of the third data writing transistor M3, a gate of the fourth data writing transistor M4 is used to input the first scanning signal Scan2, and a second electrode of the fourth data writing transistor M4 is used to input the data signal Vdata.

[0060] The second data writing control signal EM2 is used to control the conduction and cut-off of the third data writing transistor M3, and the first scanning signal Scan2 is used to control the conduction and cut-off of the fourth data writing transistor M4. In this embodiment, the third data writing transistor M3 and the fourth data writing transistor M4 can be P-type transistors, that is, when the second data writing control signal EM2 is a low-level signal, the third data writing transistor M3 is turned on, and when the second data writing control signal EM2 is a high-level signal, the third data writing transistor M3 is turned off, when the first scanning signal Scan2 is a low-level signal, the fourth data writing transistor M4 is turned on, and when the first scanning signal Scan2 is a high-level signal, the fourth data writing transistor M4 is turned off.

[0061] like Figure 8 and Fig.12 As shown, in the data writing stage of the pixel driving circuit, the first data writing control signal EM1 is a high-level signal, which controls the first data writing transistor M1 to be turned off, the second data writing control signal EM2 is a low-level signal, which controls the third data writing transistor M3 to be turned on, and the first scanning signal Scan2 changes from a high-level signal to a low-level signal, which controls the second data writing transistor M2 and the fourth data writing transistor M4 to be turned on, and the data signal Vdata is written into the first node N1 through the fourth data writing transistor M4 and the third data writing transistor M3. Since the first data writing transistor M1 is turned off, the predetermined amplitude voltage signal DVH cannot be written into the first node N1 through the first data writing transistor M1.

[0062] Among them, Fig.12 and Fig.13 As shown, in the case where the current pixel driving circuit is the n-th row pixel driving circuit, the second data write control signal EM2 of the n-th row pixel driving circuit is the same as the light emitting control signal EM3 of the n-2-th row pixel driving circuit. Therefore, in the display panel, the first data write control signal EM1 of the n-th row pixel driving circuit and the light emitting control signal EM3 of the n-2-th row pixel driving circuit can reuse the same signal.

[0063] In some embodiments, Fig. 9 As shown, the pixel driving circuit also includes: a threshold compensation module 50, a first end of the threshold compensation module 50 is electrically connected to the third end of the driving module 10, a second end of the threshold compensation module 50 is electrically connected to the second node N2, and a third end of the threshold compensation module 50 is used to input the first scanning signal Scan2.

[0064] The threshold compensation module 50 is used to perform threshold compensation on the driving module under the control of the first scanning signal Scan2.

[0065] In some embodiments, Fig. 9 As shown, the threshold compensation module 50 includes at least one transistor. That is, the threshold compensation module can be composed of one transistor or multiple transistors. The transistor in the threshold compensation module can be an N-type transistor or a P-type transistor.

[0066] In some embodiments, Fig.10 As shown, the threshold compensation module 50 includes: a first dual-gate transistor M5, a first electrode of the first dual-gate transistor M5 is electrically connected to the third end of the driving module 10, a second electrode of the first dual-gate transistor M5 is electrically connected to the second node N2, and a gate of the first dual-gate transistor M5 is used to input the first scanning signal Scan2.

[0067] The first dual-gate transistor M5 includes a first transistor M51 and a second transistor M52. The first scan signal Scan2 is used to control the on and off of the first dual-gate transistor M5. In this embodiment, the first transistor M51 and the second transistor M52 can both be P-type transistors. That is, when the first scan signal Scan2 is a low-level signal, the first dual-gate transistor M5 is turned on, and when the first scan signal Scan2 is a high-level signal, the first dual-gate transistor M5 is turned off. Fig.10 and Fig.12 As shown, in the bias stage of the pixel driving circuit, when the second scanning signal Scan1 is a high-level signal and the first scanning signal Scan2 is a low-level signal, the signal of the third node N3 is virtually written into the second node N2 through the first dual-gate transistor M5 to perform threshold compensation on the driving module. In the data writing stage, the second scanning signal Scan1 is a high-level signal, the first scanning signal Scan2 is a low-level signal, and the second data writing control signal EM2 is a low-level signal, the data signal Vdata is written into the first node N1 through the fourth data writing transistor M4 and the third data writing transistor M3, and the signal of the third node N3 is written into the second node N2 through the first dual-gate transistor M5 to achieve the writing of the real data signal Vdata required for the pixel to emit light.

[0068] In some embodiments, Fig.10 As shown, the reset module 20 includes: a reset submodule 21, a first end of the reset submodule 21 is used to input the first reset signal Vref1, a second end of the reset submodule 21 is used to input the second scan signal Scan1, and a third end of the reset submodule 21 is electrically connected to the second node N2; a reset transistor M6, a first electrode of the reset transistor M6 is used to input the second reset signal Vref2, a gate of the reset transistor M6 is used to input the first scan signal Scan2, and a second electrode of the reset transistor M6 is used to be electrically connected to the anode of the light-emitting element PD1.

[0069] The reset submodule is used to transmit the first reset signal Vref1 to the second node N2 under the control of the second scan signal Scan1 to reset the second node N2. The reset transistor M6 is used to transmit the second reset signal Vref2 to the anode of the light emitting element PD1 under the control of the first scan signal Scan2 to reset the anode of the light emitting element PD1.

[0070] In the above embodiment, the reset transistor M6 is taken as a P-type transistor as an example, and the first scan signal Scan2 is used to control the on and off of the reset transistor M6. When the reset transistor M6 is a P-type transistor, the reset transistor M6 is turned off when the first scan signal Scan2 is a high-level signal, and the reset transistor M6 is turned on when the first scan signal Scan2 is a low-level signal.

[0071] In the reset phase of the pixel driving circuit, the first scan signal Scan2 is a low level signal, the reset transistor M6 is turned on, and the second reset signal Vref2 is transmitted to the anode of the light emitting element PD1 through the reset transistor M6 to reset the anode of the light emitting element PD1.

[0072] In some embodiments, Fig.10 As shown, the reset submodule 21 includes at least one transistor. That is, the reset submodule 21 can be composed of one transistor or multiple transistors. The transistor in the reset submodule 21 can be an N-type transistor or a P-type transistor.

[0073] In some embodiments, Fig.11 As shown, the reset submodule 21 includes: a second dual-gate transistor M7, a first electrode of the second dual-gate transistor M7 is used to input the first reset signal, a gate of the second dual-gate transistor M7 is used to input the second scan signal Scan1, and a third electrode of the second dual-gate transistor M7 is electrically connected to the second node N2. The second dual-gate transistor M7 includes a third transistor M71 and a fourth transistor M72, and the second scan signal Scan1 is used to control the conduction and cutoff of the second dual-gate transistor M7. In this embodiment, the third transistor M71 and the fourth transistor M72 are both P-type transistors as an example, that is, when the second scan signal Scan1 is a low-level signal, the second dual-gate transistor M7 is turned on, and when the second scan signal Scan1 is a high-level signal, the second dual-gate transistor M7 is turned off. In the reset stage of the pixel driving circuit, when the second scan signal Scan1 is a low-level signal, the third transistor M71 and the fourth transistor M72 are turned on, and the first reset signal Vref1 is transmitted to the second node N2 through the third transistor M71 and the fourth transistor M72 to reset the second node N2.

[0074] In some embodiments, Fig.11 As shown, the driving module 10 includes: a driving transistor M8, a gate of the driving transistor M8 is electrically connected to the second node N2, a first electrode of the driving transistor M8 is electrically connected to the first node N1, and a second electrode of the driving transistor M8 is electrically connected to the light emitting control module 40.

[0075] The signal of the second node N2 is used to control the on or off of the driving transistor M8. In the light-emitting stage of the pixel driving circuit, the signal of the second node N2 controls the driving transistor M8 to be turned on, the light-emitting control signal EM3 controls the first light-emitting control transistor M9 and the second light-emitting control transistor M10 to be turned on, and the signal of the first driving power line PVDD is transmitted to the anode of the light-emitting element PD1 through the first light-emitting control transistor M9, the driving transistor M8 and the second light-emitting control transistor M10, and the light-emitting element PD1 emits light.

[0076] In some embodiments, Fig.11 As shown, the light-emitting control module 40 includes: a first light-emitting control transistor M9, a first electrode of the first light-emitting control transistor M9 is electrically connected to the first driving power line PVDD, a gate of the first light-emitting control transistor M9 is used to input the light-emitting control signal EM3, and a second electrode of the first light-emitting control transistor M9 is electrically connected to the first node N1; a second light-emitting control transistor M10, a first electrode of the second light-emitting control transistor M10 is electrically connected to the third end of the driving module 10, a gate of the second light-emitting control transistor M10 is used to input the light-emitting control signal EM3, and a second electrode of the second light-emitting control transistor M10 is electrically connected to the anode of the light-emitting element PD1.

[0077] Among them, the light-emitting control signal EM3 is used to control the conduction and cutoff of the first light-emitting control transistor M9 and the second light-emitting control transistor M10. Taking the first light-emitting control transistor M9 and the second light-emitting control transistor M10 as P-type transistors, when the light-emitting control signal EM3 is a high-level signal, the first light-emitting control transistor M9 and the second light-emitting control transistor M10 are cut off, and when the light-emitting control signal EM3 is a low-level signal, the first light-emitting control transistor M9 and the second light-emitting control transistor M10 are turned on.

[0078] In the light-emitting stage of the pixel driving circuit, the light-emitting control signal EM3 is a low-level signal, the first light-emitting control transistor M9 and the second light-emitting control transistor M10 are turned on, and the signal of the first driving power line PVDD is transmitted to the anode of the light-emitting element PD1 through the first light-emitting control transistor M9, the driving transistor M8 and the second light-emitting control transistor M10 to control the light-emitting element PD1 to emit light.

[0079] In some embodiments, Fig.11 As shown, the pixel driving circuit further includes: a storage capacitor C, a first electrode of the storage capacitor C is electrically connected to the first driving power line PVDD, and a second electrode of the storage capacitor C is electrically connected to the second node N2.

[0080] The storage capacitor C is used to keep the voltage of the second node N2 unchanged during the image frame period.

[0081] It should be noted that in a specific implementation, the first electrode of the transistor can be used as its source and the second electrode as its drain, depending on the type of transistor and the signal of its gate; or, conversely, the first electrode of the transistor can be used as its drain and the second electrode can be used as its source, without making a specific distinction here.

[0082] It should be noted that, generally, transistors are divided into N-type transistors and P-type transistors. Although the above embodiments all take P-type transistors as examples, N-type transistors may be selected in the above embodiments, optionally. The N-type transistor is turned on under the control of a high-level signal and is turned off under the control of a low-level signal; the P-type transistor is turned on under the control of a low-level signal and is turned off under the control of a high-level signal.

[0083] The embodiment of the present application also provides a control method of a driving circuit. Fig.14 FIG. 1 is a flow chart of a control method of a pixel driving circuit according to an embodiment of the present application. Fig.14 and Figure 7 As shown, the above control method is used to control any one of the above pixel driving circuits, and the above method comprises the following steps:

[0084] Step S101, when the above-mentioned pixel driving circuit is in the above-mentioned bias stage, the above-mentioned light emitting control module 40 and the above-mentioned second data writing unit 32 are controlled to be turned off, and the above-mentioned first data writing unit 31 is controlled to be turned on to write the above-mentioned predetermined amplitude voltage signal into the above-mentioned first node N1. After the above-mentioned predetermined amplitude voltage signal is written into the above-mentioned first node N1, the above-mentioned first data writing unit 31 is controlled to be turned off and the above-mentioned second data writing unit 32 is turned on to control the above-mentioned pixel driving circuit to enter the above-mentioned data writing stage.

[0085] The control method of the above-mentioned driving circuit of the present application controls the first data writing unit to be turned on to write a predetermined amplitude voltage signal into the first node when the pixel driving circuit is in the bias stage. After the predetermined amplitude voltage signal is written into the first node, the first data writing unit is controlled to be turned off and the second data writing unit is controlled to be turned on to control the pixel driving circuit to enter the data writing stage, that is, all pixels are controlled to write the same predetermined amplitude voltage signal in the bias stage through the first data writing module and the second data writing module, so that all pixels are virtually written in the same state, eliminating the bright phenomenon under the black font, and solving the problem of bright black font under the display panel in the related art.

[0086] In some embodiments, Figure 7 and Fig.12 As shown, when the pixel driving circuit is in the bias stage, the light emitting control module 40 and the second data writing unit 32 are controlled to be turned off, and the first data writing unit 31 is controlled to be turned on to write the predetermined amplitude voltage signal into the first node N1. After the predetermined amplitude voltage signal is written into the first node N1, the first data writing unit 31 is controlled to be turned off and the second data writing unit 32 is controlled to be turned on to control the pixel driving circuit to enter the data writing stage, including the following steps:

[0087] Step S1011, when the pixel driving circuit is in a reset stage, the first data writing unit 31, the second data writing unit 32 and the light emitting control module 40 are controlled to be turned off, and the reset module 20 is controlled to be turned on, so as to reset the second node N2 for the first time;

[0088] Step S1012, after the second node N2 is reset for the first time, the second data writing unit 32, the light emitting control module 40 and the reset module 20 are turned off, and the first data writing unit 31 is turned on to write the predetermined amplitude voltage signal into the first node N1, so as to perform the first virtual writing on the first node N1;

[0089] Step S1013, after performing the first virtual writing to the first node N1, controlling the first data writing unit 31, the second data writing unit 32 and the light emitting control module 40 to be turned off, and controlling the reset module 20 to be turned on, so as to perform a second reset on the second node N2;

[0090] Step S1014, after resetting the second node N2 for the second time, controlling the second data writing unit 32, the light emitting control module 40 and the reset module 20 to be turned off, and controlling the first data writing unit 31 to be turned on to write the predetermined amplitude voltage signal to the first node N1 again, so as to perform a second virtual writing on the first node N1;

[0091] Step S1015, after performing the second virtual writing to the first node N1, controlling the pixel driving circuit to enter the data writing phase.

[0092] The above steps make the writing states of the first two pulses of all pixels the same in the three-pulse writing of the pixel driving circuit, so that the negative bias states of the transistors are the same, thereby eliminating the bright phenomenon under the black font.

[0093] Combine the following Fig.12 The circuit timing diagram shown in Fig.11 Taking the display panel shown as an example, the working process of the pixel driving circuit provided by the embodiment of the present invention is described. In the following description, 1 represents a high level and 0 represents a low level. It should be noted that 1 and 0 are logic potentials, which are only for better explanation of the specific working process of the embodiment of the present invention, rather than specific voltage values.

[0094] In some optional embodiments, the operation process of the pixel circuit includes a reset phase, a data writing phase and a light emitting phase. The reset phase also includes a bias phase, the bias phase is used for virtual data writing, and the data writing phase is between the reset phase and the light emitting phase.

[0095] In the t1 stage (ie, the reset stage), EM1=0, EM2=1, the light emitting control signal EM3 first changes to a high level, ie, EM3=1, and then controls Scan1=0.

[0096] The light emission control signal EM3 controls the first light emission control transistor M9 and the second light emission control transistor M10 to be turned off, and the second data writing control signal EM2 controls the third data writing transistor M3 to be turned off.

[0097] The first scan signal Scan2 first controls the second data writing transistor M2 , the fourth data writing transistor M4 , and the first double-gate transistor M5 to be turned off.

[0098] The second scan signal Scan1 controls the third transistor M71 and the fourth transistor M72 of the second double-gate transistor M7 to turn on, and the first reset signal Vref1 is transmitted to the second node N2 through the third transistor M71 and the fourth transistor M72 to reset the second node N2 for the first time.

[0099] Then, in the bias phase (i.e., phase t4), the second scan signal Scan1 becomes a high potential, the first scan signal Scan2 becomes a low potential, the first scan signal Scan2 controls the second data write transistor M2 and the first dual-gate transistor M5 to turn on, and since EM1=0, the first data write transistor M1 is turned on, and at this time, the predetermined amplitude voltage signal DVH is transmitted to the first node N1 through the second data write transistor M2 and the first data write transistor M1 to perform the first virtual write to the first node N1. At the same time, the first scan signal Scan2 controls the reset transistor M6 to turn on, and the second reset signal Vref2 is transmitted to the anode of the light-emitting element PD1 through the reset transistor M6 to reset the anode of the light-emitting element PD1 for the first time.

[0100] Afterwards, the first scan signal Scan2 becomes a high potential, controlling the second data write transistor M2, the fourth data write transistor M4 and the first dual-gate transistor M5 to be turned off, and the second scan signal Scan1 becomes a low potential, controlling the third transistor M71 and the fourth transistor M72 of the second dual-gate transistor M7 to be turned on, and the first reset signal Vref1 is transmitted to the second node N2 through the third transistor M71 and the fourth transistor M72 to reset the second node N2 for the second time.

[0101] After another biasing stage (i.e., stage t4), the second scanning signal Scan1 becomes a high potential, the first scanning signal Scan2 becomes a low potential, the first scanning signal Scan2 controls the second data writing transistor M2 and the first dual-gate transistor M5 to be turned on, and the predetermined amplitude voltage signal DVH is transmitted to the first node N1 through the second data writing transistor M2 and the first data writing transistor M1 to perform a second virtual writing on the first node N1. At the same time, the first scanning signal Scan2 controls the reset transistor M6 to be turned on, and the second reset signal Vref2 is transmitted to the anode of the light-emitting element PD1 through the reset transistor M6 to reset the anode of the light-emitting element PD1 for the second time.

[0102] In the t2 phase (ie, the data writing phase), EM1=1, EM2=0, and EM3=1.

[0103] The second scan signal Scan1 changes from a low level to a high level, controlling the third transistor M71 and the fourth transistor M72 of the second dual-gate transistor M7 to be turned off, and the light-emitting control signal EM3 controls the first light-emitting control transistor M9 and the second light-emitting control transistor M10 to be turned off. The first scan signal Scan2 changes from a high level to a low level, controlling the second data writing transistor M2, the fourth data writing transistor M4 and the first dual-gate transistor M5 to be turned on, and the data signal Vdata is transmitted to the first node N1 through the fourth data writing transistor M4 and the second data writing transistor M2. At this time, the voltage of the first node N1 is equal to the data signal Vdata, and the signal of the first node N1 is transmitted to the third node N3 through the driving transistor M8. At this time, the voltage of the third node N3 is the difference between the voltage of the data signal line Vdata and the threshold voltage of the driving transistor M8, that is, V N3 =Vdata-|V th |.

[0104] The first scan signal Scan2 controls the first transistor M51 and the second transistor M52 of the first double-gate transistor M5 to be turned on, and the signal of the third node N3 is transmitted to the second node N2 through the first transistor M51 and the second transistor M52. During this process, the voltage of the second node N2 increases slowly.

[0105] In the t3 stage (ie, the light-emitting stage), Scan1=1, Scan2=1, EM3=0, and EM2=0.

[0106] The second scan signal Scan1 controls the third transistor M71 and the fourth transistor M72 of the second dual-gate transistor M7 to be turned off, and the first scan signal Scan2 controls the first dual-gate transistor M5, the second data writing transistor M2, the fourth data writing transistor M4 and the reset transistor M6 to be turned off. The light-emitting control signal EM3 controls the first light-emitting control transistor M9 and the second light-emitting control transistor M10 to be turned on, and the signal of the second node N2 controls the driving transistor M8 to be turned on. The signal of the first driving power supply PVDD is transmitted to the anode of the light-emitting element PD1 through the first light-emitting control transistor M9, the driving transistor M8 and the second light-emitting control transistor M10, so that the light-emitting element PD1 emits light.

[0107] Based on the same inventive concept, an embodiment of the present invention further provides a display panel, such as Fig.15 As shown, the display panel 300 includes: a display area and any one of the above-mentioned pixel driving circuits.

[0108] All pixels in the above-mentioned display panel of the present application write the same predetermined amplitude voltage signal during the bias stage, so that the virtual writing state of all pixels is the same, eliminating the bright phenomenon under the black font, and solving the problem of bright black font under the display panel in the related art.

[0109] In the specific implementation, in the implementation of the present invention, a display device is also provided, and the display device includes a display panel. The display device provided in this embodiment can be an array substrate, or a terminal display device, such as a mobile phone, a computer, a television, or other display devices with display functions, and the present invention does not impose specific restrictions on this. The display device provided in the embodiment of the present invention has the beneficial effects of the pixel driving circuit provided in the embodiment of the present invention, and the specifics can be referred to in each embodiment. The specific description of the gate driving circuit is not repeated in this embodiment.

[0110] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0111] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0112] 1) The above-mentioned pixel driving circuit of the present application includes a driving module, a reset module, a data writing module and a light control module. The first end of the data writing module and the driving module are connected at a first node. The data writing module includes a first data writing unit and a second data writing unit. The first data writing unit is used to write a predetermined amplitude voltage signal to the first node in the bias stage, and the second data writing unit is used to write a data signal to the first node in the data writing stage. The second end of the driving module is connected to the reset module at the second node. The pixel driving circuit controls all pixels to write the same predetermined amplitude voltage signal in the bias stage through the first data writing module and the second data writing module, so that all pixels are in the same virtual writing state, eliminating the phenomenon of light under the black font, and solving the problem of light under the black font in the display panel in the related art.

[0113] 2) The control method of the above-mentioned driving circuit of the present application controls the first data writing unit to be turned on to write a predetermined amplitude voltage signal into the first node when the pixel driving circuit is in the bias stage. After the predetermined amplitude voltage signal is written into the first node, the first data writing unit is controlled to be turned off and the second data writing unit is turned on to control the pixel driving circuit to enter the data writing stage, that is, all pixels are controlled to write the same predetermined amplitude voltage signal in the bias stage through the first data writing module and the second data writing module, so that all pixels are virtually written in the same state, eliminating the bright phenomenon under the black font, and solving the problem of bright black font under the display panel in the related art.

[0114] 3) All pixels in the above-mentioned display panel of the present application write the same predetermined amplitude voltage signal in the bias stage, so that the virtual writing state of all pixels is the same, eliminating the bright phenomenon under the black font, and solving the problem of bright black font under the display panel in the related art.

[0115] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A pixel driving circuit, characterized in that: It includes a driving module, a reset module, a data writing module and a light emitting control module, wherein: The data writing module is connected to the first end of the driving module at a first node, and the data writing module includes a first data writing unit and a second data writing unit, wherein the first data writing unit is used to write a voltage signal of a predetermined amplitude into the first node in a bias phase, and the second data writing unit is used to write a data signal into the first node in a data writing phase; The second end of the driving module is connected to the reset module at a second node, and the reset module is used to reset the second node and the anode of the light emitting element.

2. The pixel driving circuit according to claim 1, characterized in that: The first data writing unit comprises: a first data writing transistor, wherein a first electrode of the first data writing transistor is electrically connected to the first node, and a gate of the first data writing transistor is used to input a first data writing control signal; A second data write transistor, wherein the first electrode of the second data write transistor is electrically connected to the second electrode of the first data write transistor, the gate of the second data write transistor is used to input the first scanning signal, and the second electrode of the second data write transistor is used to input the predetermined amplitude voltage signal.

3. The pixel driving circuit according to claim 1, characterized in that: The second data writing unit includes: a third data writing transistor, wherein a first electrode of the third data writing transistor is electrically connected to the first node, and a gate of the third data writing transistor is used to input a second data writing control signal; A fourth data write transistor, wherein a first electrode of the fourth data write transistor is electrically connected to a second electrode of the third data write transistor, a gate of the fourth data write transistor is used to input a first scanning signal, and a second electrode of the fourth data write transistor is used to input the data signal.

4. The pixel driving circuit according to claim 1, characterized in that: Also includes: A threshold compensation module, wherein a first end of the threshold compensation module is electrically connected to a third end of the driving module, a second end of the threshold compensation module is electrically connected to the second node, and a third end of the threshold compensation module is used to input a first scanning signal.

5. The pixel driving circuit according to claim 4, characterized in that: The threshold compensation module includes at least one transistor.

6. The pixel driving circuit according to claim 4, characterized in that: The threshold compensation module comprises: A first dual-gate transistor, wherein a first electrode of the first dual-gate transistor is electrically connected to the third end of the driving module, a second electrode of the first dual-gate transistor is electrically connected to the second node, and a gate of the first dual-gate transistor is used to input the first scanning signal.

7. The pixel driving circuit according to claim 1, characterized in that: The reset module comprises: a reset submodule, wherein a first end of the reset submodule is used to input a first reset signal, a second end of the reset submodule is used to input a second scan signal, and a third end of the reset submodule is electrically connected to the second node; A reset transistor, wherein a first electrode of the reset transistor is used to input a second reset signal, a gate of the reset transistor is used to input a first scanning signal, and a second electrode of the reset transistor is used to be electrically connected to an anode of the light emitting element.

8. The pixel driving circuit according to claim 7, characterized in that: The reset submodule includes at least one transistor.

9. The pixel driving circuit according to claim 7, characterized in that: The reset submodule comprises: A second double-gate transistor, wherein a first electrode of the second double-gate transistor is used to input the first reset signal, a gate of the second double-gate transistor is used to input the second scan signal, and a third electrode of the second double-gate transistor is electrically connected to the second node.

10. The pixel driving circuit according to claim 1, characterized in that: The driving module comprises: A driving transistor, wherein a gate of the driving transistor is electrically connected to the second node, a first electrode of the driving transistor is electrically connected to the first node, and a second electrode of the driving transistor is electrically connected to the light emitting control module.

11. The pixel driving circuit according to claim 1, characterized in that: The light emitting control module comprises: a first light emission control transistor, wherein a first electrode of the first light emission control transistor is electrically connected to a first driving power line, a gate of the first light emission control transistor is used to input a light emission control signal, and a second electrode of the first light emission control transistor is electrically connected to the first node; A second light emitting control transistor, wherein the first electrode of the second light emitting control transistor is electrically connected to the third end of the driving module, the gate of the second light emitting control transistor is used to input the light emitting control signal, and the second electrode of the second light emitting control transistor is electrically connected to the anode of the light emitting element.

12. The pixel driving circuit according to claim 1, characterized in that: The pixel driving circuit further includes: A storage capacitor, wherein a first electrode of the storage capacitor is electrically connected to the first driving power line, and a second electrode of the storage capacitor is electrically connected to the second node.

13. A method for controlling a pixel driving circuit, characterized in that: The control method is used to control the pixel driving circuit according to any one of claims 1 to 12, and the method comprises: When the pixel driving circuit is in the bias stage, the light emitting control module and the second data writing unit are controlled to be turned off, and the first data writing unit is controlled to be turned on to write the predetermined amplitude voltage signal into the first node. After the predetermined amplitude voltage signal is written into the first node, the first data writing unit is controlled to be turned off and the second data writing unit is controlled to be turned on to control the pixel driving circuit to enter the data writing stage.

14. The method according to claim 13, characterized in that When the pixel driving circuit is in the bias stage, the light emitting control module and the second data writing unit are controlled to be turned off, and the first data writing unit is controlled to be turned on to write the predetermined amplitude voltage signal into the first node; after the predetermined amplitude voltage signal is written into the first node, the first data writing unit is controlled to be turned off and the second data writing unit is controlled to be turned on to control the pixel driving circuit to enter the data writing stage, including: When the pixel driving circuit is in a reset phase, controlling the first data writing unit, the second data writing unit and the light emitting control module to be turned off, and controlling the reset module to be turned on, so as to reset the second node for the first time; After resetting the second node for the first time, controlling the second data writing unit, the light emitting control module and the reset module to be turned off, and controlling the first data writing unit to be turned on to write the predetermined amplitude voltage signal into the first node, so as to perform a first virtual writing on the first node; After performing the first virtual writing on the first node, controlling the first data writing unit, the second data writing unit and the light emitting control module to be turned off, and controlling the reset module to be turned on, so as to perform a second reset on the second node; After resetting the second node for the second time, controlling the second data writing unit, the light emitting control module and the reset module to be turned off, and controlling the first data writing unit to be turned on to write the predetermined amplitude voltage signal to the first node again, so as to perform a second virtual writing on the first node; After performing the second virtual writing on the first node, the pixel driving circuit is controlled to enter the data writing phase.

15. A display panel, characterized in that: include: A pixel driving circuit as claimed in any one of claims 1 to 12.

Images