Memory device and memory system including the same

Abstract

A memory device includes: a first core die and a second core die including a plurality of memory cells and stacked in a first direction; and a buffer die stacked with the first core die and the second core die in a first direction and including a first physical layer and a second physical layer, in which the buffer die is configured to output data of the plurality of memory cells through the first physical layer, data of the plurality of memory cells is provided from the first core die and the second core die through a through hole passing through the first core die and the second core die in a first direction, and wherein the second physical layer is separated from the first physical layer and is configured to receive a power signal from the outside.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0134570 filed on October 10, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a memory device and a memory system including the same. Background Art

[0004] As semiconductor processes increase and chip sizes decrease, power input / output performance characteristics may deteriorate due to poor thermal management performance.

[0005] Likewise, with the emphasis on data-centric computing, large-capacity memories are required; however, since there are physical limitations in integrating large-capacity memories in a single chip, methods of coupling multiple memory chips by using a chiplet structure or the like are being developed.

[0006] Additionally, coupling logic chips and memory chips together may present difficulties because the interface between chiplets is different than the interface primarily used between memory chips. Summary of the invention

[0007] According to an embodiment conceived in the present invention, a memory device includes: a first core die and a second core die, including a plurality of memory cells and stacked along a first direction; and a buffer die, stacked with the first core die and the second core die along the first direction, and including a first physical layer and a second physical layer, wherein the buffer die is configured to output data of the plurality of memory cells through the first physical layer, wherein the data of the plurality of memory cells are provided from the first core die and the second core die through through holes passing through the first core die and the second core die along the first direction, and wherein the second physical layer is separated from the first physical layer and configured to receive a power signal from the outside.

[0008] According to an embodiment conceived in the present invention, a storage system includes: a host device configured to output a data signal; an intermediate layer coupled to the host device and including a signal line in which the data signal is transmitted; and a storage device including a first physical layer and a second physical layer, wherein the first physical layer is configured to receive the data signal through the signal line and the intermediate layer, and the second physical layer is different from the first physical layer and is configured to receive a power signal from the intermediate layer.

[0009] According to an embodiment conceived in the present invention, a storage system includes: a storage device, including a first physical layer and a second physical layer, wherein the first physical layer is configured to output a data signal and is a UCIe physical layer, and the second physical layer is separated from the first physical layer and configured to receive a power signal; and a host device, including a third physical layer and a fourth physical layer, wherein the third physical layer is configured to receive the data signal output through the first physical layer, and the fourth physical layer is separated from the third physical layer and configured to provide the power signal to the storage device through the second physical layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram illustrating a configuration of a memory system according to an embodiment of the inventive concept.

[0011] Figure 2 is a view illustrating a memory system according to an embodiment of the inventive concept.

[0012] Figure 3 is a view illustrating a configuration of a core die structure according to an embodiment of the inventive concept.

[0013] Figure 4 is a view illustrating a lower surface of a buffer die according to an embodiment of the inventive concept.

[0014] Figure 5 is a block diagram illustrating a configuration of a memory device according to an embodiment of the inventive concept.

[0015] Figure 6 and Figure 7 2 is a view illustrating an operation of a memory device according to an embodiment of the inventive concept.

[0016] Figure 8 2 is a view illustrating an operation of a memory device according to an embodiment of the inventive concept.

[0017] Fig. 9 and Fig.10 is a view illustrating a memory system according to an embodiment of the inventive concept.

[0018] Fig.11 is a view illustrating a memory system according to an embodiment of the inventive concept.

[0019] Fig.12 is a view illustrating a memory system according to an embodiment of the inventive concept.

[0020] Fig.13 is a perspective view illustrating a configuration of a system device employing a memory system according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0021] Embodiments of the inventive concept will be described more fully below with reference to the accompanying drawings. As those skilled in the art will appreciate, the described embodiments can be modified in various different ways, all without departing from the spirit and scope of the inventive concept.

[0022] The drawings and descriptions should be considered illustrative in nature, rather than restrictive. Throughout the specification and drawings, the same reference numerals denote the same elements, and thus, their descriptions may be omitted.

[0023] In the drawings, various thicknesses, lengths and angles are shown, and while the arrangements shown do represent embodiments of the inventive concept, it should be understood that modifications of various thicknesses, lengths and angles are possible within the spirit and scope of the inventive concept, and the inventive concept is not necessarily limited to the specific thicknesses, lengths and angles shown.

[0024] Figure 1 is a view illustrating a configuration of a memory system according to an embodiment of the inventive concept.

[0025] Reference Figure 1 , the storage system 1 may include a storage device 10 and a host device 20. The storage device 10 and the host device 20 may be coupled to each other through a plurality of physical layers PHY1 to PHY4, so that the storage device 10 and the host device 20 can communicate with each other. For example, the host device 20 may provide a clock signal CLK, a command CMD, an address ADDR, a data signal DQ, and a power signal PWR to the storage device 10 through a plurality of physical layers PHY1 to PHY4.

[0026] The memory device 10 may be a high bandwidth memory (HBM) device including a plurality of memory channels MCHa to MCHh (see Figure 3 ); however, the memory device is not limited thereto and may be a dynamic random access memory DRAM, such as a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate (LPDDR) SDRAM, a graphic double data rate (GDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), etc. The plurality of memory channels MCHa to MCHh may include Figure 5 A memory cell array comprising a plurality of memory cells.

[0027] The memory device 10 may include a first physical layer PHY1 and a second physical layer PHY2. The first physical layer PHY1 and the second physical layer PHY2 may be different types from each other and may be separately provided in the memory device 10.

[0028] The memory device 10 may receive a clock signal CLK, a command CMD, and an address ADDR through the first physical layer PHY1, and may send and receive a data signal DQ through the first physical layer PHY1. In an embodiment of the inventive concept, the first physical layer PHY1 may be a component of an interface for die-to-die communication, and may be a physical layer (hereinafter, referred to as PHY) as the lowest physical layer. In an embodiment of the inventive concept, the first physical layer PHY1 may be a physical layer of a high-speed serial interface.

[0029] In an embodiment of the present inventive concept, the first physical layer PHY1 can physically couple the system to send data, perform conversion and control of electrical signals, synchronize with clock signals, link training, etc., and control components related to the sideband for receiving clock signals, etc.

[0030] In an embodiment of the inventive concept, the memory device 10 may receive a clock signal CLK, a command CMD, and an address ADDR from an interposer through a first physical layer PHY1 and a signal line SL, and may transmit and receive a data signal DQ to and from the interposer through the first physical layer PHY1.

[0031] In an embodiment of the inventive concept, the first physical layer PHY1 may be a UCIe PHY based on Universal Chiplet Interconnect Express (UCIe) which is an open standard. In addition, the first physical layer PHY1 may comply with electrical signal standards, the number of physical channels, and bump pitch requirements proposed in UCIe.

[0032] For example, when the first physical layer PHY1 is a UCIe PHY and operates at a standard package level, the first physical layer PHY1 may be designed with specifications such as a data signal rate of about 4GT / s to about 32GT / s, 16 physical channels, a bump pitch of about 100μm to about 130μm, a channel reach of about 25mm or less, etc. In addition, for example, when the first physical layer PHY1 is a UCIe PHY and operates at an advanced package level, the first physical layer PHY1 may be designed with specifications such as a data signal rate of about 4GT / s to about 32GT / s, 64 physical channels, a bump pitch of about 25μm to about 55μm, a channel reach of about 2mm or less, etc.

[0033] In an embodiment of the inventive concept, the first physical layer PHY1 may include a serializer / deserializer (SER / DES) 295S. The first physical layer PHY1 may perform read and write operations based on the number of data terminals disclosed in the memory device 10 through the serializer / deserializer 295S while complying with UCIe as an open standard. The memory device 10 may perform serialization and deserialization according to a write operation and a read operation.

[0034] In an embodiment of the inventive concept, in terms of interoperability of the first physical layer PHY1, a voltage swing of a data signal DQ input to the first physical layer PHY1 may be approximately 0.8 V or less, for example, 0.7 V or less. For example, when 0 V is applied to the first physical layer PHY1 as a ground voltage, a maximum voltage of the data signal DQ applied to the first physical layer PHY1 may be approximately 0.8 V.

[0035] Furthermore, in an embodiment of the inventive concept, the first physical layer PHY1 may perform a training operation on a reference voltage. Based on the trained reference voltage, a data signal DQ input to the first physical layer PHY1 may be received as data.

[0036] Due to the above-mentioned specifications of the first physical layer PHY1 , the first physical layer PHY1 may operate at a low voltage and low power with high power efficiency.

[0037] In an embodiment of the inventive concept, when the first physical layer PHY1 is a UCIe PHY, the memory device 10 and the host device 20 may support protocols including: a peripheral component interconnect express (hereinafter, referred to as PCIe) protocol, a compute express link (hereinafter, referred to as CXL) protocol, a stream protocol, etc., but the inventive concept is not limited thereto. The CXL protocol may include CXL.ip, CXL.mem, CXL.cache, etc., but is not limited thereto.

[0038] The memory device 10 may receive a power signal PWR through a second physical layer PHY2. In an embodiment of the present invention, the second physical layer PHY2 may be a component of an interface for die-to-die communication, and may be a physical layer (hereinafter referred to as PHY) as the lowest physical layer. In an embodiment of the present invention, the memory device 10 may receive a power signal PWR from an interposer through a second physical layer PHY2. In an embodiment of the present invention, the memory device 10 may receive a power supply voltage, a drive voltage, a word line boost voltage, and a ground voltage of the memory device 10 through a power signal PWR without arranging a separate charge pump.

[0039] In an embodiment of the present inventive concept, the second physical layer PHY2 may be one of high bandwidth memory (HBM) 2E / 2PHY and HBM3 PHY compliant with JEDEC HBM, or may be one of high bandwidth interconnect (hereinafter referred to as HBI) (HBI) PHY, DDR5 / 4PHY, and ultra short reach / extra short reach (USR / XSR) PHY, but the present inventive concept is not limited thereto.

[0040] The host device 20 may include a third physical layer PHY3, a fourth physical layer PHY4, a memory controller 20MC, and a power management integrated circuit 20PM. In the host device 20, the third physical layer PHY3 and the fourth physical layer PHY4 may be different types from each other and may be separately provided in the host device 20.

[0041] The host device 20 may be in the form of a separate logic chip or a plurality of chiplets. In an embodiment of the inventive concept, the host device 20 may be a system on chip (SoC), a graphics processing unit (GPU) die, a central processing unit (CPU) die, etc. In an embodiment of the inventive concept, the host device 20 may include a memory controller 20MC.

[0042] The memory controller 20MC may provide various signals to the memory device 10 through the third physical layer PHY3 and the fourth physical layer PHY4 , thereby controlling memory operations (such as a write operation, a read operation, etc.).

[0043] The third physical layer PHY3 may correspond to the first physical layer PHY1, and the memory controller 20MC may send a clock signal CLK, a command CMD, and an address ADDR to the memory device 10 through the third physical layer PHY3 and the signal line SL, and may send a data signal DQ to the memory device 10 and receive the data signal DQ from the memory device 10 through the third physical layer PHY3 and the signal line SL.

[0044] In an embodiment of the inventive concept, the third physical layer PHY3 may be a UCIe PHY. The third physical layer PHY3 may comply with requirements set forth in UCIe as an open standard. The set forth requirements may be requirements described in association with the first physical layer PHY1 as an example.

[0045] The fourth physical layer PHY4 may correspond to the second physical layer PHY2 , and the host device 20 may provide the memory device 10 with a power signal PWR generated by the power management integrated circuit 20PM through the fourth physical layer PHY4 and the power line PL.

[0046] In an embodiment of the inventive concept, the fourth physical layer PHY4 may be one of HBM 2E / 2PHY and HBM3 PHY conforming to JEDEC HBM, or may be one of HBIPHY, DDR5 / 4PHY, and USR / XSR PHY, but the inventive concept is not limited thereto.

[0047] The power management integrated circuit 20PM may provide a driving voltage to various components of the memory system 1 including the host device 20 , or may perform power management on the components.

[0048] For example, the power management integrated circuit 20PM may provide a driving voltage (eg, Figure 5 The driving voltage VDD and Figure 5 The power management integrated circuit 20PM can adjust the driving voltage of the host device 20 as needed. For example, when it is necessary to ensure the duration of the host device 20, the power management integrated circuit 20PM can reduce the driving voltage of the host device 20, or can stop providing the driving voltage to save power. In addition, when it is necessary to ensure the performance of the host device 20, the power management integrated circuit 20PM can increase the driving voltage of the host device 20.

[0049] Figure 2 is a view illustrating a memory system according to an embodiment of the inventive concept. Figure 3 is a view illustrating a configuration of a core die structure according to an embodiment of the inventive concept. Figure 4 is a view illustrating a lower surface of a buffer die according to an embodiment of the inventive concept.

[0050] Reference Figures 1 to 4 , a memory system 1 a may include a memory device 10 a , a host device 20 a , an interposer 30 , and a printed circuit board (PCB) 40 .

[0051] The memory device 10a and the host device 20a may be disposed and mounted on the interposer 30 . The memory device 10a and the host device 20a may be disposed not to overlap each other in the third direction Z. For example, the memory device 10a and the host device 20a may be disposed side by side on the interposer 30 .

[0052] The memory device 10a may include a memory die 100 including four core dies 100_1 to 100_4 stacked on each other along a third direction Z, and a buffer die 200. A plurality of first bumps MB may be formed between every two dies of the stacked core dies 100_1 to 100_4 and between the dies of the stacked core dies 100_1 to 100_4 and the buffer die 200, and between the plurality of stacked first bumps MB, through silicon vias (TSVs) may be formed to pass through the core dies 100_1 to 100_4.

[0053] In an embodiment of the inventive concept, the memory device 10a may include five or more core dies that are stacked. In an embodiment of the inventive concept, the buffer die 200 may be stacked above the stacked core dies 100_1 to 100_4 instead of below the stacked core dies 100_1 to 100_4.

[0054] Figure 3 is a diagram showing a configuration of four stacked core dies 100_1 to 100_4 according to an embodiment conceived in the present invention, and the stacked core dies 100_1 to 100_4 may respectively include two memory channels MCHa and MCHc, two memory channels MCHb and MCHd, two memory channels MCHe and MCHg, and two memory channels MCHf and MCHh, and each of the memory channels MCHa to MCHh may include a predetermined number of memory bodies.

[0055] Memory channels MCHa, MCHb, MCHe, and MCHf may be respectively disposed on the left side of the core dies 100_1 to 100_4 in the XY plane, and memory channels MCHc, MCHd, MCHg, and MCHh may be respectively disposed on the right side of the core dies 100_1 to 100_4 in the XY plane. Each of the memory channels MCHa, MCHb, MCHe, and MCHf is individually disposed in the corresponding core die of the core dies 100_1 to 100_4 along the Z direction. Each of the memory channels MCHc, MCHd, MCHg, and MCHh is individually disposed in the corresponding core die of the core dies 100_1 to 100_4 along the Z direction.

[0056] Between each of the memory channels MCHa, MCHb, MCHe and MCHf, corresponding data terminals DQ1a to DQ4a, DQ1b to DQ4b, DQ1e to DQ4e or DQ4f to DQ4f, corresponding command and address terminals CATa, CATb, CATe or CATf, and corresponding power terminals PTa, PTb, PTe or PTf may be included, and between each of the memory channels MCHc, MCHd, MCHg and MCHh, corresponding data terminals DQ1c to DQ4c, DQ1d to DQ4d, DQ1g to DQ4g or DQ1h to DQ4h, corresponding command and address terminals CATc, CATd, CATg or CATh, and corresponding power terminals PTc, PTd, PTg or PTh may be included. Through the data terminals DQ1a, DQ1b, DQ1e and DQ1f, the first data group DG1 can be transmitted, and through the data terminals DQ2a, DQ2b, DQ2e and DQ2f, the second data group DG2 can be transmitted. In this way, through the other data terminals (DQ3a to DQ4h), the third data group DG3 to the eighth data group DG8 can be transmitted.

[0057] A first command and address group CAG1 may be transmitted through the command and address terminals CATa, CATb, CATe, and CATf, and a second command and address group CAG2 may be transmitted through the command and address terminals CATc, CATd, CATg, and CATh. A power signal PWR may be transmitted through the power terminals PTa to PTh.

[0058] The corresponding data terminals DQ1a to DQ4a, DQ1b to DQ4b, DQ1c to DQ4c, DQ1d to DQ4d, DQ1e to DQ4e, DQ1f to DQ4f, DQ1g to DQ4g and DQ1h to DQ4h, and the corresponding command and address terminals CATa to CATh may be coupled to the first physical layer PHY1. The power terminals PTa to PTh may be coupled to the second physical layer PHY2.

[0059] exist Figure 3 In the embodiment, the data terminals DQ1a to DQ4a, DQ1b to DQ4b, DQ1c to DQ4c, DQ1d to DQ4d, DQ1e to DQ4e, DQ1f to DQ4f, DQ1g to DQ4g and DQ1h to DQ4h, the command address terminals CATa to CATh, and the power terminals PTa to PTh may be respectively Figure 2In addition, the lines vertically passing through the data terminals DQ1a to DQ4a, DQ1b to DQ4b, DQ1c to DQ4c, DQ1d to DQ4d, DQ1e to DQ4e, DQ1f to DQ4f, DQ1g to DQ4g and DQ1h to DQ4h, the command and address terminals CATa to CATh, and the power terminals PTa to PTh may be through silicon vias (TSVs).

[0060] If it is assumed that n-bit data is input and output through each of the data terminals DQ1a to DQ4a, ..., DQ1h to DQ4h, 32n-bit data can be input and output through all the data terminals. If it is assumed that k-bit commands and addresses are input and output through each of the command and address terminals CATa to CATh, 8k-bit commands and addresses can be input and output through all the command and address terminals.

[0061] like Figure 3 As shown, the vertical penetrating lines of the second data group DG2 to the eighth data group DG8 can be configured like the lines corresponding to the first data group DG1, and the vertical penetrating lines of the second command and address group CAG2 can be configured like the lines corresponding to the first command and address group CAG1.

[0062] Figure 2 and Figure 3 Each of the core dies 100_1 to 100_4 shown in FIG. 1 may receive a driving voltage and a boosting voltage for a plurality of memory cells in a memory cell array through a power terminal. In response to commands and addresses applied through command and address terminals CATa to CATh, each of the core die 100_1 to 100_4 may store data input through data terminals DQ1a to DQ4a, DQ1b to DQ4b, DQ1c to DQ4c, DQ1d to DQ4d, DQ1e to DQ4e, DQ1f to DQ4f, DQ1g to DQ4g, and DQ1h to DQ4h in a memory cell selected from a plurality of memory cells in a memory cell array, or output data stored in the selected memory cell through data terminals DQ1a to DQ4a, DQ1b to DQ4b, DQ1c to DQ4c, DQ1d to DQ4d, DQ1e to DQ4e, DQ1f to DQ4f, DQ1g to DQ4g, and DQ1h to DQ4h.

[0063] Refer again Figure 2 and Figure 4 , a plurality of first direct access bumps dab, a plurality of first power bumps pb1, a plurality of first command and address bumps cab1, and a plurality of first data bumps db1 may be disposed in the third direction Z on the lower surface of the buffer die 200.

[0064] In addition, the buffer die 200 may include a first physical layer PHY1 and a second physical layer PHY2. The first physical layer PHY1 may be coupled to a plurality of first data bumps db1 and a plurality of first command and address bumps cab1, and may transmit and receive a data signal DQ. The second physical layer PHY2 may be coupled to a plurality of first power bumps pb1, and may receive a power signal PWR from the host device 20a.

[0065] The first physical layer PHY1 may be coupled to some of a plurality of through silicon vias (TSVs) disposed on the upper surface of the buffer die 200 to transmit and receive data of the memory die 100. The second physical layer PHY2 may be coupled to some of the plurality of through silicon vias (TSVs) to provide a power signal PWR to the memory die 100.

[0066] The first physical layer PHY1 may be disposed to overlap at least some of the plurality of first command and address bumps cab1 and the plurality of first data bumps db1 in the third direction Z. The second physical layer PHY2 may be disposed to overlap at least some of the plurality of first power bumps pb1 in the third direction Z.

[0067] In an embodiment of the present invention, the TSV region RTSV may be at least a partial region associated with the upper surface of the buffer die 200 and in which a through silicon via (TSV) is disposed. The TSV region RTSV may be arranged to overlap at least some of the plurality of first command and address bumps cabl and the plurality of first power bumps pb1 in a third direction Z. In an embodiment of the present invention, the TSV region RTSV may be arranged to overlap some of the plurality of first data bumps db1 in a plane in the third direction Z. In addition, the TSV region RTSV may be arranged to overlap a portion of the first physical layer PHY1 and a portion of the second physical layer PHY2 in the third direction Z. In an embodiment of the present invention, the TSV region RTSV may be arranged between the first physical layer PHY1 and the second physical layer PHY2 in the XY plane.

[0068] A plurality of second command and address bumps cab2, a plurality of second data bumps db2, a plurality of second power bumps pb2, and a plurality of first control signal bumps cdb may be disposed on the lower surface of the host device 20a. The host device 20a may include a third physical layer PHY3 and a fourth physical layer PHY4. The third physical layer PHY3 may be coupled to the plurality of second data bumps db2 and the plurality of second command and address bumps cab2, and may transmit and receive data signals DQ. The fourth physical layer PHY4 may be coupled to the plurality of second power bumps pb2, and may provide a power signal PWR to the memory device 10a.

[0069] The plurality of first bumps MB, the plurality of first direct access bumps dab, the plurality of first and second power bumps pb1 and pb2, the plurality of first and second command and address bumps cabl and cab2, the plurality of first and second data bumps db1 and db2, and the plurality of first control signal bumps cdb may be micro bumps.

[0070] In an embodiment of the inventive concept, the interposer 30 may include a silicon interposer, an organic interposer, etc., but is not limited thereto. In an embodiment of the inventive concept, instead of disposing the interposer 30 on the PCB 40, an embedded multi-die interconnect bridge (EMIB) may be disposed inside the PCB 40. By disposing the interposer 30 or the EMIB, the memory system 1 may operate at an advanced packaging level.

[0071] A plurality of second direct access bumps DAFB, a plurality of third power bumps PBFB, and a plurality of second control signal bumps CDFB may be disposed on a lower surface of the interposer 30. The interposer 30 may be disposed between the PCB 40 and the memory device 10a and between the host device 20a and the PCB 40. In an embodiment of the inventive concept, the interposer may include a conductive redistribution line, a through silicon via as a vertical structure, and the like.

[0072] In an embodiment of the present invention, the interposer 30 may include a direct line, a signal line SL, a power line PL, and a plurality of control signal lines. The direct line couples a plurality of first direct access bumps dab with a plurality of second direct access bumps DAFB to each other. The signal line SL couples a plurality of first command and address bumps ca1 with a plurality of second command and address bumps cab2 to each other, and couples a plurality of first data bumps db1 with a plurality of second data bumps db2 to each other. The power line PL couples a plurality of first power bumps pb1 with a plurality of second power bumps pb2 to each other. A plurality of control signal lines couple a plurality of first control signal bumps cdb with a plurality of second control signal bumps CDFB to each other. In addition, the interposer 30 may include a power line that couples a plurality of third power bumps PBFB with a plurality of second power bumps pb2 of the host device 20a.

[0073] A plurality of direct access balls DAB, a plurality of power balls PB, and a plurality of control signal balls CDB may be disposed on a lower surface of the PCB 40 .

[0074] The plurality of second direct access bumps DAFB and the plurality of direct access balls DAB may be coupled to each other, and the plurality of third power bumps PBFB and the plurality of power balls PB may be coupled to each other through the PCB 40. In addition, the plurality of second control signal bumps CDFB and the plurality of control signal balls CDB may be coupled to each other through the PCB 40.

[0075] In some embodiments of the inventive concept, when the memory device 10a and the host device 20a are disposed on the PCB 40 without the interposer 30 and are coupled to each other through the PCB 40, the memory system 1 may operate at a standard packaging level.

[0076] Figure 5 is a block diagram illustrating a configuration of a memory device according to an embodiment of the inventive concept.

[0077] Reference Figures 1 to 5 , the memory device 10a may include a memory cell array 110, a row decoder 120, a sense amplifier 170, a control logic circuit 210, an address register 220, a memory body control logic 230, a refresh control circuit 245, a column address latch 250, a row address multiplexer 260, a column decoder 270, an I / O selection circuit 290, a data I / O buffer 295 and a voltage divider circuit 296.

[0078] The memory cell array 110 may include a predetermined number of memory banks included in the memory channels MCHa to MCHh. In addition, in an embodiment of the inventive concept, the sense amplifier 170, the row decoder 120, and the column decoder 270 may include a plurality of memory bank sense amplifiers, a plurality of memory bank row decoders, and a plurality of memory bank column decoders coupled to separate memory banks, respectively, but the inventive concept is not limited thereto.

[0079] The memory cell array 110 may include a plurality of word lines WL, a plurality of bit lines BTL, and a plurality of memory cells MC located at intersections between the word lines WL and the bit lines BTL.

[0080] The row decoder 120 may be coupled to a plurality of word lines WL and may apply a boost voltage VPP to a word line corresponding to a target memory cell during a write operation and a read operation. For example, a word line receiving the boost voltage VPP may be activated and a memory cell coupled to the activated word line may be turned on.

[0081] In an embodiment of the present inventive concept, the row decoder 120 may receive the first power signal PWR1 through the second physical layer PHY2 and the through silicon via (TSV), and apply the boost voltage VPP to the word line through the first power signal PWR1. In an embodiment of the present inventive concept, the boost voltage VPP may be in the range of about 1.5V to about 3.0V, for example, in the range of about 1.6V to about 2.6V, and for example, in the range of about 1.7V to about 1.9V.

[0082] The sense amplifier 170 may include bit line sense amplifiers coupled to the plurality of bit lines BTL, and during write and read operations, the bit line sense amplifiers corresponding to the memory cells may receive the driving voltage VDD and perform write and read operations on the memory cells.

[0083] In an embodiment of the present inventive concept, a bit line sense amplifier in the sense amplifier 170 may receive a second power signal PWR2 through a second physical layer PHY2 and a through silicon via (TSV), and may receive a driving voltage VDD for a write operation and a read operation through the second power signal PWR2. In an embodiment of the present inventive concept, the driving voltage VDD may be in a range of about 1.0 V to about 1.4 V, and, for example, in a range of about 1.1 V to about 1.2 V.

[0084] The control logic circuit 210 may control the operation of the memory device 10a. For example, the control logic circuit 210 may generate a control signal CTL so that the memory device 10a performs a read operation or a write operation. The control logic circuit 210 may include a command decoder 211 for decoding a command CMD received from the memory controller 20MC, and a mode register 212 for setting an operation mode of the memory device 10a.

[0085] For example, the command decoder 211 may decode a write enable signal, a row address strobe signal, a column address strobe signal, a channel selection signal, etc. to generate a control signal CTL corresponding to the command CMD.

[0086] The mode register 212 may store setting information for setting the operation mode of the memory device 10a. The memory controller 20MC may provide a command for a mode register write operation MRW to store the setting information in the mode register 212. In addition, the memory controller 20MC may provide a command for a mode register read operation MRR to receive the setting information stored in the mode register 212 from the memory device 10a.

[0087] The address register 220 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller 20MC. The address register 220 may provide the received bank address BANK_ADDR to the bank control logic 230 and may provide the received row address ROW_ADDR to the row address multiplexer 260 .

[0088] The bank control logic 230 may generate a bank control signal in response to the bank address BANK_ADDR. In response to the bank control signal, the row decoder 120 and the column decoder 270 may activate the corresponding bank.

[0089] The row address multiplexer 260 may receive the row address ROW_ADDR from the address register 220 and the refresh row address REF_ADDR from the control logic circuit 210. The row address multiplexer 260 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 260 may be applied to the row decoder 120.

[0090] The column address latch 250 may receive the column address COL_ADDR from the address register 220 and temporarily store the received column address COL_ADDR. In addition, the column address latch 250 may gradually increase the received column address COL_ADDR in a burst mode. The column address latch 250 may apply the temporarily stored or gradually increased column address to the column decoder 270.

[0091] With respect to the bank activated by the bank control logic 230 , the column decoder 270 may activate a sense amplifier corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the I / O gating circuit 290 .

[0092] The I / O gating circuit 290 may include input data masking logic, a read data latch for storing data DTA, and a write driver for writing data DTA, and a circuit for gating I / O data.

[0093] In an embodiment of the inventive concept, the I / O gating circuit 290 may receive a third power signal PWR3 through the second physical layer PHY2 and a through silicon via (TSV), and may receive a power voltage VDDQ for transmission, recovery, etc. of data DTA through the third power signal PWR3. In an embodiment of the inventive concept, the power voltage VDDQ may be in a range of about 1.0 V to about 1.4 V, and, for example, in a range of about 1.1 V to about 1.2 V. When the memory device 10 a operates at a low speed, the power voltage VDDQ having a reduced magnitude may be input to the I / O gating circuit 290.

[0094] For example, during a write operation, the I / O strobe circuit 290 may convert a data signal DQ received from the data I / O buffer 295 into data DTA based on the power voltage VDDQ and transmit the data DTA to the sense amplifier 170. Also, during a read operation, the I / O strobe circuit 290 may restore the data DTA received from the sense amplifier 170 based on the power voltage VDDQ and transmit the data DTA to the data I / O buffer 295.

[0095] Additionally, to support a burst mode of a burst length BL indicating a maximum number of column positions that can access bit lines in the memory device 10 a , bit lines corresponding to the burst length BL can be simultaneously accessed through the I / O gating circuit 290 .

[0096] The data I / O buffer 295 may distinguish between input data signals and output data related to the first physical layer PHY1. In an embodiment of the inventive concept, the data I / O buffer 295 may include some components of the first physical layer PHY1, and may receive a control signal CTL from the control logic circuit 210, and control the operation of the first physical layer PHY1 to perform an input or output operation.

[0097] The data I / O buffer 295 may include a serializer / deserializer 295S. The serializer / deserializer 295S may perform an operation of deserializing the data signal DQ and an operation of serializing the data DTA according to a write operation and a read operation of the memory device 10a. For example, the memory device 10a may perform operations on the memory die 100 through serialization and deserialization operations while complying with the requirements for the number of physical channels proposed in UCIe.

[0098] For example, when the memory device 10a performs a write operation, the serializer / deserializer 295S may perform an operation of deserializing the data signal DQ input to the physical channel of the first physical layer PHY1. In addition, when the memory device 10a performs a read operation, the serializer / deserializer 295S may perform an operation of serializing the data DTA output from the I / O strobe circuit 290 and output the data signal DQ to the physical channel of the first physical layer PHY1.

[0099] In addition, the data I / O buffer 295 can synchronize the data signal DQ input from the memory controller 20MC and the data DTA to be output to the memory controller 20MC with the clock signal. In addition, the data I / O buffer 295 can adjust the voltage level for the data DTA output from the I / O gating circuit 290 based on the I / O voltage VCCIO, and the data I / O buffer 295 can output the data signal DQ. The voltage adjusted for the data signal DQ can comply with the requirements of the standard to which the first physical layer PHY1 complies.

[0100] For example, according to UCIe as an open standard, the voltage swing of the data signal DQ may be about 0.9V or less. In an embodiment, the voltage of the data signal DQ may be in the range of about 0.2V to about 0.6V, and for example, in the range of about 0.3V to about 0.5V.

[0101] The voltage divider circuit 296 may receive the fourth power signal PWR4 through the second physical layer PHY2 and a through silicon via (TSV), and receive the power voltage VDDQ through the fourth power signal PWR4 .

[0102] The voltage divider circuit 296 may perform a voltage division bias operation on the power voltage VDDQ. The voltage divider circuit 296 may provide the data I / O buffer 295 with an I / O voltage VCCIO and an auxiliary voltage VCCAON through the voltage division bias operation on the power voltage VDDQ.

[0103] The voltage divider circuit 296 may provide the data I / O buffer 295 with an I / O voltage VCCIO and an auxiliary voltage VCCAON, which are voltages relatively lower than each of the boosting voltage VPP, the driving voltage VDD, and the power voltage VDDQ.

[0104] In an embodiment of the inventive concept, the voltage divider circuit 296 may perform a voltage division bias operation on the power voltage VDDQ, but the inventive concept is not limited thereto. For example, the voltage divider circuit 296 may perform a voltage division bias operation based on a power signal PWR provided to the second physical layer PHY2.

[0105] The auxiliary voltage VCCAON may be a voltage input to maintain a firmware and clock signal driving the memory device 10a, and may be provided to the data I / O buffer 295. In an embodiment of the inventive concept, the auxiliary voltage VCCAON may be in a range of about 0.45V to about 0.85V, and for example, in a range of about 0.55V to about 0.75V.

[0106] The memory device 10a may receive a ground voltage through the second physical layer PHY2, and the received ground voltage may be applied to components in the memory device 10a. For example, the ground voltage may be 0V, but the inventive concept is not limited thereto.

[0107] The memory device 10a of the present invention can receive the power signal PWR including the first power signal PWR1 to the fourth power signal PWR4 through the second physical layer PHY2 without a separate charge pump. By setting the first physical layer PHY1 and the second physical layer PHY2 in the buffer die 200 instead of a separate charge pump, the interface for the logic chip can be applied to the memory device 10a and the power efficiency and area overhead of the memory device 10a can be increased.

[0108] In an embodiment of the present invention, the memory cell array 110, the row decoder 120 and the sense amplifier 170 may be included in the memory die 100, and the control logic circuit 210, the address register 220, the memory body control logic 230, the refresh control circuit 245, the column address latch 250, the row address multiplexer 260, the column decoder 270, the I / O selection circuit 290, the data I / O buffer 295 and the voltage divider circuit 296 may be included in the buffer die 200.

[0109] Figure 6 and Figure 7 2 is a view illustrating an operation of a memory device according to an embodiment of the inventive concept.

[0110] Figure 6 and Figure 7 is a diagram showing a read operation of the memory device 10a. Figure 1 , Figure 5 , Figure 6 and Figure 7 When the memory device 10a performs a read operation, at time t1, the voltage applied to the word line WL may be increased from the ground voltage Vss to the boost voltage VPP, whereby the word line WL may be activated. For example, the ground voltage Vss may be 0V, and the boost voltage VPP may be approximately 1.8V, but they are not limited thereto.

[0111] Based on the activation of the word line WL, at time t2, the memory die 100 may perform a read operation based on the driving voltage VDD and provide data DTA to the I / O gating circuit 290. The I / O gating circuit 290 may restore the input data DTA based on the power voltage VDDQ and provide the data DTA to the data I / O buffer 295.

[0112] The data DTA may include first data DTA1 to m-th data DTAm, and "m" may be determined by the number of data terminals in the memory die 100 and may be an integer. The first data DTA1 to m-th data DTAm may be output together and may be output by different data terminals. For example, "m" may be equal to 1024, but is not limited thereto. In an embodiment of the inventive concept, a burst length BL of the first data DTA1 to m-th data DTAm may be equal to "N".

[0113] In addition, the voltage of the data DTA may be within a range between the ground voltage Vss and the power voltage / driving voltage (VDDQ, VDD). For example, the ground voltage Vss may be 0V, and the power voltage / driving voltage (VDDQ, VDD) may be approximately 1.1V, but the inventive concept is not limited thereto. The data voltage swing dV1, which is the difference between the maximum voltage value and the minimum voltage value of the data DTA, may be approximately 1.1V, but the inventive concept is not limited thereto.

[0114] At time t3, the data I / O buffer 295 may convert the input data DTA into a data signal DQ based on the I / O voltage VCCIO. The serializer / deserializer 295S may convert the first to mth data DTA1 to DTAm into first to nth data signals DQ1 to DQn while serializing them.

[0115] The data signal DQ may include a first data signal DQ1 to an nth data signal DQn, and "n" may be determined by the number of physical channels of the first physical layer PHY1 and may be an integer. The first data signal DQ1 to the nth data signal DQn may be output together and may be output through different physical channels. For example, "n" may be equal to 64, but the inventive concept is not limited thereto. In an embodiment of the inventive concept, a burst length BL of the first data signal DQ1 to the nth data signal DQn may be equal to "M".

[0116] In an embodiment of the inventive concept, a ratio of the number of data DTAs to the number of data signals DQ may be "m" to "n", and "m" to "n" may be the inverse of "N" to "M", where "N" to "M" is a ratio of a burst length BL of the data DTA to a burst length of the data signal DQ. For example, when the number of data terminals outputting the data DTA is 1024, the data DTA includes first to 1024th data, the number of physical channels outputting the data signal DQ is 64, and the data signal DQ includes first to 64th data signals, the ratio of the burst length BL of the data DTA to the burst length of the data signal DQ may be 1 to 16.

[0117] The voltage of the data signal DQ may be within a range between the first I / O voltage VCCIO1 and the second I / O voltage VCCIO2 based on the I / O voltage VCCIO. For example, the first I / O voltage VCCIO1 may be approximately 0.6V, and the second I / O voltage VCCIO2 may be approximately 0.4V. For example, the data signal voltage swing dV2, which is the difference between the maximum voltage value and the minimum voltage value of the data signal DQ, may be approximately 0.2V. However, the inventive concept is not limited thereto. In an embodiment of the inventive concept, the amplitude of the first I / O voltage VCCIO1 and the second I / O voltage VCCIO2 may be smaller than the amplitude of the provided I / O voltage VCCIO, and may be smaller than the amplitude of the power voltage / drive voltage (VDDQ, VDD) and the boost voltage VPP.

[0118] Figure 8 2 is a view illustrating an operation of a memory device according to an embodiment of the inventive concept. Figure 8 is a diagram showing a write operation of the memory device 10a. Figure 1 , Figure 5 and Figure 8 , when the memory device 10a performs a write operation, the data I / O buffer 295 and the I / O gating circuit 290 may convert the data signal DQ into data DTA based on the power voltage VDDQ.

[0119] The serializer / deserializer 295S of the data I / O buffer 295 may deserialize the first to nth data signals DQ1 to DQn. Also, the data I / O buffer 295 may provide the data signal DQ obtained by the deserialization to the I / O strobe circuit 290.

[0120] The I / O gating circuit 290 may output the data signal DQ obtained by deserialization based on the input power voltage VDDQ as data DTA. The data DTA may include first to mth data DTA1 to DTAm.

[0121] In an embodiment of the inventive concept, a ratio of the number of data signals DQ to the number of data DTA may be "n" to "m", and "n" to "m" may be the inverse of "M" to "N", and "M" to "N" is a ratio of a burst length BL of the data signal DQ to a burst length of the data DTA. For example, when the number of physical channels of the input data signal DQ is 64, the data signal DQ includes the first data signal to the 64th data signal, the number of data terminals of the input data DTA is 1024, and the data DTA includes the first data to the 1024th data, the ratio of the burst length BL of the data signal DQ to the burst length of the data DTA may be 16 to 1.

[0122] Fig. 9 and Fig.10 is a view illustrating a memory system according to an embodiment of the inventive concept. Fig. 9 and Fig.10 The storage system 1b, storage device 10b and host device 20b in the embodiment may correspond to Figures 2 to 8 1 , a storage system 1a, a storage device 10a and a host device 20a.

[0123] Fig. 9 and Fig.10 The storage system 1b in Figures 2 to 8 1a in the present invention, and for ease of description, the differences will be described in detail. The components not described in the present invention may be described by Figures 2 to 8 In other words, redundant descriptions may be omitted hereinafter.

[0124] Reference Figure 1 , Figure 2 , Fig. 9 and Fig.10 , the host device 20b of the storage system 1b may include a first host device 20b1 and a second host device 20b2. In an embodiment of the inventive concept, the first host device 20b1 and the second host device 20b2 may be chiplets in the form of dies separated from each other.

[0125] In an embodiment of the inventive concept, the first host device 20b1 and the second host device 20b2 may be mounted on the interposer 30. In an embodiment of the inventive concept, the first host device 20b1 and the second host device 20b2 may be disposed not to overlap each other in the third direction Z.

[0126] The first host device 20b1 may include a 3_1st physical layer PHY3_1 and a 4_1st physical layer PHY4_1. In an embodiment of the inventive concept, in the first host device 20b1, the 3_1st physical layer PHY3_1 and the 4_1st physical layer PHY4_1 may be different types from each other and separately provided.

[0127] The 3_1st physical layer PHY3_1 may correspond to the first physical layer PHY1. The first host device 20b1 may transmit a clock signal CLK, a command CMD, and an address ADDR to the memory device 10b through the 3_1st physical layer PHY3_1 and a first signal line SL1 as some of the signal lines SL, and may transmit and receive a data signal DQ to and from the memory device 10b.

[0128] In an embodiment of the inventive concept, the 3_1st physical layer PHY3_1 may be a UCIe PHY. The 3_1st physical layer PHY3_1 may comply with requirements set forth in UCIe as an open standard. The set forth requirements may be requirements described in association with the first physical layer PHY1 as an example.

[0129] The 4_1st physical layer PHY4_1 may correspond to the second physical layer PHY2 , and the first host device 20 b 1 may provide the memory device 10 b with a power signal PWR generated by the power management integrated circuit 20PM through the 4_1st physical layer PHY4_1 and the power line PL.

[0130] In an embodiment of the inventive concept, the 4_1 th physical layer PHY4_1 may be one of HBM 2E / 2PHY and HBM3 PHY conforming to JEDEC HBM, or may be one of HBI PHY, DDR5 / 4PHY, and USR / XSR_PHY, but the inventive concept is not limited thereto.

[0131] The second host device 20b2 may include a 3_2nd physical layer PHY3_2 and a 4_2nd physical layer PHY4_2. In an embodiment of the inventive concept, in the second host device 20b2, the 3_2nd physical layer PHY3_2 and the 4_2nd physical layer PHY4_2 may be different types from each other and are separately provided.

[0132] The 3_2nd physical layer PHY3_2 may correspond to the first physical layer PHY1. The second host device 20b2 may transmit a clock signal CLK, a command CMD, and an address ADDR to the memory device 10b through the 3_2nd physical layer PHY3_2 and second signal lines SL2 as some of the signal lines SL, and may transmit and receive a data signal DQ to and from the memory device 10b.

[0133] In an embodiment of the inventive concept, the 3_2nd physical layer PHY3_2 may be a UCIe PHY. The 3_2nd physical layer PHY3_2 may comply with requirements set forth in UCIe as an open standard. The set forth requirements may be requirements described in association with the first physical layer PHY1 as an example.

[0134] The 4_2nd physical layer PHY4_2 may correspond to the second physical layer PHY2, and the second host device 20b2 may provide the power signal PWR generated by the power management integrated circuit 20PM to the memory device 10b through the 4_2nd physical layer PHY4_2 and the power line PL.

[0135] In an embodiment, the 4_2 th physical layer PHY4_2 may be one of HBM 2E / 2 PHY and HBM3 PHY conforming to JEDEC HBM, or may be one of HBI PHY, DDR5 / 4 PHY, and USR / XSR PHY, but the inventive concept is not limited thereto.

[0136] In an embodiment of the inventive concept, the 3_1st physical layer PHY3_1 and the 3_2nd physical layer PHY3_2 may be coupled to each other through a wire CL disposed in the intermediate layer 30, and the first host device 20b1 and the second host device 20b2 may transmit and receive data signals DQ through the 3_1st physical layer PHY3_1 and the 3_2nd physical layer PHY3_2 and the wire CL.

[0137] Fig.11 is a view illustrating a memory system according to an embodiment of the inventive concept. Fig.11 The storage system 1c, storage device 10c and first host device 20c1 in the embodiment may correspond to Figures 2 to 8 1 , a storage system 1a, a storage device 10a and a host device 20a.

[0138] Fig.11 The storage system 1c in Figures 2 to 8 1a in the present invention, and for ease of description, the differences will be described in detail. The components not described in the present invention may be described by Figures 2 to 8 In other words, redundant descriptions may be omitted hereinafter.

[0139] Reference Figure 1 , Figure 2 and Fig.11 , the host device 20c of the storage system 1c may further include a second host device 20c2. In an embodiment of the inventive concept, the first host device 20c1 and the second host device 20c2 may be small chips in the form of dies separated from each other.

[0140] In an embodiment of the inventive concept, the first host device 20c1 may be mounted and disposed on the interposer 30, and the second host device 20c2 may be disposed on the first host device 20c1. In an embodiment of the inventive concept, the first host device 20c1 and the second host device 20c2 may overlap each other in the third direction Z.

[0141] The second host device 20c2 may include a 3_2th physical layer PHY3_2.

[0142] The 3_2nd physical layer PHY3_2 may correspond to the first physical layer PHY1. The second host device 20c2 may be coupled to the first host device 20c1 through the 3_2nd physical layer PHY3_2 and bumps disposed under the second host device 20c2, such as a plurality of third command and address bumps cab3 and a plurality of third data bumps db3.

[0143] The second host device 20c2 may transmit and receive a clock signal CLK, a command CMD, an address ADDR, and a data signal DQ to and from the first host device 20c1, and may receive a power signal PWR.

[0144] In an embodiment of the inventive concept, the 3_2nd physical layer PHY3_2 may be a UCIe PHY. The 3_2nd physical layer PHY3_2 may comply with requirements set forth in UCIe as an open standard. The set forth requirements may be requirements described in association with the first physical layer PHY1 as an example.

[0145] Fig.12 is a view illustrating a memory system according to an embodiment of the inventive concept. Fig.12 The storage system 1d, storage device 10d and host device 20d in the embodiment may correspond to Figures 2 to 8 1 , a storage system 1a, a storage device 10a and a host device 20a.

[0146] Fig.12 The storage system 1d in Figures 2 to 8 1a in the present invention, and for ease of description, the differences will be described in detail. The components not described in the present invention may be described by Figures 2 to 8 In other words, redundant descriptions may be omitted hereinafter.

[0147] Reference Figure 1 , Figure 2 and Fig.12 ,and Figure 2 Compared with the storage system 1a in FIG. 1 , the storage system 1d may further include a co-packaged optical (CPO) device.

[0148] According to an embodiment of the inventive concept, a co-packaged optical (CPO) device may be mounted on the interposer 30 and may be disposed between the memory device 10d and the host device 20d. The co-packaged optical (CPO) device, the memory device 10d, and the host device 20d may be disposed so as not to overlap each other in the third direction Z, but the inventive concept is not limited thereto.

[0149] In an embodiment of the inventive concept, a co-packaged optical (CPO) device and a host device 20d may be coupled via a signal line SL disposed in an interposer 30. The signal line SL may couple a plurality of command and address bumps cabc and a plurality of data bumps dbc disposed on a lower surface of the co-packaged optical (CPO) device in a third direction Z to a plurality of second command and address bumps cab2 and a plurality of second data bumps db2 disposed on a lower surface of the host device 20d, respectively.

[0150] The co-packaged optical (CPO) device and the memory device 10d may be coupled to each other through an optical fiber OF.

[0151] A co-packaged optical (CPO) device may include a photoelectric conversion element and an electro-optical conversion element. The photoelectric conversion element may be a photodiode element, and the electro-optical conversion element may be a laser diode element, but the inventive concept is not limited thereto.

[0152] In an embodiment of the inventive concept, a co-packaged optical (CPO) device may convert an electrical input signal into an optical signal and transmit the optical signal to an optical fiber OF. In addition, a co-packaged optical (CPO) device may convert an optical signal input through an optical fiber OF into an electrical signal.

[0153] In an embodiment of the inventive concept, the first physical layer PHY1d of the buffer die 200' may include an optical connector CONNECTOR, and the optical connector CONNECTOR may be coupled to the optical fiber OF. The optical connector CONNECTOR may include a photoelectric conversion element and an electro-optical conversion element, and may receive an optical signal input from the optical fiber OF and convert it into an electrical signal. In addition, the optical connector CONNECTOR may be used as an optical driver to convert the electrical signal of the storage device 10d into an optical signal, and provide the optical signal to the optical fiber OF.

[0154] Fig.13 is a perspective view illustrating a configuration of a system device employing a memory system according to an embodiment of the inventive concept.

[0155] Reference Fig.13 The system device 1000 may be a memory module including at least one memory device 1010 and a system on chip (SOC) 1020 mounted on a package substrate 1040 such as a printed circuit board as a semiconductor package. An interposer 1030 may be optionally provided on the package substrate 1040.

[0156] The memory device 1010 may be formed in the form of a chip on chip (CoC). The memory device 1010 may include a memory die 1100 including at least one core die stacked on a buffer die 1200. The memory die 1100 and the buffer die 1200 may be coupled to each other through a through silicon via (TSV).

[0157] The buffer die 1200 may include a first physical layer that converts a data signal input to the memory chip 1100 into data and exchanges the data signal with the system on chip 1020 , and a second physical layer that receives a power signal for driving the memory device 1010 .

[0158] According to an embodiment of the inventive concept, the first physical layer and the second physical layer may be of different types from each other and may be separately set. The buffer die 1200 may include the first physical layer and the second physical layer, which can receive power for driving the memory device 1010 while performing communication with the on-chip system 1020 without a separate charge pump.

[0159] The buffer die 1200 may control the operation of the first physical layer and the second physical layer, thereby performing serialization and deserialization operations on a data signal input or to be output to the on-chip system 1020. The buffer die 1200 may include the first physical layer and the second physical layer, and may apply reference to the first physical layer and the second physical layer. Figures 1 to 12 Described embodiments.

[0160] The memory device 1010 may be a high bandwidth memory (HBM), for example, about 500 GB / sec to about 1 TB / sec or more.

[0161] While the inventive concept has been shown and described with reference to embodiments thereof, it will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept.

Claims

1. A storage device, comprising: A first core die and a second core die including a plurality of memory cells and stacked along a first direction; as well as A buffer die is stacked with the first core die and the second core die along the first direction and includes a first physical layer and a second physical layer, wherein the buffer die is configured to output data of the multiple storage cells through the first physical layer, wherein the data of the multiple storage cells are provided from the first core die and the second core die through through holes passing through the first core die and the second core die along the first direction, and wherein the second physical layer is separated from the first physical layer and the second physical layer is configured to receive a power signal from the outside.

2. The memory device according to claim 1, wherein: The first physical layer is a Universal Chiplet Interconnect Express (UCIe) physical layer.

3. The memory device according to claim 2, wherein: The buffer die is disposed on an interposer, and The first physical layer is configured to output a data signal to the interposer based on data of the plurality of memory cells.

4. The memory device according to claim 1, wherein: The buffer die further includes a data input / output I / O buffer configured to output a data signal based on the data of the plurality of memory cells, and The data I / O buffer is configured to output the data signal based on an I / O voltage obtained by dividing a power voltage received from the second physical layer.

5. The memory device according to claim 4, wherein: The buffer die is configured to output the data signal generated based on the I / O voltage through the first physical layer.

6. The memory device according to claim 5, wherein: The same ground voltage is applied to the buffer die and the first core die and the second core die, The I / O voltage range is 0.2V to 0.6V, and The driving voltage of the first core die and the second core die ranges from 1.0V to 1.4V.

7. The memory device according to claim 6, wherein: The buffer die also includes a voltage divider circuit configured to generate the I / O voltage by dividing the power voltage.

8. The memory device according to claim 1, wherein: The second physical layer is one of a high bandwidth memory HBM 2E / 2 physical layer or an HBM 3 physical layer.

9. The memory device according to claim 8, wherein: The buffer die also includes an I / O gating circuit configured to latch data of the plurality of memory cells, and The I / O gating circuit is configured to receive a power voltage through the second physical layer.

10. The memory device according to claim 1, wherein: The first core die and the second core die include a row decoder configured to drive a word line coupled to the plurality of memory cells, and The row decoder is configured to receive a boosted voltage through the second physical layer.

11. The memory device according to claim 10, wherein: The second physical layer is coupled to the via, and The row decoder is configured to receive the boosted voltage through the second physical layer and the via.

12. The memory device according to claim 1, wherein: The upper surface of the buffer die includes a TSV region, wherein the through-hole is disposed on the TSV region, and The TSV region is disposed between the first physical layer and the second physical layer.

13. The memory device according to claim 1, wherein: The first physical layer includes an optical connector, and The data of the plurality of storage units are output in the form of optical signals through the optical fiber coupled to the optical connector.

14. A storage system comprising: a host device configured to output a data signal; an interposer coupled to the host device and comprising a signal line in which the data signal is transmitted; as well as A memory device includes a first physical layer and a second physical layer, wherein the first physical layer is configured to receive the data signal through the signal line and the interposer, and the second physical layer is different from the first physical layer and is configured to receive a power signal from the interposer.

15. The storage system according to claim 14, wherein: The host device includes a first host device and a second host device separated from each other, The first host device is configured to output the data signal and includes a third physical layer, the third physical layer is a Universal Chiplet Interconnect Express (UCIe) physical layer, and The second host device is configured to output the data signal and includes a fourth physical layer, the fourth physical layer being a UCIe physical layer.

16. The storage system according to claim 15, wherein: The first physical layer is a UCIe physical layer, and The third physical layer and the fourth physical layer are each configured to output the data signal to the first physical layer through the intermediate layer.

17. The storage system according to claim 16, wherein: The first host device and the second host device do not vertically overlap each other on the interposer.

18. The storage system according to claim 15, wherein: The first host device and the second host device vertically overlap each other.

19. The storage system according to claim 18, wherein: The second host device is arranged on the first host device, The second host device is configured to send the data signal to the first host device based on UCIe, and The first host device is configured to send the data signal to the memory device based on the UCIe.

20. A storage system comprising: A memory device comprising a first physical layer and a second physical layer, wherein the first physical layer is configured to output a data signal and is a UCIe physical layer, and the second physical layer is separated from the first physical layer and configured to receive a power signal; and A host device includes a third physical layer and a fourth physical layer, wherein the third physical layer is configured to receive the data signal output through the first physical layer, and the fourth physical layer is separated from the third physical layer and configured to provide the power signal to the storage device through the second physical layer.

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