DRAM Read / Write Timing Adjustment Circuit and DRAM

Abstract

The DRAM read / write timing adjustment circuit and DRAM provided by the embodiments of the present disclosure include: a test mode control signal generation module, a delay module, and an adjustment module; the test mode control signal generation module obtains a test coding signal corresponding to a control signal, and when the coding value of the target coding bit of the test coding signal is a preset coding value, generates a test mode control signal corresponding to the control signal according to the test coding signal, where the control signal is a control signal in the DRAM that causes an error in the read / write timing; the delay module receives the control signal and generates a delayed control signal after delaying the control signal by a preset duration; the adjustment module generates a target control signal according to the test mode control signal, the control signal, and the delayed control signal, and the pulse width of the target control signal is greater than or less than the pulse width of the control signal. This enables the timing of the DRAM read / write process to meet the specified timing and avoids errors in the read / write data of the storage unit.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of memory technologies and related technologies. Specifically, it relates to a DRAM read / write timing adjustment circuit and a DRAM suitable for the same. Background Art

[0002] A DRAM (Dynamic Random Access Memory) is an internal memory that includes one or more memory arrays. Each memory array is composed of M×N memory cells. Each memory cell is located at the intersection of a WL (Word Line) and a BL (Bit Line) and is used to store data. As the size of DRAM chips is further reduced, the failure ratio caused by the read / write of memory cells gradually increases, thereby affecting the yield of DRAM memory chips.

[0003] When the timing during the read / write process of the DRAM does not meet the regulations, the read / write data of the memory cells may be incorrect. These failed memory cells may cause the chip to fail, thereby reducing the chip yield. Summary of the Invention

[0004] Embodiments described herein provide a DRAM read / write timing adjustment circuit and a DRAM, such that the timing during the DRAM read / write process meets the specified timing, avoiding incorrect read / write data of memory cells.

[0005] In a first aspect, according to the content of the present disclosure, a DRAM read / write timing adjustment circuit is provided, including: a test mode control signal generation module, a delay module, and an adjustment module;

[0006] The test mode control signal generation module is configured to obtain a test coding signal corresponding to a control signal, and when the coding value of a target coding bit of the test coding signal is a preset coding value, generate a test mode control signal corresponding to the control signal according to the test coding signal, where the control signal is a control signal in the DRAM that causes incorrect read / write timing;

[0007] The delay module is configured to receive the control signal and generate a delayed control signal after delaying the control signal by a preset duration;

[0008] The adjustment module is configured to generate a target control signal according to the test mode control signal, the control signal, and the delayed control signal, where the pulse width of the target control signal is greater than or less than the pulse width of the control signal.

[0009] In some embodiments of the present disclosure, the test mode control signal generation module includes a test mode determination unit, a target test coding signal generation unit, and a test mode control signal generation unit;

[0010] The test mode determination unit is configured to obtain the coding value of the target coding bit of the test coding signal, and when the coding value of the target coding bit of the test coding signal is the same as the preset coding value, generate a first test signal to the target test coding signal generation unit;

[0011] The target test coding signal generation unit is configured to invert the test coding signal according to the first test signal to obtain a target test coding signal;

[0012] The test mode control signal generation unit is configured to generate a test mode control signal according to the target test coding signal.

[0013] In some embodiments of the present disclosure, the test mode determination unit includes a first latch. The data input terminal of the first latch receives the coding value of the target coding bit of the test coding signal, the enable terminal of the first latch receives an enable signal, and the data output terminal of the first latch outputs a test signal.

[0014] In some embodiments of the present disclosure, the target test coding signal generation unit includes a first inverter and a first NOR gate. The input terminal of the first inverter receives the test signal, the output terminal of the first inverter is electrically connected to the first input terminal of the first NOR gate, the second input terminal of the first NOR gate receives the test coding signal, and the output terminal of the first NOR gate outputs a target test coding signal.

[0015] In some embodiments of the present disclosure, the test mode control signal generation unit includes a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a fifth AND gate, a sixth AND gate, a seventh AND gate, and a second latch. The first input terminal of the first AND gate receives the encoded value of the eleventh encoded bit of the target test encoded signal, and the second input terminal of the first AND gate receives the encoded value of the tenth encoded bit of the target test encoded signal. The first input terminal of the second AND gate receives the encoded value of the ninth encoded bit of the target test encoded signal, and the second input terminal of the second AND gate receives the encoded value of the eighth encoded bit of the target test encoded signal. The first input terminal of the third AND gate receives the encoded value of the sixth encoded bit of the target test encoded signal, and the second input terminal of the third AND gate receives the encoded value of the fifth encoded bit of the target test encoded signal. The output terminal of the first AND gate is electrically connected to the first input terminal of the fourth AND gate, the output terminal of the second AND gate is electrically connected to the second input terminal of the fourth AND gate, the output terminal of the fourth AND gate is electrically connected to the first input terminal of the fifth AND gate, the output terminal of the third AND gate is electrically connected to the second input terminal of the fifth AND gate, the output terminal of the fifth AND gate is electrically connected to the first input terminal of the sixth AND gate, the second input terminal of the sixth AND gate receives the encoded value of the twelfth encoded bit of the target test encoded signal, the output terminal of the sixth AND gate is electrically connected to the first input terminal of the seventh AND gate, the second input terminal of the seventh AND gate receives the encoded value of the fourth encoded bit of the target test encoded signal, the output terminal of the seventh AND gate is electrically connected to the enable terminal of the second latch, the data input terminal of the second latch receives the encoded values of the zeroth encoded bit to the third encoded bit of the target test encoded signal, and the data output terminal of the second latch outputs a test mode control signal.

[0016] In some embodiments of the present disclosure, the adjustment module includes an eighth AND gate and a second NOR gate. The first input terminal of the eighth AND gate receives the test mode control signal, the second input terminal of the eighth AND gate receives a delay control signal, the output terminal of the eighth AND gate is electrically connected to the first input terminal of the second NOR gate, the second input terminal of the second NOR gate receives the control signal, and the output terminal of the second NOR gate outputs a target control signal.

[0017] In some embodiments of the present disclosure, the adjustment module includes a second inverter, an OR gate, and a NAND gate. The input terminal of the second inverter receives the test mode control signal, the output terminal of the second inverter is electrically connected to the first input terminal of the OR gate, the second input terminal of the OR gate receives the delay control signal, the output terminal of the OR gate is electrically connected to the first input terminal of the NAND gate, the second input terminal of the NAND gate receives the control signal, and the output terminal of the NAND gate outputs a target control signal.

[0018] In some embodiments of the present disclosure, the test mode control signal generation module further includes a test mode control signal inversion unit and an exclusive OR unit;

[0019] The test mode control signal inversion unit is configured to generate an inverted test mode control signal opposite to the test mode control signal according to the test mode control signal;

[0020] The exclusive OR unit is configured to generate a target test mode control signal according to the test mode control signal and the inverted test mode control signal.

[0021] In some embodiments of the present disclosure, the test mode control signal inversion unit includes at least a switching transistor, a capacitor, and a third inverter. The exclusive OR unit includes an exclusive OR gate. The first end of the switching transistor is electrically connected to the power supply voltage node. The second end of the switching transistor and the first end of the capacitor are electrically connected to the input end of the third inverter. The second end of the capacitor is electrically connected to the voltage node. The output end of the third inverter is electrically connected to the first input end of the exclusive OR gate. The second input end of the exclusive OR gate receives the test mode control signal. The output end of the exclusive OR gate outputs the target test mode control signal.

[0022] In a second aspect, according to the content of the present disclosure, there is provided a DRAM, including the circuit according to any one of the first aspect.

[0023] After the DRAM read / write timing adjustment circuit and the DRAM provided by the embodiments of the present disclosure determine that a control signal of the DRAM determination control module causes an error in the read / write data of the storage unit in the memory, first, the test mode control signal generation module obtains a test coding signal corresponding to the control signal. When the coding value of the target coding bit of the test coding signal is a preset coding value, a test mode control signal is generated to the adjustment module. The delay module delays the control signal that causes the read / write timing error of the DRAM by a preset duration and then generates a delayed control signal. Through the delayed control signal, the adjustment module can adjust the pulse width of the control signal after generating the test mode control signal. The adjustment module generates a target control signal according to the received test mode control signal, control signal, and delayed control signal. The generated target control signal makes the pulse of the control signal narrower or wider compared with the control signal, so that the timing of the control signal output by the control module to SA, WL, CSL, etc. changes, so that the timing of the DRAM read / write process meets the specified timing, and the error of the read / write data of the storage unit is avoided. Description of the Drawings

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be understood that the following described drawings only relate to some embodiments of the present disclosure and do not limit the present disclosure, where:

[0025] Figure 1 It is a schematic structural diagram of a DRAM read / write timing adjustment circuit provided by an embodiment of the present disclosure;

[0026] Figure 2 It is a schematic structural diagram of another DRAM read / write timing adjustment circuit provided by an embodiment of the present disclosure;

[0027] Figure 3 It is a schematic structural diagram of a circuit of a test mode determination unit provided by an embodiment of the present disclosure;

[0028] Figure 4 It is a schematic structural diagram of a circuit of a target test coding signal generation unit provided by an embodiment of the present disclosure;

[0029] Figure 5 It is a schematic structural diagram of a circuit of a test mode control signal generation unit provided by an embodiment of the present disclosure;

[0030] Figure 6A It is a schematic structural diagram of a circuit of an adjustment module provided by an embodiment of the present disclosure;

[0031] Figure 6B It is a timing diagram of a target control signal generated by an adjustment module provided by an embodiment of the present disclosure;

[0032] Figure 7A It is a schematic structural diagram of another adjustment module provided by an embodiment of the present disclosure;

[0033] Figure 7B It is a timing diagram of a target control signal generated by another adjustment module provided by an embodiment of the present disclosure;

[0034] Figure 8 It is a schematic structural diagram of yet another DRAM read / write timing adjustment circuit provided by an embodiment of the present disclosure;

[0035] Figure 9 It is a partial schematic structural diagram of a test mode control signal generation module in a DRAM read / write timing adjustment circuit provided by an embodiment of the present disclosure. Detailed implementation manners

[0036] In order to make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of the present disclosure without creative efforts shall also fall within the scope of protection of the present disclosure.

[0037] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Further will be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless expressly so defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0038] In all embodiments of the present disclosure, terms such as "first" and "second" are only used to distinguish one component (or a part of a component) from another component (or another part of a component).

[0039] Unless the context clearly indicates otherwise, the singular forms of the words used in this specification and the appended claims include the plural, and vice versa. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the phrases "comprising" and "including" will be interpreted as inclusive rather than exclusive. Likewise, the terms "including" and "or" should be interpreted as inclusive, unless such an interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it is located after a group of terms, the said "example" is merely illustrative and explanatory, and should not be considered exclusive or extensive.

[0040] Based on the problems existing in the prior art, embodiments of the present disclosure provide a DRAM read / write timing adjustment circuit. Figure 1 is a schematic structural diagram of a DRAM read / write timing adjustment circuit provided by an embodiment of the present disclosure. As Figure 1 shown, the DRAM read / write timing adjustment circuit includes: a test mode control signal generation module 10, a delay module 20, and an adjustment module 30; the test mode control signal generation module 10 is configured to obtain a test coding signal corresponding to a control signal, and when the coding value of the target coding bit of the test coding signal is a preset coding value, generate a test mode control signal corresponding to the control signal, where the control signal is a control signal in the DRAM that causes an error in the read / write timing; the delay module 20 is configured to receive the control signal and generate a delayed control signal after delaying the control signal by a preset duration; the adjustment module 30 is configured to generate a target control signal according to the test mode control signal, the control signal, and the delayed control signal.

[0041] Specifically, in a DRAM, a control module outputs control signals to a sense amplifier (SA), a word line (WL), a column switch line (CSL), etc., to implement read and write control of the DRAM. However, when the timing of the control signals output by the control module to the SA, WL, CSL, etc. is incorrect, such that the timing of the memory read and write process does not meet the specified timing, the read and write data of the memory cell may be incorrect. Based on the problems existing in the prior art, the DRAM read and write timing adjustment circuit provided by the embodiments of the present disclosure first obtains a test coding signal corresponding to the control signal, wherein the test coding signal corresponding to each control signal is stored in the DRAM.

[0042] After the DRAM determines that a control signal of the control module causes the read and write data of the memory cell in the DRAM to be incorrect, first, the test mode control signal generation module 10 obtains the test coding signal corresponding to the control signal, and determines whether to generate a test mode control signal by comparing the coding value of the target coding bit of the test coding signal with the preset coding value. Specifically, when the coding value of the target coding bit of the test coding signal is the preset coding value, a test mode control signal is generated; when the coding value of the target coding bit of the test coding signal is different from the preset coding value, a test mode control signal is not generated.

[0043] Among them, the preset coding value is 1.

[0044] The delay module 20 delays the control signal that causes the read and write timing of the DRAM to be incorrect by a preset duration and then generates a delay control signal. By delaying the control signal that causes the read and write timing of the DRAM to be incorrect to obtain the delay control signal, it is possible to enable the adjustment module to adjust the pulse width of the control signal after generating the test mode control signal.

[0045] It should be noted that the delay module includes multiple delay elements, and the number of delay elements is related to the test mode control signal generated by the test mode control signal generation module. Therefore, under different test mode control signals, the delay control signals generated by the delay module are different.

[0046] The adjustment module 30 generates a target control signal according to the received test mode control signal, control signal, and delay control signal. The generated target control signal has a narrower or wider pulse compared to the control signal, such that the timing of the control signals output by the control module to the SA, WL, CSL, etc. is changed, so that the timing of the DRAM read and write process meets the specified timing, and the read and write data of the memory cell is prevented from being incorrect.

[0047] The DRAM read / write timing adjustment circuit provided by the embodiments of the present disclosure, after a control signal of the DRAM determination control module causes the read / write data of the storage unit in the memory to be in error, first, the test mode control signal generation module obtains a test coding signal corresponding to the control signal. When the coding value of the target coding bit of the test coding signal is a preset coding value, a test mode control signal is generated and sent to the adjustment module. The delay module delays the control signal that causes the read / write timing of the DRAM to be in error by a preset duration and then generates a delayed control signal. Through the delayed control signal, the adjustment module can adjust the pulse width of the control signal after generating the test mode control signal. The adjustment module generates a target control signal according to the received test mode control signal, control signal, and delayed control signal. The generated target control signal has a narrower or wider pulse compared with the control signal, so that the timing of the control signal output by the control module to SA, WL, CSL, etc. is changed, and the timing of the DRAM read / write process meets the specified timing, avoiding the read / write data of the storage unit from being in error.

[0048] Based on the above embodiments, Figure 2 FIG. 5 is a schematic structural diagram of another DRAM read / write timing adjustment circuit provided by the embodiments of the present disclosure. As Figure 2 shown, the test mode control signal generation module 10 includes a test mode determination unit 11, a target test coding signal generation unit 12, and a test mode control signal generation unit 13. The test mode determination unit 11 is configured to obtain the coding value of the target coding bit of the test coding signal, and when the coding value of the target coding bit of the test coding signal is the same as the preset coding value, generate a first test signal to the target test coding signal generation unit. The target test coding signal generation unit 12 is configured to invert the test coding signal according to the first test signal to obtain a target test coding signal. The test mode control signal generation unit 13 is configured to generate a test mode control signal according to the target test coding signal.

[0049] Specifically, the test mode determination unit of the test mode control signal generation module generates a test signal by obtaining the relationship between the coding value of the target coding bit of the test coding signal and the preset coding value. When the coding value of the target coding bit of the test coding signal is the same as the preset coding value, a first test signal is generated. When the coding value of the target coding bit of the test coding signal is different from the preset coding value, a second test signal is generated.

[0050] It should be noted that when the target coding value of the test coding signal is the same as the preset coding value, it indicates that the control signal corresponding to the test coding signal makes the read / write process of the DRAM not meet the timing requirements. When the target coding value of the test coding signal is different from the preset coding value, it indicates that the control signal corresponding to the test coding signal makes the read / write process of the DRAM meet the timing requirements. Therefore, when the coding value of the target coding bit of the test coding signal is the same as the preset coding value, a first test signal is generated to the target test coding signal generation unit, so that when the target test coding signal generation unit receives the first test signal, it selects the input test coding signal and inverts the test coding signal to obtain the target test coding signal.

[0051] Specifically, when the target test coding signal generation unit 12 receives the first test signal, the target test coding signal generation unit 12 inverts the test coding signal to obtain the target test coding signal; when the target test coding signal generation unit receives the second test signal, the target test coding signal assigns the coding value of each coding bit of the test coding signal to zero and then outputs it.

[0052] Specifically, when the test mode control signal generation unit 13 receives the target test coding signal, it determines whether to generate a test mode control signal by processing the coding value of each coding bit of the target test coding signal.

[0053] In a specific implementation manner, in combination with Figure 3 , the test mode determination unit 11 includes a first latch SR1. The data input terminal of the first latch SR1 receives the coding value of the target coding bit of the test coding signal. The enable terminal of the first latch SR1 receives the enable signal. The data output terminal of the first latch SR1 outputs the test signal.

[0054] As Figure 3 shown, the data input terminal of the first latch SR1 receives the coding value of the target coding bit of the test coding signal. The enable terminal of the first latch SR1 receives the enable signal. When the enable terminal of the first latch SR1 is in the enabled state, if the data input terminal is 1, the first latch SR1 will store the coding value of the target coding bit of the test coding signal input by the current data input terminal to the data output terminal at the rising edge of the next clock pulse. That is, if the coding value of the target coding bit of the test coding signal is 1, the first latch outputs the first test signal (1) to the target test coding signal generation unit. If the coding value of the target coding bit of the test coding signal is 0, the first latch outputs the second test signal (0) to the target test coding signal generation unit.

[0055] In an embodiment of the present disclosure, the test coding signal is Address<12:0>, and the target coding bit of the test coding signal is the seventh bit, that is, Address<7>. If Address<7>=1, the first test signal Test=1 generated by the test mode determination unit; if Address<7>=0, the second test signal Test=0 generated by the test mode determination unit.

[0056] As Figure 4 shown, the target test coding signal generation unit 12 includes a first inverter F1 and a first nor gate NOR1. The input end of the first inverter F1 receives the test signal Test, the output end of the first inverter F1 is electrically connected to the first input end of the first nor gate NOR1, the second input end of the first nor gate NOR1 receives the test coding signal Address<12:0>, and the output end of the first nor gate NOR1 outputs the target test coding signal TRA<12:0>.

[0057] Specifically, the first inverter F1 receives the test signal Test output by the first latch SR1. If the test signal output by the first latch SR1 is the first test signal (1), the first inverter F1 outputs a low level (0); if the test signal output by the first latch SR1 is the second test signal (0), the first inverter F1 outputs a high level (1). The first input end of the first nor gate NOR1 receives the level signal output by the first inverter F1, and the second input end of the first nor gate NOR1 receives the test coding signal Address<12:0>. When the level signal output by the first inverter F1 is a low level (0), the first nor gate NOR1 takes the inverse of the coding values of each coding bit of the test coding signal Address<12:0> received at the second input end and outputs to obtain the target test coding signal TRA<12:0>. When the level signal output by the first inverter F1 is a high level (1), the first nor gate NOR1 assigns zero to the coding values of each coding bit of the test coding signal received at the second input end and outputs, that is, the target test coding signal is not generated.

[0058] As Figure 5As shown, the test mode control signal generation unit 13 includes a first AND gate A1, a second AND gate A2, a third AND gate A3, a fourth AND gate A4, a fifth AND gate A5, a sixth AND gate A6, a seventh AND gate A7, and a second latch SR2. The first input terminal of the first AND gate A1 receives the encoded value TRA<11> of the eleventh encoded bit of the target test encoded signal, and the second input terminal of the first AND gate A1 receives the encoded value TRA<10> of the tenth encoded bit of the target test encoded signal. The first input terminal of the second AND gate A2 receives the encoded value TRA<9> of the ninth encoded bit of the target test encoded signal, and the second input terminal of the second AND gate A2 receives the encoded value TRA<8> of the eighth encoded bit of the target test encoded signal. The first input terminal of the third AND gate A3 receives the encoded value TRA<6> of the sixth encoded bit of the target test encoded signal, and the second input terminal of the third AND gate A3 receives the encoded value TRA<5> of the fifth encoded bit of the target test encoded signal. The output terminal of the first AND gate A1 is electrically connected to the first input terminal of the fourth AND gate A4, the output terminal of the second AND gate A2 is electrically connected to the second input terminal of the fourth AND gate A4, the output terminal of the fourth AND gate A4 is electrically connected to the first input terminal of the fifth AND gate A5, the output terminal of the third AND gate A3 is electrically connected to the second input terminal of the fifth AND gate A5, the output terminal of the fifth AND gate A5 is electrically connected to the first input terminal of the sixth AND gate A6, the second input terminal of the sixth AND gate A6 receives the encoded value TRA<12> of the twelfth encoded bit of the target test encoded signal, the output terminal of the sixth AND gate A6 is electrically connected to the first input terminal of the seventh AND gate A7, the second input terminal of the seventh AND gate A7 receives the encoded value TRA<4> of the fourth encoded bit of the target test encoded signal, the output terminal of the seventh AND gate A7 is electrically connected to the enable terminal of the second latch SR2, the data input terminal of the second latch SR2 receives the encoded values TRA<3:0> of the zeroth to third encoded bits of the target test encoded signal, and the data output terminal of the second latch SR2 outputs a test mode control signal Test mode code.

[0059] Specifically, as Figure 5 shown, when the encoded values of the twelfth, eleventh, tenth, ninth, eighth, sixth, fifth, and fourth encoded bits of the target test encoded signal are 1, the seventh AND gate outputs a high level to the second latch, enabling the second latch. The second latch outputs a test mode control signal according to the encoded values of the zeroth to third encoded bits of the target test encoded signal received at the data input terminal.

[0060] Exemplarily, if the seventh AND gate outputs a high level to the second latch, when the encoding values of the 0th to 3rd encoding bits of the target test encoding signal received by the data input terminal of the second latch are 0001, the test mode control signal output by the second latch is 1 (i.e., high level); if the seventh AND gate outputs a high level to the second latch, when the encoding values of the 0th to 3rd encoding bits of the target test encoding signal received by the data input terminal of the second latch are 0010, the test mode control signal output by the second latch is 2 (i.e., high level); if the seventh AND gate outputs a high level to the second latch, when the encoding values of the 0th to 3rd encoding bits of the target test encoding signal received by the data input terminal of the second latch are 0100, the test mode control signal output by the second latch is 4 (i.e., high level); if the seventh AND gate outputs a high level to the second latch, when the encoding values of the 0th to 3rd encoding bits of the target test encoding signal received by the data input terminal of the second latch are 1000, the test mode control signal output by the second latch is 8 (i.e., high level). If the seventh AND gate outputs a high level to the second latch, when the encoding values of the 0th to 3rd encoding bits of the target test encoding signal received by the data input terminal of the second latch are 0000, the test mode control signal output by the second latch is 0 (i.e., low level). In addition, when the seventh AND gate outputs a low level to the second latch, regardless of the values of the encoding values of the 0th to 3rd encoding bits of the target test encoding signal received by the data input terminal of the second latch, the test mode control signal output by the second latch is 0 (i.e., low level).

[0061] It should be noted that different control signals correspond to different test mode control signals, and different test mode control signals adjust the pulse width of the control signal by different amounts.

[0062] As a specific implementable manner, in combination with Figure 6A and Figure 6B , the adjustment module 30 includes an eighth AND gate A8 and a second NOR gate NOR2. The first input terminal of the eighth AND gate A8 receives the test mode control signal Test mode code, the second input terminal of the eighth AND gate A8 receives the delay control signal Dly Control Signal, the output terminal of the eighth AND gate A8 is electrically connected to the first input terminal of the second NOR gate NOR2, the second input terminal of the second NOR gate NOR2 receives the control signal ControlSignal, and the output terminal of the second NOR gate NOR2 outputs the target control signal Output.

[0063] In combination with Figure 6A and Figure 6B, first, the eighth AND gate receives the test mode control signal and the delay control signal. After taking the intersection of the test mode control signal and the delay control signal, the eighth AND gate outputs to the second NOR gate. The second NOR gate takes the intersection of the intersection of the test mode control signal and the delay control signal and the control signal, and then outputs the target control signal, realizing that the pulse width of the output target control signal is increased compared with the control signal.

[0064] As another specific implementable manner, in combination with Figure 7A and Figure 7B , the adjustment module 30 includes a second inverter F2, an OR gate OR, and a NAND gate NA. The input end of the second inverter F2 receives the test mode control signal Test mode code. The output end of the second inverter F2 is electrically connected to the first input end of the OR gate OR. The second input end of the OR gate OR receives the delay control signal Dly Control Signal. The output end of the OR gate OR is electrically connected to the first input end of the NAND gate NA. The second input end of the NAND gate NA receives the control signal Control Signal. The output end of the NAND gate NA outputs the target control signal Output.

[0065] In combination with Figure 7A and Figure 7B , the second inverter inverts the test mode control signal and then outputs it to the OR gate. Specifically, when the test mode control signal is at a high level, the output of the second inverter to the first input end of the OR gate is at a low level. Since the first input end of the OR gate is at a low level, the OR gate outputs the delay control signal input at the second input end. The NAND gate takes the intersection of the delay control signal and the control signal and then inverts it to output the target control signal, realizing that the pulse width of the output target control signal is decreased compared with the control signal.

[0066] Based on the above embodiments, Figure 8 is a schematic structural diagram of another DRAM read / write timing adjustment circuit provided by an embodiment of the present disclosure. As shown in Figure 8 , the test mode control signal generation module further includes a test mode control signal inversion unit 14 and an exclusive-OR unit 15; the test mode control signal inversion unit 14 is configured to generate an inverted test mode control signal opposite to the test mode control signal according to the test mode control signal; the exclusive-OR unit 15 is configured to generate a target test mode control signal according to the test mode control signal and the inverted test mode control signal.

[0067] Among them, as shown in Figure 9As shown, the test mode control signal inverting unit 14 at least includes a switch tube M, a capacitor C and a third inverter F3, the XOR unit includes an XOR gate XOR, the first end of the switch tube M is electrically connected to the power supply voltage node, the second end of the switch tube M and the first end of the capacitor C are electrically connected to the input end of the third inverter F3, the second end of the capacitor C is electrically connected to the voltage node, the output end of the third inverter F3 is electrically connected to the first input end of the XOR gate XOR, the second input end of the XOR gate XOR receives the test mode control signal Test mode code, and the output end of the XOR gate XOR outputs the target test mode control signal Tar Test mode code.

[0068] In the above embodiment, the adjustment of the DRAM read and write timing when the DRAM is in the test mode is exemplified. In order to adjust the DRAM read and write timing when the DRAM is in the normal working mode, at this time, by setting the test mode control signal generation module to also include a test mode control signal inversion unit and an XOR unit, first, the test mode control signal inversion unit receives the test mode control signal. When the test mode control signal is at a high level, the reverse test mode control signal output by the test mode control signal inversion unit is at a low level. When the test mode control signal is at a low level, the reverse test mode control signal output by the test mode control signal inversion unit is at a high level. At this time, the XOR unit receives the test mode control signal and the reverse test mode control signal respectively. Regardless of whether the test mode control signal is at a high level or a low level, the XOR unit will output a high level, that is, the target test mode control signal generated by the XOR unit is a high level, so that when the coding value of the target coding bit of the test coding signal is different from the preset coding value (that is, the DRAM is in the normal working mode), the DRAM read and write timing can also be adjusted.

[0069] As a specific implementation method, when the test mode control signal is at a high level, a control signal is output to the switch tube to control the switch tube to be turned on, the input end of the third inverter receives a high level, the third inverter outputs a low level to the XOR gate, the first input end of the XOR gate receives a low level, the second input end of the XOR gate receives a high level, and the target test mode control signal output by the XOR gate is a high level; when the test mode control signal is at a low level, a high voltage is connected to the second end of the capacitor to break down the capacitor, the input end of the third inverter receives a low level, the third inverter outputs a high level to the XOR gate, the first input end of the XOR gate receives a high level, the second input end of the XOR gate receives a low level, and the target test mode control signal output by the XOR gate is a high level. It is achieved that regardless of whether the coding value of the target coding bit of the test coding signal is the same as the preset coding value (that is, the DRAM normal working mode or the test working mode), the DRAM read and write timing can be adjusted.

[0070] Embodiments of the present disclosure also provide a DRAM, which includes the DRAM read / write timing adjustment circuit provided by the embodiments of the present disclosure and has the beneficial effects described in any of the above embodiments.

[0071] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular forms are also intended to include the plural forms. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they specify the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0072] It should be understood that the phrase "in an embodiment" or "in an embodiment" mentioned throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the present application. Therefore, the appearances of "in an embodiment" or "in an embodiment" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that in various embodiments of the present application, the order numbers of the above steps / processes do not mean the order of execution. The order of execution of each step / process should be determined by its function and internal logic and should not constitute any limitation to the implementation process of the embodiments of the present application. Moreover, the serial numbers of the embodiments of the present application are only for description and do not represent the advantages or disadvantages of the embodiments.

[0073] It should be noted that the terms "first", "second", etc. in the specification, claims, and drawings of the present application are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0074] The above are only the preferred embodiments of the present disclosure and are not used to limit the present disclosure. For those skilled in the art, the present disclosure may have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A DRAM read / write timing adjustment circuit, characterized in that: include: Test mode control signal generation module, delay module and adjustment module; The test mode control signal generating module is configured to obtain a test coding signal corresponding to the control signal, and when the coding value of the target coding bit of the test coding signal is a preset coding value, generate a test mode control signal corresponding to the control signal according to the test coding signal, wherein the control signal is a control signal that causes a read and write timing error in the DRAM; The delay module is configured to receive a control signal and generate a delayed control signal after delaying the control signal for a preset time length; The adjustment module is configured to generate a target control signal according to the test mode control signal, the control signal and the delay control signal, wherein a pulse width of the target control signal is greater than or less than a pulse width of the control signal.

2. The circuit according to claim 1, characterized in that The test mode control signal generating module includes a test mode determining unit, a target test code signal generating unit and a test mode control signal generating unit; The test mode determination unit is configured to obtain a coding value of a target coding bit of the test coding signal, and generate a first test signal to the target test coding signal generation unit when the coding value of the target coding bit of the test coding signal is the same as a preset coding value; The target test code signal generating unit is configured to invert the test code signal according to the first test signal to obtain a target test code signal; The test mode control signal generating unit is configured to generate a test mode control signal according to the target test code signal.

3. The circuit according to claim 2, characterized in that The test mode determination unit includes a first latch, a data input terminal of the first latch receives a coding value of a target coding bit of the test coding signal, an enable terminal of the first latch receives an enable signal, and a data output terminal of the first latch outputs a test signal.

4. The circuit according to claim 2, characterized in that The target test code signal generating unit includes a first inverter and a first NOR gate, the input end of the first inverter receives a test signal, the output end of the first inverter is electrically connected to the first input end of the first NOR gate, the second input end of the first NOR gate receives the test code signal, and the output end of the first NOR gate outputs a target test code signal.

5. The circuit according to claim 2, characterized in that The test mode control signal generating unit includes a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a fifth AND gate, a sixth AND gate, a seventh AND gate and a second latch, wherein a first input end of the first AND gate receives a code value of an eleventh code bit of the target test code signal, a second input end of the first AND gate receives a code value of a tenth code bit of the target test code signal, a first input end of the second AND gate receives a code value of a ninth code bit of the target test code signal, a second input end of the second AND gate receives a code value of an eighth code bit of the target test code signal, a first input end of the third AND gate receives a code value of a sixth code bit of the target test code signal, a second input end of the third AND gate receives a code value of a fifth code bit of the target test code signal, an output end of the first AND gate is electrically connected to a first input end of the fourth AND gate, and The output end of the second AND gate is electrically connected to the second input end of the fourth AND gate, the output end of the fourth AND gate is electrically connected to the first input end of the fifth AND gate, the output end of the third AND gate is electrically connected to the second input end of the fifth AND gate, the output end of the fifth AND gate is electrically connected to the first input end of the sixth AND gate, the second input end of the sixth AND gate receives the coding value of the twelfth coding bit of the target test coding signal, the output end of the sixth AND gate is electrically connected to the first input end of the seventh AND gate, the second input end of the seventh AND gate receives the coding value of the fourth coding bit of the target test coding signal, the output end of the seventh AND gate is electrically connected to the enable end of the second latch, the data input end of the second latch receives the coding values ​​of the zeroth coding bit to the third coding bit of the target test coding signal, and the data output end of the second latch outputs a test mode control signal.

6. The circuit according to claim 1, characterized in that The adjustment module includes an eighth AND gate and a second NOR gate, the first input end of the eighth AND gate receives the test mode control signal, the second input end of the eighth AND gate receives the delay control signal, the output end of the eighth AND gate is electrically connected to the first input end of the second NOR gate, the second input end of the second NOR gate receives the control signal, and the output end of the second NOR gate outputs the target control signal.

7. The circuit according to claim 1, characterized in that The adjustment module includes a second inverter, an OR gate and a NAND gate, the input end of the second inverter receives the test mode control signal, the output end of the second inverter is electrically connected to the first input end of the OR gate, the second input end of the OR gate receives the delay control signal, the output end of the OR gate is electrically connected to the first input end of the NAND gate, the second input end of the NAND gate receives the control signal, and the output end of the NAND gate outputs the target control signal.

8. The circuit according to claim 1, characterized in that The test mode control signal generating module further includes a test mode control signal inverting unit and an XOR unit; The test mode control signal inversion unit is configured to generate an inverse test mode control signal opposite to the test mode control signal according to the test mode control signal; The XOR unit is configured to generate a target test mode control signal according to the test mode control signal and the reverse test mode control signal.

9. The circuit according to claim 8, characterized in that The test mode control signal inversion unit at least includes a switch tube, a capacitor and a third inverter, the XOR unit includes an XOR gate, the first end of the switch tube is electrically connected to the power supply voltage node, the second end of the switch tube and the first end of the capacitor are electrically connected to the input end of the third inverter, the second end of the capacitor is electrically connected to the voltage node, the output end of the third inverter is electrically connected to the first input end of the XOR gate, the second input end of the XOR gate receives the test mode control signal, and the output end of the XOR gate outputs the target test mode control signal.

10. A DRAM, characterized in that: The invention comprises the circuit described in any one of claims 1 to 9.

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