ECC protection control system and method for RAM of AHB interface

Abstract

The invention provides an ECC protection control system and method for an RAM of an AHB interface, the system comprises an AHBtoRAM protocol conversion module, an ECC RAM read-write control module and an RAM unit, the ECC RAM read-write control module is connected with the AHBtoRAM protocol conversion module and the RAM unit, the ECC RAM read-write control module comprises a read-write control module, an ECC encoder, an ECC decoder and a register, the read-write control module is used for controlling a handshake signal HREADY of the AHB interface, and the register is connected with the AHBtoRAM protocol conversion module and the RAM unit. And generating an RAM read operation and an RAM write operation. According to the method, the timing signoff difficulty of the rear end of the system can be reduced, and meanwhile, the efficient read-write ECC RAM efficiency of the AHB is ensured.

Description

Technical Field

[0001] The present invention relates to the field of RAM ECC, and in particular to an ECC protection control system and method for an AHB interface RAM. Background Art

[0002] AHB (Advanced High-performance Bus) is a high-speed, high-performance bus that supports two-stage pipeline operation. The AHB transmission mode consists of two phases. The first phase is the address transfer (address phase), and the second phase is the data transfer (data phase). The end of each phase is marked by the completion of the HREADY signal handshake. The transfer size of each AHB transfer is optional, and the typical sizes supported are byte (8-bit), half-word (16-bit), and word (32-bit). Typical applications include the connection between the CPU core and the high-speed RAM, DMA, and Bridge inside the system.

[0003] RAM (Random Access Memory) is a volatile memory that relies on electricity to maintain the stored data, which makes the data easy to lose. In the CPU system, RAM not only stores data, but also stores instructions. During the long-term uninterrupted operation of the system, the errors will increase over time, which is very likely to cause the system to crash. Therefore, an effective means is needed to protect the data stored in RAM. The ECC (Error Checking and Correction) mechanism is a common method to protect RAM stored data. It has error detection and correction functions, which can significantly reduce the possibility of system crashes, server failures and data corruption.

[0004] The current implementation process of the ECC protection mechanism is as follows: the ECC error correction code is generated when writing to the RAM and is stored in the same address of the RAM together with the valid write data. If the RAM does not have a bit write mask feature, the ECC encoder circuit can add an error correction code to the valid data in the same cycle of data writing, and then write the valid data and the error correction code together to the RAM; if the RAM has a bit write mask feature, and only some bits of the current address are to be rewritten when writing to the RAM, it is necessary to first read out the data stored before the RAM write address, and then merge the newly written data with the read data according to the rules according to the RAM's wen (write enable) signal, and finally pass the merged data through the ECC encoder circuit to add an error correction code to the valid data, and then write the valid data and the error correction code together to the RAM. When reading the RAM, the RAM read data (error correction code + valid data) passes through the ECC decoder circuit for error detection and correction to generate the final RAM read data (valid data).

[0005] For the RAM of the AHB interface, since AHB supports different transfer sizes, the RAM usually supports the bitwrite mask feature. For the AHB write RAM operation, it needs to be disassembled into reading first, merging, and then writing. If the RAM is written in the same cycle as the RAM read data, there is a path from the RAM read data port to the write data port, which greatly increases the difficulty of the back-end timing signoff. For the AHB read RAM operation, the RAM read data output itself has a large delay time. After being sent to the AHB HRDATA interface through the ECCdecoder circuit, the delay will be further increased. After passing through the AHB bus matrix to reach the master end, the delay is already very large. As the AHB bus working clock increases, the difficulty of the back-end timing signoff also increases.

[0006] In order to solve the above problems, a register (interpolation) in the first-level sequential logic is usually added in the middle of the lengthy combinational logic to segment the combinational logic, which can greatly reduce the path delay, make the back-end timing signoff easier, and save power consumption, area and human resources. However, the interpolation processing of the RAM read and write path often reduces the efficiency of AHB access to RAM. Therefore, how to achieve efficient AHB write RAM and AHB read RAM operations in the case of interpolation of RAM read and write paths is of engineering significance. Summary of the invention

[0007] The first object of the present invention is to provide an ECC protection control system for an AHB interface RAM with high read and write access efficiency and reduced timing signoff difficulty.

[0008] The second object of the present invention is to provide an ECC protection control method for an AHB interface RAM with high read and write access efficiency and reduced timing signoff difficulty.

[0009] In order to achieve the above-mentioned first purpose, the present invention provides an ECC protection control system of an AHB interface RAM, comprising an AHBtoRAM protocol conversion module, an ECC RAM read-write control module, and a RAM unit, wherein the ECC RAM read-write control module is connected to the AHBtoRAM protocol conversion module and the RAM unit respectively, and the ECC RAM read-write control module comprises a read-write control module, an ECCencoder, an ECC decoder, and a register;

[0010] Among them, the handshake signal HREADY of the AHB interface is directly provided by the ECC RAM read-write control module, and the ECC RAM read-write control module can obtain the signals HSEL and HWRITE of the AHB interface. The RAM read data passes through the first-level register and then passes through the ECC decoder combinational logic circuit.

[0011] The AHBtoRAM protocol conversion module only includes combinational logic circuits. The output ports HSEL and HWRITE of the AHBtoRAM protocol conversion module are connected to the input port of the read-write control module. The control signal input port HREADY of the AHBtoRAM protocol conversion module is connected to the output port of the read-write control module. The ram control signal and address data output port of the AHBtoRAM protocol conversion module are connected to the input port of the read-write control module. The write data input port of the RAM unit is connected to the data output port of the ECC encoder. The data input port of the ECC encoder is connected to the data output port of the read-write control module. The data input port of the register is connected to the read data output port of the RAM unit. The ECC decoder data input port is connected to the data output port of the register. The ECC decoder data output port is connected to the read-write control module. The ECC decoder data output port is connected to the HRDATA input port of the AHBtoRAM protocol conversion module. The RAM unit control signal input port is connected to the read-write control module.

[0012] In order to achieve the above-mentioned second purpose, the present invention also provides an ECC protection control method for an AHB interface RAM, which is applied to the above-mentioned ECC protection control system of an AHB interface RAM, wherein the following steps are included: if the AHB interface continuously writes to the RAM, the read / write control module dynamically adjusts the control behavior according to the size of the AHB write data. If it is a continuous overall write, each dataphase initiates a write RAM operation, and the signal HREADY remains at a high level. If it is a continuous write If the AHB interface reads RAM continuously, the read / write control module has the function of predicting the next read address and initiating the next RAM read operation in advance (pre-reading). In the next clock cycle after initiating the first RAM read operation, the pre-reading process is entered: the next address read RAM operation is initiated in advance, the size relationship of the two RAM read addresses is compared, and it is determined whether the RAM read address is in ascending or descending order, and the RAM read address is advanced in the subsequent clock cycle. The address is based on the second read address and is increased or decreased by 1 in each clock cycle. If the predicted RAM read address is inconsistent with the next RAM address actually read by the AHB, the RAM read operation is re-initiated according to the actual RAM address, and the pre-reading process is re-entered.

[0013] Compared with the prior art, the present invention has the following beneficial technical effects:

[0014] 1. The handshake signal HREADY of the AHB interface of the present invention is directly provided by the read-write control module, and the read-write control module can obtain the signals HSEL and HWRITE of the AHB interface. The RAM read data passes through the first-level register and then passes through the ECC decoder combinational logic circuit. The beneficial effects achieved by the present invention include: (1) The read-write control module can flexibly control the receiving progress of the AHB read-write transmission, and can obtain the current AHB read-write status in real time, with the maximum read-write control freedom, which is beneficial to improving the read-write access efficiency; (2) The insertion of the register on the RAM read data path reduces the path delay between the RAM read data and the logic that uses the read data later, reducing the difficulty of the entire system back-end timing signoff.

[0015] 2. The AHB interface of the present invention writes RAM, and the control module selects the optimal control method according to the AHB transmission size, so that there are RAM read and write operations in each clock cycle. When the AHB reads RAM, the control module adopts a pre-reading mechanism to read the next RAM address in advance, so that the AHB read data can be returned faster. The beneficial effects achieved by the present invention also include: it can ensure efficient AHB reading and writing ECCRAM efficiency. When the AHB continuously writes N data to the RAM as a whole, the number of clock cycles required is only N+1. When the AHB continuously writes N data to the RAM with a write mask, the number of clock cycles required is only 2*N+1. When the AHB interface continuously reads N RAM data and the address is incremented or decremented, the number of clock cycles required is only N+2. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A structural block diagram of an embodiment of an ECC protection control system for an AHB interface RAM of the present invention;

[0017] Figure 2 It is a flowchart of the write timing of the read-write control module in an embodiment of the ECC protection control method of an AHB interface RAM of the present invention;

[0018] Figure 3 A timing diagram of controlling the writing timing of a system in an embodiment of an ECC protection control method for an AHB interface RAM of the present invention;

[0019] Figure 4 It is a flow chart of the read timing of the read / write control module in an embodiment of the ECC protection control method of an AHB interface RAM of the present invention;

[0020] Figure 5 The present invention is a timing diagram of controlling the system read timing in an embodiment of an ECC protection control method for an AHB interface RAM.

[0021] Figure numerals: 11, AHBtoRAM protocol conversion module; 12, ECC RAM read-write control module; 121, read-write control module; 122, ECC encoder; 123, ECC decoder; 124, register; 13, RAM unit. DETAILED DESCRIPTION

[0022] An ECC protection control system embodiment of an AHB interface RAM:

[0023] See also Figure 1In this embodiment, an ECC protection control system of an AHB interface RAM includes an AHBtoRAM protocol conversion module 11, an ECC RAM read-write control module 12, and a RAM unit 13. The RAM unit 13 is a RAM IP core. The ECC RAM read-write control module 12 includes a read-write control module 121, an ECC encoder 122 (encoder), an ECC decoder 123 (decoder), and a register 124.

[0024] The AHBtoRAM protocol conversion module 11 is a pure combinational logic circuit, which generates an output signal cen_i based on the external input AHB signals HSEL and HTRANS, generates an output signal gwen_i based on the external input AHB signals HSEL, HTRANS, HWRITE, generates an output signal wen_i based on the external input AHB signals HSEL, HTRANS, HWRITE, HADDR, and HSIZE, generates an output signal a_i based on the external input AHB signal HADDR, and the output signal d_i is the same as the external input AHB signal HWDATA, and outputs the external input AHB signals HSEL and HWRITE to ECC The RAM read-write control module 12 outputs the handshake signal HREADY and the read data signal HRDATA output by the ECCRAM read-write control module 12 to the external AHB interface. The RAM control and address data signals cen_i, gwen_i, wen_i, a_i, and d_i are custom interface signals. cen_i, gwen_i, wen_i, and a_i are address phase signals, and d_i is a data phase signal, which supports Pipeline pipelining.

[0025] The read-write control module 121 is the core module, which controls the progress of AHB read-write transmission through the output signal HREADY, analyzes the module input signal, generates RAM control and address signals cen_o (chip enable), gwen_o (globalwrite enable), wen_o (write enable), a_o (address), and generates RAM write data signal ram_d. The signals cen_o, gwen_o, wen_o, a_o, and ram_d comply with the RAM standard read-write protocol.

[0026] The data input end of ECC encoder 122 is connected to the RAM write data signal ram_d of the read / write control module 121, and the data output end of ECC encoder 122 is connected to the write data port of RAM unit 13. ECC encoder 122 is used to perform ECC encoding on the write data signal ram_d, and the encoded signal is ram_d_ecc.

[0027] The data input end of register 124 is connected to the read data port of RAM unit 13, and the input read data signal ram_q_ecc is valid read data + ECC error correction code. Register 124 is used to store and output the read data of RAM unit 13 and perform interpolation processing on the read data path. The input read data signal ram_q_ecc is valid data + ECC error correction code.

[0028] The data input end of ECC decoder123 is connected to the data output end of register 124, and the data output end ram_q of ECC decoder123 is connected to the read-write control module 121 and the AHBtoRAM protocol conversion module 11. ECC decoder123 is used to decode the read data of the registered RAM unit 13, and the input signal HRDATA of the AHBtoRAM protocol conversion module 11 is the same as the data output signal ram_q of ECC decoder123.

[0029] The working clocks of the read / write control module 121 , the register 124 , and the RAM unit 13 use the externally input AHB interface clock signal HCLK.

[0030] The ECC encoder and ECC decoder modules of the present invention are not limited to the ECC method.

[0031] An ECC protection control method embodiment of an AHB interface RAM:

[0032] This embodiment is based on the ECC protection control system of the AHB interface RAM of the above embodiment. Figure 2 and Figure 4 , Figure 2 The writing process of the ECC protection control system of the AHB interface RAM of this embodiment is shown. Figure 4 The read process of the ECC protection control system of the AHB interface RAM of this embodiment is shown.

[0033] See also Figure 2 , the read-write control module includes the following steps in the writing process:

[0034] S11: Receive the write RAM control command and latch the write address and write mask.

[0035] S12: Determine whether to write the entire file.

[0036] When the write enable signal wen_i is all 0, it is determined to be a whole byte write, and step S13 is continued; when wen_i is not all 0, it is determined to be a partial byte write, and the process jumps to S14.

[0037] S13: Based on the input RAM write data signal, generate a RAM write enable signal, a RAM write address signal, and a RAM write data signal. At the same time, the next write RAM control command may be received, and it is necessary to jump to step S11.

[0038] S14: Generate a RAM read enable signal and a read address signal based on the input RAM write address signal.

[0039] S15: Latch the input RAM write data.

[0040] S16: receiving the next RAM write control command, latching the write address and write mask, and generating the next RAM read enable signal and read address signal based on the input RAM write address signal.

[0041] S17: Based on the read data stored in the previous RAM read operation, the RAM write data latched in the previous time, the RAM write mask latched in the previous time, and the RAM write address latched in the previous time, a RAM write enable signal, a RAM write address signal, and a RAM write data signal of the previous RAM write operation are generated. The RAM write data input for the next RAM write operation is latched. Jump to S16 at this time.

[0042] See also Figure 3 In the write timing, when the data is written continuously as a whole, the write address increases from A0 to A2. Since the signal HREADY is always kept at a high level, the write data D0~D2 can be received in the next clock cycle of the corresponding address phase and generate the final RAM write operation. At this time, D0~D2 of the signals d_i and ram_d are the same, and only 4 clock cycles are needed to write 3 data. Based on the timing rules, it can be concluded that when AHB continuously writes N data to RAM as a whole, the number of clock cycles required is N+1. When writing data with a continuous write mask, the write address increases from A3 to A7. The signal HREADY generates low and high levels alternately in each clock cycle. Each write to RAM needs to be broken down into reading the RAM first, merging the registered RAM read data with the latched RAM write data, and finally generating the final RAM write operation. The D3x~D7x of the signal ram_d is the write data finally written to the RAM addresses A3~A7. Starting from the second write address (A4) clock cycle, each clock cycle can alternately generate RAM read and write operations. Since A7 is the last write address, there is only one clock cycle between the successful handshake of the input write address A7 and the final RAM write address A7. It only takes 11 clock cycles to write 5 data. Based on the timing rules, it can be concluded that when the AHB continuously writes N data to the RAM with a write mask, the number of clock cycles required is 2*N+1.

[0043] See also Figure 4 The read-write control module includes the following steps in the reading process:

[0044] S21: Receive a RAM read control command.

[0045] S22: Generate a RAM read enable signal and a read address signal based on the input RAM read address signal.

[0046] S23: Based on the signals HSEL, HWRITE, and the input RAM read address, the next RAM read enable signal and read address signal are generated in advance.

[0047] S24: predict the next read address and generate the next RAM read enable signal and read address signal in advance.

[0048] S25: Determine whether the predicted read address is consistent with the actual read address.

[0049] Among them, when the predicted read address is consistent with the actual read address, it indicates that the pre-reading is successful, and then jump to step S24 to continue pre-reading the next RAM address; when the predicted read address is inconsistent with the actual read address, it indicates that the pre-reading fails, and then jump to step S22 to generate a RAM read enable signal and a read address signal based on the actual input RAM read address signal.

[0050] See also Figure 5 In the read timing, the read address a_i increases from A0 to A4, and the read address increases or decreases by 1 in turn. The read address a_i increases from A7 to A11, and the read address increases or decreases by 1 in turn. The relationship between the read addresses A4 and A7 is not an increase or decrease of 1. In the next clock cycle after initiating the read of the A0 address, the read of the A1 address will be initiated in advance. The A1 address lasts for two clock cycles. In the second clock cycle of the A1 address, the read of the A2 address is initiated in advance. In the clock cycle of the A2 address, the A3 address is pre-read. Similarly, the A5 address is pre-read at the A4 address, but the A7 address is received later. At this time, the pre-reading fails. It can be observed that in the A7 address clock cycle, the read of the A7 address is initiated. In the next clock cycle after initiating the read of the A7 address, the read of the A8 address will be initiated in advance, and then the pre-reading process will be re-entered. The pre-reading operation will be initiated in the clock cycle before the actual read address is valid. Based on the timing rules, it can be concluded that when the AHB interface continuously reads N RAM data and the address increases or decreases, the number of clock cycles required is N+2.

[0051] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited thereto, and various changes can be made within the knowledge scope of technicians in the relevant technical field without departing from the purpose of the present invention.

Claims

1. An ECC protection control system for an AHB interface RAM, characterized in that: The invention comprises an AHB to RAM protocol conversion module (11), an ECC RAM read-write control module (12) and a RAM unit (13), wherein the ECC RAM read-write control module (12) is connected to the AHB to RAM protocol conversion module (11) and the RAM unit (13) respectively, and the ECC RAM read-write control module (12) comprises a read-write control module (121), an ECC encoder (122), an ECC decoder (123) and a register (124); The handshake signal HREADY of the AHB interface is directly provided by the ECC RAM read-write control module (12), and the ECC RAM read-write control module (12) can obtain the signals HSEL and HWRITE of the AHB interface. The RAM read data passes through the primary register (124) and then passes through the ECC decoder (123) combinational logic circuit.

2. The ECC protection control system of the AHB interface RAM according to claim 1, characterized in that The AHBtoRAM protocol conversion module (11) only includes a combinational logic circuit; The signal output ports HSEL and HWRITE of the AHBtoRAM protocol conversion module (11) are connected to the input port of the ECC RAM read-write control module (12); An input port HREADY of the AHBtoRAM protocol conversion module (11) is connected to an output port of the ECC RAM read-write control module (12); The RAM control and address data output port of the AHB to RAM protocol conversion module (11) is connected to the input port of the ECC RAM read-write control module (12).

3. The ECC protection control system of the AHB interface RAM according to claim 1, characterized in that: The write data input port of the RAM unit (13) is connected to the data output port of the ECC encoder (122); the data input port of the ECC encoder (122) is connected to the data output port of the ECC RAM read-write control module (12).

4. The ECC protection control system of the AHB interface RAM according to claim 1, characterized in that: The data input port of the register (124) is connected to the read data output port of the RAM unit (13), the data input port of the ECC decoder (123) is connected to the data output port of the register (124), and the data output port of the ECC decoder (123) is connected to the ECC RAM read and write control module (12).

5. The ECC protection control system of the AHB interface RAM according to claim 4, characterized in that: The data output port of the ECC decoder (123) is connected to the HRDATA input port of the AHBtoRAM protocol conversion module (11).

6. The ECC protection control system of the AHB interface RAM according to claim 1, characterized in that: The control signal input port of the RAM unit (13) is connected to the ECC RAM read-write control module (12).

7. An ECC protection control method for an AHB interface RAM, applied to the system according to any one of claims 1 to 6, characterized in that: The ECC RAM read / write control module (12) directly controls the AHB interface handshake signal HREADY; if the AHB interface continuously writes to the RAM, the ECC RAM read / write control module (12) dynamically adjusts the control behavior according to the size of the AHB write data; If the AHB interface reads the RAM continuously, the ECC RAM read-write control module (12) predicts the next read address and initiates the next RAM read operation in advance.

8. The ECC protection control method of the AHB interface RAM according to claim 7, characterized in that: If it is a continuous overall write, a write RAM operation is initiated in each dataphase, and the AHB signal HREADY remains at a high level.

9. The ECC protection control method of the AHB interface RAM according to claim 7, characterized in that: If the write mask is written continuously, the AHB signal HREADY is controlled to be high or low so that the next address read RAM operation and the previous address write RAM operation are initiated alternately.

10. The ECC protection control method of the AHB interface RAM according to claim 7, characterized in that: In the next clock cycle after initiating the first RAM read operation, the pre-read process is entered: the next address read RAM operation is initiated in advance, the size relationship of the two RAM read addresses is compared, and it is determined whether the RAM read address is in ascending or descending order, and the RAM read address is advanced in the subsequent clock cycle. The address is increased or decreased by 1 in each clock cycle based on the second read address. If the predicted RAM read address is inconsistent with the next actual RAM address read by AHB, the RAM read operation is re-initiated according to the actual RAM address, and the pre-read process is re-entered.

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