A vertical wire bonding and FC chip packaging method and structure

Abstract

This invention discloses a method and structure for packaging using vertical wire bonding and FC chips, belonging to the field of chip packaging technology. It eliminates the redundant design of the adapter board, which can reduce the thickness of the product package and meet the requirements of thinness and lightness. At the same time, due to the change in product size, the packaging cost can also be reduced. In addition, by using an FC chip instead of an adapter board, the product gains the performance of an additional chip, thereby improving the overall performance of the product.

Description

Technical Field

[0001] This invention belongs to the field of chip packaging technology, specifically a method and structure for chip packaging using vertical wire bonding and FC. Background Technology

[0002] Currently, POP (Package on Package) products mainly rely on traditional WB (wire bonding) and adapter boards (substrates) for packaging. In this process, the WB chip and adapter board are precisely bonded to the substrate, and wire bonding establishes a bond between the chip and the substrate, and between the adapter board and the substrate. The adapter board acts as a relay medium, primarily responsible for transmitting signals from one IC to another, enabling the effective combination of the two ICs.

[0003] However, when the adapter board only serves as a relay medium for communication, some problems may be encountered, such as signal attenuation during transmission, electromagnetic interference, and insufficient heat dissipation. These problems may affect the overall performance and reliability of the POP package. Summary of the Invention

[0004] This invention provides a method and structure for vertical wire bonding and FC chip packaging, which solves the problems of signal attenuation, electromagnetic interference and insufficient heat dissipation caused by the adapter board used in existing POP products, which only serves as a relay medium for communication.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A method for packaging chips using vertical wire bonding and FC (Flash Fibre) technology includes:

[0007] Arrange the substrate carrier, including the top substrate and the bottom substrate;

[0008] A chip layer and an FC chip are disposed on the bottom substrate;

[0009] Vertical wire bonding is used to connect the chip layer and FC chip to the top substrate to create a pathway and form a preliminary product;

[0010] The initial product is packaged, and the bottom substrate is removed after packaging.

[0011] Preferably, the bottom substrate is made of fiberglass board.

[0012] Preferably, the chip layer is connected to the top substrate via a FOW chip adhesive film.

[0013] Preferably, solder balls are arranged on the upper surface of the top substrate.

[0014] Preferably, each chip in the chip layer is connected to the top substrate via vertical wire bonding.

[0015] Preferably, the FC chip is bonded to the bottom substrate using chip adhesive.

[0016] Preferably, the FC chip has a bump on the side near the bottom substrate.

[0017] Preferably, a molding compound filler is used to fill the space between the top substrate and the bottom substrate.

[0018] Preferably, the chips on the chip layer are connected to each other by a chip adhesive film.

[0019] A vertical wire bonding and FC chip packaging structure is obtained by packaging based on a vertical wire bonding and FC chip packaging method.

[0020] Compared with the prior art, the present invention has the following beneficial effects: The present invention provides a method for packaging using vertical wire bonding and FC chip, which eliminates the redundant design of the adapter board, reduces the thickness of the product package, meets the requirements of thinness and lightness, and reduces the packaging cost due to the change in product size; in addition, by using FC chip instead of adapter board, the product gains the performance of an additional chip, thereby improving the overall performance of the product. Attached Figure Description

[0021] Figure 1 This is a flowchart of a method for packaging chips using vertical wire bonding and FC according to the present invention;

[0022] Figure 2 This is a front view of a packaging structure utilizing vertical wire bonding and FC chip according to the present invention;

[0023] Figure 3 This is a front view of the present invention after removing the underlying substrate using vertical wire bonding and FC chip packaging structure;

[0024] Figure 4 This is a top view of a vertical wire bonding and FC chip packaging structure according to the present invention;

[0025] Figure 5 This is a front view and external connection combination diagram of a vertical wire bonding and FC chip packaging structure according to the present invention.

[0026] In the diagram, 1-solder ball; 2-top substrate; 3-FOW chip adhesive film; 4-chip; 5-chip adhesive film; 6-bottom substrate; 7-chip adhesive; 8-FC chip bump; 9-FC chip; 10-bonding wire; 11-molding filler; 12-another IC Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0028] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0029] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0030] In the description of the embodiments of the present invention, it should be noted that if terms such as "upper," "lower," "horizontal," or "inner" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of the invention is in use, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Furthermore, terms such as "first" and "second" are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0031] Furthermore, the use of the term "horizontal" does not imply that the component must be absolutely horizontal, but rather that it can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0032] In the description of the embodiments of the present invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention according to the specific circumstances.

[0033] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings.

[0034] like Figure 3 As shown, the present invention provides a method for packaging chips using vertical wire bonding and FC (Flash Fibre) technology, comprising:

[0035] S101 arranges a substrate carrier, including a top substrate 2 and a bottom substrate 6;

[0036] S102 has a chip layer and an FC chip 9 disposed on the bottom substrate;

[0037] S103 uses vertical wire bonding to connect the chip layer and FC chip 9 to the top substrate 2 to form a preliminary product;

[0038] S104 encapsulates the initial product, and after encapsulation, removes the bottom substrate 6.

[0039] The bottom substrate 6 is made of fiberglass board.

[0040] Fiberglass sheets possess high strength, excellent insulation properties, and thermal stability, effectively supporting encapsulation structures and improving the reliability and stability of the encapsulation. Furthermore, they exhibit good processability, facilitating manufacturing and processing into the required shapes and sizes.

[0041] The chip layer is connected to the top substrate via FOW chip adhesive film.

[0042] FOW (Film Over Wire) die-attach films offer excellent electrical and mechanical strength, along with good thermal and chemical stability. This bonding method helps ensure a strong connection between the die layer and the top substrate, improving the overall reliability of the package.

[0043] Solder balls 1 are arranged on the upper surface of the top substrate 2.

[0044] Solder ball 1 serves as an external connection point, facilitating easy connection to other electronic components or circuit boards. This connection method features high density, low resistance, and low inductance, contributing to improved package electrical performance and signal transmission speed.

[0045] Each chip in the chip layer is connected to the top substrate 2 via vertical wire bonding.

[0046] Vertical wire bonding technology enables high-density, high-reliability connections between the chip layer and the top substrate. This connection method can significantly reduce package size and improve package integration and performance.

[0047] The FC chip 9 is bonded to the bottom substrate 6 using chip adhesive 7.

[0048] Chip adhesive 7 provides a strong bond, ensuring the stability and reliability of the FC chip 9 during the packaging process. It also provides cushioning and shock absorption, helping to protect the FC chip 9 from mechanical damage.

[0049] The FC chip 9 has a bump on the side near the bottom substrate 6, which can optimize the signal transmission path, reduce signal attenuation and reflection, and improve the electrical performance of the package.

[0050] A molding compound filler 11 is filled between the top substrate 2 and the bottom substrate 6.

[0051] The molding compound filler 11 provides additional mechanical support and protection, enhancing the overall structural strength of the package. Simultaneously, it prevents external factors such as moisture and dust from corroding and damaging the internal circuitry, improving the package's reliability and stability.

[0052] The chips on the chip layer are connected to each other by a chip adhesive film 5.

[0053] The chip adhesive film 5 provides a stable connection, ensuring electrical connections and signal transmission between chips on the chip layer. It also provides cushioning and shock absorption, helping to protect the chips from mechanical damage. Furthermore, this connection method simplifies the packaging process and reduces manufacturing costs.

[0054] The present invention also provides a packaging structure using vertical wire bonding and FC chip, which is obtained by packaging using a method of vertical wire bonding and FC chip.

[0055] Although embodiments of the present invention have been described above in conjunction with the accompanying drawings, the present invention is not limited to the specific embodiments and application fields described above. The specific embodiments described above are merely illustrative and instructive, and not restrictive. Those skilled in the art, guided by the specification, can make many other modifications without departing from the scope of the claims of the present invention, and all of these modifications are within the scope of protection of the present invention.

Claims

1. A method for packaging chips using vertical wire bonding and FC (Flash Fibre) technology, characterized in that, include: The substrate carrier is arranged, including a top substrate (2) and a bottom substrate (6). A chip layer and an FC chip are disposed on the bottom substrate (9); Vertical wire bonding is used to connect the chip layer and FC chip (9) to the top substrate (2) to form a preliminary product; The initial product is packaged, and the bottom substrate is removed after packaging (6). The FC chip (9) is bonded to the bottom substrate (6) by chip adhesive (7); The FC chip (9) has a bump on the side near the bottom substrate (6); A molding compound filler (11) is filled between the top substrate (2) and the bottom substrate (6).

2. The method for packaging FC chips using vertical wire bonding according to claim 1, characterized in that, The bottom substrate (6) is made of fiberglass board.

3. The method for packaging FC chips using vertical wire bonding according to claim 1, characterized in that, The chip layer is connected to the top substrate via FOW chip adhesive film (3).

4. The method for packaging chips using vertical wire bonding and FC according to claim 1, characterized in that, Solder balls (1) are arranged on the upper surface of the top substrate (2).

5. The method for packaging FC chips using vertical wire bonding according to claim 1, characterized in that, Each chip in the chip layer is connected to the top substrate (2) by vertical wire bonding.

6. The method for packaging FC chips using vertical wire bonding according to claim 1, characterized in that, The chips (4) on the chip layer are connected to each other by a chip adhesive film (5).

7. A packaging structure utilizing vertical wire bonding and FC chips, characterized in that, It is obtained by packaging using the vertical wire bonding and FC chip packaging method according to any one of claims 1-6.

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