Semiconductor device and manufacturing method thereof

Abstract

The embodiment of the invention relates to a semiconductor device and a manufacturing method thereof. A semiconductor device includes a semiconductor substrate, a multi-layer wiring structure formed on the semiconductor substrate, a guard ring formed so as to surround a circuit formation region and penetrate the multi-layer wiring structure, and a pad formed on the multi-layer wiring structure. A protective film is formed so as to cover the multilayer wiring structure, the guard ring, and the pad. The trench is formed so as to penetrate the protective film and reach the interior of the multilayer wiring structure. A trench is formed so as to surround the guard ring. The guard ring includes wiring formed on the multilayer wiring structure. The trench is spaced apart from and adjacent to the wiring. A bottom surface of the trench is inclined so as to continuously deepen in a direction from the circuit formation region toward a peripheral region surrounding the circuit formation region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2023-173746 filed on October 5, 2023, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. Background Art

[0003] The present invention relates to a semiconductor device and a method for manufacturing the same, and can be preferably used for, for example, a semiconductor device having a guard ring and a method for manufacturing the same.

[0004] In a semiconductor device, a protection structure called a guard ring or a seal ring is formed for preventing moisture from entering.

[0005] The disclosed techniques are listed below.

[0006] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2004-79596

[0007] Patent Document 1 describes a technique related to a semiconductor device having a seal ring. Patent Document 1 describes that an opening 123 is formed in a passivation film 120 so as to surround the outside of a seal ring 110 . Summary of the invention

[0008] In a semiconductor device having a guard ring, it is desired to improve reliability.

[0009] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

[0010] According to one embodiment, a semiconductor device includes a semiconductor substrate, a multilayer wiring structure formed on the semiconductor substrate, a protection ring formed so as to surround a circuit formation area and to penetrate the multilayer wiring structure, and a pad formed on the multilayer wiring structure. The semiconductor device also includes a protective film, which is formed so as to cover the multilayer wiring structure, the protection ring and the pad. The semiconductor device also includes a groove, which is formed so as to surround the protection ring, and is formed so as to penetrate the protection film and reach the inside of the multilayer wiring structure. The protection ring includes a first wiring, which is formed on the multilayer wiring structure so as to surround the circuit formation area. The bottom surface of the groove is inclined so as to continuously deepen in the direction from the circuit formation area toward the peripheral area surrounding the circuit formation area.

[0011] According to one embodiment, the reliability of a semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is an overall plan view of the semiconductor device of the first embodiment.

[0013] Figure 2 is a cross-sectional view of main parts of the semiconductor device of the first embodiment.

[0014] Figure 3 is a cross-sectional view of main parts of the semiconductor device of the first embodiment.

[0015] Figure 4 is a plan view illustrating a semiconductor substrate used in the manufacturing process of the semiconductor device of the first embodiment.

[0016] Figure 5 is a cross-sectional view of main parts in the manufacturing process of the semiconductor device of the first embodiment.

[0017] Figure 6 It is the successor Figure 5 A cross-sectional view of the main components following the semiconductor device manufacturing process.

[0018] Figure 7 It is the successor Figure 6 A cross-sectional view of the main components following the semiconductor device manufacturing process.

[0019] Figure 8 It is the successor Figure 7 A cross-sectional view of the main components following the semiconductor device manufacturing process.

[0020] Fig. 9 It is the successor Figure 8 A cross-sectional view of the main components following the semiconductor device manufacturing process.

[0021] Fig.10 It is the successor Fig. 9 A cross-sectional view of the main components after the manufacturing process of a semiconductor device.

[0022] Fig.11 It is the successor Fig.10 A cross-sectional view of the main components following the semiconductor device manufacturing process.

[0023] Fig.12 is a cross-sectional view of main parts of the semiconductor device of the study example.

[0024] Fig.13 is a cross-sectional view of main parts in the manufacturing process of the semiconductor device of the first embodiment.

[0025] Fig.14 It is the successor Fig.13 A cross-sectional view of the main components following the semiconductor device manufacturing process.

[0026] Fig.15 It is the successor Fig.14A cross-sectional view of the main components following the semiconductor device manufacturing process.

[0027] Fig.16 It is the successor Fig.15 A cross-sectional view of the main components following the semiconductor device manufacturing process.

[0028] Fig.17 It is the successor Fig.16 A cross-sectional view of the main components following the semiconductor device manufacturing process.

[0029] Fig.18 is a cross-sectional view of main parts of a semiconductor device which is a modification of the first embodiment.

[0030] Fig.19 is a cross-sectional view of main parts of a semiconductor device of a second embodiment.

[0031] Fig. 20 is a cross-sectional view of main parts of a semiconductor device of a modification of the second embodiment.

[0032] Fig.21 is a cross-sectional view of main parts in the manufacturing process of the semiconductor device of the second embodiment.

[0033] Fig. 22 It is the successor Fig.21 A cross-sectional view of the main components following the semiconductor device manufacturing process.

[0034] Fig.23 It is the successor Fig. 22 A cross-sectional view of the main components following the semiconductor device manufacturing process.

[0035] Fig.24 It is the successor Fig.23 A cross-sectional view of the main components following the semiconductor device manufacturing process.

[0036] Fig.25 It is the successor Fig.24 A cross-sectional view of the main components following the semiconductor device manufacturing process.

[0037] Fig.26 It is the successor Fig.25 A cross-sectional view of the main components following the semiconductor device manufacturing process.

[0038] Fig. 27 is a cross-sectional view of main parts of the semiconductor device of the third embodiment.

[0039] Fig.28 is a cross-sectional view of main parts of a semiconductor device of a modification of the third embodiment.

[0040] Fig.29 is a cross-sectional view of main parts during the manufacturing process of the semiconductor device of the third embodiment.

[0041] Fig.30 It is the successor Fig.29 A cross-sectional view of the main components following the semiconductor device manufacturing process.

[0042] Fig.31 It is the successor Fig.30 A cross-sectional view of the main components following the semiconductor device manufacturing process. DETAILED DESCRIPTION

[0043] In the following embodiments, when necessary for convenience, a description divided into multiple parts or embodiments will be given, but unless otherwise specified, these parts or embodiments are not independent of each other, and one is a modification of another, details, supplementary description, etc. Some or all of the relationship. In addition, in the following embodiments, when the number of elements, etc. (including number, numerical value, amount, range, etc.) is mentioned, unless otherwise specified or clearly limited to a specific number in principle, the number is not limited to a specific number, and the number can be equal to or greater than the specific number, or can be equal to or less than the specific number. In addition, in the following embodiments, it is self-evident that components (including element steps, etc.) are not necessarily necessary unless otherwise specified or are considered to be obviously necessary in principle. Similarly, in the following embodiments, when the shape, positional relationship, etc. of components, etc. are mentioned, unless otherwise specified or unless clearly considered in principle, it is assumed that the contents of those substantially approximate or similar to the shape, etc. are included. This also applies to the above-mentioned numerical value and range.

[0044] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. Note that in all the drawings used to describe the embodiments, components having the same function are represented by the same reference numerals, and repeated descriptions thereof will be omitted. In addition, in the following embodiments, the description of the same or similar components will not be repeated in principle unless it is particularly necessary.

[0045] In addition, in the drawings used in the embodiments, hatching may be omitted to make the drawings easy to see even in cross-sectional views. In addition, hatching may be applied to make the drawings easy to see even in plan views.

[0046] (First embodiment)

[0047] <Structure of semiconductor device>

[0048] A semiconductor device according to the present embodiment will be described with reference to the drawings. Figure 1 : is an overall plan view of the semiconductor device CP according to the present embodiment. Figure 2is a cross-sectional view of the main parts of the semiconductor device CP according to the present embodiment. Figure 1 The cross-sectional view taken along line AA in Figure 2 Corresponding. Figure 1 In FIG. 1 , the position of the guard ring GR is indicated by a double-dashed line, and the position of the trench TR is indicated by a dotted line. Figure 1 In FIG. 1 , the circuit forming region CR and the peripheral region PR are hatched. Figure 1 In FIG. 1 , the hatching direction of the circuit forming region CR and the hatching direction of the peripheral region PR are different from each other. Figure 2 In FIG. 1 , the left end of the semiconductor device CP is the side surface SM of the semiconductor device CP. When the semiconductor wafer is cut along the dicing region, the side surface SM of the semiconductor device CP corresponds to the cutting surface. Figure 2 , the right end of the semiconductor device CP corresponds to a position inside the semiconductor device CP, not a side surface of the semiconductor device CP. Figure 3 It's a picture. Figure 2 is a cross-sectional view of a portion of Figure 2 The structure above the interlayer insulating film L4.

[0049] like Figure 1 As shown, the semiconductor device (semiconductor chip) CP includes a circuit forming region CR, a peripheral region PR located on the periphery (periphery) of the circuit forming region CR, a guard ring GR formed in the peripheral region PR, and a trench TR formed in the peripheral region PR. The guard ring may also be referred to as a seal ring.

[0050] Various circuits are formed in the circuit forming region CR. In a plan view, the peripheral region PR surrounds the circuit forming region CR. That is, in a plan view, the peripheral region PR corresponds to a region between the side surface SM of the semiconductor device CP and the circuit forming region CR.

[0051] Note that the term “planar view” refers to a case of observing in a plane parallel to the main surface of the semiconductor substrate SB constituting the semiconductor device CP.

[0052] In a plan view, the guard ring GR is formed in the peripheral region PR of the semiconductor device CP so as to surround the circuit formation region CR. That is, the guard ring GR is formed along the periphery of the semiconductor device CP.

[0053] In plan view, trench TR is formed in peripheral region PR of semiconductor device CP so as to surround guard ring GR. Trench TR and guard ring GR extend in parallel along the periphery of semiconductor device CP, and trench TR is located between side surface SM of semiconductor device CP and guard ring GR in plan view.

[0054] Next, we will refer to Figure 2 and Figure 3 A specific configuration of the semiconductor device CP of the present embodiment is described.

[0055] like Figure 2 As shown, the semiconductor device CP of the present embodiment includes a semiconductor substrate SB made of single crystal silicon or the like, a multilayer wiring structure formed on the semiconductor substrate SB, a pad PD formed on the multilayer wiring structure, a wiring M6a formed on the multilayer wiring structure, and a protective film PA formed on the multilayer wiring structure. The protective film PA is formed so as to cover the multilayer wiring structure, the pad PD, and the guard ring GR. Here, the multilayer wiring structure corresponds to a wiring structure including a plurality of wiring layers.

[0056] like Figure 2 As shown, a semiconductor element such as a metal insulator semiconductor field effect transistor (MISFET) 2 is formed on a semiconductor substrate SB. The main surface of the semiconductor substrate SB has the above-mentioned circuit formation region CR and a peripheral region PR, and the semiconductor element such as the MISFET 2 is formed in the circuit formation region CR.

[0057] For example, an element isolation region ST is formed on a semiconductor substrate SB by a shallow trench isolation (STI) method or the like, and the MISFET 2 is formed in an active region of the semiconductor substrate SB defined by the element isolation region ST. The MISFET 2 includes a source region SR and a drain region DR formed on the semiconductor substrate SB, and a gate electrode GE formed on the semiconductor substrate SB via a gate insulating film.

[0058] Furthermore, here, MISFET is described as an example of a semiconductor element, but a capacitance element, a resistance element, a memory element, a transistor having another configuration, or the like may also be formed.

[0059] A multilayer wiring structure (multilayer wiring layer) including a plurality of interlayer insulating films and a plurality of wiring layers is formed on the main surface of the semiconductor substrate SB.

[0060] That is, multiple interlayer insulating films L1, L2, L3, L4, L5, L6 and L7 are stacked on the semiconductor substrate SB, and wirings M1, M1a, M1b, M2, M2a, M2b, M3, M3a, M3b, M4, M4a, M4b, M5, M5a and M5b are formed in the multiple interlayer insulating films L1, L2, L3, L4, L5, L6 and L7.

[0061] Specifically, the interlayer insulating film L2 is formed on the interlayer insulating film L1, the interlayer insulating film L3 is formed on the interlayer insulating film L2, the interlayer insulating film L4 is formed on the interlayer insulating film L3, the interlayer insulating film L5 is formed on the interlayer insulating film L4, the interlayer insulating film L6 is formed on the interlayer insulating film L5, and the interlayer insulating film L7 is formed on the interlayer insulating film L6. The interlayer insulating film L7 is the uppermost interlayer insulating film among the multiple interlayer insulating films of the multilayer wiring structure. Note that each of the interlayer insulating films L1, L2, L3, L4, L5, L6, and L7 may be a single-layer insulating film or a stacked insulating film including a plurality of insulating films.

[0062] Wirings M1, M1a, and M1b are wirings of a first wiring layer. The first wiring layer is the lowest wiring layer among a plurality of wiring layers included in a multilayer wiring structure. Wirings M2, M2a, and M2b are wirings of a second wiring layer, which is a wiring layer one layer higher than the first wiring layer. Wirings M3, M3a, and M3b are wirings of a third wiring layer, which is a wiring layer one layer higher than the second wiring layer. Wirings M4, M4a, and M4b are wirings of a fourth wiring layer, which is a wiring layer one layer higher than the third wiring layer. Wirings M5, M5a, and M5b are wirings of a fifth wiring layer, which is a wiring layer one layer higher than the fourth wiring layer. The fifth wiring layer is the highest wiring layer among a plurality of wiring layers included in a multilayer wiring structure. Note that the number of wiring layers included in a multilayer wiring structure is not limited to five layers.

[0063] The via portion V1 is embedded in the interlayer insulating film L1. Figure 2 In the case of, each of the wirings M1, M1a, M1b, M2, M2a, M2b, M3, M3a, M3b, M4, M4a, and M4b is a damascene wiring. Therefore, the wirings M1, M1a, and M1b are embedded in the interlayer insulating film L2, the wirings M2, M2a, and M2b are embedded in the interlayer insulating film L3, the wirings M3, M3a, and M3b are embedded in the interlayer insulating film L4, and the wirings M4, M4a, and M4b are embedded in the interlayer insulating film L5. In addition, the wirings M1, M1a, M1b, M2, M2a, M2b, M3, M3a, M3b, M4, M4a, and M4b may be wirings formed by patterning a conductive film.

[0064] exist Figure 2 In the case of , the wirings M5, M5a and M5b are wirings formed by patterning the conductive film. Therefore, the wirings M5, M5a and M5b are formed on the interlayer insulating film L6. The via portions V2 and V2a are embedded in the interlayer insulating film L6. The wiring M5 is connected to the wiring M4 via the via portion V2. The wiring M5a is connected to the wiring M4a via the via portion V2a. The wirings M5, M5a and M5b may be damascene wirings.

[0065] In a plan view, wirings M1, M2, M3, M4, and M5 are formed in the circuit formation region CR, and wirings M1a, M1b, M2a, M2b, M3a, M3b, M4a, M4b, M5a, and M5b are formed in the peripheral region PR.

[0066] The pad (pad electrode) PD and the wiring M6a are formed on the interlayer insulating film L7. In a plan view, the pad PD is formed in the circuit formation region CR, and the wiring M6a is formed in the peripheral region PR. The pad PD is connected to the wiring M5 via the via portion V3 embedded in the opening of the interlayer insulating film L7. The wiring M6a is connected to the wiring M5a via the via portion V3a embedded in the opening of the interlayer insulating film L7.

[0067] The pad PD and the wiring M6a are formed in the same layer. That is, the pad PD and the wiring M6a are formed by patterning a common conductive film. The pad PD and the wiring M6a are not connected and are separated from each other.

[0068] The insulating protection film PA is formed on the interlayer insulating film L7 so as to cover the pad PD and a portion of the wiring M6a. The protection film PA is a passivation film. The protection film PA is composed of a single-layer insulating film or a stacked insulating film of a plurality of insulating films. Figure 3 In the case of , the protection film PA is composed of a stacked film of the silicon nitride film NT and the silicon oxide film OX on the silicon nitride film NT.

[0069] The entire wiring M6a is covered by the protective film PA. That is, the wiring M6a is not exposed from the protective film PA. At least a part of the pad PD is exposed from the opening OP1 of the protective film PA.

[0070] The pad PD exposed from the opening OP1 of the protection film PA serves as an external terminal of the semiconductor device CP. For example, a conductive connection member such as a bonding wire may be connected to the pad PD exposed from the opening OP1 of the protection film PA.

[0071] Furthermore, a base metal film (not shown) may be formed on the pad PD, and the base metal film on the pad PD may be exposed from the opening OP1 of the protection film PA. The base metal film is composed of, for example, a stacked film of a nickel (Ni) film and a gold (Au) film on the nickel (Ni) film.

[0072] The wiring M6a and the pad PD are preferably made of a metal material containing aluminum (Al) as a main component (main component). In this case, the pad PD is an aluminum pad, and the wiring M6a is an aluminum wiring.

[0073] In addition, if Figure 1 , Figure 2 and Figure 3 As shown, a guard ring GR is formed in the peripheral region PR of the semiconductor device CP. The guard ring GR is formed so as to penetrate the multilayer wiring structure.

[0074] The guard ring GR is formed of wirings (metal patterns) M1a, M2a, M3a, M4a, M5a, and M6a for a guard ring and via portions V1a, V2a, and V3a for a guard ring.

[0075] exist Figure 2 In the case of, the wirings M2, M2a, M2b, M3, M3a, M3b, M4, M4a and M4b are respectively dual damascene wirings. Therefore, each of the wirings M2a, M3a and M4a for the guard ring includes a via portion integrally. The wirings M2, M2a, M2b, M3, M3a, M3b, M4, M4a and M4b may be single damascene wirings.

[0076] The thickness of the wire M6a for the guard ring is the same as the thickness of the pad PD. Therefore, the thickness of the wire M6a for the guard ring is greater than the thickness of each of the guard ring wires M1a, M2a, M3a, M4a, and M5a.

[0077] The guard ring GR is formed into a metal wall shape by the wiring M1a, M2a, M3a, M4a, M5a and M6a for the guard ring and the via portions V1a, V2a and V3a for the guard ring. That is, by arranging the wiring M6a for the guard ring, the via portion V3a, the wiring M5a, the via portion V2a, the wiring M4a, the wiring M3a, the wiring M2a, the wiring M1a and the via portion V1a in the vertical direction, the guard ring GR is formed into a metal wall shape.

[0078] As described above, in a plan view, the guard ring GR is formed in the peripheral region PR of the semiconductor device CP so as to surround the circuit formation region CR. Therefore, in a plan view, the wiring M6a, the via portion V3a, the wiring M5a, the via portion V2a, the wiring M4a, the wiring M3a, the wiring M2a, the wiring M1a, and the via portion V1a for the guard ring are formed in the peripheral region PR of the semiconductor device CP so as to surround the circuit formation region CR.

[0079] By providing the guard ring GR, moisture can be prevented from entering from the side surface SM of the semiconductor device by the guard ring GR. That is, the guard ring GR has a function of blocking moisture from entering. Therefore, by providing the guard ring GR, the reliability of the semiconductor device can be improved.

[0080] The wiring M1a, M2a, M3a, M4a, M5a and M6a for the guard ring and the via portions V1a, V2a and V3a are formed to form the guard ring GR and do not have the function of connecting a semiconductor element or a circuit. On the other hand, the wiring M1, M2, M3, M4 and M5 are formed to connect a semiconductor element or a circuit.

[0081] In addition, in a plan view, wirings M1b, M2b, M3b, M4b, and M5b as dummy wirings are formed in the peripheral region PR. The dummy wirings are not electrically connected to the semiconductor element formed on the semiconductor substrate SB, are not connected to the pad PD, and do not constitute the guard ring GR. Therefore, each of the wirings M1b, M2b, M3b, M4b, and M5b is not electrically connected to any of the wirings M1, M2, M3, M4, and M5, and is not electrically connected to any of the wirings M1a, M2a, M3a, M4a, M5a, and M6a for the guard ring. Each of the wirings M1b, M2b, M3b, M4b, and M5b is a dummy wiring electrically independent of the other wirings.

[0082] The trench TR is formed on the surface of the semiconductor device CP. The trench TR is adjacent to the wiring M6a and is spaced apart from the wiring M6a.

[0083] like Figure 2 and Figure 3 As shown, the trench TR is formed so as to penetrate the protective film PA and reach the inside of the multilayer wiring structure. Figure 2 and Figure 3 In the case of , the trench TR is formed so as to penetrate the protective film PA and reach the inside of the interlayer insulating film L7, and the bottom surface BS of the trench TR is located in the middle of the thickness of the interlayer insulating film L7. In this case, the interlayer insulating film L7 is exposed on the bottom surface BS of the trench TR. The trench TR may be formed so as to penetrate the protective film PA and the interlayer insulating film L7 and reach the inside of the interlayer insulating film L6. In this case, the interlayer insulating film L6 is exposed on the bottom surface BS of the trench TR.

[0084] The trench TR has a function of suppressing or preventing cracks from occurring in the multilayer wiring structure in the circuit forming region CR in a dicing step (cutting step) when manufacturing the semiconductor device CP. The trench TR will be described in detail later.

[0085] <Semiconductor Device Manufacturing Process>

[0086] Next, an example of a manufacturing process of the semiconductor device of the present embodiment will be described. Figures 1 to 3 The semiconductor device CP shown can be manufactured by the following manufacturing process. Figure 4 1 is a plan view illustrating a semiconductor substrate SB used in a manufacturing process of the semiconductor device according to the present embodiment. Figures 5 to 11 is a cross-sectional view of main components in the manufacturing process of the semiconductor device of this embodiment, and illustrates Figure 2 The corresponding cross section.

[0087] First, if Figure 4 and Figure 5 As shown, a semiconductor substrate SB made of single-crystal silicon, etc. is prepared. At this stage, the semiconductor substrate SB is a substantially disk-shaped semiconductor wafer.

[0088] like Figure 4 As shown, the semiconductor substrate SB includes a plurality of chip regions 1A as regions where semiconductor chips (semiconductor devices CP) are to be obtained and a dicing region 1B between adjacent chip regions 1A, and each chip region 1A is surrounded by the dicing region 1B in a plan view. That is, in the semiconductor substrate SB, a plurality of chip regions 1A are arranged in an array, and the region between adjacent chip regions 1A corresponds to the dicing region 1B. In a cutting step (cutting step) to be described later, each chip region 1A is divided by cutting (cutting) the semiconductor substrate SB along the dicing region 1B, and a semiconductor chip (semiconductor device CP) is obtained.

[0089] Next, a semiconductor element such as a MISFET 2 is formed in each chip region 1A of the semiconductor substrate SB. Hereinafter, an example of a process of forming the MISFET 2 will be briefly described.

[0090] like Figure 6 As shown, the element isolation region ST is formed on the semiconductor substrate SB using the STI method, etc. Next, the gate electrode GE is formed on the semiconductor substrate SB via a gate insulating film. Next, the source region SR and the drain region DR are formed on the semiconductor substrate SB by ion implantation.

[0091] Next, if Figure 7 As shown, a multilayer wiring structure including a plurality of interlayer insulating films L1, L2, L3, L4, L5, L6 and L7 and a plurality of wiring layers is formed on the semiconductor substrate SB. Hereinafter, an example of steps of forming the multilayer wiring structure will be described.

[0092] like Figure 7As shown, the interlayer insulating film L1 is formed on the semiconductor substrate SB so as to cover the MISFET 2. Next, the via portion V1 is embedded in the interlayer insulating film L1. Next, the interlayer insulating film L2 is formed on the interlayer insulating film L1, and then the wirings M1, M1a and M1b are buried in the interlayer insulating film L2. Next, the interlayer insulating film L3 is formed on the interlayer insulating film L2, and then the wirings M2, M2a and M2b are buried in the interlayer insulating film L3. Next, the interlayer insulating film L4 is formed on the interlayer insulating film L3, and then the wirings M3, M3a and M3b are buried in the interlayer insulating film L4. Next, the interlayer insulating film L5 is formed on the interlayer insulating film L4, and then the wirings M4, M4a and M4b are embedded in the interlayer insulating film L5. Next, after the interlayer insulating film L6 is formed on the interlayer insulating film L5, the via portions V2 and V2a are embedded in the interlayer insulating film L6. Next, the wirings M5, M5a, and M5b are formed on the interlayer insulating film L6. Next, the interlayer insulating film L7 is formed on the interlayer insulating film L6 so as to cover the wirings M5, M5a, and M5b, and then the via portions V3 and V3a are buried in the interlayer insulating film L7. In this way, a multilayer wiring structure can be formed.

[0093] Next, if Figure 8 As shown, the pad PD and the wiring M6a are formed on the interlayer insulating film L7. For example, the pad PD and the wiring M6a can be formed by forming a conductive film on the interlayer insulating film L7 and then patterning the conductive film.

[0094] In a plan view, wirings M1, M2, M3, M4, and M5 and pads PD are formed in the circuit formation region CR in each chip region 1a, and wirings M1a, M2a, M3a, M4a, M5a, and M6a are formed in the peripheral region PR in each chip region 1A. In a plan view, wirings M1b, M2b, M3b, M4b, and M5b are formed in the dicing region 1B and the peripheral region PR in each chip region 1A.

[0095] In a plan view, a guard ring GR including wirings M1a, M2a, M3a, M4a, M5a, and M6a for a guard ring and via portions V1a, V2a, and V3a is formed in each chip region 1A. In a plan view, the guard ring GR is formed in the peripheral region PR in each chip region 1A so as to surround the circuit forming region CR.

[0096] Next, if Fig. 9 As shown, the protection film PA is formed on the interlayer insulating film L7 so as to cover the pad PD and the wiring M6a.

[0097] Next, if Fig.10As shown, an opening OP1 and a trench TR are formed. The opening OP1 and the trench TR may be formed using a photolithography technique and an etching technique. The opening OP1 is formed so as to penetrate the protection film PA, and at least a portion of the pad PD is exposed from the opening OP1 of the protection film PA.

[0098] The trench TR is formed so as to penetrate the protective film PA and reach the inside of the multilayer wiring structure. Fig.10 In the case of , the trench TR is formed so as to penetrate the protective film PA and reach the inside of the interlayer insulating film L7, and the bottom surface BS of the trench TR is located in the middle of the thickness of the interlayer insulating film L7. In this case, the interlayer insulating film L7 is exposed on the bottom surface BS of the trench TR. The trench TR may be formed so as to penetrate the protective film PA and the interlayer insulating film L7 and reach the inside of the interlayer insulating film L6. In this case, the interlayer insulating film L6 is exposed on the bottom surface BS of the trench TR.

[0099] In a plan view, a trench TR is formed in the peripheral region PR in each chip region 1A so as to surround the guard ring GR.

[0100] Next, if Fig.11 As shown, the cutting step is performed to cut the semiconductor substrate SB and the structure (multilayer wiring structure) on the semiconductor substrate SB along the dicing area 1B. Thus, a semiconductor device CP is obtained from each chip area 1A of the semiconductor substrate SB. The cut surface obtained by cutting corresponds to the side surface SM of the semiconductor device CP. Note that the thickness of the semiconductor substrate SB can be reduced by grinding the back surface of the semiconductor substrate SB before the cutting step.

[0101] <Research History>

[0102] Fig.12 is a cross-sectional view of main parts of a semiconductor device of a research example studied by the inventors of the present application, and illustrates Figure 3 The corresponding cross section.

[0103] exist Fig.12 In the semiconductor device of the research example shown, a trench TR101 is formed instead of the trench TR. The bottom surface BS101 of the trench TR101 is parallel to the main surface of the semiconductor substrate SB. Therefore, the depth of the bottom surface BS101 of the trench TR101 is constant regardless of the position in the trench TR101. The trench TR101 is formed so as to penetrate the protective film PA and reach the inside of the multilayer wiring structure.

[0104] In the cutting step when manufacturing a semiconductor device, there is a concern that cracks are generated on the cutting surface by the cutting blade and extend to the multilayer wiring structure of the chip region 1A. Since wirings M1, M2, M3, M4, and M5 electrically connected to the semiconductor element or circuit are formed in the multilayer wiring structure of the circuit forming region CR, it is necessary to prevent cracks from occurring in the multilayer wiring structure of the circuit forming region CR.

[0105] The groove TR101 has a function of suppressing or preventing cracks from being generated on the cut surface by the cutting blade in the cutting step and the cracks from extending to the multilayer wiring structure in the chip region 1A. This is because, if the groove TR101 is formed, cracks may appear below the groove TR101 with the groove TR101 as the starting point or the end point. In the cutting step, by intentionally generating cracks below the groove TR101 with the groove TR101 as the starting point or the end point, the cracks generated in the cut surface can be suppressed or prevented from developing to the multilayer wiring structure in the circuit formation region CR.

[0106] However, according to the research of the inventors of this application, it has been found that Fig.12 The following problems arise in the case of the research example shown.

[0107] In the case of the studied example, in the cutting step, cracks may occur with the corner K101 or the corner K102 of the trench TR101 as a start point or an end point.

[0108] Note that the corner K101 is formed by the bottom surface BS101 of the trench TR101 and the side surface S101 of the trench TR101. The corner K102 is formed by the bottom surface BS101 of the trench TR101 and the side surface S102 of the trench TR101. The side surface S101 of the trench TR101 and the side surface S102 of the trench TR101 face each other. In a plan view, the distance (interval) between the corner K101 of the trench TR101 and the wiring M6a is greater than the distance (interval) between the corner K102 of the trench TR101 and the wiring M6a.

[0109] The probability of occurrence of a crack starting or ending at the corner K101 of the trench TR101 is substantially the same as the probability of occurrence of a crack starting or ending at the corner K102 of the trench TR101. Then, compared with the case where the crack occurs at the corner K101 of the trench TR101 as the starting or ending point, in the case where the crack occurs at the corner K102 of the trench TR101 as the starting or ending point, the distance between the crack and the circuit forming region CR is short. Therefore, compared with the case where the crack occurs at the corner K101 of the trench TR101 as the starting or ending point, in the case where the crack occurs at the corner K102 of the trench TR101 as the starting or ending point, the possibility that the crack affects the multilayer wiring structure of the circuit forming region CR is high. Since the wirings M1, M2, M3, M4, and M5 electrically connected to the semiconductor element or circuit are formed in the multilayer wiring structure of the circuit formation region CR, in order to improve the reliability of the semiconductor device, it is desirable to minimize the possibility that cracks generated with the trench TR101 as the starting point or end point affect the multilayer wiring structure of the circuit formation region CR. Therefore, in order to improve the reliability of the semiconductor device, it is desirable to generate cracks with the corner K101 of the trench TR101 as the starting point or end point instead of the corner K102 of the trench TR101 in the cutting step.

[0110] In addition, the groove TR101 is formed in order to intentionally generate cracks with the groove TR101 as the starting point or the end point in the cutting step. When the depth of the groove TR101 is shallow, cracks with the groove TR101 as the starting point or the end point in the cutting step are unlikely to occur. When the thickness of the protective film PA increases, the depth of the groove TR101 increases, and the generation of cracks with the groove TR101 as the starting point or the end point is promoted in the cutting step. However, increasing the thickness of the protective film PA increases the cost required to form the protective film PA, resulting in an increase in the manufacturing cost of the semiconductor device. Therefore, in order to suppress the manufacturing cost of the semiconductor device, it is expected that even when the depth of the groove TR101 is shallow, cracks with the groove TR101 as the starting point or the end point may occur in the cutting step.

[0111] Therefore, the inventors of the present application have studied the shape of the trench TR101 , and found that it is desirable to form the trench TR in place of the trench TR101 in the present embodiment.

[0112] <Structure of trench TR>

[0113] Reference Figures 1 to 3 The structure of the trench TR formed in the semiconductor device according to the present embodiment is described.

[0114] like Figure 1 As shown, in a plan view, a trench TR is formed in the peripheral region PR of the semiconductor device CP so as to surround the guard ring GR.

[0115] In the dicing step, by intentionally generating cracks below the trench TR with the trench TR as a start point or an end point, cracks generated by the dicing blade on the cutting surface can be suppressed or prevented from developing into the multilayer wiring structure in the circuit forming region CR.

[0116] In the present embodiment, the bottom surface BS of the trench TR is not parallel to the main surface of the semiconductor substrate SB, but is inclined relative to the main surface of the semiconductor substrate SB. Specifically, the bottom surface BS of the trench TR is formed to be inclined so as to continuously deepen in the direction from the circuit formation region CR toward the peripheral region PR. In other words, the depth of the bottom surface BS of the trench TR is the smallest (shallowest) at the corner K2, gradually increases (deepest) from the corner K2 toward the corner K1, and becomes the largest (deepest) at the corner K1. As a result, in the cutting step, cracks may appear not with the corner K2 of the trench TR but with the corner K1 of the trench TR as the starting point or end point.

[0117] The inclination angle of bottom surface BS of trench TR relative to the main surface of semiconductor substrate SB is, for example, equal to or greater than 3 degrees. In addition, the difference between the depth of bottom surface BS at corner K1 and the depth of bottom surface BS at corner K2 is, for example, equal to or greater than 0.2 micrometers.

[0118] Note that the corner K1 is formed by the bottom surface BS of the groove TR and the side surface S1 of the groove TR. The corner K2 is formed by the bottom surface BS of the groove TR and the side surface S2 of the groove TR. The corner K1 and the corner K2 are positioned on two sides opposite to each other via the bottom surface BS in the direction from the circuit formation area CR toward the peripheral area PR. The side surface S1 of the groove TR and the side surface S2 of the groove TR face each other, and in the side surfaces S1 and S2 of the groove TR, the side surface S2 of the groove TR is closer to the wiring M6a than the side surface S1 of the groove TR. That is, in a plan view, the distance (interval) between the side surface S1 of the groove TR and the wiring M6a is greater than the distance (interval) between the side surface S2 of the groove TR and the wiring M6a. Therefore, in a plan view, the distance (interval) between the corner K1 of the groove TR and the wiring M6a is greater than the distance (interval) between the corner K2 of the groove TR and the wiring M6a. Furthermore, in a plan view, the distance (interval) between the corner K1 of the trench TR and the circuit forming region CR is larger than the distance (interval) between the corner K2 of the trench TR and the circuit forming region CR.

[0119] In the present embodiment, the probability of occurrence of a crack starting or ending at the corner K1 of the trench TR is greater than the probability of occurrence of a crack starting or ending at the corner K2 of the trench TR. Then, in the case where the crack occurs starting or ending at the corner K1 of the trench TR, the distance between the crack and the circuit forming region CR is larger than in the case where the crack occurs starting or ending at the corner K2 of the trench TR. Therefore, in the case where the crack occurs starting or ending at the corner K1 of the trench TR, the possibility of the crack affecting the multilayer wiring structure in the circuit forming region CR is low, compared with the case where the crack occurs starting or ending at the corner K2 of the trench TR.

[0120] In the present embodiment, the bottom surface BS of the trench TR is formed to be inclined so as to continuously deepen in the direction from the circuit forming region CR toward the peripheral region PR. Therefore, in the cutting step, the probability of occurrence of cracks with the corner K2 of the trench TR as the starting point or the end point can be suppressed, and the probability of occurrence of cracks with the corner K1 of the trench TR as the starting point or the end point can be increased. As a result, cracks can be preferentially generated not at the corner K2 of the trench TR, but at the corner K1 of the trench TR, so that cracks can be suppressed or prevented from affecting the multilayer wiring structure in the circuit forming region CR. Therefore, the reliability of the semiconductor device can be improved.

[0121] In addition, since the bottom surface BS of the trench TR is formed to be inclined so as to continuously deepen in the direction from the circuit formation region CR toward the peripheral region PR, the trench TR is more likely to generate cracks in the cutting step than the trench TR101. That is, when the depth of the corner K1 of the trench TR is the same as the depth of the corners K101 and K102 of the trench TR101, the trench TR is more likely to generate cracks than the trench TR101. Therefore, in the present embodiment, even when the depth of the trench TR is shallow, in the cutting step, cracks may be generated with the corner K1 of the trench TR as the starting point or the end point. Therefore, in the present embodiment, even when the thickness of the protective film PA is small, in the cutting step, cracks may be generated with the corner K1 of the trench TR as the starting point or the end point. When the thickness of the protective film PA is reduced, the time and cost required to form the protective film PA can be suppressed, and the manufacturing cost of the semiconductor device can be suppressed. In addition, since the trench TR can be made shallow, excessive over-etching can be prevented in the etching step for forming the trench TR and the opening OP1.

[0122] The thickness of the protective film PA is, for example, 0.4 μm to 2.5 μm. As described above, even when the thickness of the protective film PA is thin, cracks having the corner K1 of the trench TR as a start point or an end point can be accurately generated in the cutting step.

[0123] In addition, the multilayer wiring structure formed on the main surface of the semiconductor substrate SB preferably includes a plurality of low dielectric constant insulating films. Therefore, the parasitic capacitance between the plurality of wirings included in the multilayer wiring structure can be reduced. For example, a low dielectric constant insulating film can be used as the interlayer insulating films L2, L3, L4 and L5, and a silicon oxide film can be used as the interlayer insulating films L1, L6 and L7.

[0124] The low dielectric constant insulating film is made of a low dielectric constant material (low-k material). The low dielectric constant material has a lower dielectric constant than silicon oxide.

[0125] The low dielectric constant insulating film can be, for example, SiOF obtained by adding fluorine (F) to a silicon oxide film, SiOC obtained by adding carbon (C) to a silicon oxide film, SiCH, SiOCH or SiCN of a material containing carbon (C) and silicon (Si), polysiloxane composed of silicon (Si) and oxygen (O), polyparaxylene or polyarylether as an organic polymer material, methyl silsesquioxane (MSQ), methyl hydrogen silsesquioxane (MHSQ), or benzocyclobutene (BCB) as an aromatic organic material, a porous material obtained by introducing pores into these materials, or a stacked film of these materials.

[0126] The low dielectric constant insulating film has low adhesion. For this reason, when the multilayer wiring structure includes a plurality of low dielectric constant insulating films, cracks may extend through the interface between the insulating films, and thus there is a concern that the cracks extend to the multilayer wiring structure in the circuit forming region CR. However, even in the case where the multilayer wiring structure includes a plurality of low dielectric constant insulating films, by forming the trench TR, it is possible to accurately prevent the cracks from extending to the multilayer wiring structure in the circuit forming region CR.

[0127] <Step of Forming Trench TR>

[0128] Will refer to Figures 13 to 17 An example of a process of forming the trench TR is described. Figures 13 to 17 is a cross-sectional view of main components in a manufacturing process of the semiconductor device according to the present embodiment.

[0129] like Fig. 9 and Fig.13 As shown, the protection film PA is formed on the interlayer insulating film L7 so as to cover the pad PD and the wiring M6a. Fig.13 It is a graphic with Fig. 9 It is a cross-sectional view of the same step, and illustrates the structure above the interlayer insulating film L4.

[0130] The wiring M6a has a side surface MS1 and a side surface MS2 opposite to the side surface MS1. The side surface MS1 of the wiring M6a is a side surface of the inner periphery of the wiring M6a, and the side surface MS2 of the wiring M6a is a side surface of the outer periphery of the wiring M6a. In a plan view, the pad PD faces the side surface MS1 of the wiring M6a. In a plan view, the side surface MS2 of the wiring M6a faces the dicing area 1B.

[0131] exist Fig.13 In the case of , the protection film PA is composed of a stacked film of the silicon nitride film NT and the silicon oxide film OX on the silicon nitride film NT. Each of the silicon nitride film NT and the silicon oxide film OX can be formed using, for example, a CVD method.

[0132] Next, if Fig.14 As shown, a photoresist layer PT1 is formed on the protection film PA.

[0133] A step caused by the wiring M6a is formed on the surface of the protective film PA, and the photoresist layer PT1 is formed so as to cover the step. Reflecting this, the photoresist layer PT1 has a region PT1a, and in a plan view, between the wiring M6a and the scribe area 1B, the thickness of the photoresist layer PT1 gradually decreases as the distance from the side surface MS2 of the wiring M6a increases. The region PT1a is located near the wiring M6a. The thickness of the photoresist layer PT1 in the region PT1a is the largest near the side surface MS2 of the wiring M6a, and gradually decreases as the distance from the side surface MS2 of the wiring M6a increases. That is, in the region PT1a, the photoresist layer PT1 has a trailing shape.

[0134] Next, if Fig.15 As shown, after the photoresist layer PT1 is exposed using a photomask (not shown), the photoresist layer PT1 is developed to form openings OP2 and OP3 in the photoresist layer PT1.

[0135] The opening OP2 is an opening for forming the opening OP1. In a plan view, the opening OP2 is formed in the predetermined area where the opening OP1 is formed. Therefore, in a plan view, the opening OP2 is included in the pad PD. The photoresist layer PT1 is not retained at the bottom of the opening OP2, and the opening OP2 is formed so as to penetrate the photoresist layer PT1.

[0136] The opening OP3 is an opening or a groove for forming the trench TR. In a plan view, the opening OP3 is formed in a trench TR formation predetermined region. In a plan view, the opening OP3 is formed in a region PT1a of the photoresist layer PT1.

[0137] In a plan view, the shortest distance (closest distance) between the opening OP3 and the wiring M6a is, for example, 0.1 micrometers to 1.5 micrometers. The groove TR is formed to align with the opening OP3. Therefore, in a plan view, the shortest distance (closest distance) between the groove TR and the wiring M6a is 0.1 micrometers to 1.5 micrometers. In addition, the thickness of the wiring M6a is, for example, 0.5 micrometers to 1.5 micrometers.

[0138] The opening OP3 has a side surface OP3a and a side surface OP3b facing each other. Of the side surfaces OP3a and OP3b of the opening OP3, the side surface OP3b is positioned closer to the wiring M6a than the side surface OP3a. That is, in a plan view, the distance (interval) between the side surface OP3a of the opening OP3 and the wiring M6a is greater than the distance (interval) between the side surface OP3b of the opening OP3 and the wiring M6a.

[0139] A portion of the photoresist layer PT1 remains at the bottom of the opening OP3. This can be implemented by adjusting the exposure amount in the exposure process of the photoresist layer PT1.

[0140] In a plan view, the opening OP3 is formed in the region PT1a of the photoresist layer PT1. Reflecting this, at the bottom of the opening OP3, the remaining thickness of the photoresist layer PT1 is the largest near the side surface OP3b of the opening OP3, and gradually decreases in the direction from the side surface OP3b of the opening OP3 toward the side surface OP3a of the opening OP3. As a result, the bottom surface OP3c of the opening OP3 is inclined relative to the main surface of the semiconductor substrate SB. Specifically, the bottom surface OP3c of the opening OP3 is inclined so as to gradually deepen in the direction from the side surface OP3b of the opening OP3 toward the side surface OP3a of the opening OP3.

[0141] Next, if Fig.16 As shown, by using the photoresist layer PT1 as an etching mask, the protection film PA and the interlayer insulating film L7 are etched to form the opening OP1 and the trench TR. Hereinafter, this etching step is referred to as an etching step using the photoresist layer PT1. The opening OP1 is formed by etching the protection film PA below the opening OP2, and the trench TR is formed by etching the protection film PA and the multilayer wiring structure below the opening OP3. Thereafter, as shown in FIG. Fig.17 As shown, the photoresist layer PT1 is removed by ashing or the like.

[0142] In the etching step using the photoresist layer PT1, the protection film PA exposed from the opening OP2 of the photoresist layer PT1 is etched to form the opening OP1 of the protection film PA. Therefore, the opening OP1 of the protection film PA is formed aligned with the opening OP2 of the photoresist layer PT1. A portion of the pad PD is exposed from the opening OP1 of the protection film PA.

[0143] In the etching step using the photoresist layer PT1, the photoresist layer PT1 remaining at the bottom of the opening OP3 is etched and removed, and in addition, the protective film PA exposed from the opening OP3 of the photoresist layer PT1 and the interlayer insulating film L7 under the protective film PA are etched. Therefore, the trench TR is formed so as to penetrate the protective film PA and reach the inside of the multilayer wiring structure. The trench TR is formed to be aligned with the opening OP3 of the photoresist layer PT1. That is, the side surface S1 of the trench TR is formed to be aligned with the side surface OP3a of the opening OP3 of the photoresist layer PT1, and the side surface S2 of the trench TR is formed to be aligned with the side surface OP3b of the opening OP3 of the photoresist layer PT1.

[0144] As described above, before the etching step using the photoresist layer PT1, the remaining thickness of the photoresist layer PT1 at the bottom of the opening OP3 of the photoresist layer PT1 gradually decreases in the direction from the side surface OP3b of the opening OP3 toward the side surface OP3a of the opening OP3. Reflecting this, after the etching step using the photoresist layer PT1, the bottom surface BS of the trench TR is inclined relative to the main surface of the semiconductor substrate SB. Specifically, the bottom surface BS of the trench TR is inclined so as to gradually deepen in the direction from the side surface S2 of the trench TR toward the side surface S1 of the trench TR.

[0145] In this way, the trench TR and the opening OP1 can be formed. The bottom surface BS of the trench TR is formed to be inclined so as to continuously deepen in the direction from the side surface S2 of the trench TR to the side surface S1 of the trench TR. In other words, the depth of the bottom surface BS of the trench TR is shallowest at the corner K2, gradually deepens from the corner K2 toward the corner K1, and becomes deepest at the corner K1. As a result, in the cutting step performed subsequently, with the corner K1 of the trench TR as the starting point or the end point, cracks are likely to occur.

[0146] Note that the direction from the side surface S2 to the side surface S1 of the trench TR, the direction from the circuit formation region CR to the peripheral region PR, and the direction from the circuit formation region CR to the dicing region 1B are the same.

[0147] Thereafter, by performing the dicing step as described above, the semiconductor substrate SB and the structures on the semiconductor substrate SB are cut along the dicing region 1B.

[0148] <Edit>

[0149] Fig.18 1 is a cross-sectional view illustrating main parts of a semiconductor device according to a modification of the present embodiment. Fig.18 In the figure, the structure below the interlayer insulating film L3 is omitted.

[0150] exist Fig.18 In the case of the modification shown, the wiring M4b (hereinafter, referred to as the wiring M4b1) as a dummy wiring is arranged below the corner K1 of the trench TR. In addition, the wiring M4b as a dummy wiring is not arranged below the corner K2 of the trench TR. Therefore, in a plan view, the corner K1 of the trench TR overlaps with the wiring M4b1, but the corner K2 of the trench TR does not overlap with the wiring M4b.

[0151] In addition, a wiring M3b (hereinafter, referred to as wiring M3b1) as a dummy wiring is arranged below the wiring M4b1, the wiring M4b1 is arranged below the corner K1 of the trench TR, and a wiring M2b (hereinafter, referred to as wiring M2b1) as a dummy wiring is arranged below the wiring M3b1. In a plan view, the shape of each of the wirings M4b1, M3b1, and M2b1 is, for example, a rectangular isolation pattern or a linear pattern.

[0152] Note that, in plan view, the wiring M3b1 partially overlaps with the wiring M4b1, but the wiring M3b1 deviates from the wiring M4b1 in the direction from the circuit formation region CR toward the peripheral region PR. In plan view, the amount of deviation of the wiring M3b1 from the wiring M4b1 is, for example, half the width of the wiring M3b1 or less. In addition, in plan view, the wiring M2b1 partially overlaps with the wiring M3b1, but the wiring M2b1 deviates from the wiring M3b1 in the direction from the circuit formation region CR toward the peripheral region PR. In plan view, the amount of deviation of the wiring M2b1 from the wiring M3b1 is, for example, half the width of the wiring M2b1 or less.

[0153] Therefore, in the cutting step, the cracks that have entered from the cutting surface by the cutting blade can be guided along the surface of the dummy wiring (here, the wiring M2b1, the wiring M3b1, and the wiring M4b1) to reach the corner K1 of the groove TR. As a result, the cracks that have entered from the cutting surface by the cutting blade can be suppressed or prevented from extending to the multilayer wiring structure in the circuit forming region CR. Therefore, the performance of the semiconductor device can be improved.

[0154] Fig.18 The technical idea of ​​the modification shown can also be applied to the second embodiment and the third embodiment described later.

[0155] (Second embodiment)

[0156] The semiconductor device of the second embodiment is different from the semiconductor device of the first embodiment in the structure of the trench TR. Except for this, the semiconductor device of the second embodiment has a structure similar to that of the semiconductor device of the first embodiment.

[0157] Will refer to Fig.19 The structure of the trench TR formed in the semiconductor device of the second embodiment is described. Fig.19 is a cross-sectional view of the main parts of the semiconductor device of the second embodiment, and illustrates Figure 3 Corresponding cross-sectional view. Similar to Figure 3 , also in Fig.19 In the figure, the structure below the interlayer insulating film L5 is not illustrated. In addition, in the following description, the difference between the trench TR in the second embodiment and the trench TR in the first embodiment will be mainly described.

[0158] In the second embodiment, the bottom surface BS of the trench TR is substantially parallel to the main surface of the semiconductor substrate SB. In the second embodiment, the sub-trench STR is formed at the corner K1 of the trench TR. No sub-trench is formed at the corner K2 of the trench TR.

[0159] The width of the sub-trench STR is smaller than the width of the trench TR. Here, each of the width of the trench TR and the width of the sub-trench STR corresponds to the width in the direction parallel to the main surface of the semiconductor substrate SB and in the direction from the side surface S1 of the trench TR to the side surface S2. The width of the trench TR is the distance (interval) between the side surface S1 and the side surface S2 of the trench TR.

[0160] In the second embodiment, the sub-groove STR is formed at the corner K1 of the trench TR, and the sub-groove is not formed at the corner K2 of the trench TR. As a result, in the cutting step, cracks may occur not with the corner K2 of the trench TR but with the corner K1 of the trench TR as the starting point or end point.

[0161] In the second embodiment, the sub-groove STR is formed at the corner K1 of the trench TR, and the sub-groove is not formed at the corner K2 of the trench TR. Therefore, in the cutting step, cracks can be preferentially generated with the sub-groove STR of the trench TR as the starting point or the end point. As a result, cracks can be suppressed or prevented from affecting the multilayer wiring structure in the circuit forming region CR. Therefore, the reliability of the semiconductor device can be improved.

[0162] In addition, in the second embodiment, since the sub-groove STR is formed at the corner K1 of the trench TR, the trench TR in the second embodiment is more likely to generate cracks in the cutting step than the trench TR101 in the study example. That is, when the depth of the bottom surface BS of the trench TR is the same as the depth of the bottom surface BS101 of the trench TR101, the trench TR is more likely to generate cracks than the trench TR101. Therefore, in the second embodiment, even when the depth of the trench TR is shallow, cracks with the sub-groove STR of the trench TR as the starting point or end point may be generated in the cutting step. Therefore, in the second embodiment, even when the thickness of the protective film PA is small, cracks with the sub-groove STR of the trench TR as the starting point or end point may be generated in the cutting step. When the thickness of the protective film PA is reduced, the cost required to form the protective film PA can be suppressed, and the manufacturing cost of the semiconductor device can be suppressed. In addition, since the trench TR can be made shallower, excessive over-etching can be prevented in the etching step for forming the trench TR and the opening OP1.

[0163] The trench TR has a slit shape. Fig.19 In the case of , the sub-groove STR also has a slit shape. That is, Fig.19 As shown, in a cross-sectional view perpendicular to the extending direction of the trench TR, a bottom portion of the trench TR other than the sub-trench STR is flat, and a bottom portion of the sub-trench STR is also flat.

[0164] Fig. 20 is a cross-sectional view of main parts of a semiconductor device according to a modification of the second embodiment; Fig. 20 In the case of , the sub-groove STR has a peak shape. That is, Fig. 20 As shown, in a cross-sectional view perpendicular to the extending direction of the trench TR, the shape of the sub-trench STR is a shape having a sharp tip portion. Note that the bottom portion of the sub-trench STR corresponds to the tip portion of the peak shape.

[0165] exist Fig.19 situation and Fig. 20 In both cases, in the cutting step, cracks can be preferentially generated with the sub-groove STR of the groove TR as the starting point or the end point.

[0166] Next, we will refer to Fig.13 and Figure 21 to Figure 26 An example of a process of forming the trench TR in the second embodiment is described. Figure 21 to Figure 26 is a cross-sectional view of main parts in the manufacturing process of the semiconductor device of the second embodiment.

[0167] As in the first embodiment, also in the second embodiment, Fig.13As shown, the protection film PA is formed on the interlayer insulating film L7 so as to cover the pad PD and the wiring M6a.

[0168] Next, if Fig.21 As shown, after the photoresist layer PT2 is formed on the protective film PA, the photoresist layer PT2 is subjected to exposure processing and development processing to form an opening OP4 in the photoresist layer PT2. The opening OP4 is formed so as to penetrate the photoresist layer PT2. In a plan view, the opening OP4 is formed in a predetermined area for forming the sub-groove STR. The opening OP2 is not formed in the photoresist layer PT2.

[0169] Next, if Fig. 22 As shown, the silicon oxide film OX exposed from the opening OP4 of the photoresist layer PT2 is etched to form an opening OP5 in the silicon oxide film OX. The opening OP5 of the silicon oxide film OX is formed so as to match the opening OP4 of the photoresist layer PT2. Therefore, the opening OP5 of the silicon oxide film OX is formed in the sub-groove STR formation predetermined area.

[0170] Next, if Fig.23 As shown, the photoresist layer PT2 is removed by ashing or the like.

[0171] Next, if Fig.24 As shown, after the photoresist layer PT3 is formed on the protection film PA, the photoresist layer PT3 is subjected to exposure processing and development processing to form openings OP2 and OP6 in the photoresist layer PT3. The openings OP2 and OP6 are formed so as to penetrate the photoresist layer PT3.

[0172] The opening OP6 is an opening for forming the trench TR. In a plan view, the opening OP3 is formed in the trench TR formation predetermined region. Therefore, in a plan view, the opening OP5 of the silicon oxide film OX is included in the opening OP6 of the photoresist layer PT3.

[0173] Next, if Fig.25 As shown in FIG. 1 , the opening OP1 and the trench TR are formed by etching the protective film PA and the interlayer insulating film L7 using the photoresist layer PT3 as an etching mask. Hereinafter, this etching step is referred to as an etching step using the photoresist layer PT3. Fig.26 As shown, the photoresist layer PT3 is removed by ashing or the like.

[0174] In the etching step using the photoresist layer PT3, the protection film PA exposed from the opening OP2 of the photoresist layer PT3 is etched to form the opening OP1 of the protection film PA. Part of the pad PD is exposed from the opening OP1 of the protection film PA.

[0175] In the etching step using the photoresist layer PT3, the protective film PA exposed from the opening OP6 of the photoresist layer PT3 and the interlayer insulating film L7 under the protective film PA are etched to form the trench TR and the sub-trench STR. After the opening OP5 of the silicon oxide film OX is formed in the sub-trench STR formation predetermined area, the sub-trench STR is formed at the corner K1 of the trench TR, which reflects the etching step using the photoresist layer PT3.

[0176] In this way, the trench TR and the opening OP1 can be formed. The sub-groove STR is formed at the corner K1 of the trench TR, and the sub-groove is not formed at the corner K2 of the trench TR. As a result, in the cutting step performed later, cracks are likely to occur with the sub-groove STR of the trench TR as the starting point or end point.

[0177] Thereafter, by performing the dicing step as described above, the semiconductor substrate SB and the structures on the semiconductor substrate SB are diced along the dicing region 1B.

[0178] (Third Embodiment)

[0179] The semiconductor device of the third embodiment is different from the semiconductor devices of the first and second embodiments in the structure of the trench TR. Except for this, the semiconductor device of the third embodiment has a structure similar to that of the semiconductor devices of the first and second embodiments.

[0180] Reference Fig. 27 The structure of the trench TR formed in the semiconductor device of the third embodiment is described. Fig. 27 is a cross-sectional view of the main parts of the semiconductor device of the third embodiment, and illustrates Figure 3 and Fig.19 Corresponding cross-sectional view. Similar to Figure 3 , also in Fig. 27 In the figure, the structure below the interlayer insulating film L5 is not illustrated. In addition, in the following description, the difference between the trench TR in the third embodiment and the trench TR in the first embodiment will be mainly described.

[0181] The trench TR in the third embodiment corresponds to the case where the sub-trench STR in the second embodiment is formed in the trench TR in the first embodiment. That is, similarly to the first embodiment, also in the third embodiment, the bottom surface BS of the trench TR is inclined relative to the main surface of the semiconductor substrate SB. In addition, similarly to the second embodiment, also in the third embodiment, the sub-trench STR is formed at the corner K1 of the trench TR. No sub-trench is formed at the corner K2 of the trench TR.

[0182] Therefore, if Fig. 27As shown, between the corner K2 of the trench TR and the sub-trench STR, the bottom surface BS of the trench TR is formed to be inclined so as to continuously deepen in the direction from the circuit formation region CR toward the peripheral region PR. In other words, the depth of the bottom surface BS of the trench TR is the smallest (shallowest) at the corner K2, and gradually becomes larger (deeper) from the corner K2 toward the sub-trench STR.

[0183] In the third embodiment, since the bottom surface BS of the trench TR is inclined similarly to that in the first embodiment, and the sub-trench STR is formed at the corner K1 of the trench TR, in the cutting step, cracks may occur with the sub-trench STR formed at the corner K1 of the trench TR as a starting point or an end point. That is, compared with the trench TR in the first embodiment and the trench TR in the second embodiment, the trench TR in the third embodiment is more likely to generate cracks in the cutting step. Therefore, it is also possible to suppress or prevent the cracks from affecting the multilayer wiring structure in the circuit forming region CR. Therefore, it is also possible to improve the reliability of the semiconductor device.

[0184] In addition, in the third embodiment, even when the depth of the trench TR is shallow, cracks may be generated in the cutting step with the sub-groove STR of the trench TR as the starting point. Therefore, in the third embodiment, even when the thickness of the protective film PA is small, cracks may be generated in the cutting step with the sub-groove STR of the trench TR as the starting point. When the thickness of the protective film PA is reduced, the cost required to form the protective film PA can be suppressed, and the manufacturing cost of the semiconductor device can be suppressed. In addition, since the trench TR can be made shallower, excessive over-etching can be prevented in the etching step for forming the trench TR and the opening OP1.

[0185] Similar to Fig.19 The sub groove STR, Fig. 27 The sub-groove STR has a slit shape.

[0186] Fig.28 is a cross-sectional view of main parts of a semiconductor device according to a modification of the third embodiment. Fig. 20 The sub groove STR, Fig.28 The sub-groove STR has a peak shape. Fig. 27 situation and Fig.28 In both cases, in the cutting step, cracks can be preferentially generated with the sub-groove STR of the groove TR as the starting point or the end point.

[0187] Next, we will refer to Fig.13 , Fig.14 and Figure 29 to Figure 31 An example of a process of forming the trench TR in the third embodiment is described. Figure 29 to Figure 31is a cross-sectional view of main parts during the manufacturing process of the semiconductor device of the third embodiment.

[0188] Similar to the first embodiment, in the third embodiment, Fig.13 As shown, the protection film PA is formed on the interlayer insulating film L7 so as to cover the pad PD and the wiring M6a.

[0189] Next, similar to the first embodiment, also in the third embodiment, as Fig.14 As shown, a photoresist layer PT1 is formed on the protection film PA.

[0190] Next, if Fig.29 As shown, after the photoresist layer PT1 is exposed using a photomask (not shown), the photoresist layer PT1 is developed to form openings OP2 and OP3 in the photoresist layer PT1.

[0191] The opening OP2 in the third embodiment is similar to the opening OP2 in the first embodiment. The opening OP3 in the third embodiment is different from the opening OP3 in the first embodiment in the following points.

[0192] In a plan view, the photoresist layer PT1 is not retained in the predetermined area for forming the sub-groove STR. That is, at the bottom of the opening OP3, the photoresist layer PT1 is not retained near the side surface OP3a of the opening OP3, and the protective film PA is exposed. In a plan view, between the side surface OP3b of the opening OP3 and the predetermined area for forming the sub-groove STR, the remaining thickness of the photoresist layer PT1 is the largest near the side surface OP3b of the opening OP3, and gradually decreases in a direction from the side surface OP3b of the opening OP3 toward the side surface OP3a of the opening OP3. As a result, in a plan view, between the side surface OP3b of the opening OP3 and the predetermined area for forming the sub-groove STR, the bottom surface OP3c of the opening OP3 is inclined so as to gradually deepen in a direction from the side surface OP3b of the opening OP3 toward the side surface OP3a of the opening OP3. In a plan view, the bottom surface OP3c of the opening OP3 is formed by the surface of the photoresist layer PT1 between the side surface OP3b of the opening OP3 and the sub-groove STR formation predetermined region. On the other hand, in the sub-groove STR formation predetermined region, the bottom surface OP3c of the opening OP3 is formed by the upper surface of the protective film PA.

[0193] Next, if Fig.30 As shown, by using the photoresist layer PT1 as an etching mask, the protection film PA and the interlayer insulating film L7 are etched to form the opening OP1 and the trench TR. Hereinafter, this etching step is referred to as an etching step using the photoresist layer PT1. Fig.31As shown, the photoresist layer PT1 is removed by ashing or the like.

[0194] In the etching step using the photoresist layer PT1, the protection film PA exposed from the opening OP2 of the photoresist layer PT1 is etched to form the opening OP1 of the protection film PA. Part of the pad PD is exposed from the opening OP1 of the protection film PA.

[0195] In the etching step using the photoresist layer PT1, the photoresist layer PT1 remaining at the bottom of the opening OP3 is etched and removed, and further, the protective film PA exposed from the opening OP3 of the photoresist layer PT1 and the interlayer insulating film L7 under the protective film PA are etched. Thus, the trench TR is formed so as to penetrate the protective film PA and reach the inside of the multilayer wiring structure.

[0196] As described above, before the etching step using the photoresist layer PT1, in a plan view, between the side surface OP3b of the opening OP3 and the predetermined area for forming the sub-groove STR, the remaining thickness of the photoresist layer PT1 gradually decreases in the direction from the side surface OP3b of the opening OP3 toward the side surface OP3a of the opening OP3. Reflecting this, after the etching step using the photoresist layer PT1, in a plan view, between the side surface S2 of the trench TR and the sub-groove STR, the bottom surface BS of the trench TR is inclined so as to gradually deepen in the direction from the side surface S2 of the trench TR toward the side surface S1 of the trench TR. In addition, before the etching step using the photoresist layer PT1, the sub-groove STR is formed at the corner K1 of the trench TR by the etching step using the photoresist layer PT1, which reflects that the photoresist layer PT1 does not remain in the predetermined area for forming the sub-groove STR in a plan view.

[0197] In this way, the opening OP1, the trench TR, and the sub-groove STR can be formed. Between the side surface S2 of the trench TR and the sub-groove STR, the bottom surface BS of the trench TR is formed to be inclined so as to continuously deepen in the direction from the side surface S2 of the trench TR toward the side surface S1 of the trench TR. In other words, the depth of the bottom surface BS of the trench TR is shallowest at the corner K2, and gradually deepens as it approaches the sub-groove STR from the corner K2. Then, the sub-groove STR is formed at the corner K1 of the trench TR. As a result, in the cutting step performed subsequently, cracks may occur with the sub-groove STR formed at the corner K1 of the trench TR as the starting point or end point.

[0198] Thereafter, by performing the dicing step as described above, the semiconductor substrate SB and the structures on the semiconductor substrate SB are cut along the dicing region 1B.

[0199] Although the invention made by the inventors of the present application has been specifically described based on the embodiments, the present invention is not limited to these embodiments, and it goes without saying that various modifications can be made without departing from the gist of the present invention.

Claims

1. A semiconductor device, comprising: a semiconductor substrate having a main surface; a circuit forming region formed on the main surface; a peripheral region formed on the periphery of the circuit forming region in a plan view; a multilayer wiring structure formed on the main surface and including a plurality of insulating films and a plurality of wiring layers; a guard ring formed in the peripheral region so as to surround the circuit formation region and so as to penetrate the multilayer wiring structure; a pad formed on the multi-layer wiring structure; a protective film formed so as to cover the multilayer wiring structure, the guard ring, and the pad; as well as a groove formed in the peripheral region so as to surround the guard ring and formed so as to penetrate the protection film and reach the inside of the multilayer wiring structure, wherein the guard ring includes a first wiring formed on the multilayer wiring structure so as to surround the circuit formation area, wherein the groove is spaced apart from the first wiring and is adjacent to the first wiring, and A bottom surface of the groove is formed to be inclined so as to continuously deepen from the circuit forming region toward the peripheral region in a first direction.

2. The semiconductor device according to claim 1, wherein an inclination angle of the bottom surface of the trench relative to the main surface of the semiconductor substrate is equal to or greater than 3 degrees.

3. The semiconductor device according to claim 1, wherein the groove has a first corner and a second corner, the first corner and the second corner are located on two sides opposite to each other via the bottom surface in the first direction, wherein in a plan view, the distance between the first corner and the first wiring is greater than the distance between the second corner and the first wiring, and Wherein a sub-trench is formed at the first corner of the trench.

4. The semiconductor device according to claim 3, The sub-grooves have a slit shape.

5. The semiconductor device according to claim 3, The sub-grooves have a peak shape.

6. The semiconductor device according to claim 1, wherein the groove has a first corner and a second corner, the first corner and the second corner are located on two sides opposite to each other via the bottom surface in the first direction, wherein in a plan view, the distance between the first corner and the first wiring is greater than the distance between the second corner and the first wiring, and A dummy wiring is formed below the first corner in the multi-layer wiring structure, and the dummy wiring is electrically independent from other wirings.

7. The semiconductor device according to claim 1, The multilayer wiring structure includes a plurality of low dielectric constant insulating films.

8. The semiconductor device according to claim 1, The protective film is composed of a stacked film of a silicon nitride film and a silicon oxide film on the silicon nitride film.

9. The semiconductor device according to claim 1, The thickness of the protective film is 0.4 micrometers to 2.5 micrometers.

10. A semiconductor device comprising: a semiconductor substrate having a main surface; a circuit forming region formed on the main surface; a peripheral region formed on the periphery of the circuit forming region in a plan view; a multilayer wiring structure formed on the main surface and including a plurality of insulating films and a plurality of wiring layers; a guard ring formed in the peripheral region so as to surround the circuit formation region and so as to penetrate the multilayer wiring structure; a pad formed on the multi-layer wiring structure; a protective film formed so as to cover the multilayer wiring structure, the guard ring, and the pad; as well as a groove formed in the peripheral region so as to surround the guard ring and formed so as to penetrate the protection film and reach the inside of the multilayer wiring structure, wherein the guard ring includes a first wiring formed on the multilayer wiring structure so as to surround the circuit formation area, wherein the groove is spaced apart from the first wiring and is adjacent to the first wiring, wherein the groove has a first corner and a second corner, the first corner and the second corner being located on two sides opposite to each other via the bottom surface of the groove in a direction from the circuit forming region toward the peripheral region, wherein in a plan view, the distance between the first corner and the first wiring is greater than the distance between the second corner and the first wiring, and Wherein a sub-trench is formed at the first corner of the trench.

11. The semiconductor device according to claim 10, The sub-grooves have a slit shape.

12. The semiconductor device according to claim 10, The sub-grooves have a peak shape.

13. The semiconductor device according to claim 10, The protective film is composed of a stacked film of a silicon nitride film and a silicon oxide film on the silicon nitride film.

14. The semiconductor device according to claim 10, The thickness of the protective film is 0.4 micrometers to 2.5 micrometers.

15. A method for manufacturing a semiconductor device, the method comprising: (a) preparing a semiconductor substrate having a chip region from which a semiconductor chip is obtained and a dicing region surrounding the chip region; (b) forming a multi-layer wiring structure, a guard ring penetrating the multi-layer wiring structure, and a pad on the multi-layer wiring structure on the semiconductor substrate; (c) forming a protective film so as to cover the multilayer wiring structure, the guard ring and the pad; (d) forming a groove so as to penetrate the protective film and reach the inside of the multilayer wiring structure; and (e) cutting the semiconductor substrate and the multilayer wiring structure along the dicing region, wherein the multilayer wiring structure includes a plurality of insulating films and a plurality of wiring layers, wherein in step (b), the guard ring is formed in the chip region so as to surround a circuit forming area of ​​the chip region in a plan view, wherein in step (d), the trench is formed so as to surround the guard ring in the chip region in a plan view, wherein the guard ring includes a first wiring formed on the multilayer wiring structure so as to surround the circuit formation area, wherein the groove is spaced apart from the first wiring and is adjacent to the first wiring, and Wherein in step (d), the bottom surface of the groove is formed to be inclined so as to continuously deepen in a direction from the circuit forming region toward the dicing region.

16. The method for manufacturing a semiconductor device according to claim 15, Wherein step (d) comprises: (d1) forming a photoresist layer on the protective film; (d2) forming a first opening in the photoresist layer; as well as (d3) forming the groove by etching the protective film and the multilayer wiring structure below the first opening using the photoresist layer as an etching mask, wherein the first opening formed in step (d2) has a first side surface and a second side surface facing each other, and a portion of the photoresist layer remains in the first opening, wherein in a plan view, a distance between the first side surface and the first wiring is greater than a distance between the second side surface and the first wiring, and Wherein at a bottom portion of the first opening formed in step (d2), a remaining thickness of the photoresist layer gradually decreases in a direction from the second side surface of the first opening toward the first side surface of the first opening.

17. The method for manufacturing a semiconductor device according to claim 16, wherein the photoresist layer formed in step (d1) has a first region near the first wiring, the thickness of the first region decreases as the distance from the first wiring increases, and Wherein in step (d2), the first opening is formed in the first region of the photoresist layer.

18. The method for manufacturing a semiconductor device according to claim 16, wherein in step (d2), the first opening and the second opening are formed in a photoresist layer, and wherein in step (d3), the trench is formed by etching the protective film and the multilayer wiring structure below the first opening, and a third opening is formed in the protective film by etching the protective film below the second opening, and Part of the pad is exposed from the third opening of the protection film.

19. The method for manufacturing a semiconductor device according to claim 15, In a plan view, the shortest distance between the groove and the first wiring is 0.1 micrometers to 1.5 micrometers.

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