Chip packaging structure and method, heat dissipation cover processing method and electronic equipment

Abstract

The embodiment of the invention provides a chip packaging structure and method, a heat dissipation cover processing method and electronic equipment. The chip packaging structure comprises a packaging substrate; a plurality of types of chips; the chips of the same kind are connected with the packaging substrate through the salient point structures of the same kind; the plurality of types of chips are connected with the packaging substrate by adopting a plurality of types of salient point structures to form a packaging height difference, and the packaging height of the chips is the height between the top surfaces of the chips and the top surface of the packaging substrate after the chips are connected with the packaging substrate by adopting the salient point structures; the heat dissipation cover comprises a height difference compensation structure which is used for compensating the packaging height difference formed by the various types of chips, so that the various types of chips are in contact with the heat dissipation cover; wherein a height reference chip exists in the multiple types of chips, and the layout of the height difference compensation structure is determined according to the packaging height difference of other chips in the multiple types of chips relative to the height reference chip. According to the chip packaging structure provided by the embodiment of the invention, the flexibility of chip packaging is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor packaging technology, and specifically to a chip packaging structure, method, heat dissipation cover processing method and electronic equipment. Background Art

[0002] Multi-chip packaging technology is used to package multiple chips in the same chip packaging structure to achieve connection and collaborative work between multiple chips. To simplify the packaging process, when multiple chips are packaged, the same bump structure can be used, and multiple chips are designed to be highly consistent; among them, the bump structure is a connection structure used in the package to electrically connect the chip to the packaging substrate.

[0003] Although the above multi-chip packaging method simplifies the packaging process, it limits the flexibility of packaging. Therefore, how to provide a chip packaging structure to improve the flexibility of chip packaging has become a technical problem that technical personnel in this field need to solve urgently. Summary of the invention

[0004] In view of this, an embodiment of the present application provides a chip packaging structure, which can improve the flexibility of chip packaging.

[0005] To achieve the above objectives, the embodiments of the present application provide the following technical solutions.

[0006] In a first aspect, an embodiment of the present application provides a chip packaging structure, including:

[0007] Package substrate;

[0008] Multiple types of chips;

[0009] Multiple types of bump structures, similar chips are connected to the packaging substrate through the same type of bump structures; after multiple types of chips are connected to the packaging substrate using multiple types of bump structures, a packaging height difference is formed, and the chip packaging height is the height between the top surface of the chip and the top surface of the packaging substrate after the chip is connected to the packaging substrate using the bump structure;

[0010] A heat dissipation cover, wherein the heat dissipation cover comprises a height difference compensation structure for compensating for the packaging height difference formed by the multiple types of chips so that the multiple types of chips are all in contact with the heat dissipation cover; wherein there is a height reference chip among the multiple types of chips, and the layout of the height difference compensation structure is determined according to the packaging height difference of other chips in the multiple types of chips relative to the height reference chip.

[0011] Optionally, the height reference chip is a type of chip with the largest number of chips among the multiple types of chips, wherein the number of each type of chip among the multiple types of chips is at least one; and the area of ​​the heat dissipation cover corresponding to the height reference chip is set as a planar structure.

[0012] Optionally, the height difference compensation structure includes a protrusion structure and a groove structure;

[0013] The protruding structure corresponds to a low-position chip among the multiple types of chips, and the low-position chip is a chip among the multiple types of chips whose packaging height is lower than that of the height reference chip;

[0014] The groove structure corresponds to a high-position chip among the multiple types of chips, and the high-position chip is a chip among the multiple types of chips whose packaging height is higher than the height reference chip.

[0015] Optionally, it further includes: a connection layer, used to connect the top surface of the chip and the heat dissipation cover;

[0016] Among them, the planar structure of the heat dissipation cover is connected to the height reference chip through the connection layer; the protruding structure of the heat dissipation cover is connected to the low-position chip through the connection layer; and the groove structure of the heat dissipation cover is connected to the high-position chip through the connection layer.

[0017] Optionally, the height of the connection layer is set to: the height between the top surface of the height reference chip and the plane structure of the heat dissipation cover;

[0018] The protrusion height of the protrusion structure is set to: the height between the top surface of the low-position chip and the plane structure of the heat dissipation cover minus the height of the connection layer;

[0019] The groove height of the groove structure is set to: the height of the connection layer minus or plus the height between the top surface of the high-position chip and the plane structure of the heat dissipation cover.

[0020] Optionally, also include:

[0021] The bottom filling layer is used to fill the gap between the bottom surface of the chip and the packaging substrate.

[0022] Optionally, the connection layer is a welding layer, and the material of the welding layer is indium; the material of the bottom filling layer is epoxy resin.

[0023] Optionally, the multiple types of bump structures include at least solder bumps and copper pillar bumps.

[0024] In a second aspect, an embodiment of the present application provides a heat dissipation cover processing method, comprising: obtaining chip packaging design data, wherein the chip packaging design data comprises: chip parameters of multiple types of chips to be packaged, bump structure parameters of multiple types of bump structures, and adoption information of bump structure types adopted by various types of chips, wherein chips of the same type adopt the same type of bump structures to connect the packaging substrate;

[0025] According to the chip packaging design data, determine the height reference chip among the multiple types of chips, and the packaging height difference of other chips among the multiple types of chips relative to the height reference chip; wherein the packaging height of the chip is the height between the top surface of the chip and the top surface of the packaging substrate after the chip is connected to the packaging substrate using a bump structure, and the packaging height difference is formed after multiple types of chips are connected to the packaging substrate using multiple types of bump structures;

[0026] Determine processing parameters of the heat dissipation cover according to the package height difference, wherein the processing parameters at least include: layout parameters of a height difference compensation structure of the heat dissipation cover, wherein the height difference compensation structure is used to compensate for the package height difference formed by the multiple types of chips;

[0027] The heat dissipation cover is obtained by processing based on the processing parameters of the heat dissipation cover.

[0028] In a third aspect, an embodiment of the present application provides a chip packaging method, including:

[0029] Providing a packaging substrate;

[0030] Connecting multiple types of chips to a packaging substrate through multiple types of bump structures, wherein the same type of chips are connected to the packaging substrate through the same type of bump structures; after the multiple types of chips are connected to the packaging substrate through the multiple types of bump structures, a packaging height difference is formed, and the packaging height of the chip is the height between the top surface of the chip and the top surface of the packaging substrate after the chip is connected to the packaging substrate using the bump structure;

[0031] A heat sink is connected to the top surface of the multiple types of chips, and the heat sink includes a height difference compensation structure for compensating for the packaging height difference formed by the multiple types of chips, so that the multiple types of chips are all in contact with the heat sink; wherein there is a height reference chip among the multiple types of chips, and the layout of the height difference compensation structure is determined according to the packaging height difference of other chips in the multiple types of chips relative to the height reference chip.

[0032] In a fourth aspect, an embodiment of the present application provides an electronic device, wherein the electronic device includes the chip packaging structure described above.

[0033] The chip packaging structure provided in the embodiment of the present application includes: a packaging substrate; multiple types of chips; multiple types of bump structures, where chips of the same type are connected to the packaging substrate through the same type of bump structures; after the multiple types of chips are connected to the packaging substrate using the multiple types of bump structures, a packaging height difference will be formed, wherein the packaging height of the chip is the height between the top surface of the chip and the top surface of the packaging substrate after the chip is connected to the packaging substrate using the bump structure; a heat dissipation cover, wherein the heat dissipation cover is provided with a height difference compensation structure, which can be used to compensate for the packaging height difference formed by the multiple types of chips, so that the multiple types of chips are all in contact with the heat dissipation cover; wherein there is a height reference chip among the multiple types of chips, and the layout of the height difference compensation structure can be determined according to the packaging height difference of other chips in the multiple types of chips relative to the height reference chip.

[0034] It can be seen that the chip packaging structure provided in the embodiment of the present application can be applicable to multiple types of chips and multiple types of bump structures, wherein chips of the same type are connected to the packaging substrate through the same type of bump structure, thereby avoiding the need to use the same bump structure when packaging multiple chips and the situation where the height of each chip is consistent (i.e. avoiding the situation where multi-chip packaging is limited to packaging multiple chips of the same type), thereby improving the flexibility of chip packaging; that is, the chip packaging structure provided in the embodiment of the present application does not limit the type of chip and bump structure type applicable to the packaging. When chips of the same type are connected to the packaging substrate through the same type of bump structure, the embodiment of the present application supports multiple types of chips to be packaged using multiple types of bump structures, thereby reducing the applicability limitations of chip packaging and improving the flexibility of chip packaging. At the same time, since multiple types of chips will form a package height difference after connecting the package substrate using multiple types of bump structures, when designing the heat dissipation cover, the embodiment of the present application is provided with a height difference compensation structure on the heat dissipation cover, and the layout of the height difference compensation structure is determined according to the package height difference of other chips in the multiple types of chips used for packaging relative to the height reference chip, so that the height difference compensation structure can be used to compensate for the package height difference formed by the multiple types of chips, so that the multiple types of chips are all in contact with the heat dissipation cover, thereby ensuring the heat dissipation requirements of the multiple types of chips used for packaging. It can be seen that the embodiment of the present application can support the selection of multiple types of chips by multi-chip packaging technology, and ensure the heat dissipation requirements of multiple types of chips after packaging, so the embodiment of the present application can improve the flexibility of chip packaging and improve the heat dissipation performance of chip packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0036] Figure 1This is an example diagram of a chip packaging structure;

[0037] Figure 2 This is an example diagram of another chip packaging structure;

[0038] Figure 3 is another example diagram of a chip packaging structure;

[0039] Figure 4 is an example diagram of a chip packaging structure using a protruding structure;

[0040] Figure 5 is an example diagram of a chip packaging structure using a groove structure;

[0041] Figure 6 is based on Figure 4 A local enlarged view of the raised structure;

[0042] Figure 7 is based on Figure 5 A local enlarged view of the groove structure;

[0043] Figure 8 is based on Figure 5 Another partial enlarged view of the groove structure;

[0044] Fig. 9 is a flow chart of a heat dissipation cover processing method provided in an embodiment of the present application;

[0045] Fig.10 It is a flow chart of a chip packaging method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0047] Multi-chip packaging technology is used to package multiple chips in the same chip packaging structure, and considering the heat dissipation problem after the multiple chips are packaged, the multi-chip packaging technology can use a chip packaging structure with a heat dissipation cover design. In other words, the chip will generate heat when it is working. If the chip is not heat-dissipated, the excessive temperature of the chip will lead to problems such as chip performance degradation, shortened life, and reduced reliability. Therefore, in order to effectively manage and disperse the heat generated by the chip, the multi-chip packaging technology uses a chip packaging structure with a heat dissipation cover design when packaging multiple chips in the same chip packaging structure, so that the heat generated by multiple chips is absorbed and conducted through the heat dissipation cover.

[0048] To ensure heat dissipation performance, multiple chips used in the package must be in contact with the heat dissipation cover. Therefore, a multi-chip packaging method can be: the multiple chips used in the package are designed to be highly consistent, and the multiple chips are connected to the packaging substrate using the same bump structure, thereby ensuring that the multiple chips are in contact with the heat dissipation cover at the same height.

[0049] For ease of understanding, Figure 1 An example diagram of a chip packaging structure is shown, referring to Figure 1 , the chip packaging structure encapsulates a chip 101 and a chip 102, wherein the chip 101 and the chip 102 are designed to be of the same height; at the same time, the chip 101 and the chip 102 are connected to the packaging substrate 104 using the same bump structure 103. Since the chip 101 and the chip 102 are of the same height and use the same bump structure, after the chip 101 and the chip 102 are connected to the packaging substrate 104, the upper surfaces (i.e., the top surfaces) of the chip 101 and the chip 102 can contact the heat dissipation cover 105 at the same height, ensuring the effective contact between the chip 101 and the chip 102 and the heat dissipation cover, and further ensuring the heat dissipation treatment of the chip 101 and the chip 102 during the working process.

[0050] Figure 1 Although the chip packaging structure shown simplifies the packaging process, multi-chip packaging can only be applied to multiple chips with the same height and the same bump structure, which reduces the flexibility of chip packaging. Figure 1 The chip packaging structure shown is not suitable for different types of chips with inconsistent heights, and is not suitable for using multiple types of bump structures when packaging multiple chips, and has significant applicability limitations.

[0051] However, using multiple types of chips and multiple types of bump structures for multi-chip packaging will cause height differences between multiple chips during packaging, which will result in the heat sink being unable to effectively contact the chips used in the package. In other words, due to the inconsistency of the heights of multiple types of chips and the heights of multiple types of bump structures, height differences may occur when multiple types of chips and multiple types of bump structures are used in multi-chip packaging at the same time. For ease of understanding, Figure 2 Another example of a chip packaging structure is shown in FIG. Figure 2The chip 210 is connected to the packaging substrate 230 using a bump structure 211, and the chip 220 is connected to the packaging substrate 230 using a bump structure 222, wherein the heights of the chip 210 and the chip 220 are inconsistent (for example, the chip 210 and the chip 220 are chips of different types, so the heights of the chip 210 and the chip 220 are inconsistent), and the heights of the bump structure 211 and the bump structure 222 are inconsistent (for example, the bump structure 211 and the bump structure 222 are bump structures of different types, so the heights of the bump structure 211 and the bump structure 222 are inconsistent), so that a height difference is formed between the chip 210 and the chip 220 during packaging, and the height difference will cause the heat dissipation cover to be unable to effectively contact the chip 210 and the chip 220.

[0052] Therefore, when the multi-chip packaging technology supports the selection of multiple types of chips and multiple types of bump structures, the above-mentioned height difference problem needs to be solved to ensure heat dissipation performance. In view of this, the embodiment of the present application provides a chip packaging structure that can solve the above-mentioned height difference problem and meet the needs of multi-chip packaging of multiple types of different chips using multiple types of different bump structures, thereby improving the flexibility of chip packaging and ensuring heat dissipation performance. Figure 3 Another example of a chip packaging structure is shown in FIG. Figure 3 , the chip packaging structure may include:

[0053] The packaging substrate 300 can be used as a carrier for semiconductor chip packaging and can provide electrical connection, support, protection, heat dissipation and other functions for the chip.

[0054] Multiple types of chips, that is, the types of multiple chips used in the multi-chip package are of multiple types, that is, the embodiments of the present application support the packaging of multiple chips, and the chip types of the multiple chips belong to at least two categories; for example, the chip types of the multiple chips used in the package are different (that is, each chip belongs to a different type of chip), and for example, the chip types of the multiple chips used in the package are partially the same (that is, among the multiple chips used in the package, some chips have the same chip type, while another part of the chips have different chip types).

[0055] In an optional implementation, the different types of chips referred to in the embodiments of the present application may be chips of different chip heights. For example, chips of the same type have the same chip height, while chips of different chip heights are regarded as different types of chips.

[0056] For ease of example, Figure 3 Take four chips as an example, where two chips 312 are of the same type, that is, the heights of the two chips 312 are consistent. Figure 3 The chip 311, the two chips 312 and the chip 313 shown are of different chip types; it should be noted that Figure 3Only four chips are used as an example for illustration. The embodiment of the present application supports no limit on the number of multiple chips that can be packaged, and the chip types of the multiple chips that can be packaged are at least two categories.

[0057] Multiple types of bump structures, that is, the types of the multiple bump structures used in the multi-chip package are of multiple types, that is, the embodiments of the present application support the use of multiple bump structures for packaging, and the bump structure types of the multiple bump structures belong to at least two types; for example, the bump structure types of the multiple bump structures used in the package are different (that is, each bump structure belongs to a different type of bump structure), and for example, the bump structure types of the multiple bump structures used in the package are partially the same (that is, among the multiple bump structures used in the package, some of the bump structures have the same bump structure type, while the bump structure types of another part of the bump structures are different).

[0058] In the embodiment of the present application, the bump structure may include at least solder bumps and copper pillar bumps. In the actual packaging process, the corresponding bump structure may be selected to achieve connection with the packaging substrate according to the application and performance requirements of various chips.

[0059] In the embodiment of the present application, chips of the same type can be connected to the packaging substrate 300 through the same type of bump structure; that is, in the embodiment of the present application, one type of bump structure can be used to connect multiple types of different chips to the packaging substrate, and the type of bump structure used by any type of chip is not limited, as long as chips of the same type use the same type of bump structure to be connected to the packaging substrate.

[0060] In an optional implementation, based on the different chip heights of different types of chips and the different heights of different types of bump structures, a packaging height difference will be formed after multiple types of chips are connected to the packaging substrate using multiple types of bump structures, wherein the chip packaging height is the height between the top surface of the chip and the top surface of the packaging substrate after the chip is connected to the packaging substrate using the bump structure.

[0061] It should be further explained that, based on the fact that chips of the same type have the same chip height and bump structures of the same type have the same height, when multiple types of chips and multiple types of bump structures are used in a multi-chip package, after chips of the same type are connected to the package substrate through the same bump structure, chips of the same type have the same package height difference, while the package height difference of chips of different types may be different, thereby forming a package height difference between the multiple types of chips used in the multi-chip package.

[0062] Example, combined Figure 3As shown, the two chips 312 have the same chip height, and both chips 312 are connected to the package substrate through the same type of first bump structure 321, wherein the first bump structure 321 is a solder bump. Chip 311 is also connected to the package substrate through a solder bump, but chip 311 and chip 312 are different types of chips, that is, the heights of chip 311 and chip 312 are inconsistent, so chip 311 and chip 312 form a package height difference;

[0063] Chip 313 is connected to the packaging substrate through a second bump structure 322, wherein the second bump structure 322 is a copper pillar bump. Chip 313 and chip 312 are different types of chips, that is, the heights of chip 313 and chip 312 are inconsistent. At the same time, the copper pillar bumps used in chip 313 and the solder bumps used in chip 312 are different types of bump structures, and the heights of the copper pillar bumps and the solder bumps are inconsistent. Therefore, chips 313 and 312 form a packaging height difference, and similarly, chips 313 and chip 311 also form a packaging height difference.

[0064] The heat dissipation cover 330 includes a height difference compensation structure 331 for compensating for the packaging height difference formed by the multiple types of chips so that the multiple types of chips are all in contact with the heat dissipation cover; wherein there is a height reference chip among the multiple types of chips, and the layout of the height difference compensation structure 331 is determined according to the packaging height difference of other chips in the multiple types of chips relative to the height reference chip.

[0065] In an embodiment of the present application, the chip packaging structure includes a heat dissipation cover 330, which can absorb and conduct the heat generated by multiple chips when working; since a packaging height difference is formed when multiple types of chips are packaged, the heat dissipation cover is provided with a height difference compensation structure, which can be used to compensate for the packaging height difference formed by the multiple types of chips, so that the multiple types of chips are all in contact with the heat dissipation cover, meeting the needs of packaging multiple types of chips with multiple types of different bump structures, thereby improving the flexibility of chip packaging and enhancing the heat dissipation performance of chip packaging.

[0066] In an embodiment of the present application, there is a height reference chip among the multiple types of chips, and the layout of the height difference compensation structure can be determined according to the packaging height difference of other chips in the multiple types of chips relative to the height reference chip.

[0067] In an optional implementation, the height reference chip can be a type of chip with the largest number of chips among multiple types of chips, wherein the number of each type of chip among the multiple types of chips is at least one; and the area of ​​the heat dissipation cover corresponding to the height reference chip is set as a planar structure.

[0068] by Figure 3For example, among the multiple types of chips, the number of chips 312 is two, that is, the number of chips 312 is the largest, and chip 312 can be used as the height reference chip among the multiple types of chips. Since the same type of chips use the same type of bump structure, the same type of chips have the same packaging height, and the type of chips with the largest number of chips is used as the height reference chip, and the height reference chip is set as a plane structure in the area corresponding to the heat dissipation cover, then the type of chips with the largest number of chips (for example, two chips 312) is a plane structure in the area corresponding to the heat dissipation cover, and then in the packaging process, for the type of chips with the largest number of chips among the multiple types of chips used for packaging, the heat dissipation cover can maintain a plane structure, and no other processing steps are required, thereby reducing the processing cost and difficulty of the heat dissipation cover.

[0069] In the embodiment of the present application, based on the packaging height difference between other chips used in the packaging and the height reference chip, the other chips in the multiple types of chips except the height reference chip can be divided into low-position chips and high-position chips.

[0070] In an optional implementation, the low-position chip may be a chip among the multiple types of chips whose packaging height is lower than the height reference chip, and the high-position chip may be a chip among the multiple types of chips whose packaging height is higher than the height reference chip.

[0071] Furthermore, based on the low-position chip and the high-position chip, the embodiment of the present application can set two different types of height difference compensation structures for the low-position chip and the high-position chip.

[0072] In an optional implementation, the height difference compensation structure may include a protruding structure and a recessed structure, wherein the protruding structure corresponds to a low-position chip among the multiple types of chips; and the recessed structure corresponds to a high-position chip among the multiple types of chips.

[0073] In an alternative embodiment, Figure 4 An example diagram of a chip packaging structure using a protruding structure is shown. Figure 4 , assuming that chip 401 is used as a height reference chip and the package height of chip 402 is lower than that of chip 401 , chip 402 is a low-position chip, and the height difference compensation structure of the heat dissipation cover 330 corresponding to the chip 402 area is a protruding structure 403 .

[0074] In another alternative embodiment, Figure 5 An example diagram of a chip packaging structure using a groove structure is shown. Figure 5 , assuming that chip 501 is used as a height reference chip and the package height of chip 502 is higher than that of chip 501 , chip 502 is a high-position chip, and the height difference compensation structure of the heat dissipation cover 330 corresponding to the chip 502 area is a groove structure 503 .

[0075] In the embodiment of the present application, Figure 3 , Figure 4 and Figure 5 The chip packaging structure further includes a connection layer 340 , and the connection layer 340 is used to connect the top surface of the chip with the heat dissipation cover 330 .

[0076] The connection layer 340 can act as a bridge for heat conduction between the chip and the heat dissipation cover, and can quickly transfer the heat generated by the chip when it is working to the heat dissipation cover, and dissipate it to the surrounding environment through the heat dissipation cover.

[0077] In an optional implementation, the planar structure of the heat dissipation cover 330 can be connected to the height reference chip through the connection layer; the protrusion structure 403 of the heat dissipation cover can be connected to the low-position chip (for example, chip 402) through the connection layer 340; and the groove structure 503 of the heat dissipation cover can be connected to the high-position chip (for example, chip 502) through the connection layer 340.

[0078] The height of the connection layer may be set to be the height between the top surface of the height reference chip and the planar structure of the heat dissipation cover, and thus the height reference chip may be connected to the heat dissipation cover via the connection layer.

[0079] In the embodiment of the present application, by comparing the height of the other chips used in the package with the height reference chip, the type of height difference compensation structure (convex structure or groove structure) of the other chips corresponding to the heat dissipation cover area can be determined. Furthermore, the height of the height difference compensation structure can be determined according to the height of the connection layer and the packaging height difference of the other chips relative to the height reference chip; wherein the other chips can be regarded as any chip other than the height reference chip among the multiple chips used in the package.

[0080] In an optional implementation, the protrusion height of the protrusion structure may be set to: the height between the top surface of the low-position chip and the planar structure of the heat dissipation cover minus the height of the connection layer;

[0081] The groove height of the groove structure can be set to: the height of the connection layer minus or plus the height between the top surface of the high-position chip and the plane structure of the heat dissipation cover.

[0082] In an alternative embodiment, Figure 6 is based on Figure 4 A partial enlarged view of the raised structure, combined with Figure 4 and Figure 6 , the height between the top surface of the low-position chip 402 and the planar structure of the heat dissipation cover 330 is a, the height of the connection layer 340 is m, and the value of the height h of the protruding structure 403 is am.

[0083] In another optional embodiment, in a high-position chip, if the top surface of the high-position chip is lower than the planar structure of the heat dissipation cover, the height of the groove structure can be set to the height of the connection layer minus the height between the top surface of the high-position chip and the planar structure of the heat dissipation cover. Figure 7 is based on Figure 5 A partial enlarged view of the groove structure, combined with Figure 5 and Figure 7 , the height of the connection layer 340 is m, the height between the top surface of the high-position chip 502 and the planar structure of the heat dissipation cover 330 is b, and the value of the height h of the groove structure 503 is mb.

[0084] In another optional embodiment, in a high-position chip, if the top surface of the high-position chip is higher than the planar structure of the heat dissipation cover, the height of the groove structure can be set to the height of the connection layer plus the height between the top surface of the high-position chip and the planar structure of the heat dissipation cover. Figure 8 based on Figure 5 Another partial enlarged view of the groove structure, refer to Figure 8 , the height of the connection layer 340 is m, the height between the top surface of the high-position chip 502 and the planar structure of the heat dissipation cover 330 is c, and the value of the height h of the groove structure 503 is m+c.

[0085] In the embodiment of the present application, the connection layer 340 may be a welding layer, and the material of the welding layer may be indium. Indium has high thermal conductivity, and can effectively conduct the heat generated by the chip to the heat dissipation cover, thereby improving the heat dissipation efficiency; at the same time, it has good insulation and stability, and can protect the chip and reduce damage.

[0086] Further, in the embodiments of the present application, refer to Figure 3 The chip packaging structure further includes a bottom filling layer 350 for filling the gap between the bottom surface of the chip and the packaging substrate. The material of the bottom filling layer 350 can be epoxy resin.

[0087] After the chip is connected to the package substrate through the bump structure, the gap between the chip and the package substrate can be filled with bottom filling material to protect the bump structure and the chip from physical impact and wear, and reduce damage caused by mechanical stress such as vibration. Among them, epoxy resin has good bonding properties and mechanical strength, can provide good mechanical connection, improve the stability and durability of the package structure, and can be used as bottom filling material.

[0088] It can be seen that the chip packaging structure provided in the embodiment of the present application can be applicable to multiple types of chips and multiple types of bump structures, wherein chips of the same type are connected to the packaging substrate through the same type of bump structure, thereby avoiding the need to use the same bump structure when packaging multiple chips and the situation where the height of each chip is consistent (i.e. avoiding the situation where multi-chip packaging is limited to packaging multiple chips of the same type), thereby improving the flexibility of chip packaging; that is, the chip packaging structure provided in the embodiment of the present application does not limit the type of chip and bump structure type applicable to the packaging. When chips of the same type are connected to the packaging substrate through the same type of bump structure, the embodiment of the present application supports multiple types of chips to be packaged using multiple types of bump structures, thereby reducing the applicability limitations of chip packaging and improving the flexibility of chip packaging. At the same time, since multiple types of chips will form a package height difference after connecting the package substrate using multiple types of bump structures, when designing the heat dissipation cover, the embodiment of the present application is provided with a height difference compensation structure on the heat dissipation cover, and the layout of the height difference compensation structure is determined according to the package height difference of other chips in the multiple types of chips used for packaging relative to the height reference chip, so that the height difference compensation structure can be used to compensate for the package height difference formed by the multiple types of chips, so that the multiple types of chips are all in contact with the heat dissipation cover, thereby ensuring the heat dissipation requirements of the multiple types of chips used for packaging. It can be seen that the embodiment of the present application can support the selection of multiple types of chips by multi-chip packaging technology, and ensure the heat dissipation requirements of multiple types of chips after packaging, so the embodiment of the present application can improve the flexibility of chip packaging and improve the heat dissipation performance of chip packaging.

[0089] The embodiment of the present application also provides a heat dissipation cover processing method, which can be applied to a computer numerical control (CNC) system, and the heat dissipation cover in the chip packaging structure described above is obtained by controlling the processing by the CNC system. Fig. 9 is a flow chart of a heat dissipation cover processing method provided in an embodiment of the present application, referring to Fig. 9 The heat dissipation cover processing method includes the following steps.

[0090] Step S901: Obtain chip packaging design data, the chip packaging design data including: chip parameters of multiple types of chips to be packaged, bump structure parameters of multiple types of bump structures, and adoption information of bump structure types adopted by various types of chips, wherein chips of the same type adopt the same type of bump structures to connect the packaging substrate.

[0091] The heat sink cover processing method provided in the embodiment of the present application can obtain chip packaging design data, which may include chip parameters of multiple types of chips and parameters of the bump structures used by each type of chip, and then the heat sink cover can be processed according to the acquired chip packaging design data.

[0092] In the embodiment of the present application, the chip parameters may at least include the heights of various types of chips, and the bump structure parameters may at least include the heights of various types of bump structures.

[0093] Step S902: Determine the height reference chip among the multiple types of chips and the packaging height difference of other chips among the multiple types of chips relative to the height reference chip based on the chip packaging design data; wherein the chip packaging height is the height between the top surface of the chip and the top surface of the packaging substrate after the chip is connected to the packaging substrate using a bump structure, and the packaging height difference is formed after multiple types of chips are connected to the packaging substrate using multiple types of bump structures.

[0094] In the embodiment of the present application, according to the obtained chip packaging data, the height reference chip among the multiple types of chips and the packaging height difference of other chips among the multiple types of chips relative to the height reference chip can be determined. Among them, the packaging height in the embodiment of the present application is the height between the top surface of the chip and the top surface of the packaging substrate after the chip is connected to the packaging substrate using a bump structure. Since the heights of multiple types of chips are inconsistent, the heights of the bump structures used by each type of chip are also inconsistent. Therefore, after multiple types of chips are connected to the packaging substrate using multiple types of bump structures, a packaging height difference will be formed.

[0095] In an optional implementation, the height reference chip can be a type of chip with the largest number of chips among multiple types of chips, wherein the number of each type of chips among the multiple types of chips is at least one; the processing parameters also include: layout parameters of the planar structure of the heat dissipation cover, and the layout parameters of the planar structure are set to correspond to the height reference chip.

[0096] In the embodiment of the present application, since the chip heights of each type of chip are consistent, the type of chip with the largest number among the multiple types of chips is selected as the height reference chip, that is, the type of chip with the most consistent heights and the largest number among the multiple types of chips is selected as the height reference chip.

[0097] Furthermore, the layout parameter setting of the planar structure of the heat sink cover in the embodiment of the present application corresponds to the height reference chip, that is, the heat sink cover area corresponding to the largest number of chips among the multiple types of chips is a planar structure, and no other processing steps are required, thereby reducing the processing cost and difficulty of the heat sink cover. Subsequently, only the heat sink cover area corresponding to the chip whose packaging height is different from the height reference chip among other chips needs to be processed to form a height difference compensation structure.

[0098] Step S903: determining processing parameters of the heat dissipation cover according to the package height difference, wherein the processing parameters at least include: layout parameters of a height difference compensation structure of the heat dissipation cover, wherein the height difference compensation structure is used to compensate for the package height difference formed by the multiple types of chips.

[0099] In an embodiment of the present application, based on the packaging height difference of other chips relative to the height reference chip, the processing parameters of the heat sink cover can be determined, wherein the processing parameters of the heat sink cover can at least include layout parameters of the height difference compensation structure on the heat sink cover corresponding to the multiple types of chips, and the height difference compensation structure can be used to compensate for the packaging height difference formed by the multiple types of chips.

[0100] In an optional implementation, the layout parameters of the height difference compensation structure may include: layout parameters of the protrusion structure of the heat dissipation cover, and layout parameters of the groove structure.

[0101] Among them, the layout parameters of the protrusion structure are set to correspond to the low-position chip among the multiple types of chips, and the low-position chip is a chip among the multiple types of chips whose packaging height is lower than the height reference chip; the layout parameters of the groove structure are set to correspond to the high-position chip among the multiple types of chips, and the high-position chip is a chip among the multiple types of chips whose packaging height is higher than the height reference chip.

[0102] In an embodiment of the present application, based on a height comparison between other chips and the height reference chip, other chips can be divided into low-position chips whose package height is lower than that of the height reference chip, and high-position chips whose package height is higher than that of the height reference chip. Then, the layout type of the corresponding height difference compensation structure can be determined according to different types of chips, wherein the low-position chip corresponds to a protruding structure and the high-position chip corresponds to a groove structure.

[0103] Furthermore, the height of the height difference compensation structure can be determined according to the height of the connection layer and the package height difference of the chip relative to the height reference chip. The connection layer can be used to connect the top surface of the chip with the heat dissipation cover in the chip packaging structure, and the height of the connection layer can be set to be the height between the top surface of the height reference chip and the planar structure of the heat dissipation cover.

[0104] In an embodiment of the present application, the layout parameters of the protrusion structure include the protrusion height of the protrusion structure, and the protrusion height of the protrusion structure can be set to: the height between the top surface of the low-position chip and the planar structure of the heat dissipation cover, minus the height of the connecting layer; the layout parameters of the groove structure include the groove height of the groove structure; the groove height of the groove structure is set to: the height of the connecting layer, minus or plus the height between the top surface of the high-position chip and the planar structure of the heat dissipation cover.

[0105] Wherein, in the high-position chip, if the top surface of the high-position chip is lower than the plane structure of the heat dissipation cover, the height of the groove structure can be set to the height of the connection layer minus the height between the top surface of the high-position chip and the plane structure of the heat dissipation cover. If the top surface of the high-position chip is higher than the plane structure of the heat dissipation cover, the height of the groove structure can be set to the height of the connection layer plus the height between the top surface of the high-position chip and the plane structure of the heat dissipation cover.

[0106] Step S904: processing the heat dissipation cover based on the processing parameters of the heat dissipation cover.

[0107] In an embodiment of the present application, based on the processing parameters of the heat sink cover determined above, the CNC system can control the corresponding packaging process device to process the heat sink cover, thereby meeting the requirements of packaging the above-mentioned multiple types of chips with multiple types of different bump structures, thereby improving the flexibility of chip packaging.

[0108] The embodiment of the present application further provides a chip packaging method. The chip packaging method described below can be referenced in correspondence with the contents of the chip packaging structure described above.

[0109] Fig.10 is a flow chart of a chip packaging method provided in an embodiment of the present application, referring to Fig.10 , the chip packaging method may include:

[0110] Step S1001: providing a packaging substrate; connecting multiple types of chips to the packaging substrate through multiple types of bump structures, wherein the same type of chips are connected to the packaging substrate through the same type of bump structures; after the multiple types of chips are connected to the packaging substrate through the multiple types of bump structures, a packaging height difference is formed, and the packaging height of the chip is the height between the top surface of the chip and the top surface of the packaging substrate after the chip is connected to the packaging substrate using the bump structure.

[0111] Step S1002: Connect a heat sink cover to the top surface of the multiple types of chips, wherein the heat sink cover includes a height difference compensation structure for compensating for the packaging height difference formed by the multiple types of chips, so that the multiple types of chips are all in contact with the heat sink cover; wherein a height reference chip exists among the multiple types of chips, and a layout of the height difference compensation structure is determined according to the packaging height difference of other chips in the multiple types of chips relative to the height reference chip.

[0112] Optionally, the height reference chip is a type of chip with the largest number of chips among the multiple types of chips, wherein the number of each type of chip among the multiple types of chips is at least one; and the area of ​​the heat dissipation cover corresponding to the height reference chip is set as a planar structure.

[0113] Optionally, the height difference compensation structure includes a protrusion structure and a groove structure; and the heat dissipation cover is connected to the top surface of the plurality of types of chips includes:

[0114] Connecting the planar structure via a connection layer on the top surface of the height reference chip among the plurality of types of chips;

[0115] The protruding structure is connected to the top surface of a low-position chip among the plurality of types of chips through a connecting layer, wherein the low-position chip is a chip among the plurality of types of chips whose packaging height is lower than that of the height reference chip;

[0116] The groove structure is connected to the top surface of a high-position chip among the multiple types of chips through a connection layer, and the high-position chip is a chip among the multiple types of chips whose packaging height is higher than the height reference chip.

[0117] Optionally, the height of the connection layer is set to: the height between the top surface of the height reference chip and the plane structure of the heat dissipation cover;

[0118] The protrusion height of the protrusion structure is set to: the height between the top surface of the low-position chip and the plane structure of the heat dissipation cover minus the height of the connection layer;

[0119] The groove height of the groove structure is set to: the height of the connection layer minus or plus the height between the top surface of the high-position chip and the plane structure of the heat dissipation cover.

[0120] Optionally, also include:

[0121] Filling the gap between the bottom surface of the chip and the packaging substrate through the bottom filling layer;

[0122] Wherein, the connection layer is a welding layer, and the material of the welding layer is indium; the material of the bottom filling layer is epoxy resin.

[0123] An embodiment of the present application provides an electronic device, such as a terminal device or a server device, wherein the electronic device includes the chip packaging structure described in the aforementioned embodiment.

[0124] The above describes multiple implementation schemes provided by the embodiments of the present application. The various optional methods introduced in each implementation scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as implementation schemes disclosed and open in the embodiments of the present application.

[0125] Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined by the claims.

Claims

1. A chip packaging structure, characterized in that: include: Package substrate; Multiple types of chips; Multiple types of bump structures: chips of the same type are connected to the package substrate through the same bump structures; After various types of chips are connected to the packaging substrate using various types of bump structures, a packaging height difference is formed. The packaging height of the chip is the height between the top surface of the chip and the top surface of the packaging substrate after the chip is connected to the packaging substrate using the bump structure. A heat dissipation cover, wherein the heat dissipation cover comprises a height difference compensation structure for compensating for the packaging height difference formed by the multiple types of chips so that the multiple types of chips are all in contact with the heat dissipation cover; wherein there is a height reference chip among the multiple types of chips, and the layout of the height difference compensation structure is determined according to the packaging height difference of other chips in the multiple types of chips relative to the height reference chip.

2. The chip packaging structure according to claim 1, characterized in that: The height reference chip is a chip of the largest number among the multiple types of chips, wherein the number of each type of chip among the multiple types of chips is at least one; and the area of ​​the heat dissipation cover corresponding to the height reference chip is set as a planar structure.

3. The chip packaging structure according to claim 2, characterized in that: The height difference compensation structure includes a convex structure and a concave structure; The protruding structure corresponds to a low-position chip among the multiple types of chips, and the low-position chip is a chip among the multiple types of chips whose packaging height is lower than that of the height reference chip; The groove structure corresponds to a high-position chip among the multiple types of chips, and the high-position chip is a chip among the multiple types of chips whose packaging height is higher than the height reference chip.

4. The chip packaging structure according to claim 3, characterized in that: Also included: a connection layer, used to connect the top surface of the chip with the heat dissipation cover; Among them, the planar structure of the heat dissipation cover is connected to the height reference chip through the connection layer; the protruding structure of the heat dissipation cover is connected to the low-position chip through the connection layer; and the groove structure of the heat dissipation cover is connected to the high-position chip through the connection layer.

5. The chip packaging structure according to claim 4, characterized in that: The height of the connection layer is set to be: the height between the top surface of the height reference chip and the plane structure of the heat dissipation cover; The protrusion height of the protrusion structure is set to: the height between the top surface of the low-position chip and the plane structure of the heat dissipation cover minus the height of the connection layer; The groove height of the groove structure is set to: the height of the connection layer minus or plus the height between the top surface of the high-position chip and the plane structure of the heat dissipation cover.

6. The chip packaging structure according to claim 4, characterized in that: Also includes: The bottom filling layer is used to fill the gap between the bottom surface of the chip and the packaging substrate.

7. The chip packaging structure according to claim 6, characterized in that: The connection layer is a welding layer, the material of which is indium; the material of the bottom filling layer is epoxy resin.

8. The chip packaging structure according to any one of claims 1 to 7, characterized in that: The multiple types of bump structures include at least solder bumps and copper pillar bumps.

9. A heat dissipation cover processing method, characterized in that: include: Obtain chip packaging design data, wherein the chip packaging design data includes: chip parameters of multiple types of chips to be packaged, bump structure parameters of multiple types of bump structures, and adoption information of bump structure types adopted by various types of chips, wherein chips of the same type adopt the same type of bump structures to connect the packaging substrate; According to the chip packaging design data, determine the height reference chip among the multiple types of chips, and the packaging height difference of other chips among the multiple types of chips relative to the height reference chip; wherein the packaging height of the chip is the height between the top surface of the chip and the top surface of the packaging substrate after the chip is connected to the packaging substrate using a bump structure, and the packaging height difference is formed after multiple types of chips are connected to the packaging substrate using multiple types of bump structures; Determine processing parameters of the heat dissipation cover according to the package height difference, wherein the processing parameters at least include: layout parameters of a height difference compensation structure of the heat dissipation cover, wherein the height difference compensation structure is used to compensate for the package height difference formed by the multiple types of chips; The heat dissipation cover is obtained by processing based on the processing parameters of the heat dissipation cover.

10. The heat dissipation cover processing method according to claim 9, characterized in that: The height reference chip is a type of chip with the largest number of chips among the multiple types of chips, wherein the number of each type of chip among the multiple types of chips is at least one; the processing parameters also include: layout parameters of the planar structure of the heat dissipation cover, and the layout parameters of the planar structure are set to correspond to the height reference chip.

11. The heat dissipation cover processing method according to claim 10, characterized in that: The layout parameters of the height difference compensation structure include: layout parameters of the protrusion structure of the heat dissipation cover, and layout parameters of the groove structure; The layout parameters of the protruding structure are set to correspond to the low-position chip among the multiple types of chips, and the low-position chip is a chip among the multiple types of chips whose packaging height is lower than the height reference chip; The layout parameters of the groove structure are set to correspond to the high-position chip among the multiple types of chips, and the high-position chip is a chip among the multiple types of chips whose packaging height is higher than the height reference chip.

12. The heat dissipation cover processing method according to claim 11, characterized in that: The layout parameters of the protrusion structure include the protrusion height of the protrusion structure; the protrusion height of the protrusion structure is set to: the height between the top surface of the low-position chip and the plane structure of the heat dissipation cover minus the height of the connection layer; Wherein, the connection layer is used to connect the top surface of the chip and the heat dissipation cover in the chip packaging structure, and the height of the connection layer is set to: the height between the top surface of the height reference chip and the plane structure of the heat dissipation cover; The layout parameters of the groove structure include the groove height of the groove structure; the groove height of the groove structure is set to: the height of the connection layer minus or plus the height between the top surface of the high-position chip and the plane structure of the heat dissipation cover.

13. A chip packaging method, characterized in that: include: Providing a packaging substrate; Connecting multiple types of chips to a packaging substrate through multiple types of bump structures, wherein the same type of chips are connected to the packaging substrate through the same type of bump structures; after the multiple types of chips are connected to the packaging substrate through the multiple types of bump structures, a packaging height difference is formed, and the packaging height of the chip is the height between the top surface of the chip and the top surface of the packaging substrate after the chip is connected to the packaging substrate using the bump structure; A heat sink is connected to the top surface of the multiple types of chips, and the heat sink includes a height difference compensation structure for compensating for the packaging height difference formed by the multiple types of chips, so that the multiple types of chips are all in contact with the heat sink; wherein there is a height reference chip among the multiple types of chips, and the layout of the height difference compensation structure is determined according to the packaging height difference of other chips in the multiple types of chips relative to the height reference chip.

14. The chip packaging method according to claim 13, characterized in that: The height reference chip is a chip of the largest number among the multiple types of chips, wherein the number of each type of chip among the multiple types of chips is at least one; and the area of ​​the heat dissipation cover corresponding to the height reference chip is set as a planar structure.

15. The chip packaging method according to claim 14, characterized in that: The height difference compensation structure includes a protrusion structure and a groove structure; the heat dissipation cover connected to the top surface of the plurality of types of chips includes: Connecting the planar structure via a connection layer on the top surface of the height reference chip among the plurality of types of chips; The protruding structure is connected to the top surface of a low-position chip among the plurality of types of chips through a connecting layer, wherein the low-position chip is a chip among the plurality of types of chips whose packaging height is lower than that of the height reference chip; The groove structure is connected to the top surface of a high-position chip among the multiple types of chips through a connection layer, and the high-position chip is a chip among the multiple types of chips whose packaging height is higher than the height reference chip.

16. The chip packaging method according to claim 15, characterized in that: The height of the connection layer is set to be: the height between the top surface of the height reference chip and the plane structure of the heat dissipation cover; The protrusion height of the protrusion structure is set to: the height between the top surface of the low-position chip and the plane structure of the heat dissipation cover minus the height of the connection layer; The groove height of the groove structure is set to: the height of the connection layer minus or plus the height between the top surface of the high-position chip and the plane structure of the heat dissipation cover.

17. The chip packaging method according to any one of claims 15 to 16, characterized in that: Also includes: Filling the gap between the bottom surface of the chip and the packaging substrate through the bottom filling layer; Wherein, the connecting layer is a welding layer, and the material of the welding layer is indium; The material of the bottom filling layer is epoxy resin.

18. An electronic device, characterized in that: Comprising the chip packaging structure as described in any one of claims 1-8.

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