Semiconductor device structure with efficient heat dissipation structure through

Abstract

The invention provides a semiconductor device structure having an efficient heat dissipation structure throughout a chip and a monolithic fabrication method thereof. The semiconductor device structure includes a heat dissipation structure, such as a high thermal conductivity pillar and / or plate within a semiconductor substrate, to improve heat dissipation. The device structure includes a semiconductor substrate having an original semiconductor surface, a circuit component located within a semiconductor body region of the semiconductor substrate, and a vertical heat dissipation pillar in the semiconductor substrate and surrounding the semiconductor body region. Wherein the vertical heat dissipation column comprises a heat dissipation material, and the heat conductivity of the heat dissipation material is higher than the heat conductivity of the semiconductor substrate or higher than the heat conductivity of the silicon oxide.

Description

Technical Field

[0001] The present invention relates to semiconductor device structures, and more particularly to transistor structures and circuits thereof including heat dissipation structures (eg, high thermal conductivity columns and / or plates within a semiconductor substrate) to improve heat dissipation of the transistor. Background Art

[0002] The monolithic integration capability of silicon chips has rapidly evolved from GSI (Giga-scale integration: more than a few billion transistors on each die) to TSI (Tera-scale integration: several trillion transistors on each die), and chip performance has been significantly improved. The power consumption of operating such a large number of transistors has correspondingly increased dramatically, which disadvantageously increases the junction temperature of the transistors, thereby disadvantageously increasing the temperature of the entire chip due to the current limited heat dissipation capabilities (for example, the thermal conductivity of silicon dioxide is very low (1.3-1.5 W / m×K), and the thermal conductivity of silicon itself is not very high (about 148 W / m×K)). This material and device structure problem leads to a negative cycle effect, that is, higher die temperature will reduce the speed of the transistor, and then it is inevitable to design to increase the power of the circuit to increase the performance of the transistor, but this mechanism causes the die temperature to increase severely, thereby making the heat dissipation problem more serious. In fact, the problem of insufficient heat dissipation leading to increased chip operating temperature is regarded as the most serious problem to be solved in the entire chip industry, so as to avoid it becoming a major obstacle to integrating more devices on the die.

[0003] However, progress in reducing GSI chip temperatures has not been as great as it could be. In fact, as technology nodes shrink further (e.g., minimum feature size shrinks from 7nm to 5nm to 3nm, etc.), transistors must become smaller, oxide coverage as a percentage of the total transistor size increases, and the heat dissipation capacity of the device junction is further concentrated. Although there are many ways to dissipate heat, such as covering the entire chip from the outside with a high thermal pad, or using a liquid cooling loop outside the packaged chip, these methods are all expensive and inefficient and cannot effectively reduce the junction temperature of the transistor. Summary of the invention

[0004] The present invention focuses on creating a special High Heat-Removal (HHR) structure during the monolithic process of manufacturing the transistor itself. This HHR structure is like a monolithic heat sink connected to the entire tube die to maximize the heat dissipation area. In addition, this HHR structure can connect the entire edge of the tube die, so that some heating pads or thermal vias can be easily connected to create a larger heat dissipation path from the tube die to facilitate its connection to the external environment of the tube die and the packaged chip.

[0005] This novel HHR structure is seen as the closest way to achieve a very effective heat sink function directly associated with a single transistor, and the multiple HHR structures are all directly connected to the entire die as one optimized "heat sink" built into the die (called HSiD: Heat Sink in Die) or into the substrate. Thus, the present invention provides an inventive concept on how to build transistors with associated HHRs using familiar monolithic integration processes, and how the die itself can have an integrated internal HSiD to form an effective heat sink path within the chip.

[0006] One embodiment of the present invention provides a device structure including a heat dissipation structure (e.g., a high thermal conductivity column and / or plate in a semiconductor substrate) to improve heat dissipation. The device structure includes a semiconductor substrate having an original semiconductor surface, a circuit component located in a semiconductor body region of the semiconductor substrate, and a vertical heat dissipation column in the semiconductor substrate and surrounding the semiconductor body region. The vertical heat dissipation column includes a heat dissipation material having a thermal conductivity higher than the thermal conductivity of the semiconductor substrate or higher than the thermal conductivity of silicon oxide.

[0007] According to one aspect of the present invention, the semiconductor substrate includes an edge region away from the circuit component, and the vertical heat dissipation column extends from a position adjacent to or close to the circuit component to the edge region close to the semiconductor substrate.

[0008] According to one aspect of the present invention, the heat dissipation material is BN, AlN or metal.

[0009] According to an aspect of the present invention, a vertical heat dissipation column includes a layer formed of a heat dissipation material, and a heat conduction column covering the layer formed of the heat dissipation material.

[0010] According to one aspect of the present invention, the heat conductor comprises metal.

[0011] According to one aspect of the present invention, the semiconductor substrate includes an edge region away from the circuit component, and the layer formed of the heat dissipation material extends from a position adjacent to or close to the circuit component to the edge region close to the semiconductor substrate.

[0012] According to one aspect of the present invention, a vertical heat dissipation column includes a layer formed of a heat dissipation material, and an isolation column covering the thin layer formed of the heat dissipation material.

[0013] According to an aspect of the present invention, the spacer comprises silicon oxide.

[0014] According to one aspect of the present invention, the semiconductor substrate includes an edge region away from the circuit component, and the layer formed of the heat dissipation material extends from a position adjacent to or close to the circuit component to the edge region close to the semiconductor substrate.

[0015] According to one aspect of the present invention, the device structure further includes a shallow trench isolation (STI) region surrounding the semiconductor body region, wherein the vertical heat sink is within the STI region.

[0016] According to an aspect of the invention, the circuit component is a transistor, a resistor, a capacitor, a diode, or an inductor.

[0017] Another embodiment of the present invention provides a semiconductor device structure. The semiconductor device structure includes a semiconductor substrate having an original semiconductor surface, a first transistor located in a first semiconductor body region of the semiconductor substrate, a second transistor located in a second semiconductor body region of the semiconductor substrate, and a vertical heat sink in the semiconductor substrate. The second transistor is away from the first transistor rather than close to it. The vertical heat sink includes a heat sink material, and the thermal conductivity of the heat sink material is higher than the thermal conductivity of the semiconductor substrate or higher than the thermal conductivity of silicon oxide. The vertical heat sink extends from the first semiconductor body region to the second semiconductor body region.

[0018] According to one aspect of the present invention, the semiconductor substrate includes an edge region away from the first transistor and the second transistor, and the vertical heat dissipation column further extends to the edge region close to the semiconductor substrate.

[0019] According to one aspect of the present invention, the device substrate further includes a first horizontal heat sink directly below the first transistor and a second horizontal heat sink directly below the second transistor, wherein the vertical heat sink column connects or thermally couples the first horizontal heat sink and the second horizontal heat sink; wherein the first horizontal heat sink and / or the second horizontal heat sink include another heat sink material having another thermal conductivity, the other thermal conductivity of the other heat sink material being higher than the thermal conductivity of the semiconductor substrate or higher than the thermal conductivity of silicon oxide.

[0020] According to an aspect of the present invention, the heat dissipation material and / or another heat dissipation material is BN, AlN, or metal.

[0021] According to one aspect of the present invention, a first horizontal heat sink is connected or thermally coupled to a bottom surface of a drain region of a first transistor and a bottom surface of a source region of the first transistor, and the first horizontal heat sink is connected to a vertical heat sink; a second horizontal heat sink is connected or thermally coupled to a bottom surface of a drain region of a second transistor and a bottom surface of a source region of the second transistor, and the second horizontal heat sink is connected to a vertical heat sink.

[0022] According to one aspect of the present invention, the device structure further includes a shallow trench isolation (STI) region, wherein the vertical heat sink is within the STI region.

[0023] According to one aspect of the present invention, the top surface of the STI region is higher than the original semiconductor surface; wherein a recess is formed between the STI region and the gate structure of the first transistor, and a metal plug is formed in the recess and contacts the top of the drain region of the first transistor or the top of the source region of the first transistor.

[0024] According to one aspect of the present invention, the first horizontal heat dissipation plate and / or the second horizontal heat dissipation plate further includes a thin oxide layer covering another heat dissipation material.

[0025] One embodiment of the present invention provides a device structure including a heat dissipation structure (e.g., a high thermal conductivity column and / or plate in a semiconductor substrate) to improve heat dissipation. The device structure includes a semiconductor substrate having an original semiconductor surface, a circuit component located in a semiconductor body region of the semiconductor substrate, and a horizontal heat dissipation plate in the semiconductor substrate and below the circuit component. The horizontal heat dissipation plate includes a first heat dissipation material having a first thermal conductivity, the first thermal conductivity of the first heat dissipation material being higher than the thermal conductivity of the semiconductor substrate or higher than the thermal conductivity of silicon oxide.

[0026] According to an aspect of the present invention, the first heat dissipation material is BN, AlN or metal.

[0027] According to one aspect of the present invention, the horizontal heat dissipation plate further includes a thin oxide layer covering the first heat dissipation material.

[0028] According to one aspect of the present invention, the device structure further includes a shallow trench isolation region surrounding the semiconductor body region, and the horizontal heat sink extends outwardly to the shallow trench isolation region.

[0029] According to one aspect of the present invention, the semiconductor substrate includes an edge region away from the circuit component, and the horizontal heat dissipation plate further extends to the edge region close to the semiconductor substrate.

[0030] According to one aspect of the present invention, the heat sink is connected to the horizontal heat sink plate near the edge area of ​​the semiconductor substrate through holes above the horizontal heat sink plate.

[0031] According to one aspect of the present invention, the heat dissipation substrate is connected to the horizontal heat dissipation plate through holes below the horizontal heat dissipation plate.

[0032] According to one aspect of the present invention, the heat dissipation substrate includes a thermally conductive via or a heat sink connected to a horizontal heat dissipation plate.

[0033] According to an aspect of the present invention, the circuit component is a transistor, a resistor, a capacitor, a diode, or an inductor.

[0034] According to one aspect of the present invention, the circuit component is a transistor, the transistor includes a source region, a drain region and a channel region, and the horizontal heat sink connects the bottom surface of the source region and the bottom surface of the drain region.

[0035] According to one aspect of the present invention, the horizontal heat dissipation plate includes a first horizontal heat dissipation plate and a second horizontal heat dissipation plate. There is a gap between the first horizontal heat dissipation plate and the second horizontal heat dissipation plate, and the gap is directly below the channel region of the transistor.

[0036] According to one aspect of the present invention, there is a first PN junction between the source region and the channel region, there is a second PN junction between the drain region and the channel region, and both the first PN junction and the second PN junction are directly above the horizontal heat sink.

[0037] According to one aspect of the present invention, the transistor is a fin structure transistor, and the fin width of the fin structure transistor is substantially the same as the width of a horizontal heat sink directly below the fin structure transistor.

[0038] According to one aspect of the present invention, the device structure further includes a vertical heat dissipation column, which is in the semiconductor substrate and surrounds the circuit component; wherein the horizontal heat dissipation plate connects the vertical heat dissipation column, and the vertical heat dissipation column includes a second heat dissipation material with a second thermal conductivity, and the second thermal conductivity of the second heat dissipation material is higher than the thermal conductivity of the semiconductor substrate or higher than the thermal conductivity of silicon oxide.

[0039] According to one aspect of the present invention, the semiconductor substrate includes an edge region away from the circuit component, and the vertical heat dissipation column extends from the circuit component to the edge region close to the semiconductor substrate.

[0040] According to one aspect of the present invention, the device structure further comprises a shallow trench isolation region surrounding the semiconductor body region, wherein the vertical heat sink is within the shallow trench isolation region.

[0041] Another embodiment of the present invention provides a method for manufacturing a semiconductor device structure. The method includes: preparing a semiconductor substrate made of semiconductor material, the semiconductor substrate having an original semiconductor surface; defining an active region having a semiconductor body and forming a shallow trench isolation region surrounding the active region and extending to an edge region of the semiconductor substrate; and depositing a first heat dissipation material in the shallow trench isolation region, wherein a first thermal conductivity of the first heat dissipation material is higher than a thermal conductivity of the semiconductor substrate or higher than a thermal conductivity of silicon oxide.

[0042] According to an aspect of the present invention, the first heat dissipation material extends from the active area to an edge area close to the semiconductor substrate.

[0043] According to one aspect of the present invention, after forming the first heat dissipation material, the method further includes: forming a circuit element in the active area, wherein the circuit element is a transistor, a resistor, a capacitor, a diode, or an inductor.

[0044] According to an aspect of the present invention, the first heat dissipation material is BN, AlN or metal.

[0045] According to one aspect of the present invention, the step of forming a first heat dissipation material includes: etching down a shallow trench isolation region to expose multiple sidewalls of a semiconductor body; forming multiple vertical spacers to cover the exposed multiple sidewalls of the semiconductor body; further etching down the shallow trench isolation region and exposing multiple deeper silicon sidewalls of the semiconductor body; removing semiconductor material from the exposed multiple deeper silicon sidewalls to form multiple empty tunnel regions within the active region; and depositing the first heat dissipation material within the multiple empty tunnel regions and on the shallow trench isolation region.

[0046] According to one aspect of the present invention, the step of removing semiconductor material from the exposed plurality of deeper silicon sidewalls includes: thermally oxidizing the semiconductor material from the exposed plurality of deeper silicon sidewalls; and etching the oxidized semiconductor material to form a plurality of empty tunnel regions.

[0047] According to one aspect of the present invention, the step of removing semiconductor material from the exposed plurality of deeper silicon sidewalls includes: laterally etching the semiconductor material from the exposed plurality of deeper silicon sidewalls to form a plurality of empty tunnel regions.

[0048] According to one aspect of the present invention, before depositing the first heat dissipation material in the plurality of empty tunnel regions, the method further includes: thermally oxidizing the semiconductor material exposed by the plurality of empty tunnel regions.

[0049] According to one aspect of the present invention, before depositing the first heat dissipation material in the plurality of empty tunnel regions, the method further includes: removing the plurality of vertical spacers.

[0050] According to one aspect of the present invention, before etching the shallow trench isolation region downward to expose a plurality of sidewalls of the semiconductor body, the method further includes: forming a protection layer covering a center portion of the active region.

[0051] These and other objects of the present invention will no doubt become apparent to those having ordinary skill in the art after reading the following detailed description of the preferred embodiment as illustrated in the various figures and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to make the above-mentioned objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein:

[0053] Figure 1is a flow chart of a method for manufacturing a high heat dissipation (HHR) structure in a substrate or a die according to an embodiment of the present invention;

[0054] Figure 2a and Figure 2b are a top view and a cross-sectional view showing a structure after an active region and a shallow trench isolation (STI) region are formed;

[0055] Figure 3a and Figure 3b are a top view and a cross-sectional view showing a structure after a protection area made of nitride is formed above the middle of an active area;

[0056] Figure 4a and Figure 4b are a top view and a cross-sectional view showing the structure after vertical spacers are formed to cover the exposed silicon sidewalls;

[0057] Figure 5a and Figure 5b are a top view and a cross-sectional view showing the structure after deeper silicon sidewalls are exposed;

[0058] Figure 6a , Figure 6b and Figure 6c is a top view and two different cross-sectional views showing a structure after a plurality of empty tunnel regions are formed;

[0059] Figure 7a and Figure 7b are a top view and a cross-sectional view showing the structure after depositing a high heat dissipation material;

[0060] Figure 8a and Figure 8b A top view and a cross-sectional view showing the structure after a horizontal heat dissipation plate (Horizontal Heat-Dissipation Plate; HHDP) and a vertical heat dissipation column (Vertical Heat-Dissipation Column; VHDC) are formed;

[0061] Figure 9a and Figure 9b 1 is a top view and a cross-sectional view showing the structure of HHDP and VHDC after formation according to another embodiment;

[0062] Fig.10 is a diagram showing that the HHDP is connected to the VHDC and extends to the edge of the chip / die;

[0063] Fig.11 is a diagram showing a low temperature transistor according to the present invention;

[0064] Fig.12a and Figure 12b1 is a top view and a cross-sectional view showing a structure after deeper silicon sidewalls are exposed according to another embodiment;

[0065] Fig.13a , Fig.13b and Fig.13c 1 is a top view and two different cross-sectional views showing a structure after thermal oxide is formed along a deeper silicon sidewall according to another embodiment;

[0066] Fig.14a and Fig.14b 1 is a top view and a cross-sectional view showing a structure after a plurality of empty tunnel regions are formed according to another embodiment;

[0067] Fig.15a and Fig.15b 1 is a top view and a cross-sectional view showing a structure after a thin thermal oxide layer is formed according to another embodiment;

[0068] Fig.16a and Fig.16b 1 is a top view and a cross-sectional view showing a structure after depositing a high heat dissipation material according to another embodiment;

[0069] Fig.17a and Fig.17b 1 is a top view and a cross-sectional view showing a structure after a horizontal heat dissipation plate (HHDP) and a vertical heat dissipation column (VHDC) are formed according to another embodiment;

[0070] Fig.18 is a diagram showing another embodiment in which the HHDP is connected to the VHDC and extends to the edge of the chip / die;

[0071] Fig.19 is a diagram showing a low temperature transistor according to another embodiment of the present invention; and

[0072] Fig. 20 A diagram showing the results of a 3D low-temperature transistor operation and heat generation model simulation.

[0073] Reference numerals:

[0074] 10,15,20,25,30,35,40,45,50:Step 101: Pad Oxide Layer

[0075] 102: Pad nitride layer-1

[0076] 103: Active area

[0077] 104: Concave groove area

[0078] 201: Shallow Trench Isolation Area

[0079] 301: Pad nitride layer-2

[0080] 401: Oxide layer

[0081] 403: Pad nitride layer-3

[0082] 601: Empty Tunnel Area

[0083] 602: Thermal oxide layer

[0084] 603: Tunnel area

[0085] 701: Oxide layer

[0086] 702:Z Material

[0087] 801: Oxide layer

[0088] 901: Oxide layer

[0089] 902:Z Material

[0090] 903: Oxide layer

[0091] 1101: Gate metal region

[0092] 1102: High dielectric constant dielectric

[0093] 1103: Source region

[0094] 1104: drain region

[0095] 1105:Metal contact components

[0096] 1201: Gate metal region

[0097] 1202: High dielectric constant dielectric

[0098] 1203: Source region

[0099] 1204: Drain region

[0100] 1205:Metal contact components

[0101] t1,t2: depth

[0102] t3: thickness DETAILED DESCRIPTION

[0103] The most popular transistors currently use a FinFET / Tri-gate structure in a complementary metal oxide semiconductor (CMOS) circuit configuration, which has an N-type metal oxide semiconductor (NMOS) and a P-type metal oxide semiconductor (PMOS). Therefore, FinFET NMOS is used as an example to illustrate the key features of the present invention, which is related to the HHR structure in the substrate or die, and should be easily extended to PMOS or other types of transistors, such as gate all around transistors (GAA), sheet transistors, or planar transistors. Another feature of the invention is a manufacturing method that requires only a few processing steps.

[0104] Next, please refer to Figure 1 , which is a flow chart of a method for manufacturing an HHR structure in a substrate or a die according to an embodiment of the present invention.

[0105] Step 10: Get Started.

[0106] Step 15: Based on a substrate (eg, a P-type silicon substrate), define an active region and form an STI region.

[0107] Step 20: Form a protection area above the middle of the active area with a nitride layer.

[0108] Step 25: Etch down the STI region and form vertical spacers to cover the exposed silicon sidewalls.

[0109] Step 30: Etch the STI region further downward and expose the deeper silicon sidewalls.

[0110] Step 35: Remove silicon material from the exposed deeper silicon sidewalls to form an empty tunnel region.

[0111] Step 40: Remove the vertical spacers, form a horizontal heat dissipation plate (HHDP) in the vertical empty area and form a vertical heat dissipation column (VHDC) in the STI area.

[0112] Step 45: Form transistors in the active area.

[0113] Step 50: End.

[0114] The above-mentioned manufacturing method is described in detail as follows.

[0115] 1. Option A to implement HHR structure

[0116] Please refer to Figure 2a and Figure 2b, which is related to step 15. First, a thin pad oxide layer 101 is thermally grown on the top of the silicon surface (original silicon surface: OSS), and then a pad nitride layer-1 102 is deposited. An active area having a transistor body or a fin structure is defined using photolithography and etching technology. The active area is formed into an island-type active area 103. A composite layer of the pad nitride layer-1 102 and the pad oxide 101 covers the active area 103. A recessed trench area 104 (for example, its depth t1 is about 250 nm) connected to the wafer is formed outside the active area. Then, a thick oxide is deposited, and a chemical-mechanical-polishing (CMP) technology is used to make the top surface of the STI (shallow trench isolation) area 201 and the top surface of the pad nitride layer-1 102 coplanar (see Figure 2a and Figure 2b Figure 2b, where Figure 2a and Figure 2b A top view and a cross-sectional view are shown respectively).

[0117] Please refer to Figure 3a and Figure 3b , which is related to step 20. Deposit a pad nitride layer-2 301, and use a photolithography masking technique to leave a portion of this pad nitride layer-2 301 in the middle of the active area 103, which is specially designed to retain the silicon pillar area to ensure that the NMOS is a bulk device rather than a SOI device (in Figure 6a , Figure 6b and Figure 6c will become clearer later). Figure 3a and Figure 3b middle, Figure 3a and Figure 3b A top view and a cross-sectional view are shown respectively.

[0118] Please refer to Figure 4a and Figure 4b , which is related to step 25. The oxide inside the exposed STI region 201 is etched away to a depth t2 (e.g., 70 nm deep). The pad nitride layer-2 301 is retained, but the oxide of the STI region 201 inside the area protected by the pad nitride layer-2 301 is also kept unaffected and maintained at the same height as the surface of the pad nitride layer-1 102. Thus, all silicon surfaces below the OSS (original silicon surface) are exposed. Next, a thin oxide layer 401 (e.g., about 1.5 nm thick) is grown on the multiple sidewalls using a thermal oxidation method. Then, another pad nitride layer-3 403 is deposited. An anisotropic etching technique is used to make the pad nitride layer-3 403 a spacer on the vertical sidewalls. Under appropriate deliberate design, the pad nitride layer-2 301 remains on its flat surface, but becomes thinner due to the anisotropic etching that forms the pad nitride layer-3 403 (see Figure 4aand Figure 4b in, Figure 4a and Figure 4b A top view and a cross-sectional view are shown respectively).

[0119] Please refer to Figure 5a and Figure 5b , which is related to step 30. Anisotropic etching technology is used to remove the oxide layer exposed in most of the STI region 201 by a thickness of t3, and the thickness t3 is equal to 8nm, which results in a flat oxide surface and the distance between the top of the exposed oxide surface and the OSS is about 78nm (t2+t3). Anisotropic etching technology is used to remove the exposed thin oxide layer 401 by a thickness of about 1.5nm, so that the silicon on the sidewall is exposed (see Figure 5a and Figure 5b ,in Figure 5a and Figure 5b A top view and a cross-sectional view are shown respectively).

[0120] Please refer to Figure 6a , Figure 6b and Figure 6c , which is related to step 35. A portion of the exposed silicon surface is removed using an anisotropic etching technique, in particular, the etching rate in the crystal direction (110) can be optimized to be faster than the etching rate in the crystal direction (100) (see reference [1], Prem Pal, Kazuo Sato et al. "Surfactant Adsorption on Single-Crystal Silicon Surfaces in TMAH Solution: Orientation-Dependent Adsorption Detected by In Situ Infrared Spectroscopy" JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 18, No. 6, DECEMBER 2009 pp 1345-1356). Therefore, the silicon layer along the formed exposed area can be removed to form an empty tunnel region 601, but the removal process can be well controlled to stop at a suitable adjustment time to leave the silicon protected by the vertical distance below the pad nitride layer-3 403 (spacer) (see reference [1], Prem Pal, Kazuo Sato et al. "Surfactant Adsorption on Single-Crystal Silicon Surfaces in TMAH Solution: Orientation-Dependent Adsorption Detected by In Situ Infrared Spectroscopy" JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 18, No. 6, DECEMBER 2009 pp 1345-1356). Figure 6a , Figure 6b and Figure 6c ,in Figure 6a and Figure 6b The top view and the cross-sectional view are shown respectively. Figure 6c Shows cross-sections based on different cutting lines).

[0121] It should be noted here that we can use different processes to achieve similar Figure 6a, Figure 6b and Figure 6c For example, in the formation of Figure 5a and Figure 5b After the structure shown, a thermal oxidation process can be used to grow in a direction away from the exposed silicon area, rather than using the aforementioned anisotropic etching technique to remove a portion of the exposed silicon surface. Since the horizontal distance of the exposed silicon area may be somewhat narrow, the oxide layer (e.g., thermal oxide) grown below the top surface of the silicon island can quickly fill the horizontal gap and have a good smooth close-up shape, but the bulk silicon material under the cover of the pad nitride layer-3 403 (spacer) is also well protected to serve as a strong pillar area to connect the semiconductor body region of the transistor to the wafer substrate without being over-oxidized. Next, the thermal oxide is removed using an anisotropic etching technique to obtain a similar Figure 6a , Figure 6b and Figure 6c The above-mentioned thermal oxidation method and etching process to remove silicon will be described in Option B below.

[0122] Please refer to Figure 7a , Figure 7b , Figure 8a and Figure 8b , which is related to step 40. Anisotropic etching technology is used to remove the pad nitride layer-3 403 (spacer). A very thin oxide layer 701 (eg, 1 nm) is grown using a thermal oxidation process to well protect the newly formed and exposed silicon surface. Next, a suitable material with very high thermal conductivity but an insulator in electrical conductivity is selected [e.g., boron nitride (BN), which is an electrical insulator but has very high thermal conductivity, for example, 600 W / m×K, compared to 149 W / m×K of silicon material (see reference [2], https: / / en.wikipedia.org / wiki / Boron_nitride), and can be used to effectively fill holes through a chemical vapor deposition (CVD) process; or aluminum nitride (AlN) material is used, which has a thermal conductivity of up to 321 W / m×K (see reference [4], https: / / en.wikipedia.org / wiki / Aluminium_nitride); or any other suitable material is used as the so-called Z material 702]. Next, a CVD process is used to fill the empty tunnel region 601 formed as a result of the above-mentioned processing, for example, a BN material is selected. Of course, the vacancies in the STI region are filled with BN material (see reference [4], https: / / en.wikipedia.org / wiki / Aluminum_nitride). Figure 7a and Figure 7b ,in Figure 7a and Figure 7b A top view and a cross-sectional view are shown respectively).

[0123] Then, a CMP technique may be used to remove the BN material or Z material 702 on the pad nitride layer-1 102 to form a flat surface topography, and an anisotropic etching technique may be further used to remove some of the BN material or Z material 702 on the STI region 201. Next, an oxide layer 801 is deposited on the surface and made coplanar with the pad nitride layer-1 102. After the pad nitride layer-2 301 is removed, the silicon surface is covered by the pad nitride layer-1 102 and the STI region 201 covered by oxide, and a similar process may be performed to complete the MOS transistor in the remaining semiconductor active region (see Figure 8a and Figure 8b ,in Figure 8a and Figure 8b A top view and a cross-sectional view are shown respectively).

[0124] Therefore, some BN material or Z material 702 is filled into the empty tunnel region under the silicon body region of the FinFET / Tri-gate device and is protected from being affected by the semiconductor body and the wafer substrate, and is thus named a horizontal heat dissipation plate (HHDP), such as Figure 8a and Figure 8b As shown. Some materials are filled into the vertical empty area of ​​STI, which is named as vertical heat dissipation column (VHDC). In the novel device structure, the source / drain region of the transistor is located in HDDP and VHDC. The thermal conductivity of HDDP and VHDC is higher than that of silicon or silicon dioxide materials. HDDP and VHDC surround the transistor of traditional design. In fact, the hottest area of ​​the transistor when fully operating is concentrated in the p / n junction area between the source region and the drain region. The source region and the drain region are respectively connected to the channel region of the transistor. The multiple HDDP and VHDC structures can effectively dissipate the heat generated by the multiple p / n junction areas.

[0125] After describing the key points of the present invention, more design variations of HDDP and VHDC may be described in detail below. For example, after the BN material or Z material 702 is completed by a CVD process, the focus is on inserting this high thermal conductivity material into the empty tunnel region 601. Next, an anisotropic etching technique may be used to remove the vertical BN material or Z material 702 within the STI region 201. Next, an anisotropic etching technique may also be used to remove or etch down the bottom oxide material of the STI region 201 (for example, only a 20 nm thick oxide is retained in the STI region without damaging the BN material that has been horizontally inserted into the empty tunnel region 601). Next, the BN material or Z material 702 is deposited a second time in the vacancy of the STI region. This is a two-step method for forming the BN material or Z material 702. The first step is to form the HHDP, and then the second step is to optimize the volume of the BN material or Z material 702 in all STI regions (see Figure 9a and Figure 9b,in Figure 9a and Figure 9b A top view and a cross-sectional view are shown respectively).

[0126] It should also be noted that the STI region 201 extends throughout the entire wafer substrate. Since the HHDP material is all below the body region of the MOSFETs / transistors and connects to all VHDC materials within the STI region 201, this constructed high heat dissipation material network can serve as a connected heat sink for the operating PN junction of the transistor. By using familiar monolithic process methods to design multiple Z material heat sinks within a monolithic die and the multiple Z material heat sinks are all connected to the edge ring of the chip or die, the top surface can be opened to contact the BN material or Z material 702 within the STI region 201, so that the heat sink of the entire die can be connected to the outer edge of the chip / die to dissipate heat more directly and effectively (see Fig.10 ). For example, the lead frame can be designed so that the BN material or Z material 702 is directly connected to a larger area of ​​the lead frame material to meet this function, or a flip-die connection method can be used to dissipate the heat from all the semiconductor circuits with HHDP and VHDC structures proposed by the present invention. Of course, there can be two or more body regions in the semiconductor substrate, and each body region is surrounded by BN material or Z material 702, and the BN material or Z material 702 extends from one body region to another body region and further extends to the edge of the chip / die. Each body region can accommodate circuit components, such as transistors.

[0127] In addition to the heat sink that is connected from the top surface to the VHDC (and / or HHDP) inside the chip / die at the edge of the chip / die for heat dissipation (see Fig.10 ), in another embodiment, the chip / die having the VHDC (and / or HHDP) can be thinned first and then opened to expose the VHDC (and / or HHDP) so that another substrate with thermal vias or a heat sink can be connected to the VHDC (and / or HHDP) from the bottom of the chip / die.

[0128] Another possibility is to use a similar method as described in this embodiment to construct not only the first HHDP structure, but also to construct a second HHDP structure in the monolithic transistor region at a greater distance from the OSS (original silicon surface).

[0129] Fig.11The final transistor structure is marked, which has HHDP and VHDC microstructures to become a new "cryogenic transistor (CQT)", which is the best term to describe one embodiment of the present invention. This CQT structure can realize the scale-up (more transistors) and scale-down (smaller transistor size) strategy from the current GSI (giga-scale integration) to the TSI (tera-scale integration) era in the near future. The heat dissipation path of the newly created chip or die is a direct thermal path from the transistor level to the entire die level. As mentioned above, under the current cooling methods of the die and package / heterogeneous integrated module, there are some designs that can make the die-level thermal path even the chip-level thermal path, which of course can provide an effective heat sink for the chip package and / or some heterogeneous integrated modules (for example, through silicon vias (TSV) or through interconnect vias (TIV)).

[0130] exist Fig.11 In the embodiment, the transistor includes a gate structure, the gate structure includes a gate metal region 1101 and a high dielectric constant (Hi-K) dielectric 1102. The transistor also includes a source region 1103, the source region 1103 includes a lightly doped region extending laterally from the sidewall of the substrate, and a heavily doped region extending laterally from the sidewall of the lightly doped region. The multiple lightly doped regions and the heavily doped regions are formed by a selective growth method, such as an epitaxial growth method. There is a metal contact component 1105 between the gate structure of the transistor and the STI region 201 / 801 on the source region 1103. It should be noted that the top surface of 801 in the STI region is higher than the OSS, for example, coplanar with the top of the gate structure, so as to automatically form a contact hole without using an optical lithography process to form the contact hole, and therefore the metal contact component 1105 is self-aligned to the source region 1103. In addition, in another embodiment, the metal contact element 1105 may not only connect to the top of the source region 1103, but also connect to the most lateral sidewall of the source region 1103. The transistor also includes a drain region 1104, and the structure of the drain region 1104 may be the same or substantially the same as that of the source region 1103, and the relevant description thereof is omitted here.

[0131] In addition, in another embodiment, the process of forming the horizontal heat sink plate (HHDP) can be omitted and only the vertical heat sink column (VHDC) can be constructed. Since the vertical heat sink column (VHDC) is in the STI region 201 distributed on the entire die / chip, the multiple constructed VHDCs are also thermally connected to each other. Therefore, the constructed high heat dissipation VHDC network can serve as a connection heat sink for the operating PN junction of the transistor in the die / chip.

[0132] The VHDC can be made of a single high heat dissipation material as described above, and can also be made of a composite structure. For example, the VHDC includes a layer (or thin layer) formed of a first high heat dissipation material (such as BN, AlN, etc.), and another metal or metalloid column covering the first high heat dissipation material. Since the VHDC is located within the STI and the metalloid material is surrounded by the first high heat dissipation material, the first high heat dissipation material is not conductive when the transistors in the die / chip are operating, and the metalloid material of the VHDC will not affect the operation of the transistors in the die / chip. In another embodiment, the VHDC includes a layer (or thin layer) formed of a first high heat dissipation material (such as BN, AlN, etc.), and another non-conductive column (such as oxide) covering the first high heat dissipation material. This layer formed of the first high heat dissipation material can further extend to the edge of the die / chip and form the aforementioned heat dissipation network.

[0133] Since the vertical heat dissipation columns (VHDCs) are in the STI region 201 distributed throughout the die / chip, those constructed VHDCs are also thermally connected to each other. Thus, the constructed high heat dissipation VHDC network can serve as a connection heat sink for the operating PN junctions of the transistors in the die / chip.

[0134] In addition, in another embodiment, only a horizontal heat dissipation plate (HHDP) may be constructed. The horizontal heat dissipation plate (HHDP) may extend outward to the STI region 201 or connect to other high heat dissipation materials on the STI region 201. Then, an oxide layer 801 may be deposited on the surface and coplanar with the pad nitride layer-1 102. It is worth noting that the top of the STI region 201 is higher than the original semiconductor surface of the semiconductor substrate (e.g., Si substrate).

[0135] Since the horizontal heat dissipation plate (HHDP) can extend to the STI region 201 distributed on the entire die / chip, those constructed HHDPs are also thermally connected to each other. Therefore, the constructed high heat dissipation HHDP network can serve as a connection heat sink for the operating PN junction of the transistor in the die / chip.

[0136] 2. Option B to implement HHR structure

[0137] Another embodiment of the present invention is described below, based on the method of Option B. Figure 4a and Figure 4b , an anisotropic etching technique is used to remove the exposed oxide layer in most of the STI regions 201 by a thickness of t3, where t3 is equal to 160 nm, resulting in a flat oxide surface and a distance between the top of the exposed oxide surface and the original silicon surface of about 230 nm (t2+t3). An anisotropic etching technique is used to remove the exposed thin oxide layer 401 by a thickness of about 1.5 nm, so that the silicon on the sidewall is exposed (see Fig.12a and Figure 12b ,in Fig.12a and Figure 12b A top view and a cross-sectional view are shown respectively).

[0138] As mentioned above, in Option B, thermal oxidation is used to grow in a direction away from the exposed silicon on the sidewalls, rather than directly etching the exposed silicon on the sidewalls. Since the horizontal distance of the exposed silicon area may be somewhat narrow (especially for FinFETs, where the width of the transistor plane may be less than 20nm), the thermal oxide layer 602 grown under the silicon island or active area 103 can quickly fill the horizontal gap and have a good smooth close-up shape, but the bulk silicon material under the cover of the pad nitride layer-3 403 (spacer) is also well protected to serve as a strong pillar area to connect the semiconductor body region of the transistor to the wafer substrate without being over-oxidized (see Fig.13a , Fig.13b and Fig.13c ,in Fig.13a and Fig.13b The top view and the cross-sectional view are shown respectively. Fig.13c Another cross-sectional view based on a different cutting line is shown).

[0139] Next, an anisotropic etching technique is used to remove the grown thermal oxide layer 602, resulting in a horizontal hollow or tunnel region 603. An anisotropic etching technique is used to remove the pad nitride layer-3 403 (spacer) (see Fig.14a and Fig.14b ,in Fig.14a and Fig.14b A top view and a cross-sectional view are shown respectively).

[0140] A thermal oxidation process is used to grow a very thin oxide layer 901 (eg, 1 nm) to well protect the newly formed and exposed silicon surface (see Fig.15a and Fig.15b ,in Fig.15a and Fig.15b A top view and a cross-sectional view are shown respectively).

[0141] Next, a suitable material with very high thermal conductivity but an insulator in electrical conduction is selected [e.g., boron nitride (BN), which is an electrical insulator but has very high thermal conductivity, for example, 600 W / m×K, compared to 149 W / m×K of silicon material, and can be used to effectively fill the horizontal hollow or tunnel region 603 through a CVD process; or an aluminum nitride (AlN) material is used, which has a thermal conductivity of up to 321 W / m×K; or any other suitable Z material 902]. Next, a CVD process is used to fill the horizontal hollow or tunnel region 603 formed by the above-mentioned processing results, for example, BN is selected. Of course, of course, the vacancies in the STI region are filled with BN material (see Fig.16a and Fig.16b ,in Fig.16a and Fig.16b Of course, a suitable material may be tungsten or other metals with high thermal conductivity, as long as the oxide layer 901 separates this material from the silicon body of the transistor.

[0142] Next, a CMP technique may be used to remove the BN material or Z material 902 on the pad nitride layer-1 102 to form a flat surface topography, and an anisotropic etching technique may be further used to remove some of the BN material or Z material 902 on the STI region 201. Next, an oxide layer 903 is deposited on the surface and made coplanar with the pad nitride layer-1 102 (see FIG. Fig.17a and Fig.17b ,in Fig.17a and Fig.17b 2 and 3. A top view and a cross-sectional view are shown respectively.) After the pad nitride layer-2 301 is removed, the silicon surface is covered by the nitride layer-1 201 and the STI region 201 covered by oxide, and a similar process can be performed to complete the MOS transistor in the remaining semiconductor active region.

[0143] As previously described, the STI region 201 extends throughout the entire wafer. Since the HHDP material is all below the body region of the MOSFETs / transistors and connects all VHDC BNs within the STI region 201, this constructed high heat dissipation material network can serve as a connected heat sink for the operating interface of the transistor. By using familiar monolithic process methods to design multiple Z material heat sinks within a monolithic die and the multiple Z material heat sinks are all connected to the edge ring of the chip, the top surface can be opened to contact the BN material or Z material 902 within the STI region 201, so that the heat sink of the entire die can be connected to the outer edge of the chip to dissipate heat more directly and effectively (for example, the lead frame can be designed to allow the BN material or Z material 902 to directly connect to a larger area of ​​lead frame material to meet this function, or a flip-die connection method can be used to dissipate heat from all HHDP and VHDC structures proposed in the present invention) (see Fig.18 ).

[0144] Fig.19 Another final transistor structure is shown, which has HHDP and VHDC microstructures to become a new "low temperature transistor (CQT)". Similarly, Fig.19 The transistors in Fig.11 The transistors in are the same or substantially the same, and their description is omitted here. In addition, Fig.19 The gate metal region 1201, the high dielectric constant (Hi-K) dielectric 1202, the source region 1203, the drain region 1204 and the metal contact component 1205 are respectively Fig.11The middle gate metal region 1101, high-k dielectric 1102, source region 1103, drain region 1104 and metal contact element 1105 have the same functions, so their description is omitted. In addition, in another embodiment, the process of forming the horizontal heat dissipation plate (HHDP) can be omitted and only the vertical heat dissipation column (VHDC) can be constructed. In addition, as mentioned above, Fig.18 and Fig.19 The VHDC in the embodiment can be made of a single high heat dissipation material as mentioned above, and can also be made of a composite structure.

[0145] Some simulation results of 3D low temperature transistor operation and heat generation model have proved the effective points disclosed in the present invention (see Fig. 20 ), where the architecture of the 3D transistor is Fig. 20 When the material of HHDP (corresponding to area 1, such as Fig. 20 As shown in the left figure) is BN, and the material of VHDC (corresponding to the "material at STI", such as Fig. 20 The first column of the upper right table shows that the ΔT (difference between the pn junction temperature T_junction and the ambient temperature T_ambient) is also BN, and the ΔT (difference between the pn junction temperature T_junction and the ambient temperature T_ambient) will be 53°C, when T_ambient is 40°C. On the other hand, if the material of region 1 is oxide and the material at the STI is also oxide, then when T_ambient is 40°C, the ΔT will be as high as 121°C. Therefore, according to the present invention, T_junction is significantly reduced. Fig. 20 The upper right table also lists different material combinations (e.g. oxide, Si, BN) at region 1 and STI and their ΔT results. In addition, the present invention can be applied not only to heat dissipation of transistors, but also to heat dissipation of any circuit device (e.g. resistors, capacitors, diodes, inductors, etc.). The following describes some benefits of the HSiD (heat sink in die) of the present invention, as well as simulation demonstrations using 3D modeling tools:

[0146] (1) Currently, monolithic dies containing a large number of transistors only have heat dissipation paths through silicon materials, oxide materials, and metal interconnect layers, and all of these multiple materials do not have high thermal conductivity. Therefore, the current method is to use an expensive heat sink after the die or packaged chip is completed, and then use a metal plate to contact the vicinity of the die or packaged chip to achieve some heat dissipation path. Afterwards, use expensive liquid cooling methods, or even use electric fan systems to reduce the temperature. These multiple methods are not only added after the monolithic die or chip is formed (not very effective), but also very expensive. This new invention achieves the shortest path near the transistor junction, which should be the most direct and effective cooling method. The heat sink is formed in a monolithic process, and the cost of the heat sink of the present invention is lower than other methods that use external materials and additives and are other non-monolithic processes.

[0147] (2) HHDP and VHDC can be interconnected or formed in-situ through Z material. This on-die heat sink covers almost the entire die area, but compared with SOI structure, the transistor can maintain a bulk structure.

[0148] (3) Since the connected heat sink network can be extended to the edge of the die through appropriate design methods, the heat dissipation path can be extended to the external bonding area or lead frame area or other effective heterogeneous integration methods of the electronic system environment. This invention is believed to be a fundamental change in all future transistor and die / chip design structures, which can very effectively dissipate heat from the die to the system.

[0149] (4) As shown in thermal simulations, the junction temperature of the transistor can be maintained at a much lower temperature (e.g., 65°C) than that of existing transistors (e.g., 105°C). Better PPAC (performance, power, area, cost) will undoubtedly bring better results than expected. Therefore, the possibility of moving towards the TSI era is higher, or it is expected that some high-power applications can be realized by using power transistors and more transistors.

[0150] (5) Since the Z material (eg, BN) is deposited before the formation of transistors or circuit elements, the process of depositing the Z material (eg, BN) will not affect the subsequent formation of transistors or circuit elements.

[0151] Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the definition of the claims.

Claims

1. A device structure, comprising: A semiconductor substrate having an original semiconductor surface; a circuit element located in a semiconductor body region of the semiconductor substrate; and a vertical heat dissipation column in the semiconductor substrate and surrounding the semiconductor body region, The vertical heat dissipation column includes a heat dissipation material, and a thermal conductivity of the heat dissipation material is higher than a thermal conductivity of the semiconductor substrate or higher than a thermal conductivity of silicon oxide.

2. The device structure according to claim 1, characterized in that: The semiconductor substrate comprises an edge region far away from the circuit component. The vertical heat dissipation column extends from a position adjacent to the circuit component to the edge region close to the semiconductor substrate.

3. The device structure according to claim 1, characterized in that: The heat dissipation material is BN, AlN or metal.

4. The device structure according to claim 1, characterized in that: The vertical heat dissipation column includes a layer formed by the heat dissipation material and a heat conduction column, and the heat conduction column covers the layer formed by the heat dissipation material.

5. The device structure according to claim 4, characterized in that: The heat conductive column comprises metal.

6. The device structure according to claim 4, characterized in that: The semiconductor substrate comprises an edge region far away from the circuit element, and the layer formed by the heat dissipation material extends from a position adjacent to the circuit element to the edge region close to the semiconductor substrate.

7. The device structure according to claim 1, characterized in that: The vertical heat dissipation column includes a layer formed by the heat dissipation material and an isolation column, and the isolation column covers the layer formed by the heat dissipation material.

8. The device structure according to claim 7, characterized in that: The spacer comprises silicon oxide.

9. The device structure according to claim 7, characterized in that: The semiconductor substrate includes an edge region away from the circuit element, and the layer formed by the heat dissipation material extends from a position adjacent to or close to the circuit element to the edge region close to the semiconductor substrate.

10. The device structure according to claim 1, characterized in that: The invention further comprises a shallow trench isolation (STI) region surrounding the semiconductor body region, wherein the vertical heat dissipation column is in the shallow trench isolation region.

11. The device structure according to claim 10, characterized in that: The circuit element is a transistor, a resistor, a capacitor, a diode, or an inductor.

12. The device structure according to claim 11, characterized in that: The transistor is a fin structure transistor, a planar transistor, a gate all around transistor (GAA transistor), or a sheet transistor.

13. The device structure according to claim 1, characterized in that: The semiconductor substrate includes an edge area away from the circuit component. The vertical heat dissipation column extends from a position adjacent to the circuit component to the edge area close to the semiconductor substrate. A heat sink is connected to the vertical heat dissipation column close to the edge area of ​​the semiconductor substrate through a hole above the vertical heat dissipation column.

14. The device structure according to claim 1, characterized in that: A heat dissipation substrate is connected to the vertical heat dissipation column through a hole below the vertical heat dissipation column.

15. The device structure according to claim 14, characterized in that: The heat dissipation substrate includes a thermal via or a heat sink connected to the vertical heat dissipation column.

16. A device structure comprising: A semiconductor substrate having an original semiconductor surface; a first transistor located in a first semiconductor body region of the semiconductor substrate; a second transistor located in a second semiconductor body region of the semiconductor substrate, wherein the second transistor is far away from but not close to the first transistor; and A vertical heat dissipation column is provided in the semiconductor substrate, wherein the vertical heat dissipation column comprises a heat dissipation material, a thermal conductivity of the heat dissipation material is higher than a thermal conductivity of the semiconductor substrate or higher than a thermal conductivity of silicon oxide, and the vertical heat dissipation column extends from the first semiconductor body region to the second semiconductor body region.

17. The device structure according to claim 16, characterized in that: The semiconductor substrate includes an edge region far away from the first transistor and the second transistor, and the vertical heat dissipation column further extends to the edge region close to the semiconductor substrate.

18. The device structure according to claim 16, characterized in that: Also includes: a first horizontal heat sink directly below the first transistor; and a second horizontal heat sink, directly below the second transistor, The vertical heat dissipation column connects or thermally couples the first horizontal heat dissipation plate and the second horizontal heat dissipation plate, and the first horizontal heat dissipation plate and / or the second horizontal heat dissipation plate include another heat dissipation material with another thermal conductivity, and the other thermal conductivity of the other heat dissipation material is higher than the thermal conductivity of the semiconductor substrate or higher than the thermal conductivity of silicon oxide.

19. The device structure according to claim 18, characterized in that: The heat dissipation material and / or the other heat dissipation material is BN, AlN, or metal.

20. The device structure according to claim 18, characterized in that: The first horizontal heat dissipation plate is connected or thermally coupled to a bottom surface of a drain region of the first transistor and a bottom surface of a source region of the first transistor, and the first horizontal heat dissipation plate is connected to the vertical heat dissipation column. The second horizontal heat dissipation plate is connected or thermally coupled to a bottom surface of a drain region of the second transistor and a bottom surface of a source region of the second transistor, and the second horizontal heat dissipation plate is connected to the vertical heat dissipation column.

21. The device structure according to claim 20, characterized in that: It further comprises a shallow trench isolation region, wherein the vertical heat dissipation column is in the shallow trench isolation region.

22. The device structure according to claim 21, characterized in that: A top surface of the shallow trench isolation region is higher than the original semiconductor surface, a recess is formed between the shallow trench isolation region and a gate structure of the first transistor, and a metal plug is formed in the recess and contacts a top of the drain region of the first transistor or a top of the source region of the first transistor.

23. The device structure according to claim 18, characterized in that: The first horizontal heat dissipation plate and / or the second horizontal heat dissipation plate further includes a thin oxide layer covering the other heat dissipation material.

24. A device structure comprising: A semiconductor substrate having an original semiconductor surface; a circuit element located in a semiconductor body region of the semiconductor substrate; and a horizontal heat sink in the semiconductor substrate and below the circuit component, The horizontal heat dissipation plate includes a first heat dissipation material with a first thermal conductivity. The first thermal conductivity of the first heat dissipation material is higher than a thermal conductivity of the semiconductor substrate or higher than a thermal conductivity of silicon oxide.

25. The device structure according to claim 24, characterized in that: The first heat dissipation material is BN, AlN or metal.

26. The device structure according to claim 25, characterized in that: The horizontal heat dissipation plate further includes a thin oxide layer covering the first heat dissipation material.

27. The device structure according to claim 24, characterized in that: The invention further comprises a shallow trench isolation (STI) region surrounding the semiconductor body region, and the horizontal heat sink extends outward to the shallow trench isolation region.

28. The device structure according to claim 27, characterized in that: The semiconductor substrate comprises an edge region away from the circuit component, and the horizontal heat dissipation plate further extends to the edge region close to the semiconductor substrate.

29. The device structure according to claim 28, characterized in that: A heat sink is connected to the horizontal heat sink near the edge region of the semiconductor substrate through a hole above the horizontal heat sink.

30. The device structure according to claim 24, characterized in that: A heat dissipation substrate is connected to the horizontal heat dissipation plate through a hole below the horizontal heat dissipation plate.

31. The device structure according to claim 30, characterized in that: The heat dissipation substrate includes a heat conduction through hole or a heat sink connected to the horizontal heat dissipation plate.

32. The device structure according to claim 24, characterized in that: The circuit element is a transistor, a resistor, a capacitor, a diode, or an inductor.

33. The device structure according to claim 24, characterized in that: The circuit component is a transistor, which includes a source region, a drain region and a channel region. The horizontal heat dissipation plate connects a bottom surface of the source region and a bottom surface of the drain region.

34. The device structure according to claim 33, characterized in that: The horizontal heat dissipation plate includes a first horizontal heat dissipation plate and a second horizontal heat dissipation plate. There is a gap between the first horizontal heat dissipation plate and the second horizontal heat dissipation plate, and the gap is directly below the channel area of ​​the transistor.

35. The device structure according to claim 33, characterized in that: There is a first PN junction between the source region and the channel region, and there is a second PN junction between the drain region and the channel region. Both the first PN junction and the second PN junction are located directly above the horizontal heat sink.

36. The device structure according to claim 33, characterized in that: The transistor is a fin structure transistor, and a fin width of the fin structure transistor is substantially the same as a width of the horizontal heat dissipation plate directly below the fin structure transistor.

37. The device structure according to claim 24, characterized in that: It also includes a vertical heat dissipation column, which is in the semiconductor substrate and surrounds the circuit component. The horizontal heat dissipation plate is connected to the vertical heat dissipation column, and the vertical heat dissipation column includes a second heat dissipation material with a second thermal conductivity. The second thermal conductivity of the second heat dissipation material is higher than the thermal conductivity of the semiconductor substrate or higher than the thermal conductivity of silicon oxide.

38. The device structure according to claim 37, characterized in that: The semiconductor substrate comprises an edge region far away from the circuit component, and the vertical heat dissipation column extends from the circuit component to the edge region close to the semiconductor substrate.

39. The device structure according to claim 37, characterized in that: The invention further comprises a shallow trench isolation region surrounding the semiconductor body region, wherein the vertical heat dissipation column is in the shallow trench isolation region.

40. A method for manufacturing a device structure, comprising: Preparing a semiconductor substrate made of a semiconductor material, the semiconductor substrate having an original semiconductor surface; defining an active region having a semiconductor body and forming a shallow trench isolation region surrounding the active region and extending to an edge region of the semiconductor substrate; and A first heat dissipation material is deposited in the shallow trench isolation region, wherein a first thermal conductivity of the first heat dissipation material is higher than a thermal conductivity of the semiconductor substrate or higher than a thermal conductivity of silicon oxide.

41. The manufacturing method according to claim 40, characterized in that The first heat dissipation material extends from the active area to the edge area close to the semiconductor substrate.

42. The manufacturing method according to claim 40, characterized in that Also includes: After forming the first heat dissipation material, a circuit element is formed in the active area, wherein the circuit element is a transistor, a resistor, a capacitor, a diode, or an inductor.

43. The manufacturing method according to claim 40, characterized in that The first heat dissipation material is BN, AlN or metal.

44. The manufacturing method according to claim 40, characterized in that The step of forming the first heat dissipation material comprises: Etching down the shallow trench isolation region to expose a plurality of sidewalls of the semiconductor body; forming a plurality of vertical spacers to cover the exposed sidewalls of the semiconductor body; Further etching down the shallow trench isolation region and exposing a plurality of deeper silicon sidewalls of the semiconductor body; removing the semiconductor material from the exposed deeper silicon sidewalls to form a plurality of empty tunnel regions within the active region; as well as The first heat dissipation material is deposited in the plurality of empty tunnel regions and on the shallow trench isolation region.

45. The manufacturing method according to claim 44, characterized in that The step of removing the semiconductor material from the exposed deeper silicon sidewalls comprises: thermally oxidizing the semiconductor material from the exposed plurality of deeper silicon sidewalls; as well as The oxidized semiconductor material is etched to form the plurality of empty tunnel regions.

46. ​​The manufacturing method according to claim 44, characterized in that The step of removing the semiconductor material from the exposed deeper silicon sidewalls comprises: The semiconductor material is laterally etched from the exposed deeper silicon sidewalls to form the empty tunnel regions.

47. The manufacturing method according to claim 44, characterized in that Also includes: Before depositing the first heat dissipation material in the plurality of empty tunnel regions, the semiconductor material exposed by the plurality of empty tunnel regions is thermally oxidized.

48. The manufacturing method according to claim 47, characterized in that Also includes: Before depositing the first heat dissipation material in the plurality of empty tunnel regions, the plurality of vertical spacers are removed.

49. The manufacturing method according to claim 40, characterized in that Also includes: Before etching the shallow trench isolation region downward to expose the plurality of sidewalls of the semiconductor body, a protection layer is formed covering a central portion of the active region.

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