Devices, systems, and methods for embedded bridge architecture

Abstract

Methods, systems, and devices are disclosed that include a first layer including a first computing device, a first multi-device package, and a second multi-device package. The first computing device may be between the first multi-device package and the second multi-device package. The second layer may include a first redistribution layer on a first side of the second layer facing the first layer, the first redistribution layer electrically connecting the first computing device to the first multi-device package, and the first redistribution layer electrically connecting the first computing device to the second multi-device package. The first layer may include a third multi-device package and a fourth multi-device package, wherein the first computing device is between the third multi-device package and the fourth multi-device package.

Description

Technical Field

[0001] The subject matter disclosed herein relates to microelectronic packaging and integrated circuit (IC) packaging. More particularly, the subject matter disclosed herein relates to a packaging architecture featuring a bridge. Background Art

[0002] Semiconductor devices can be connected to additional devices and circuits on different substrates. Forming connections between substrates can provide increased computing. However, forming connections between substrates can lead to complications. Packaging describes a general method for connecting and integrating multiple computing components together in an integrated unit, and can involve multiple different types of integrated circuits on multiple substrates that can be combined into a single unit. Packaging can also describe a method of protecting multiple computing components within a single unit by using various techniques that provide thermal, physical, and electrical protection. The background technology concepts discussed herein are for informational purposes only and are not intended to limit the present disclosure. The background technology or fields described herein should not be intended to limit the disclosure herein to a specific use or concept. Summary of the invention

[0003] Example embodiments provide a device including a first layer, the first layer including a first computing device, a first multi-device package, and a second multi-device package. The first computing device may be between the first multi-device package and the second multi-device package. The second layer may include a first redistribution layer on a first side of the second layer facing the first layer, the first redistribution layer electrically connecting the first computing device to the first multi-device package, and the first redistribution layer electrically connecting the first computing device to the second multi-device package. The first layer may include a third multi-device package and a fourth multi-device package, wherein the first computing device is between the third multi-device package and the fourth multi-device package. The first redistribution layer may electrically connect the first computing device to the third multi-device package, and the first redistribution layer may electrically connect the first computing device to the fourth multi-device package. The first computing device may be between the second multi-device package and the fourth multi-device package. The first layer may include a second computing device, a fifth multi-device package, and a sixth multi-device package, wherein the second computing device is between the sixth multi-device package and the fifth multi-device package. The first redistribution layer may electrically connect the second computing device to the sixth multi-device package, and the first redistribution layer may electrically connect the second computing device to the fifth multi-device package. The second layer may include a second redistribution layer on a second side of the second layer, the second side being opposite to the first side. The first bridge may be arranged between the first redistribution layer and the second redistribution layer. The first multi-device package may include at least a first device stack and a second device stack on the first multi-device die. The first device stack may include one or more of a memory device and a processing device. The first multi-device die may electrically connect the first device stack and the second device stack to the first redistribution layer.

[0004] Example embodiments provide a system including a first layer having a first computing device, a first multi-device package, and a second multi-device package. The first computing device may be between the first multi-device package and the second multi-device package. The second layer may include a first bridge and a second bridge, the first bridge electrically connecting the first computing device to the first multi-device package, and the second bridge electrically connecting the first computing device to the second multi-device package. The first layer may include a second computing device, a third multi-device package, and a fourth multi-device package. The second layer may include a third bridge and a fourth bridge, wherein the third bridge electrically connects the second computing device to the third multi-device package, and the fourth bridge electrically connects the second computing device to the fourth multi-device package. The second layer may include a first redistribution layer on a first side of the second layer, the first redistribution layer between the first bridge and the first multi-device package. The second layer may include a second redistribution layer, the second redistribution layer on a second side of the second layer opposite to the first side, the first bridge between the first redistribution layer and the second redistribution layer. The first multi-device package may include at least one memory device or a processing device. The first layer may include a base die, the base die between the first computing device and the first bridge.

[0005] Example embodiments provide a method comprising: forming an interposer having a first bridge and a second bridge; forming a first redistribution layer on a first side of the interposer, the first redistribution layer being communicatively coupled to the first bridge and the second bridge; mounting a computing device on the interposer and on the first redistribution layer; mounting a first multi-device package and a second multi-device package on the interposer and on the first redistribution layer, the computing device being arranged between the first multi-device package and the second multi-device package; depositing a dielectric layer over the interposer, coupling the first multi-device package to the computing device via the first bridge; and coupling the second multi-device package to the computing device via the second bridge. The first multi-device package and the second multi-device package may have substantially identical devices. Mounting the computing device on the interposer may include mounting a base die on the first redistribution layer and mounting the computing device on the base die. Forming the interposer may include forming a second redistribution layer on a second side of the interposer, the second side being opposite to the first side. Depositing a dielectric layer over the interposer may include depositing a dielectric material between the first multi-device package, the second multi-device package, and the computing device. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In the following sections, various aspects of the subject matter disclosed herein will be described with reference to exemplary embodiments shown in the accompanying drawings, in which:

[0007] Figure 1A depicts a perspective view of an example embodiment of a package structure according to various embodiments of the subject matter disclosed herein;

[0008] Figure 1Bdepicts an enlarged perspective view of an example embodiment of a package structure according to various embodiments of the subject matter disclosed herein;

[0009] Figure 2 depicts a plan view of an example embodiment of a package structure according to various embodiments of the subject matter disclosed herein;

[0010] Figure 3 depicts a plan view of an example embodiment of a package structure according to various embodiments of the subject matter disclosed herein;

[0011] Figure 4A Depicting a cross-sectional view of an example embodiment of a package structure assembly at a first time according to various embodiments of the subject matter disclosed herein;

[0012] Figure 4B Depicting a cross-sectional view of an example embodiment of a package structure assembly at a second time according to various embodiments of the subject matter disclosed herein;

[0013] Figure 4C depicts a cross-sectional view of an example embodiment of a package structure assembly at a third time according to various embodiments of the subject matter disclosed herein;

[0014] Figure 4D depicts a cross-sectional view of an example embodiment of a package structure assembly at a fourth time according to various embodiments of the subject matter disclosed herein;

[0015] Figure 5 Depicted are example embodiments of methods of forming a package structure according to various embodiments of the subject matter disclosed herein;

[0016] Figure 6 Depicting a cross-sectional view of an example embodiment of a package structure assembly according to various embodiments of the subject matter disclosed herein;

[0017] Figure 7 depicts a plan view of an example embodiment of a package structure assembly according to various embodiments of the subject matter disclosed herein;

[0018] Fig. 8A Depicting a cross-sectional view of an example embodiment of a package structure assembly at a first time according to various embodiments of the subject matter disclosed herein;

[0019] Figure 8B Depicting a cross-sectional view of an example embodiment of a package structure assembly at a second time according to various embodiments of the subject matter disclosed herein;

[0020] Figure 8C depicts a cross-sectional view of an example embodiment of a package structure assembly at a third time according to various embodiments of the subject matter disclosed herein;

[0021] Fig.8Ddepicts a cross-sectional view of an example embodiment of a package structure assembly at a fourth time according to various embodiments of the subject matter disclosed herein;

[0022] Fig. 8E depicts a cross-sectional view of an example embodiment of a package structure assembly at a fifth time according to various embodiments of the subject matter disclosed herein;

[0023] Figure 8F depicts a cross-sectional view of an example embodiment of a package structure assembly at a sixth time according to various embodiments of the subject matter disclosed herein;

[0024] Figure 8G depicts a cross-sectional view of an example embodiment of a package structure assembly at a seventh time according to various embodiments of the subject matter disclosed herein; and

[0025] Fig. 9 An example embodiment of a method of forming a package structure according to various embodiments of the subject matter disclosed herein is depicted. DETAILED DESCRIPTION

[0026] In the following detailed description, many specific details are set forth in order to provide a thorough understanding of the present disclosure. However, those skilled in the art will appreciate that the disclosed aspects may be practiced without these specific details. In other instances, well-known methods, processes, components, and circuits are not described in detail to avoid obscuring the subject matter disclosed herein.

[0027] References throughout this specification to "one embodiment" or "embodiment" mean that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment disclosed herein. Therefore, the phrases "in one embodiment" or "in an embodiment" or "according to an embodiment" (or other phrases with similar meanings) that appear in various places throughout this specification may not necessarily all refer to the same embodiment. In addition, specific features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In this regard, as used herein, the word "exemplary" means "used as an example, instance or illustration". Any embodiment described herein as "exemplary" should not be interpreted as necessarily being more preferred or advantageous than other embodiments. In addition, specific features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In addition, depending on the context discussed herein, singular terms may include corresponding plural forms, and plural terms may include corresponding singular forms. Similarly, hyphenated terms (e.g., "two-dimensional," "predetermined," etc.) may occasionally be used interchangeably with corresponding non-hyphenated versions (e.g., "two-dimensional," "predetermined," etc.), and capitalized terms (e.g., "counterclockwise," "three-dimensional," etc.) may be used interchangeably with corresponding non-capitalized versions (e.g., "counterclockwise," "three-dimensional," etc.). Such occasional interchangeable usage should not be considered inconsistent with each other.

[0028] In addition, depending on the context of the discussion herein, singular terms may include corresponding plural forms, and plural terms may include corresponding singular forms. It should also be noted that the various drawings (including component drawings) shown and discussed herein are for illustrative purposes only and are not drawn to scale. For example, for clarity, the size of some elements may be enlarged relative to other elements. In addition, if deemed appropriate, reference numerals are repeated in the drawings to indicate corresponding and / or similar elements.

[0029] The terms used herein are only used for the purpose of describing some example embodiments and are not intended to limit the claimed subject matter. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "include" and / or "comprise" specify the presence of the features, integers, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups thereof.

[0030] It should be understood that when an element or layer is referred to as being on, "connected to" or "coupled to" another element or layer, it can be directly on, directly connected to or coupled to another element or layer, or there can be intermediate elements or layers. In contrast, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element or layer, there are no intermediate elements or layers. The same reference numerals always refer to the same elements. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items.

[0031] As used herein, the terms "first", "second", etc. are used as labels for the nouns that precede them and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) unless explicitly defined as such. In addition, the same figure mark may be used across two or more figures to refer to parts, components, blocks, circuits, units, or modules with the same or similar functions. However, such use is only for simplicity of illustration and ease of discussion; it does not mean that the construction or architectural details of such components or units are the same in all embodiments, or that such commonly referenced parts / modules are the only way to implement some example embodiments disclosed herein.

[0032] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the subject matter belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly so defined herein.

[0033] As used herein, a substrate may refer to various materials and structures, including wafers using silicon, wafers using silicon on insulator (SOI) (such as glass), wafers of other semiconductor materials (such as germanium), and other semiconductor materials on insulators. In some embodiments, the substrate may include organic materials. In some embodiments, the substrate may be referred to as a wafer, a die, and a chip individually or in combination. Therefore, in some embodiments, the bonding substrate may be referred to as a die-to-die (D2D) bonding, a wafer-to-wafer bonding (W2W), or a die-to-wafer bonding (D2W). In some embodiments, the substrate may include circuits, such as integrated circuits, including central processing units (CPUs), logic chips, memories (such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate DRAM or DDR DRAM), application processors (AP), graphics processing units (GPUs), other forms of auxiliary processing units (xPU), artificial intelligence (AI) chips, high bandwidth memory (HBM) interfaces, and other application-specific integrated circuits (ASICs). In some embodiments, a combination of circuits may be present on a substrate. In some embodiments, the substrate may include a packaged chip.

[0034] As used herein, high bandwidth memory or HBM may refer to a chip structure that includes one or more HBM modules. In some embodiments, HBM may be manufactured by advanced silicon node processes.

[0035] As used herein, packaging refers to the process of forming interconnections between substrates. In some embodiments, the interconnection can be between direct surfaces and involve W2W, D2D and D2W bonding. In other embodiments, the technology including wire bonding and other forms of indirect bonding can be performed alone or in combination with W2W, D2D and D2W bonding. In some embodiments, the circuits can be bonded directly facing each other, and in other embodiments, flip chip bonding can be used. In some embodiments, interconnection can be performed between substrates on the front side or circuit side of the substrate. In other embodiments, interconnection can be performed on the back or back side of the substrate opposite to the circuit structure. In some embodiments, the interconnection may include through-silicon vias (TSVs) or other forms of through-chip vias, in which one or more substrates can be connected using a path that travels through an interposer (such as another substrate or chip). In some embodiments, connections on the surface of a substrate (such as a pad) can be used to form interconnections, and additional materials (such as solder) between pads can be used to form interconnections.

[0036] As used herein, a conductor may refer to a variety of conductive materials, including materials that may be used alone or in combination with other materials, such as in the form of alloys. In some embodiments, the conductor is copper (Cu). In some embodiments, the copper (Cu) may be in the form of Cu(II), Cu(III), or other forms of copper, alone or in combination with additional elements, including cobalt (Co) and ruthenium (Ru). Such a list of elements is not intended to be exhaustive, and in other embodiments, any other known type of conductive material may be used.

[0037] As used herein, a device stack or stack of devices may refer to a combination of memory and supporting circuit architectures, for example, chiplets and dies containing separate memory elements, supporting processing units, input-output (I / O) circuits, and other forms of integrated chips. As used herein, hybrid bonding may be defined as bonding a conductive portion to a conductive portion (such as a metal-metal bond), and bonding a dielectric portion to a dielectric portion (such as a dielectric-dielectric bond).

[0038] As used herein, a bridge refers to a substrate, die, or other material having one or more conductive paths that can form a connection between one or more semiconductor devices and a substrate, interposer, or other packaging structure. The bridge may include one or more traces that form a connection path along the bridge between one or more devices connected to the bridge. An embedded bridge as used herein may refer to a bridge in a layer within a semiconductor package and may be used interchangeably with a bridge.

[0039] Various embodiments of devices, systems, and methods related to packaging architectures are disclosed herein to modularly create stacked logic and memory building block frames. Increasing the number of devices and the number of device stacks can utilize additional methods of connecting computing devices to device stacks to allow for more intensive computing. The stacked logic and memory building block architecture may include a base chip that provides logic, routing, and power delivery to one or more device stacks. A multi-stacked die may include one or more device stacks on a shared substrate. The multi-stacked die may then be mounted on a shared interposer with a computing device and additional multi-stacked dies. Signals between the computing device and the device stack may be routed via a shared interposer, including routing via one or more bridges in a shared interposer that may be embedded between two or more redistribution layers. As used herein, a device stack or stack of devices may refer to a combination of memory and supporting circuit architectures, for example, a chiplet and die containing separate memory elements, supporting processing units, I / O circuits, and other forms of integrated chips.

[0040] In some embodiments, a backside power delivery network (BSPDN) may be formed on the back side of a substrate and have a signal network formed on the front side of the same substrate. In some embodiments, the BSPDN and the signal network may be formed on separate substrates and transferred to the same substrate. The BSPDN and the signal network may be separated by a transistor layer. The transistor layer may also include multiple transistors. Transistors may provide different functions and take different forms, including a logic layer. The BSPDN and the signal network may form a single monolithic structure on the same die in a semiconductor foundry process. The stacked device module may be formed separately in a semiconductor foundry process, the same semiconductor foundry process, or may have multiple components formed in multiple semiconductor foundry processes and assembled in a package assembly process.

[0041] Figure 1A A perspective view of an exemplary embodiment of a device packaging architecture 100 is depicted. Figure 1B An enlarged view of a portion of a device package architecture 100 is depicted. A support substrate 102 supports an interposer 104. The interposer 104 connects one or more multi-device packages 112 on a multi-device die 120 to a first computing device 108 and a second computing device 109. The first computing device 108 and the second computing device 109 can be mounted on a base die 106. In some embodiments, a single computing device can be used, while in other embodiments, additional computing devices can be added, for example, 4, 6, 8, 16, or 32 computing devices can be added. In some embodiments, the first computing device 108 and the second computing device 109 can share the same base die 106, while in other embodiments, each computing device can have a separate base die 106. In some embodiments, the base die 106 can be a silicon die, while in other embodiments, various semiconductor materials can be used. In some embodiments, the computing device can include a die, a core, or a chiplet, as well as any other suitable form of circuit. As used herein, a chiplet may refer to an integrated circuit with well-defined functions, such as a microprocessor, memory device, or other computing function; wherein the chiplet enables modular design, and wherein multiple chiplets can be combined with a larger package, sharing a substrate or interposer to form a larger device. A core may refer to a single unit of a multi-core device in which multiple devices form a larger device, and wherein each device can function independently to implement multiple operation flows. In some embodiments, a core may take the form of a chiplet, or a chiplet may take the form of a core. However, in other embodiments, a chiplet may take the form of any other suitable integrated circuit.

[0042] Figure 2 A plan view of the device package architecture 100 is provided, showing the layout of the first computing device 108 and the second computing device 109 on the interposer 104 . Figure 3 A cross-sectional view of a device package architecture 100 is provided, showing one or more multi-device packages 112 mounted on a base interposer 104. The one or more multi-device packages 112 may include a plurality of multi-device packages. In the example embodiment shown in FIGS. 1 and 2 , a first multi-device package 113, a second multi-device package 114, a third multi-device package 115, a fourth multi-device package 116, a fifth multi-device package 117, and a sixth multi-device package 118 are included. The first multi-device package 113, the third multi-device package 115, and the fifth multi-device package 117 are on a first side of the base die 106, while the second multi-device package 114, the fourth multi-device package 116, and the sixth multi-device package 118 are on a second side of the base die 106 opposite the first side.

[0043] One or more multi-device packages 112 may include a multi-device die 120 on which a plurality of devices in chip or die form are mounted. Figure 3 In an embodiment of the present invention, the multi-device die 120 may have a first device 122 and a second device 124 mounted thereon. In some embodiments, the device may be various forms of memory, including DRAM, SRAM, and other forms of memory. In some embodiments, the device may include a core device, such as a processor or other form of microcontroller, to serve as a controller. In some embodiments, the first device 122 and the second device 124 may each include a stack of one or more devices. In some embodiments, the stack of devices may include memory devices, core devices, and combinations thereof. In some embodiments, the first device 122 and the second device 124 may include the same component devices, while in other embodiments, the component devices in the first device 122 and the second device 124 may be different. In some embodiments, the through-path may electrically connect the individual devices within the device stack to each other and to the multi-device die 120.

[0044] The number of devices within the stack of each device may vary, and the number and type of devices provided may vary based on the relative amount of computation required for each device. For example, a desired ratio between core dies and memory dies may be desired, such as 1 core per 4 memory dies may be desired in some embodiments. However, in other embodiments, for example, the ratio may vary, and in some embodiments, the ratio may be greater and include 1 core per 5, 6, 10, or even 16 memory dies.

[0045] In addition, if Figure 3 As seen in the exemplary view of FIG. 1 , a first encapsulation layer 132, such as a dielectric layer or an adhesive layer (such as a resin or epoxy) may be provided between the first device 122, the second device 124, and the multi-device die 120. In some embodiments, such as silicon nitride (Si3 N 4 ), silicon dioxide (SiO 2 ) or any other suitable dielectric material may be used to form the first encapsulation layer 132. In some embodiments, the first device 122 and the second device 124 may be encapsulated by such a first encapsulation layer 132, and may include additional encapsulation layers on the sides or top of the first device 122 and the second device 124.

[0046] In some embodiments, one or more central encapsulation layers 136 may surround computing devices including first computing device 108 and second computing device 109. Figure 3 In the example embodiment of FIG. 1 , the central encapsulation layer 136 surrounds the first computing device 108 and the second computing device 109. Additionally, one or more overmold layers 152 may surround the computing devices and the one or more multi-device packages 112. The overmold layer 152 may be a dielectric material, and in some embodiments, the mold layer may provide mechanical support, such as holding the devices in place, as well as provide electrical isolation, and may provide a thermal path for heat to pass from the devices to the transfer pathways.

[0047] On one or more multi-device packages 112, first device 122 and second device 124 may be electrically coupled to one or more routing layers 121 within multi-device die 120. One or more routing layers 121 within multi-device die 120 may, in turn, couple first device 122 and second device 124 to interposer 104. Interposer 104 may include one or more redistribution layers 105 that allow first device 122 and second device 124 to be electrically coupled to first computing device 108 and / or second computing device 109 via base die 106. Base die 106 may also include base redistribution layers 107 that allow first computing device 108 and second computing device 109 to communicate with support substrate 102.

[0048] Although in Figure 1A and Figure 3 In the exemplary embodiment of FIG. 1-1 , the first device 122 and the second device 124 are shown on a single multi-device package 112 in the one or more multi-device packages 112 , but each multi-device package 112 in the one or more multi-device packages 112 may include a pair of devices on its corresponding multi-device die 120 . Figure 3 , first multi-device package 113 includes first device 122 and second device 124, while third device 126 and fourth device 128 are shown on second multi-device package 114. Third device 126 and fourth device 128 may include second encapsulation layer 134 similar to first encapsulation layer 132.

[0049] Although referred to as wiring layers, one or more wiring layers 121 may take the form of a series of pads, bumps, vias, through vias, traces, redistribution layers, and other forms of connections for redistributing signals in various combinations. Similarly, one or more redistribution layers 105 and base redistribution layers 107 may also take the form of a series of pads, bumps, vias, through vias, traces, redistribution layers, and other forms of connections for redistributing signals in various combinations.

[0050] In some embodiments, the support substrate 102 may be an organic substrate such as a polymer, while in other embodiments, an inorganic substrate such as a semiconductor including silicon may be used, or an SOI substrate such as glass may be used alternatively. In some embodiments, the interposer 104 may be made of silicon, while in other embodiments, another form of semiconductor such as germanium may be used. In some embodiments, multiple interposer substrates may be shared on a single support substrate. In some embodiments, the support substrate 102 may be a plurality of substrates, and in some embodiments may be a plurality of substrates stacked on each other. The support substrate 102 may have an interposer 104 mounted thereon in various ways, and may include pads, bumps, microbumps, columns, balls, and other forms, such as controlled collapse chip connection (C4) bumps, either individually or in combination. As used herein, a C4 bump refers to a form of solder bump placed on a pad on the top surface of a substrate before flipping the substrate to form a flip chip. The mounting method may also include a dielectric material, which may include a material such as an adhesive, a resin, or an elastomer, which may form a connection other than a conductive connection. In some embodiments, a combination of a conductive connection and a dielectric connection may form a hybrid bond.

[0051] In addition to or in lieu of computing devices and multi-device packages, interposer 104 may include additional devices. Figure 1A In an exemplary embodiment of the present invention, one or more of the connectivity chiplets 110 can be mounted on the interposer 104. The connectivity chiplets 110 can include I / O circuits to allow the device package architecture 100 to connect to additional devices. For example, in some embodiments, the connectivity chiplets 110 can provide wireless connectivity using one or more forms of radio frequency protocols for one or more frequency spectrums. In some embodiments, the connectivity chiplets 110 can provide optical or wired communications alone or in combination with wireless communications.

[0052] In addition, if Figure 2 and Figure 3As shown in the exemplary embodiment of the present invention, the reinforcement 130 can surround the perimeter on the support substrate 102. The reinforcement 130 can be one or more parts of a rigid material to provide additional mechanical support to the support substrate 102. The reinforcement 130 can be made of a material having a higher elastic modulus than the elastic modulus of the support substrate 102, and thus can include materials such as metals (e.g., aluminum, copper, or steel), ceramics, composite materials, or another suitable material. The reinforcement 130 can be used in conjunction with a cover design to provide additional protection for the device packaging architecture 100, including preventing mechanical distortion, deformation, and warping. In some embodiments, the cover can be used to provide additional mechanical, thermal, and electrical protection for the device packaging architecture 100. In some embodiments, a coverless design can be used instead.

[0053] Figure 3 104 to the support substrate 102. Such conductive interconnects may include pads, bumps, microbumps, pillars, balls, and other forms, such as controlled collapse chip connection C4 bumps, alone or in combination. In some embodiments, the bonding layer 160 may also include a dielectric material or adhesive to provide additional strength and connection between the interposer 104 and the support substrate 102. In some embodiments, the bonding layer 160 may provide a metal bond between the interposer 104 and the support substrate 102, a dielectric bond between the interposer 104 and the support substrate 102, or in some embodiments, a bond between the interposer 104 and the support substrate 102. In some embodiments, the dielectric material or adhesive material may be inserted using an underfill technique and leave a residue 162 on the surface of the support substrate 102.

[0054] Figures 4A-4D An illustrative embodiment of a process of forming a device package architecture, such as device package architecture 100 or any other device package architecture shown herein, is depicted. Figure 5 Depicted are the components used to form Figures 4A-4D An example embodiment of a process 500 for assembling a device package of an illustrative embodiment is provided.

[0055] Figure 4A Depicted in Figure 5At S510 in, the first device package 402, the second device package 404, and the third device package 406 are each individually mounted on their own supporting tube core. For example, the first device package 402 may include the first computing device 108 and the second computing device 109 on the base tube core 106. The central encapsulation layer 136 can hold the first computing device 108 and the second computing device 109 on the base tube core 106, and can be formed to form the first device package 402 into a substantially regular shape with a flat surface. For the second device package 404 and the third device package 406, they can take the form of one or more multi-device packages 112 including the first device 122 and the second device 124 on the multi-device tube core 120. The first encapsulation layer 132 can hold the first device 122 and the second device 124 on the multi-device die 120, the second encapsulation layer 134 can hold the third device 126 and the fourth device 128 on the multi-device die 120, and the first and second encapsulation layers 132 and 134 can be formed to form the second device package 404 and the third device package 406 into a substantially regular shape with a flat surface. The mounting can take the form of various bonding methods, including metal bonding, dielectric bonding, and hybrid bonding. Additionally or alternatively, additional interconnect technologies can be used, including adhesives such as resins or epoxies. The device and computing device can be mounted using a back-end-of-line (BEOL) process. In some embodiments, the first encapsulation layer 132, the second encapsulation layer 134, and the center encapsulation layer 136 may be provided before the first device package 402, the second device package 404, and the third device package 406 are mounted on the interposer 104, while in some embodiments, the first encapsulation layer 132, the second encapsulation layer 134, and the center encapsulation layer 136 may be provided after the first device package 402, the second device package 404, and the third device package 406 are mounted on the interposer 104.

[0056] Figure 4B Depicted in Figure 5 At S520 in the embodiment, the first device package 402, the second device package 404, and the third device package 406 are mounted to the interposer 104 shared by all three devices. The mounting can take the form of various bonding methods, including metal bonding, dielectric bonding, and hybrid bonding to the connection on the device, including pads, bumps, microbumps, pillars, balls, and other forms, such as C4 bumps, alone or in combination. The mounting provides electrical connection between the computing device on the first device package 402 and the devices on the second device package 404 and the third device package 406.

[0057] Figure 4C Depicted in Figure 5At S530 in, after the first device package 402, the second device package 404, and the third device package 406 are mounted to the interposer 104, the overmold layer 152 is deposited on the first device package 402, the second device package 404, and the third device package 406. The overmold layer 152 can be a dielectric material and is deposited to encapsulate the first device package 402, the second device package 404, and the third device package 406 to the interposer 104, as well as to provide mechanical support, thermal insulation, and electrical separation. In some embodiments, the overmold layer 152 can be one or more layers of dielectric material and can be formed by an overmold process. In some embodiments, any excess material deposited on the device can be subjected to a process for smoothing and / or flattening the surface of the device, which process includes one or more grinding, polishing, and smoothing processes, including chemical mechanical polishing (CMP). In some embodiments, a thermal processing step or a heat treatment step can be used to fix the overmold layer 152 in place.

[0058] Figure 4D Depicted in Figure 5 At S540 in, the interposer 104 on which the first device package 402, the second device package 404, and the third device package 406 are mounted is mounted on the support substrate 102. The interposer 104 can be mounted to the support substrate 102 using various bonding methods, including metal bonding, dielectric bonding, and hybrid bonding to the connection on the device, including pads, bumps, microbumps, columns, balls, and other forms, such as C4 bumps, alone or in combination. In addition, a stiffener 130 may be formed on the support substrate 102 to surround the interposer 104. The stiffener 130 may be formed directly on the support substrate 102, such as by additive manufacturing of a suitable material, to provide additional rigidity to the support substrate 102, or may be formed separately and mounted on the support substrate 102 using a bonding process or an adhesive (e.g., epoxy or resin). In some embodiments, an additional layer of molding material or encapsulation material may be deposited between the interposer 104 and the stiffener 130. In some embodiments, a cover (not shown) may be further mounted to the device package architecture 100 and attached to the stiffener 130.

[0059] Figure 6 Another exemplary embodiment of an embedded bridge device packaging architecture 600 is depicted in cross-section. Figure 7 A plan view of an exemplary embodiment of an embedded bridge device packaging architecture 600 is provided. Figure 6 and Figure 7The embedded bridge device package architecture 600 of FIG. 1-3 differs from the device package architecture 100 of FIG. 1-3 in the presence of a bridge interposer 604, which differs from the interposer 104 in terms of the connections formed on and within the interposer structure. The bridge interposer 604 may include one or more embedded bridges 602 to provide a connection between the base die 106 and the one or more multi-device packages 112. The one or more embedded bridges 602 may include one or more conductive pathways to provide an electrical connection between the base die 106 and the one or more multi-device packages 112. In some embodiments, the one or more embedded bridges 602 may be used to connect the base die 106 to multiple of the one or more multi-device packages 112, while in other embodiments, the one or more embedded bridges 602 may connect the base die 106 to only one of the multi-device packages 112. In some embodiments, as Figure 6 and Figure 7 As shown, a plurality of embedded bridges 602 may be used to connect each of the multi-device packages 112 to the base die 106 , with one or more of the embedded bridges 602 being used for each of the multi-device packages 112 .

[0060] One or more embedded bridges 602 may include a first embedded bridge 620 for connecting the base die 106 to the first multi-device package 113, a second embedded bridge 621 for connecting the base die 106 to the second multi-device package 114, a third embedded bridge 622 for connecting the base die 106 to the third multi-device package 115, a fourth embedded bridge 623 for connecting the base die 106 to the fourth multi-device package 116, a fifth embedded bridge 624 for connecting the base die 106 to the fifth multi-device package 117, and a sixth embedded bridge 625 for connecting the base die 106 to the sixth multi-device package 118.

[0061] In addition, the bridge interposer 604 includes a first redistribution layer (RDL) 612 on the bottom side of the bridge interposer 604 and a second RDL 614 on the top side of the bridge interposer 604. In addition, the conductive pillars 606 can electrically connect the first RDL 612 to the second RDL 614. The bridge interposer 604 can include a molding layer 608 between the first RDL 612 and the second RDL 614. In some embodiments, the molding layer 608 can be a dielectric material that provides thermal insulation, mechanical separation, and electrical insulation between the first RDL 612, the second RDL 614, and the conductive pillars 606. The first RDL 612 can provide a series of pads, bumps, vias, through vias, traces, and other forms of connections for redistributing signals from the supporting substrate 102 to the bridge interposer 604. The second RDL 614 may in turn provide a series of pads, bumps, vias, through-vias, traces, and other forms of connections for redistributing signals from the bridge interposer 604 to the computing devices of the base die 106 and the one or more multi-device packages 112. Thus, the first and second RDLs 612, 614, and the conductive pillars 606 may provide connections between the support substrate 102, the computing devices of the base die 106, and the one or more multi-device packages 112.

[0062] exist Figure 6 A bonding layer 160 is also depicted in the exemplary embodiment of the present invention. The bonding layer 160 may include a conductive interconnect to connect the bridge interposer 604 to the support substrate 102. Such conductive interconnects may include pads, bumps, microbumps, pillars, balls, and other forms, such as controlled collapse chip connection C4 bumps, alone or in combination. In some embodiments, the bonding layer 160 may also include a dielectric material or adhesive to provide additional strength and connection between the bridge interposer 604 and the support substrate 102. In some embodiments, the bonding layer 160 may provide a metal bond between the bridge interposer 604 and the support substrate 102, a dielectric bond between the bridge interposer 604 and the support substrate 102, or a bond between the bridge interposer 604 and the support substrate 102 in some embodiments. In some embodiments, the bonding layer 160 may be directly bonded to the first RDL 612, while in other embodiments, an intermediate layer may be between the bonding layer 160 and the first RDL 612. In some embodiments, the dielectric material or adhesive material may be inserted using an underfill technique and leave a residue 162 on the surface of the support substrate 102.

[0063] Figures 8A-8F An illustrative embodiment of a process of forming a device package architecture, such as the embedded bridge device package architecture 600 or any other device package architecture described herein, is depicted. Fig. 9 Depicted are the components used to form Figures 8A-8F An example embodiment of a process 900 for assembling a device package of an illustrative embodiment is provided.

[0064] Fig. 8A Depicted in Fig. 9 At S910 in, wherein a first RDL 612 is formed on a carrier substrate 802. The carrier substrate 802 may be any suitable substrate, such as a glass substrate. In some embodiments, before the first RDL 612 is formed on the carrier substrate 802, a release layer may be formed on the carrier substrate 802. The release layer may include a material that acts as a sacrificial layer and can be cleanly removed from the carrier substrate 802 and the first RDL 612, such as a polymer, wax, epoxy, or resin. In some embodiments, the first RDL 612 may be formed using a complementary metal oxide semiconductor (CMOS) process (such as deposition, photolithography, etching, passivation directly on the carrier substrate 802). In some embodiments, the first RDL 612 may be formed on a separate substrate and transferred to the carrier substrate 802.

[0065] Figure 8B Depicted in Fig. 9 At S920 in the embodiment, a conductive pillar 606 is formed on the first RDL 612. The conductive pillar 606 may include a conductive material, including a metal such as copper, and other known conductive materials such as doped carbon. The conductive pillar 606 is bonded to the first RDL 612 and may form an interconnect layer for a second RDL 614 that is added later. In some embodiments, the conductive pillar 606 may be bonded using a metal diffusion bond between the metal material forming the conductive pillar 606 and the corresponding metal material within the first RDL 612.

[0066] Figure 8C Depicted in Fig. 9 At S930 in the step, a mold layer 608 is deposited over the conductive pillars 606 and the first RDL 612. The mold layer 608 may be a dielectric material and is deposited to provide electrical separation between the first RDL 612 and the second RDL 614 added at S940. The mold layer 608 may also provide a dielectric surface for providing a hybrid bonding structure with the second RDL 614 having the base die 106 and one or more multi-device packages 112. The mold layer 608 may also provide a surface for embedding one or more of the one or more embedded bridges 602. After embedding one or more of the one or more embedded bridges 602, the surfaces of the one or more embedded bridges 602, the mold layer 608, and the conductive pillars 606 may be subjected to a process for smoothing and / or planarizing the surface, which process includes one or more grinding, polishing, and smoothing processes, including CMP.

[0067] Fig.8D Depicted in Fig. 9At S940 in the figure, a second RDL 614 is formed on the surface of the conductive pillars 606, the mold layer 608, and one or more of the embedded bridges 602. The second RDL 614 includes a series of pads, bumps, vias, through-vias, traces, and other forms of connections for redistributing signals from the embedded layer to the appropriate locations on the top of the second RDL 614. In some embodiments, a portion of the mold layer 608 may be exposed to provide a suitable dielectric surface for forming a hybrid bond. The formation of the second RDL 614 and the first RDL 612 and the components therebetween may be referred to as a bridge interposer 604.

[0068] Fig. 8E Depicted in Fig. 9 At S950 in the figure, the packaged device 825 is mounted on the bridge interposer 604. The packaged device 825 includes a first packaged device 804, a second packaged device 806, and a third packaged device 808, which may be individually assembled devices on their own supporting dies. For example, the first packaged device 804 may include a first computing device 108 and a second computing device 109 on a base die 106, wherein a central encapsulation layer 135 encapsulates the first computing device 108 and the second computing device 109 on the base die 106. The second packaged device 806 and the third packaged device 808 may each take the form of one or more multi-device packages 112, which include a first device 122 and a second device 124 on a multi-device die 120, wherein a first encapsulation layer 132 encapsulates the first device 122 and the second device 124 on the multi-device die 120. The mounting may be performed by various bonding methods, including metal bonding, dielectric bonding, and hybrid bonding. Additionally or alternatively, additional interconnect technologies may be used, including adhesives such as resins or epoxies. BEOL processes may be used to mount the device and computing device. In some embodiments, the first encapsulation layer 132, the second encapsulation layer 134, and the center encapsulation layer 136 may be provided before the packaged device 825 is mounted on the bridge interposer 604, and in some embodiments, the first encapsulation layer 132, the second encapsulation layer 134, and the center encapsulation layer 136 may be provided after the packaged device 825 is mounted on the bridge interposer 604.

[0069] After the packaged device 825 is mounted to the bridge interposer 604, one or more overmolding layers 152 may be deposited over the first packaged device 804, the second packaged device 806, and the third packaged device 808. The overmolding layer 152 may be deposited to encapsulate the first packaged device 804, the second packaged device 806, and the third packaged device 808 to the bridge interposer 604, as well as to provide mechanical support, thermal insulation, and electrical isolation. In some embodiments, the overmolding layer 152 may be one or more layers of dielectric material and may be formed by an overmolding process. In some embodiments, any excess material deposited on the device may be subjected to a process for smoothing and / or planarizing the surface of the device, including one or more grinding, polishing, and smoothing processes, including CMP. In some embodiments, a thermal processing step or a heat treatment step may be used to fix the overmolding layer 152 in place.

[0070] Figure 8F Depicted in Fig. 9 At S960 in the embodiment, the bridge interposer 604 on which the package device 825 is mounted is released from the carrier substrate 802 at the first RDL 612. The carrier substrate 802 may be released, for example, by using one or more of layer release, chemical release, thermal release, or optical release techniques to release the adhesive layer coupling the carrier substrate 802 to the first RDL 612. For example, in some embodiments, the chemical release technique may use a solvent to directly dissolve the adhesive, while the thermal release technique may apply heat to the carrier wafer to melt the adhesive, and the optical release technique may use a laser to directly apply energy to the adhesive layer to reduce the adhesive strength.

[0071] In addition, at S960, interconnects for mounting the bridge interposer 604 on the support substrate 102 may be prepared. The interconnects may include pads, bumps, microbumps, pillars, balls, and other forms, such as C4 bumps, alone or in combination. In some embodiments, a dielectric layer or adhesive layer may also be included, including an underfill.

[0072] Figure 8G Depicted in Fig. 9At S970 in the figure, the bridge interposer 604 on which the package device 825 is mounted is mounted on the support substrate 102 via the bonding layer 160. The bonding layer 160 may include conductive interconnects to connect the bridge interposer 604 to the support substrate 102, including pads, bumps, microbumps, pillars, balls and other forms, such as controlled collapse chip connection C4 bumps, alone or in combination. In some embodiments, the bonding layer 160 may also include a dielectric material or an adhesive (such as an underfill material) to provide additional strength and connection between the bridge interposer 604 and the support substrate 102. In some embodiments, the bonding layer 160 may provide a metal bond between the bridge interposer 604 and the support substrate 102, a dielectric bond between the bridge interposer 604 and the support substrate 102, or a hybrid bond between the bridge interposer 604 and the support substrate 102 in some embodiments. In some embodiments, the bonding layer 160 may be directly bonded to the first RDL 612, while in other embodiments, an intermediate layer may be between the bonding layer 160 and the first RDL 612. In some embodiments, an underfill technique may be used to insert the dielectric material or adhesive material and leave a residue 162 on the surface of the support substrate 102. In some embodiments, a thermal or other heat treatment may be provided to strengthen the bond between the support substrate 102 and the bridge interposer 604.

[0073] In addition, a stiffener 130 may be formed on the support substrate 102 to surround the bridge interposer 604. The stiffener 130 may be formed directly on the support substrate 102, such as by additive manufacturing of a suitable material, to provide additional rigidity to the support substrate 102, or may be formed separately and mounted on the support substrate 102 using a bonding process or adhesive such as an epoxy or resin. In some embodiments, an additional layer of molding material or encapsulation material may be deposited between the bridge interposer 604 and the stiffener 130. In some embodiments, a cover may be further mounted to the device package architecture 100 and attached to the stiffener 130.

[0074] Although this specification may include many specific implementation details, the implementation details should not be interpreted as a limitation on the scope of any claimed subject matter, but rather as a description of features specific to a particular embodiment. Certain features described in the context of a separate embodiment in this specification may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although the features may be described above as acting in certain combinations and even initially claimed as such, one or more features from the claimed combination may be cut out of the combination in some cases, and the claimed combination may point to a sub-combination or a variation of the sub-combination.

[0075] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring that the operations be performed in the particular order shown or in sequence, or that all of the operations shown be performed, to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous. In addition, the separation of various system components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0076] Thus, specific embodiments of the subject matter have been described herein. Other embodiments are within the scope of the appended claims. In some cases, the actions set forth in the claims can be performed in a different order and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing may be advantageous.

[0077] As those skilled in the art will recognize, the innovative concepts described herein can be modified and varied over a wide range of applications. Therefore, the scope of the claimed subject matter should not be limited to any specific exemplary teachings discussed above, but rather is defined by the appended claims.

[0078] CROSS-REFERENCE TO RELATED APPLICATIONS

[0079] This application claims priority to U.S. Provisional Patent Application Serial No. 63 / 543,504 filed on October 10, 2023 and U.S. Provisional Patent Application Serial No. 63 / 543,505 filed on October 10, 2023, the disclosures of which are incorporated herein by reference in their entirety.

Claims

1. A device comprising: A first layer, comprising a first computing device, a first multi-device package, and a second multi-device package, wherein the first computing device is arranged between the first multi-device package and the second multi-device package; as well as A second layer includes a first redistribution layer on a first side of the second layer facing the first layer, the first redistribution layer being configured to electrically connect the first computing device to the first multi-device package, and the first redistribution layer being configured to electrically connect the first computing device to the second multi-device package.

2. The device of claim 1 , wherein the first layer comprises a third multi-device package and a fourth multi-device package, wherein the first computing device is disposed between the third multi-device package and the fourth multi-device package; and The first redistribution layer is configured to electrically connect the first computing device to the third multi-device package, and the first redistribution layer is configured to electrically connect the first computing device to the fourth multi-device package. 3 . The device of claim 2 , wherein the first computing device is disposed between the second multi-device package and the fourth multi-device package.

4. The device of claim 1, wherein the first layer further comprises a second computing device, a fifth multi-device package, and a sixth multi-device package, wherein the second computing device is disposed between the sixth multi-device package and the fifth multi-device package; and The first redistribution layer is configured to electrically connect the second computing device to the fifth multi-device package, and the first redistribution layer is configured to electrically connect the second computing device to the sixth multi-device package. 5 . The device of claim 1 , wherein the second layer comprises a second redistribution layer on a second side of the second layer opposite the first side of the second layer. The device of claim 5 , wherein a first bridge is arranged between the first redistribution layer and the second redistribution layer. 7 . The device of claim 1 , wherein the first multi-device package comprises at least a first device stack and a second device stack on a first multi-device die. 8 . The device of claim 7 , wherein the first device stack comprises at least one of a memory device and a processing device. 9 . The device of claim 7 , wherein the first multi-device die is configured to electrically couple the first device stack and the second device stack to the first redistribution layer.

10. A system comprising: A first layer, comprising a first computing device, a first multi-device package, and a second multi-device package, wherein the first computing device is arranged between the first multi-device package and the second multi-device package; as well as A second layer includes a first bridge and a second bridge, wherein the first bridge electrically couples the first computing device to the first multi-device package, and wherein the second bridge electrically couples the first computing device to the second multi-device package.

11. The system according to claim 10, wherein: The first layer includes a second computing device, a third multi-device package, and a fourth multi-device package; wherein the second computing device is arranged between the fourth multi-device package and the third multi-device package; and Wherein the second layer further comprises a third bridge and a fourth bridge, and wherein the third bridge is configured to electrically couple the second computing device to the third multi-device package, and wherein the fourth bridge is configured to electrically couple the second computing device to the fourth multi-device package. 12 . The system of claim 10 , wherein the second layer comprises a first redistribution layer on a first side of the second layer, the first redistribution layer being between the first bridge and the first multi-device package. 13 . The system of claim 12 , wherein the second layer comprises a second redistribution layer on a second side of the second layer opposite the first side, the first bridge being between the first redistribution layer and the second redistribution layer.

14. The system of claim 10, wherein the first multi-device package includes at least one of a memory device and a processing device.

15. The system of claim 10, wherein the first layer comprises a base die, and wherein the base die is disposed between the first computing device and the first bridge.

16. A method comprising: forming an interposer including a first bridge and a second bridge, and forming a first redistribution layer on a first side of the interposer, the first redistribution layer being communicatively coupled to the first bridge and the second bridge; mounting a computing device on the interposer and on the first redistribution layer; mounting a first multi-device package and a second multi-device package on the interposer and on the first redistribution layer, the computing device being disposed between the first multi-device package and the second multi-device package; depositing a dielectric layer over the interposer; coupling the first multi-device package to the computing device via the first bridge; as well as The second multi-device package is coupled to the computing device via the second bridge. 17 . The method of claim 16 , wherein the first multi-device package and the second multi-device package have substantially identical devices.

18. The method according to claim 16, wherein: Mounting the computing device on the interposer includes mounting a base die on the first redistribution layer and mounting the computing device on the base die.

19. The method of claim 16, wherein forming the interposer further comprises forming a second redistribution layer on a second side of the interposer, the second side of the interposer being opposite to the first side of the interposer.

20. The method of claim 16, wherein depositing the dielectric layer over the interposer comprises depositing a dielectric material between the first multi-device package, the second multi-device package, and the computing device.

Images