Device with surface mounted packages for copackaging

Abstract

A semiconductor package includes a first device and a second device. A structure of the first semiconductor device is similar to that of the second semiconductor device, where the first semiconductor device includes a lead frame, a first plurality of field effect transistors (FETs), a first plurality of clips, a second plurality of FETs, a second plurality of clips, and a first molded package. A method is also applied to manufacture one or more semiconductor packages. The method includes providing a lead frame, connecting a first plurality of FETs, connecting a first plurality of clips, connecting a second plurality of FETs, mounting the second plurality of clips, and forming a molded package.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packages having co-packaged field effect transistors (FETs) and devices including semiconductor packages, and more particularly, to a surface mount semiconductor package having co-packaged FETs. Background Art

[0002] Conventional motor drives and power tools contain two groups of transistors. Each of the two groups contains six transistors. To apply surface mount technology, the two groups of transistors occupy most of the top surface of the printed circuit board.

[0003] To solve the above problems, the present invention co-packages FETs in a semiconductor package, thereby occupying less top surface of a printed circuit board when surface mounting technology is applied. The semiconductor package includes a clip to facilitate high current and low impedance applications. Summary of the invention

[0004] The present invention discloses a semiconductor device, comprising a first device and a second device. The structure of the first semiconductor device is similar to that of the second semiconductor device. The first semiconductor device comprises a lead frame strip, a first group of multiple field effect transistors (FETs), a first group of multiple clips, a second group of multiple FETs, a second group of multiple clips and a first molded package.

[0005] The present invention also discloses a method for manufacturing a plurality of semiconductor packages, which comprises the steps of providing a lead frame strip, attaching a first plurality of FETs, attaching a first plurality of clips, attaching a second plurality of FETs, attaching a second plurality of clips, and forming a molded package.

[0006] Preferably, the semiconductor package provided by the present invention comprises: a lead frame, comprising: one or more lead frame units, each lead frame unit comprising: a die pad, a first lead, which is arranged on a first side of the die pad, a second lead, which is arranged on a second side of the die pad, the second side is opposite to the first side, and a third lead, which is arranged on the second side of the die pad, the die pad of each lead frame unit in the plurality of lead frame units is mechanically and electrically connected to the die pad of a corresponding adjacent lead frame unit in the plurality of lead frame units; a first group of a plurality of field effect transistors, each field effect transistor is connected to the lead frame a first plurality of clips, each clip having a first end connected to a top surface electrode of a first field effect transistor and a second end attached to a first lead of a corresponding lead frame unit; a second plurality of field effect transistors, each field effect transistor attached to a top surface of the first clip; a second plurality of clips, each clip having a first end connected to a top surface electrode of a second field effect transistor and a second end connected to a corresponding second lead; and a molded package surrounding the first plurality of field effect transistors, the first plurality of clips, the second plurality of field effect transistors, a majority of the second plurality of clips, and a majority of the first lead frame.

[0007] Preferably, each of said second plurality of clips is mechanically and electrically connected to a corresponding adjacent clip of said second plurality of clips.

[0008] Preferably, the first lead of each lead frame unit is separated from the die pad of each lead frame; and wherein the first lead of each lead frame unit is mechanically and electrically connected to the first lead in the corresponding adjacent lead frame unit.

[0009] Preferably, each first field effect transistor is flipped over and mounted on a corresponding die pad; wherein each first field effect transistor comprises a source connected to the corresponding die pad and a gate connected to the third lead.

[0010] Preferably, each second field effect transistor comprises: a bottom drain electrode connected to one of the first clips; a top source electrode connected to one of the second clips; and a top gate electrode connected to a third lead; wherein the second lead is mechanically and electrically connected to the die pad of the corresponding lead frame unit.

[0011] Preferably, a respective top surface of each of the second plurality of clips is exposed from a top surface of the molded package.

[0012] Preferably, each lead frame unit further includes a fourth lead arranged on the first side of the die pad, the fourth lead being adjacent to the first lead; wherein the first lead, the second lead, the third lead and the fourth lead in each lead frame unit are separated from each other and isolated from the die pad of each lead frame.

[0013] Preferably, each first field effect transistor comprises a bottom drain connected to the corresponding die pad.

[0014] Preferably, each second field effect transistor comprises: a bottom drain electrode connected to one of the first clips; a top source electrode connected to one of the second clips; and a top gate electrode connected to the third lead.

[0015] Preferably, a respective top surface of each of the second plurality of clips is exposed from a top surface of the molded package.

[0016] Preferably, the present invention also provides a semiconductor device, comprising: a first device comprising: a first lead frame, which comprises a first plurality of lead frame units; a first plurality of field effect transistors, each field effect transistor is connected to a corresponding lead frame unit of the first lead frame; a first plurality of clips attached to the first plurality of field effect transistors; a second plurality of field effect transistors, which are attached to the first plurality of clips; a second plurality of clips attached to the second plurality of field effect transistors; and a first molded package, which surrounds the first plurality of field effect transistors, the first plurality of clips, the second plurality of field effect transistors, and the first plurality of effect transistors, a majority of a second plurality of clips and a majority of the first lead frame; and a second device comprising: a second lead frame comprising a second plurality of lead frame units; a third plurality of field effect transistors, each field effect transistor being connected to a corresponding lead frame unit of the second lead frame; a fourth plurality of field effect transistors attached to the third plurality of clips; a fourth plurality of clips attached to the fourth plurality of field effect transistors; and a second molded package surrounding the third plurality of field effect transistors, the third plurality of clips, the fourth plurality of field effect transistors, a majority of the first plurality of clips and a majority of the second lead frame.

[0017] Preferably, each field effect transistor in the first group of multiple field effect transistors, the second group of multiple field effect transistors, the third group of multiple field effect transistors and the fourth group of multiple field effect transistors comprises: a corresponding source electrode and a corresponding gate electrode on the top surface of each field effect transistor; and a corresponding drain on the bottom surface of each field effect transistor; wherein the first group of multiple field effect transistors is flipped so that the drain of each field effect transistor in the first group of multiple field effect transistors is electrically connected to the drain electrode of the corresponding field effect transistor in the second group of multiple field effect transistors; wherein the third group of field effect transistors is flipped so that the drain electrode of each field effect transistor in the third group of field effect transistors is electrically connected to the drain electrode of the corresponding field effect transistor in the fourth group of field effect transistors.

[0018] Preferably, the second group of multiple clips includes: a first interconnect clip electrically connected to the source of each field effect transistor in the second group of multiple field effect transistors; and a first group of multiple gate clips, each gate clip electrically connected to the gate electrode of a corresponding field effect transistor in the second group of multiple field effect transistors; and wherein the fourth group of multiple clips includes a second interconnect clip electrically connected to the source of each field effect transistor in the fourth group of multiple field effect transistors; and a second group of multiple gate clips, each gate clip electrically connected to the gate electrode of a corresponding field effect transistor in the fourth group of multiple field effect transistors.

[0019] Preferably, a corresponding top surface of each of the second plurality of clips is exposed from a top surface of the first molded package; and wherein a corresponding top surface of each of the fourth plurality of clips is exposed from a top surface of the second molded package.

[0020] Preferably, each field effect transistor in the first group of multiple field effect transistors, the second group of multiple field effect transistors, the third group of multiple field effect transistors and the fourth group of multiple field effect transistors comprises: a corresponding source electrode and a corresponding gate electrode on the top surface of each field effect transistor; and a corresponding drain on the bottom surface of each field effect transistor; wherein the source of each field effect transistor in the first group of field effect transistors is electrically connected to the drain of the corresponding field effect transistor in the second group of field effect transistors; and wherein the source of each field effect transistor in the third group of field effect transistors is electrically connected to the drain of the corresponding field effect transistor in the fourth group of field effect transistors.

[0021] Preferably, the second group of multiple clips includes: a first interconnect clip electrically connected to the source of each field effect transistor in the second group of multiple field effect transistors; wherein the fourth group of multiple clips includes: a second interconnect clip electrically connected to the source of each field effect transistor in the fourth group of multiple field effect transistors.

[0022] Preferably, a corresponding top surface of each of the second plurality of clips is exposed from a top surface of the first molded package; and wherein a corresponding top surface of each of the fourth plurality of clips is exposed from a top surface of the second molded package.

[0023] Preferably, a first plurality of bonding wires connects the gate electrode of each field effect transistor in the second plurality of field effect transistors to the first interconnection clip; and a second plurality of bonding wires connects the gate electrode of each field effect transistor in the fourth plurality of field effect transistors to the second interconnection clip.

[0024] In summary, compared with the prior art, the present invention provides a surface mount package device with a co-packaged field effect transistor, in which the FET is co-packaged in a semiconductor package, thereby occupying less top surface of the printed circuit board when applying surface mounting technology, and the semiconductor package includes a clip to facilitate high current and low impedance applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1A is a circuit diagram of a semiconductor device in an example of the present disclosure, Figure 1B It is its device and circuit diagram;

[0026] Figure 2A is a circuit diagram of another semiconductor device in an example of the present disclosure, Figure 2B It is its device and circuit diagram;

[0027] Figure 3A is an isotropic view of a semiconductor package device in an example of the present disclosure, Figure 3B It is an exploded view. Figure 3C is along Figure 3A A cross-sectional view of AA';

[0028] Figure 4A is an isotropic view of another semiconductor package device in an example of the present disclosure, Figure 4B It is an exploded view. Figure 4C is along Figure 4A Cross-sectional view of BB';

[0029] Figure 5A is a top view of a semiconductor package in an example of the present disclosure. Figure 5B is a top view of another semiconductor package in an example of the present disclosure;

[0030] Figure 6 is a flow chart of a process for developing a plurality of semiconductor packages in an example of the present disclosure;

[0031] Fig. 7A , 7B, 7C, 7D, 7E, 7F, 7G, 7H, 7I and 7J show examples of manufacturing in the present disclosure Figure 6 Multiple semiconductor packaging process steps;

[0032] Figure 8 is a flow chart of a process for developing another set of semiconductor packages in an example of the present disclosure;

[0033] Fig. 9A , 9B , 9C, 9D, 9E, 9F, 9G, 9H, 9I, 9J and 9K show examples of manufacturing in the present disclosure Figure 8 Multiple semiconductor packaging process steps. DETAILED DESCRIPTION

[0034] The present invention will be further described below by describing a preferred specific embodiment in detail in conjunction with Figures 1 to 9.

[0035] Figure 1A is a circuit diagram of a semiconductor device 100 in an example of the present disclosure, Figure 1B 1 is a device and circuit diagram thereof. In one example, the semiconductor device 100 includes a surface mount package. The semiconductor device 100 includes a first device 120 as a packaged device and a second device 160 as a packaged device. In one example, the first device 120 is composed of Figure 3A In another example, the second device 160 is made of Figure 3A The semiconductor package device 300 is manufactured. The first device 120 includes a plurality of FETs. Figure 1A 1, 142, and 152, the number of FET pairs included in the first device 120 may vary. The pair 132 includes FET 132A and FET 132B. The pair 142 includes FET 142A and FET 142B. The pair 152 includes FET 152A and FET 152B. The respective drains of each of FET 132A, FET 132B, FET 142A, FET 142B, FET 152A, and FET 152B are electrically connected. The second device 160 includes a plurality of FETs. Although Figure 1A1 , three pairs of FETs (pair 172, pair 182, and pair 192) are shown, but the number of FET pairs included in the second device 160 may vary. The pair 172 includes FET 172A and FET 172B. The pair 182 includes FET 182A and FET 182B. The pair 192 includes FET 192A and FET 192B. The respective drains of each of FET 172A, FET 172B, FET 182A, FET 182B, FET 192A, and FET 192B are electrically connected.

[0036] Figure 1B FET 132B is shown stacked on top of FET 132A. FET 142B is stacked on top of FET 142A. FET 152B is stacked on top of FET 152A. FET 172B is stacked on top of FET 172A. FET 182B is stacked on top of FET 182A. FET 192B is stacked on top of FET 192A.

[0037] Figure 2A is a circuit diagram of a semiconductor device 200 in an example of the present disclosure, Figure 2B The semiconductor device 200 includes a first device 220 and a second device 260. In one example, the first device 220 is composed of Figure 4A In another example, the second device 260 is made of Figure 4A The semiconductor package device 400 is manufactured. The first device 220 includes a plurality of FETs. Figure 2A 232, pair 242, and pair 252, the number of FET pairs included in the first device 220 may vary. The pair 232 includes FET 232A and FET 232B. The pair 242 includes FET 242A and FET 242B. The pair 252 includes FET 252A and FET 252B. The drain of FET 232A is electrically connected to the source of FET 232B. The drain of FET 242A is electrically connected to the source of FET 242B. The drain of FET 252A is electrically connected to the source of FET 252B. The second device 260 includes a plurality of FETs. Although Figure 2A2. Although three pairs of FETs (pair 272, pair 282, and pair 292) are shown in FIG. 2, the number of FET pairs included in the second device 260 may vary. The pair 272 includes FET 272A and FET 272B. The pair 282 includes FET 282A and FET 282B. The pair 292 includes FET 292A and FET 292B. The drain of FET 272A is electrically connected to the source of FET 272B. The drain of FET 282A is electrically connected to the source of FET 282B. The drain of FET 292A is electrically connected to the source of FET 292B.

[0038] Figure 2B FET 232B is shown stacked on top of FET 232A. FET 242B is stacked on top of FET 242A. FET 252B is stacked on top of FET 252A. FET 272B is stacked on top of FET 272A. FET 282B is stacked on top of FET 282A. FET 292B is stacked on top of FET 292A.

[0039] Figure 3A is an isotropic view of a semiconductor package device 300 in an example of the present disclosure, Figure 3B It is an exploded view. Figure 3C is along Figure 3A The semiconductor package device 300 includes a lead frame strip 310, a first plurality of FETs 320, a first plurality of clips 340, a second plurality of FETs 360, a second plurality of clips 380, and a first molded package 398. The lead frame strip 310 includes a first plurality of lead frame units. Figure 3A312, lead frame unit 314, and lead frame unit 316 are shown in the figure, but the number of lead frame units included in the semiconductor package device 300 may vary. As shown, each lead frame unit 312, 314, and 316 includes a die pad 312P, 314P, and 316P, a first lead 312D, 314D, and 316D on a first side of the corresponding die pad, a second lead 312S, 314S, and 316S on a second side of the corresponding die pad opposite to the first side, and a third lead 312G, 314G, and 316G on a second side of the corresponding die pad. Each third lead includes an inner portion extending to a cutoff angle of the corresponding die pad and an outer portion substantially aligned with the corresponding second lead, and the top surface of the inner portion is substantially coplanar with the top surface of the corresponding die pad. In one example, the die pad of each lead frame unit is mechanically and electrically connected to the die pad of an adjacent lead frame unit. In another example, the first lead of each lead frame unit is mechanically and electrically connected to the first lead in the adjacent lead frame unit. In another example, the second lead of each lead frame unit is mechanically and electrically connected to the die pad in the corresponding lead frame unit. Each of the first plurality of FETs 320 is attached to a corresponding die pad of a lead frame unit of lead frame strip 310. FET 322 is attached to lead frame unit 312. FET 324 is attached to lead frame unit 314. FET 326 is attached to lead frame unit 316.

[0040] A first plurality of clips 340 are attached to the first plurality of field effect transistors 320. Each of the first plurality of clips 340 is attached to a corresponding FET in the first plurality of FETs 320 to connect the surface electrode to the corresponding first lead. Clip 342 is attached to FET 322. Clip 344 is attached to FET 324. Clip 346 is attached to FET 326.

[0041] A second plurality of FETs 360 are attached to the top surface of the first plurality of clips 340. Each of the second plurality of FETs 360 is attached to a corresponding clip of the first plurality of clips 340. FET 362 is attached to clip 342. FET 364 is attached to clip 344. FET 366 is attached to clip 346.

[0042] A second plurality of clips 380 is attached to a second plurality of FETs 360. The second plurality of clips 380 includes an interconnection clip 381 and a plurality of clips 391. The interconnection clip 381 includes a clip 382, ​​a clip 384, and a clip 386. The clip 382 includes a raised portion 382R. The clip 384 includes a raised portion 384R. The clip 386 includes a raised portion 386R. The clip 382 is connected to the FET 362. The clip 384 is connected to the FET 364. The clip 386 is connected to the FET 366. The plurality of clips 391 includes a clip 393, a clip 395, and a clip 397.

[0043] The first molded package 398 surrounds the first plurality of FETs 320, the first plurality of clips 340, the second plurality of FETs 360, a majority of the second plurality of clips 380, and a majority of the lead frame strip 310. By majority is meant more than 50%.

[0044] Each FET in the first plurality of FETs 320 and the second plurality of FETs 360 includes: a corresponding source (e.g., source 326S of FET 326 and source 366S of FET 366) and a corresponding gate (e.g., gate 366G of FET 366) on the top surface of each FET; and a corresponding drain (e.g., drain 326D of FET 326 and drain 366D of FET 366) on the bottom surface of each FET. The first plurality of FETs 320 are flipped so that the source of each FET is connected to the corresponding die pad, the gate of each FET is connected to the inside of the corresponding third lead, and the drain of the first plurality of FETs is electrically connected to the drain of the second plurality of FETs 360 through the corresponding first plurality of clips 340. For example, the drain 326D of FET 326 is electrically connected to the drain 366D of FET 366 through the clip 346.

[0045] Interconnect clip 381 electrically connects the source of each FET in the second plurality of FETs 360 (eg, source 366S of FET 366) to a corresponding second lead. In one example, each interconnect clip is mechanically and electrically connected to an adjacent interconnect clip in the second plurality of clips.

[0046] Each of the plurality of clips 391 electrically connects the gate electrode of a corresponding FET in the second plurality of FETs 360 to the outside of the corresponding third lead. For example, the clip 397 is electrically connected to the outside of the gate electrode 366G of the FET 366.

[0047] Figure 4A is an isotropic view of a semiconductor package device 400 in an example of the present disclosure, Figure 4B It is an exploded view. Figure 4C is along Figure 4AThe semiconductor package device 400 includes a lead frame strip 410, a first plurality of FETs 420, a first plurality of clips 440, a second plurality of FETs 460, a second plurality of clips 480, and a first molded package 498. The lead frame strip 410 includes a first plurality of lead frame units. Figure 4A 4 , three lead frame units (lead frame unit 412, lead frame unit 414, and lead frame unit 416) are shown, but the number of lead frame units included in the semiconductor package device 400 may vary. As shown, each lead frame unit 412, 414, and 416 includes a die pad 412P, 414P, and 416P, a first lead 412LX, 414LX, and 416LX on a first side of the corresponding die pad, a second lead 412S, 414S, and 416S on a second side of the corresponding die pad opposite to the first side, a third lead 412LG, 414LG, and 416LG on the second side of the corresponding die pad, and a fourth lead 412HG, 414HG, and 416HG on the first side of the corresponding die pad. In one example, the die pad of each lead frame unit is mechanically and electrically connected to the die pad of an adjacent lead frame unit. The first lead, the second lead, the third lead, and the fourth lead in each lead frame unit are separated from each other and isolated from the die pad of the unit.

[0048] Each of the first plurality of FETs 420 is attached to a die pad of a corresponding lead frame cell of the lead frame strip 410. FET 422 is attached to lead frame cell 412. FET 424 is attached to lead frame cell 414. FET 426 is attached to lead frame cell 416.

[0049] A first plurality of clips 440 are attached to the first plurality of sub-field effect transistors 420. Each of the first plurality of clips 440 is attached to a corresponding FET in the first plurality of FETs 420 to connect the surface electrode to the corresponding first lead. Clip 442 is attached to FET 422. Clip 444 is attached to FET 424. Clip 446 is attached to FET 426.

[0050] A second plurality of FETs 460 are attached to the top surface of the first plurality of clips 440. Each of the second plurality of FETs 460 is attached to a respective clip of the first plurality of clips 440. FET 462 is attached to clip 442. FET 464 is attached to clip 444. FET 466 is attached to clip 446.

[0051] A second plurality of clips 480 is attached to the second plurality of FETs 460. The second plurality of clips 480 includes clip 482, clip 484, and clip 486. Clip 482 is attached to FET 462. Clip 484 is connected to FET 464. Clip 486 is connected to FET 466.

[0052] The first molded package 498 surrounds the first plurality of FETs 420, the first plurality of clips 440, the second plurality of FETs 460, a majority of the second plurality of clips 480, and a majority of the lead frame strip 410. By majority is meant more than 50%.

[0053] Each FET in the first plurality of FETs 420 and the second plurality of FETs 460 includes: a corresponding source (e.g., source 426S of FET 426 and source 466S of FET 466) and a corresponding gate (e.g., gate 466G of FET 466) on the top surface of each FET; and a corresponding drain (e.g., drain 426D of FET 426 and drain 466D of FET 466) on the bottom surface of each FET. The source of each FET of the first plurality of FETs 420 is electrically connected to the drain of the corresponding FET of the second plurality of FETs 460. For example, source 426S of FET 426 is electrically connected to drain 466D of FET 466 through clip 446.

[0054] The second plurality of clips 480 electrically connects the source of each FET in the second plurality of FETs 460 (e.g., source 466S of FET 466) to the corresponding second lead. In one example, each of the second plurality of clips is mechanically and electrically connected to an adjacent clip in the second plurality of clips.

[0055] The semiconductor package device 400 further includes a plurality of bonding wires 491 that connect the gate electrode of each FET in the first plurality of FETs to the corresponding third lead, and a plurality of bonding wires 497 that connect the gate electrode of each field effect transistor in the second plurality of field effect transistors to the corresponding third lead. For example, the bonding wire 491 connects the gate electrode 426G of the FET 426 to the fourth lead 416HG, and the bonding wire 497 connects the gate electrode 466G of the FET 466 to the third lead 416LG.

[0056] Figure 5A 5 is a top view of a semiconductor package 500 in an example of the present disclosure. A corresponding top surface of each of the second plurality of clips is exposed from a top surface 549 of a first molded package 548. Now referring to Figure 3A and Figure 5A, top surface 592 of raised portion 382R of clip 382, ​​top surface 594 of raised portion 384R of clip 384, and top surface 596 of raised portion 386R of clip 386 are exposed from top surface 549 of first molded package 548. Exposed top surface 592, exposed top surface 594, and exposed top surface 592 improve heat dissipation.

[0057] Figure 5B 590 is a top view of a semiconductor package 560 in an example of the present disclosure. A corresponding top surface of each of the second plurality of clips is not exposed from a top surface of the molded package 598.

[0058] Figure 6 6 is a flow chart of a process 600 for developing a plurality of semiconductor packages in an example of the present disclosure. The process 600 may begin at block 602 . Figures 7A-7J The isotropic views of the corresponding steps are shown. For simplicity, Figures 7A-7J Only one semiconductor device is shown.

[0059] In block 602, reference is now made to Fig. 7A , providing a lead frame strip 710. In one example, the lead frame strip 710 includes a first plurality of lead frame units. Fig. 7A Three leadframe units (leadframe unit 712, leadframe unit 714, and leadframe unit 716) are shown in FIG. 6 , but the number of leadframe units included in the semiconductor device may vary. Block 602 may be followed by block 604.

[0060] In block 604, reference is now made to Figure 7B , applying a first solder layer 711. In an example of the present disclosure, the first solder layer 711 is applied by solder printing. Block 604 may be followed by block 606.

[0061] In block 606, reference is now made to Figure 7C , a first plurality of FETs 720 are attached to the lead frame strip 710. Each of the first plurality of FETs 720 is attached to a corresponding lead frame unit of the lead frame strip 710. FET 722 is attached to the lead frame unit 712 by a first solder layer 711. FET 724 is attached to the lead frame unit 714 by a first solder layer 711. FET 726 is attached to the lead frame unit 716 by a first solder layer 711. Block 606 may be followed by block 608.

[0062] In block 608, reference is now made to Fig.7D , applying a second solder layer 721. In an example of the present disclosure, the second solder layer 721 is applied by solder dispensing. Block 608 may be followed by block 610.

[0063] In block 610, reference is now made to Fig. 7E , a first plurality of clips 740 are attached to the first plurality of sub-field effect transistors 720. Each of the first plurality of clips 740 is attached to a corresponding FET in the first plurality of FETs 720. Clip 742 is attached to FET 722 via a second solder layer 721. Clip 744 is attached to FET 724 via a second solder layer 721. Clip 746 is attached to FET 726 via a second solder layer 721. Block 610 may be followed by block 612.

[0064] In block 612, reference is now made to Figure 7F , a third solder layer 741 is applied. In an example of the present disclosure, the third solder layer 741 is applied by solder dispensing. Block 612 may be followed by block 614.

[0065] In block 614, reference is now made to Figure 7G , a second plurality of FETs 760 are attached to the first plurality of clips 740. Each of the second plurality of FETs 760 is attached to a corresponding clip in the first plurality of clips 740. FET 762 is attached to clip 742 via a third solder layer 741. FET 764 is attached to clip 744 via a third solder layer 741. FET 766 is attached to clip 746 via a third solder layer 741. Block 614 may be followed by block 616.

[0066] In block 616, reference is now made to Figure 7H , a fourth solder layer 761 is applied. In an example of the present disclosure, the fourth solder layer 761 is applied by solder dispensing. Block 616 may be followed by block 618 .

[0067] In block 618, reference is now made to Fig.7I , a second plurality of clips 780 are attached to a second plurality of FETs 760. The second plurality of clips 780 include an interconnect clip 779 and a plurality of gate clips 791. The interconnect clip 779 includes a clip 782, a clip 784, and a clip 786. The clip 782 is attached to the FET 762 through the fourth solder layer 761. The clip 784 is attached to the FET 764 through the fourth solder layer 761. The clip 786 is attached to the FET 766 through the fourth solder layer 761. The plurality of clips 791 include a clip 793, a clip 795, and a clip 797. Block 618 may be followed by block 620.

[0068] In block 620, reference is now made to Figure 7J , forming a molded package 798. The molded package 798 surrounds the first plurality of FETs 720, the first plurality of clips 740, the second plurality of FETs 760, a majority of the second plurality of clips 780, and a majority of the lead frame strip 710. Block 620 may be followed by a singulation process to form a plurality of semiconductor package devices 300.

[0069] Figure 8 8 is a flow chart of a process 800 for developing a plurality of semiconductor packages in an example of the present disclosure. Process 800 may begin at block 802 . Figures 9A-9K An isotropic view of the corresponding steps is shown. For simplicity, Figures 9A-9K Only one semiconductor device is shown.

[0070] In block 802, reference is now made to Fig. 9A , providing a lead frame strip 910. In one example, the lead frame strip 910 includes a first plurality of lead frame units. Fig. 9A Three leadframe units (leadframe unit 912, leadframe unit 914, and leadframe unit 916) are shown, but the number of leadframe units included in the semiconductor device may vary. Block 802 may be followed by block 804.

[0071] In block 804, reference is now made to Fig. 9B , applying a first solder layer 911. In an example of the present disclosure, the first solder layer 911 is applied by solder printing. Block 804 may be followed by block 806.

[0072] In block 806, reference is now made to Fig. 9C , a first plurality of FETs 920 are attached to lead frame strip 910. Each of the first plurality of FETs 920 is attached to a corresponding lead frame cell of lead frame strip 910. FET 922 is attached to lead frame cell 912 by a first solder layer 911. FET 924 is attached to lead frame cell 914 by a first solder layer 911. FET 926 is attached to lead frame cell 916 by a first solder layer 911. Block 806 may be followed by block 808.

[0073] In block 808, reference is now made to Fig.9D , applying a second solder layer 921. In an example of the present disclosure, the second solder layer 921 is applied by solder dispensing. Block 808 may be followed by block 810.

[0074] In block 810, reference is now made to Fig.9E , a first plurality of clips 940 are attached to the first plurality of FETs 920. Each of the first plurality of clips 940 is attached to a corresponding FET in the first plurality of FETs 920. Clip 942 is connected to FET 922 via a second solder layer 921. Clip 944 is connected to FET 924 via a second solder layer 921. Clip 946 is attached to FET 926 via a second solder layer 921. Block 810 may be followed by block 812.

[0075] In block 812, reference is now made to Fig.9F, applying a third solder layer 941. In an example of the present disclosure, the third solder layer 941 is applied by solder dispensing. Block 812 may be followed by block 814.

[0076] In block 814, reference is now made to Figure 9G , a second plurality of FETs 960 are attached to the first plurality of clips 940. Each of the second plurality of FETs 960 is attached to a corresponding clip in the first plurality of clips 940. FET 962 is attached to clip 942 via a third solder layer 941. FET 964 is attached to clip 944 via a third solder layer 941. FET 966 is attached to clip 946 via a third solder layer 941. Block 814 may be followed by block 816.

[0077] In block 816, reference is now made to Figure 9H , applying a fourth solder layer 961. In an example of the present disclosure, the fourth solder layer 961 is applied by solder dispensing. Block 816 may be followed by block 818.

[0078] In block 818, reference is now made to Fig.9I , a second plurality of clips 980 are attached to a second plurality of FETs 960. The second plurality of clips 980 includes an interconnect clip 979. The interconnect clip 979 includes a clip 982, a clip 984, and a clip 986. The clip 982 is attached to the FET 962 through a fourth solder layer 961. The clip 984 is attached to the FET 964 through a fourth solder layer 961. The clip 986 is attached to the FET 966 through a fourth solder layer 981. Block 818 may be followed by block 820.

[0079] In block 820, reference is now made to Figure 9J , a plurality of bond wires 991 connects the gate electrode of each FET in the second plurality of FETs 960 to the interconnect clip 979. The plurality of bond wires 991 includes a bond wire 993, a bond wire 995, and a bond wire 997. For example, the bond wire 997 connects the gate electrode of the FET 966 to the interconnect clip 979. Block 820 may be followed by block 822.

[0080] In block 822, reference is now made to Figure 9K , forming a molded package 998. The molded package 998 surrounds the first plurality of FETs 920, the first plurality of clips 940, the second plurality of FETs 960, a majority of the second plurality of clips 980, and a majority of the lead frame strip 910. Block 822 may be followed by a singulation process to form a plurality of semiconductor package devices 400.

[0081] It will be appreciated by those skilled in the art that modifications of the embodiments disclosed herein are possible. For example, the number of FETs included in the device may vary. Other modifications may be made by those skilled in the art, and all such modifications are considered to be within the scope of the present invention, as defined by the appended claims.

Claims

1. A semiconductor package, characterized in that: Include: A lead frame, containing: One or more lead frame units, each lead frame unit comprising: A die pad, a first lead disposed on a first side of the die pad, a second lead disposed on a second side of the die pad, the second side being opposite to the first side, and a third lead disposed on a second side of the die pad, the die pad of each of the plurality of lead frame units being mechanically and electrically connected to the die pad of a corresponding adjacent lead frame unit of the plurality of lead frame units; a first plurality of field effect transistors, each field effect transistor being connected to a respective die pad of the lead frame; A first plurality of clips, each clip having a first terminal connected to the top electrode of the first field effect transistor, and a second end attached to the first lead of the corresponding lead frame unit; a second plurality of field effect transistors, each field effect transistor being attached to a top surface of the first clip; A second plurality of clips, each clip having a first terminal connected to the top electrode of the second field effect transistor, and a second end connected to a corresponding second lead; as well as A molded package surrounds the first plurality of field effect transistors, the first plurality of clips, the second plurality of field effect transistors, a majority of the second plurality of clips, and a majority of the first leadframe.

2. The semiconductor package according to claim 1, wherein: Each of the second plurality of clips is mechanically and electrically connected to a corresponding adjacent clip of the second plurality of clips.

3. The semiconductor package according to claim 1, wherein: The first lead of each lead frame unit is separated from the die pad of each lead frame; and wherein the first lead of each lead frame unit is mechanically and electrically connected to the first lead in the corresponding adjacent lead frame unit.

4. The semiconductor package according to claim 3, wherein: Each first field effect transistor is flipped over and mounted on a corresponding die pad; wherein each first field effect transistor includes a source connected to the corresponding die pad and a gate connected to the third lead.

5. The semiconductor package according to claim 4, wherein: Each second field effect transistor comprises: One connected to the bottom drain of one of the first clips, a top source electrode connected to one of the second clips, and a top gate electrode connected to a third lead, Wherein, the second lead is mechanically and electrically connected to the die pad of the corresponding lead frame unit.

6. The semiconductor package according to claim 5, wherein: A respective top surface of each of the second plurality of clips is exposed from a top surface of the molded package.

7. The semiconductor package according to claim 1, wherein: Each lead frame unit also includes a fourth lead disposed on a first side of the die pad, the fourth lead being adjacent to the first lead, wherein the first lead, the second lead, the third lead, and the fourth lead in each lead frame unit are separated from each other and isolated from the die pad of each lead frame.

8. The semiconductor package according to claim 7, wherein: Each first field effect transistor includes a bottom drain connected to a corresponding die pad.

9. The semiconductor package according to claim 8, wherein: Each second field effect transistor comprises: a bottom drain electrode connected to one of the first clips, a top source electrode connected to one of the second clips, and a top gate electrode connected to the third lead.

10. The semiconductor package according to claim 9, wherein: A respective top surface of each of the second plurality of clips is exposed from a top surface of the molded package.

11. A semiconductor device, characterized in that: Include: A first device comprises: a first leadframe comprising a first plurality of leadframe units; a first plurality of field effect transistors, each field effect transistor being connected to a respective lead frame cell of the first lead frame; a first plurality of clips attached to a first plurality of field effect transistors; a second plurality of field effect transistors attached to the first plurality of clips; a second plurality of clips attached to a second plurality of field effect transistors; and a first molded package surrounding the first plurality of field effect transistors, the first plurality of clips, the second plurality of field effect transistors, a majority of the second plurality of clips, and a majority of the first leadframe; as well as A second device comprises: a second leadframe comprising a second plurality of leadframe elements; a third plurality of field effect transistors, each field effect transistor being connected to a corresponding lead frame cell of the second lead frame; a fourth plurality of field effect transistors attached to the third plurality of clips; a fourth plurality of clips attached to a fourth group of field effect transistors; as well as A second molded package surrounds the third group of field effect transistors, the third group of clips, the fourth group of field effect transistors, a majority of the first group of clips, and a majority of the second lead frame.

12. The semiconductor device according to claim 11, wherein Each of the first plurality of field effect transistors, the second plurality of field effect transistors, the third plurality of field effect transistors, and the fourth plurality of field effect transistors comprises: A corresponding source electrode and a corresponding gate electrode are provided on the top surface of each field effect transistor; as well as a respective drain electrode on a bottom surface of each of said field effect transistors; wherein the first plurality of field effect transistors are flipped so that a drain electrode of each field effect transistor in the first plurality of field effect transistors is electrically connected to a drain electrode of a corresponding field effect transistor in the second plurality of field effect transistors; and The third group of field effect transistors is flipped so that the drain electrode of each field effect transistor in the third group of field effect transistors is electrically connected to the drain electrode of the corresponding field effect transistor in the fourth group of field effect transistors.

13. The semiconductor device according to claim 12, wherein: The second set of multiple clips contains: a first interconnect clip electrically connected to a source of each field effect transistor in a second plurality of field effect transistors; as well as a first plurality of gate clips, each gate clip electrically connected to a gate electrode of a corresponding field effect transistor of a second plurality of field effect transistors; as well as The fourth set of multiple clips includes a second interconnect clip electrically connected to a source of each field effect transistor in a fourth plurality of field effect transistors; and A second plurality of gate clips, each gate clip electrically connected to a gate electrode of a corresponding field effect transistor in a fourth plurality of field effect transistors.

14. The semiconductor device according to claim 13, wherein: A respective top surface of each of the second plurality of clips is exposed from a top surface of the first molded package; and wherein a respective top surface of each of the fourth plurality of clips is exposed from a top surface of the second molded package.

15. The semiconductor device according to claim 14, wherein: Each of the first plurality of field effect transistors, the second plurality of field effect transistors, the third plurality of field effect transistors, and the fourth plurality of field effect transistors comprises: A corresponding source electrode and a corresponding gate electrode are provided on the top surface of each field effect transistor; and a respective drain electrode on a bottom surface of each of said field effect transistors; wherein a source of each field effect transistor in the first group of field effect transistors is electrically connected to a drain of a corresponding field effect transistor in the second group of field effect transistors; and Wherein, the source of each field effect transistor in the third group of field effect transistors is electrically connected to the drain of the corresponding field effect transistor in the fourth group of field effect transistors.

16. The semiconductor device according to claim 15, wherein: The second set of multiple clips contains: a first interconnect clip electrically connected to a source of each field effect transistor in a second plurality of field effect transistors; Wherein, the fourth group of multiple clips includes: A second interconnect clip is electrically connected to a source of each field effect transistor in a fourth plurality of field effect transistors.

17. The semiconductor device according to claim 16, wherein: A respective top surface of each of the second plurality of clips is exposed from a top surface of the first molded package; and wherein a respective top surface of each of the fourth plurality of clips is exposed from a top surface of the second molded package.

18. The semiconductor device according to claim 17, wherein: a first plurality of bond wires connecting a gate electrode of each field effect transistor in a second plurality of field effect transistors to a first interconnect clip; as well as A second plurality of bond wires connects the gate electrode of each field effect transistor in the fourth plurality of field effect transistors to the second interconnect clip.

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