Integrated package and method of manufacturing the same

Abstract

The invention provides an integrated package and a method of manufacturing the same. The integrated package includes: an antenna module, the antenna module including an antenna module substrate and a top antenna structure, the top antenna structure disposed on the antenna module substrate; a first sealant that seals the antenna module; a first redistribution structure disposed on a bottom surface of the first encapsulant, the first redistribution structure including a bottom antenna structure configured to be electromagnetically energetically coupled with the top antenna structure; and a semiconductor chip mounted on a bottom surface of the first redistribution structure and electrically coupled with the bottom antenna structure.

Description

Technical Field

[0001] The present application relates generally to semiconductor technology and, more particularly, to integrated packages and methods of making the same. Background Art

[0002] As consumers want their electronic devices to be smaller, faster, and higher performing, and pack more and more functions into a single device, the semiconductor industry has been facing complex integration challenges. Antenna-in-Package (AiP) has become the mainstream antenna packaging technology for various applications. AiP allows the antenna and RF chip (e.g., transceiver) to be integrated in a single package. However, conventional AiP technology is complex, resulting in high cost and low reliability.

[0003] Therefore, a simple and cost-effective AiP technology is needed. Summary of the invention

[0004] The object of the present application is to provide a simple and cost-effective integrated package.

[0005] According to one aspect of the present application, an integrated package is provided. The integrated package may include: at least one antenna module, the at least one antenna module including an antenna module substrate and a top antenna structure, the top antenna structure being disposed on the antenna module substrate; a first sealant, the first sealant sealing the antenna module; a first redistribution structure, the first redistribution structure being disposed on a bottom surface of the first sealant, wherein the first redistribution structure includes a bottom antenna structure configured to couple electromagnetic energy with the top antenna structure; and a semiconductor chip, the semiconductor chip being mounted on a bottom surface of the first redistribution structure and electrically coupled to the bottom antenna structure.

[0006] According to another aspect of the present application, a method for manufacturing an integrated package is provided. The method may include: providing at least one antenna module, wherein the antenna module includes an antenna module substrate and a top antenna structure disposed on the antenna module substrate; attaching the antenna module to a carrier; forming a first sealant on the carrier to seal the antenna module; removing the carrier to expose a bottom surface of the first sealant; forming a first redistribution structure on the bottom surface of the first sealant, wherein the first redistribution structure includes a bottom antenna structure configured to couple electromagnetic energy with the top antenna structure; and mounting a semiconductor chip on the first redistribution structure, wherein the semiconductor chip is electrically coupled to the bottom antenna structure.

[0007] It should be understood that both the above general description and the following detailed description are exemplary and explanatory only and do not limit the present invention. Further, the accompanying drawings, which are incorporated in and constitute a part of this specification, show embodiments of the present invention and are used to explain the principles of the present invention together with the description. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The drawings cited herein form part of this specification. The features shown in the drawings only show some embodiments of the present application, rather than all embodiments of the present application, unless the specific implementation mode clearly indicates otherwise, and the reader of this specification should not make an inference to the contrary.

[0009] Figure 1 is a cross-sectional view of an integrated package according to an embodiment of the present application.

[0010] Figure 2 is a cross-sectional view of an integrated package according to another embodiment of the present application.

[0011] Figure 3 is a cross-sectional view of an integrated package according to another embodiment of the present application.

[0012] Figures 4A to 4E is a cross-sectional view showing various steps of a method for manufacturing an antenna module according to an embodiment of the present application.

[0013] Figures 5A to 5J is a cross-sectional view showing various steps of a method for manufacturing an integrated package according to an embodiment of the present application.

[0014] Figures 6A to 6H is a cross-sectional view showing steps of a method for manufacturing an integrated package according to another embodiment of the present application.

[0015] Figures 7A to 7F is a cross-sectional view showing steps of a method for manufacturing an integrated package according to another embodiment of the present application.

[0016] The same reference numbers will be used throughout the drawings to refer to the same or like parts. DETAILED DESCRIPTION

[0017] The following detailed description of exemplary embodiments of the present application refers to the accompanying drawings that form a part of the description. The accompanying drawings show specific exemplary embodiments in which the present application can be practiced. The detailed description, including the accompanying drawings, describes these embodiments in sufficient detail to enable those skilled in the art to practice the present application. Those skilled in the art may further utilize other embodiments of the present application and make logical, mechanical and other changes without departing from the spirit or scope of the present application. Therefore, the reader of the following detailed description should not interpret the description in a restrictive sense, and only the appended claims define the scope of the embodiments of the present application.

[0018] In this application, unless otherwise specifically stated, the use of the singular includes the plural. In this application, the use of "or" means "and / or" unless otherwise stated. In addition, the use of the term "includes" and other forms such as "includes" and "containing" are not limiting. In addition, unless otherwise explicitly stated, terms such as "element" or "component" cover elements and components that include one unit, as well as elements and components that include more than one subunit. In addition, the section headings used herein are for organizational purposes only and should not be construed as limiting the subject matter described.

[0019] Spatially relative terms such as "below", "below", "above", "up", "upper", "lower", "left", "right", "vertical", "horizontal", "side", etc. used herein may be used herein for ease of description to describe the relationship between an element or feature and another or more elements or features as shown in the drawings. In addition to the orientation depicted in the drawings, spatially relative terms are also intended to cover different orientations of the device when in use or in operation. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein can likewise be interpreted accordingly. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected to or coupled to the other element, or there can be intermediate elements.

[0020] In conventional AiP devices, electrical signals can be transmitted from an integrated circuit chip to an antenna through one or more traces and / or one or more conductive vias embedded in a dielectric material. However, dielectric materials (e.g., molding compounds, etc.) may suffer from problems such as current leakage, stray capacitance, etc. Therefore, the performance of conventional AiP devices may be affected.

[0021] In some embodiments of the present application, an integrated package is provided. The integrated package includes an antenna module embedded in a sealant, and the antenna module includes a top antenna structure. A redistribution structure including a bottom antenna structure is formed on the bottom surface of the sealant, and a semiconductor chip is mounted on the redistribution structure and electrically coupled to the bottom antenna structure. The bottom antenna structure is configured to couple electromagnetic energy with the top antenna structure, and thus the semiconductor chip can transmit and receive electromagnetic signals through the electromagnetically coupled bottom antenna structure and the top antenna structure. The integrated package of the present application has a simpler structure and higher cost-effectiveness. Furthermore, since there is no wire connection between the bottom antenna structure and the top antenna structure and no conductive vias are formed in the sealant, the sealant may not suffer from current leakage. In addition, the antenna module and the semiconductor chip are arranged on two opposite sides of the redistribution structure to reduce interference between them.

[0022] Figure 1 A cross-sectional view of an integrated package 100 according to an embodiment of the present application is shown. The integrated package 100 includes two antenna modules 110 each having a top antenna structure 112, a first redistribution structure (RDS: redistribution structure) 130 including two bottom antenna structures 132a, and a semiconductor chip 140 electrically coupled to the bottom antenna structures 132a. Each bottom antenna structure 132a is configured to perform electromagnetic energy coupling with a corresponding top antenna structure 112, so that the semiconductor chip 140 can transmit and receive electromagnetic signals through the electromagnetically coupled bottom antenna structures 132a and top antenna structures 112.

[0023] refer to Figure 1 , the integrated package 100 includes a first sealant 120. Two antenna modules 110 are embedded in the first sealant 120. The first sealant 120 can be made of a molding compound such as a polymer composite material. For example, the molding compound may include an epoxy resin, an epoxy resin containing a filler, an epoxy acrylate containing a filler, or a polymer containing an appropriate filler, but the scope of the present application is not limited to this. The first sealant 120 is non-conductive, can provide structural support, and environmentally protects the antenna module 110 from external elements and pollutants. In some embodiments, the first sealant 120 can be formed using compression molding, transfer molding, liquid sealant molding, or other suitable molding processes. During the molding process, the antenna module 110 can be sealed by the first sealant 120.

[0024] like Figure 1 As shown, two antenna modules 110 are embedded in a first encapsulant 120. Each antenna module 110 may be pre-formed and include at least an antenna module substrate 114 and a top antenna structure 112. Figure 1In the example shown, the bottom surface of the antenna module substrate 114 is substantially flush or coplanar with the bottom surface of the first encapsulant 120. In some embodiments, the antenna module substrate 114 may include a molding compound, such as an encapsulant, and may be formed using a molding process. For example, the antenna module substrate 114 may have the same or different material as the first encapsulant 120. In some embodiments, the antenna module substrate 114 may include a PCB prepreg component and a PCB core component assembled together. The PCB core component may include a glass-reinforced epoxy laminate. The PCB prepreg component may be made of a dielectric material and may be mounted between the two PCB core components to provide the required insulation performance. Further, the top antenna structure 112 is disposed above the antenna module substrate 114 and is configured to couple electromagnetic energy with the bottom antenna structure 132a through a mutual coupling effect. In some embodiments, the shape of the top antenna structure 112 may be similar to the shape of the bottom antenna structure 132a. For example, when viewed from the top of the integrated package 100, the top antenna structure 112 may overlap at least partially with the bottom antenna structure 132a. The more the top antenna structure 112 and the bottom antenna structure 132a overlap, the better the mutual coupling effect.

[0025] exist Figure 1 In the example shown, the antenna module 110 further includes a bottom passivation layer 116 and a cover passivation layer 118. The bottom passivation layer 116 is disposed between the antenna module substrate 114 and the top antenna structure 112 to provide electrical isolation and improve adhesion. The cover passivation layer 118 is disposed on the bottom passivation layer 116 and covers the top antenna structure 112. The cover passivation layer 118 can protect the top antenna structure 112 from external elements and pollutants in the environment. In some embodiments, the bottom passivation layer 116 and / or the cover passivation layer 118 can be made of a dielectric material having a low loss tangent property or dissipation factor (Df, for example, ≤0.02). In some embodiments, the dielectric material can have a low dielectric constant (Dk, for example, ≤4) or a high Dk (for example, >4) according to actual needs. It should be noted that the bottom passivation layer 116 and the cover passivation layer 118 can be optional. In some other embodiments, the antenna module may include only one of the bottom passivation layer and the cover passivation layer, or may include neither the bottom passivation layer nor the cover passivation layer.

[0026] exist Figure 1 In the example shown, the first sealant 120 covers the top surface and the side surface of the antenna module 110 to protect the antenna module 110. For example, the top surface of the first sealant 120 is 20 μm higher than the top surface of the antenna module 110. However, the scope of the present application is not limited thereto. For example, one or more surfaces (e.g., side surfaces) of the antenna module 110 may be exposed from the first sealant 120.

[0027] refer to Figure 1 , a first redistribution structure 130 is formed on the bottom surface of the first sealant 120. The first redistribution structure 130 may include one or more dielectric layers and one or more conductive layers between and through the dielectric layers. The conductive layers may define pads, traces, and plugs through which electrical signals or voltages may be distributed horizontally and vertically across the first redistribution structure 130.

[0028] exist Figure 1 In the example shown, the first dielectric layer 131 of the first redistribution structure 130 is disposed on the bottom surface of the first sealant 120, and a first redistribution layer (RDL) 132 is formed in the first dielectric layer 131. Further, a second dielectric layer 133 is formed on the bottom surface of the first dielectric layer 131, and a second redistribution layer 134 is formed in the second dielectric layer 133, and the second redistribution layer is electrically connected to the first redistribution layer 132. In some embodiments, the first dielectric layer 131 and the second dielectric layer 133 may include silicon nitride, silicon oxynitride, FTEOS, SiCOH, polyimide, benzocyclobutene (BCB) or other organic polymers, or a combination thereof. The first redistribution layer 132 and the second redistribution layer 134 may include one or more of Cu, Al, Sn, Ni, Au, Pd, Ag, Ti, TiW, or any other suitable conductive material. In some embodiments, Figure 1 The first redistribution structure 130 shown in FIG. 1 can be formed according to a standard embedded wafer level ball grid array (eWLB: Embedded Wafer Level Ball Grid Array) process, but aspects of the present application are not limited thereto. It should also be understood that the first redistribution structure 130 can be implemented in various structures and types, and Figure 1 The examples shown in are for illustration only. For example, the number of redistribution layers is not limited to Figure 1 Two layers shown.

[0029] Continue to refer Figure 1 , the first redistribution layer 132 may include a first portion (i.e., a bottom antenna structure 132a). The bottom antenna structure 132a may include antennas of various types or shapes, such as a planar antenna, to transmit wireless communication signals to the semiconductor chip 140 and / or receive wireless communication signals from the semiconductor chip 140. For example, the bottom antenna structure 132a may take the form of a planar coil meandering in the first dielectric layer 131. The bottom antenna structure 132a may be electrically connected to the semiconductor chip 140 through the second redistribution layer 134, the at least one conductive pillar 152, and the second redistribution structure 160, such as Figure 1 As shown. Figure 1In the example shown, the first redistribution layer 132 further includes a second portion 132 b as an interconnect structure.

[0030] refer to Figure 1 , the semiconductor chip 140 is mounted on the bottom surface of the first redistribution structure 130 by an adhesive layer 142. For example, the adhesive layer 142 may include an adhesive paste layer, a liquid adhesive layer, a prefabricated double-sided adhesive tape or sheet (e.g., a die attach tape), a printed adhesive, etc. The semiconductor chip 140 may include one or more digital chips, analog chips, or mixed signal chips, such as an application specific integrated circuit ("ASIC") chip, a sensor chip, a wireless and radio frequency (RF) chip, a memory chip, a logic chip, or a voltage regulator chip. In some embodiments, the semiconductor chip 140 may include an integrated circuit chip for wireless communication and / or signal processing, which may require an antenna for transmitting and receiving wireless signals. In some embodiments, the semiconductor chip 140 may further include an output and / or input circuit for an antenna structure for wireless communication.

[0031] like Figure 1 As shown, the semiconductor chip 140 can be a smaller semiconductor package and can be manufactured using a surface manufacturing process or other similar process, having an active surface 140a and an inactive surface 140b opposite the active surface 140a. Various types of analog or digital circuits that can be implemented as active devices and / or passive devices can be formed near the active surface 140a and electrically coupled to certain interconnect pads / bumps 143 exposed from the active surface 140a through the metal interconnect structure of the semiconductor chip 140. In contrast, the inactive surface 140b of the semiconductor chip 140 may not have any conductive patterns exposed therefrom, but the scope of the present application is not limited in this regard. Figure 1 In the example shown, the inactive surface 140 b of the semiconductor chip 140 is bonded to the first redistribution structure 130 via an adhesive layer 142 , and the interconnection bumps 143 on the active surface 140 a are electrically connected to the second redistribution structure 160 .

[0032] refer to Figure 1, a plurality of conductive pillars 152 are formed on the first redistribution structure 130 to couple the first redistribution structure 130 with the second redistribution structure 160. For example, each conductive pillar 152 may be formed on a corresponding portion of the second redistribution layer 134 of the first redistribution structure 130 and vertically extend through the second sealant 150, which is disposed on the bottom surface of the first redistribution structure 130 and seals the semiconductor chip 140. The conductive pillars 152 may include any one of various conductive materials (e.g., Cu, Al, Ag, Au, Ni, alloys thereof, etc.). For example, the conductive pillars 152 may include copper (e.g., pure copper, copper containing some impurities, etc.), a copper alloy, etc.

[0033] like Figure 1 As shown, the second sealant 150 may cover the side surfaces of the conductive pillars 152 and the interconnection bumps 143, but leave their bottom surfaces exposed, so that the conductive pillars 152 and the interconnection bumps 143 may be electrically connected to the second redistribution structure 160 through these exposed surfaces. The second sealant 150 may be made of the same material as the first sealant 120, but the scope of the present application is not limited thereto. Figure 1 In the example shown, the second redistribution structure 160 includes two dielectric layers and two conductive layers formed in the two dielectric layers. However, it should be understood that the configuration of the second redistribution structure 160 (and the first redistribution structure 130) shown in the figure is merely exemplary and not restrictive, and can be changed according to actual needs.

[0034] In addition, a plurality of conductive bumps 170 are formed on the bottom surface of the second redistribution structure 160. In some embodiments, a plurality of contact pads or underbump metallization (UBM) structures are formed on the bottom surface of the second redistribution structure 160, the plurality of contact pads or UBM structures are electrically coupled to the redistribution layer in the second redistribution structure 160, and the conductive bumps 170 are formed on the contact pads or underbump metallization structures, respectively. Figure 1 In the example shown, the conductive bump 170 is shown as a solder bump, but the scope of the present application is not limited thereto. In some other embodiments, the conductive bump 170 may include other conductive bumps, such as microbumps, metal pillars, or copper balls. In the case where the integrated package 100 is mounted on an external device or a substrate such as a printed circuit board (PCB), the conductive bump 170 may be used to electrically connect the integrated package 100 to the external device or substrate.

[0035] It should be noted that Figure 1Each of the two antenna modules 110 in the embodiment includes a top antenna structure 112 coupled to a corresponding bottom antenna structure 132a, which is connected to the semiconductor chip 140. Therefore, the two top antenna structures 112 can jointly or individually transmit electromagnetic radiation to and / or receive electromagnetic radiation from the two bottom antenna structures 132a connected to the semiconductor chip 140. However, the number or configuration of the antenna structures is not limited to Figure 1 For example, in other embodiments, the integrated package may include only one or more than two top antenna structures, or more layers of antenna structures may be formed within the integrated package. Figure 1 In the example shown, the two top antenna structures 112 are coplanar with each other, but aspects of the present application are not limited thereto. In some other embodiments, the two top antenna structures can be at different levels, so that for different target frequencies, the two antenna modules can have different heights.

[0036] Further, since the top antenna structure 112 and the bottom antenna structure 132a are electromagnetically coupled to each other, it is desirable to carefully control the distance between the top antenna structure 112 and the bottom antenna structure 132a, taking into account the patterns of the top antenna structure 112 and the bottom antenna structure 132a, and the characteristics of the antenna module substrate 114, the first dielectric layer 131, and any other intermediate layers, including the dissipation factor (Df) and the dielectric constant (Dk). For example, the distance between the top antenna structure 112 and the bottom antenna structure 132a may be 150 μm, 200 μm, 250 μm, 270 μm, 280 μm, 290 μm, 310 μm, 360 μm, or other values, depending on the specific application scenario. However, it is understood that the distance between the top antenna structure 112 and the bottom antenna structure 132a may be modified or adjusted based on actual calculations or simulation results (e.g., using commercial electromagnetic simulation software such as ANSYS HFSS).

[0037] refer to Figure 2 , which shows an integrated package 200 according to another embodiment of the present application. The integrated package 200 may have Figure 1 The integrated package 200 has a similar structure and configuration to the integrated package 100 shown in FIG. Similar or identical parts between the integrated package 200 and the integrated package 100 will not be repeated here.

[0038] Figure 2 The integrated package 200 and Figure 1 The difference of the integrated package 100 is that Figure 2The semiconductor chip 240 is mounted on the bottom surface of the first redistribution structure 230 by a flip chip bonding technique. Figure 2 As shown, the semiconductor chip 240 has an active surface 240a and an inactive surface 240b opposite to the active surface 240a. A plurality of interconnection pads / bumps 243 may be formed on the active surface 240a of the semiconductor chip 240, and then the semiconductor chip 240 is mounted on the bottom surface of the first redistribution structure 230 through the interconnection pads / bumps 243. The interconnection pads / bumps 243 electrically connect the circuits or devices formed in the semiconductor chip 240 to the conductive patterns in the first redistribution structure 230. Figure 2 In the example shown, the inactive surface 240 b of the semiconductor chip 240 is exposed from the bottom surface of the second encapsulant 250 and is in contact with the second redistribution structure 260 .

[0039] Optionally, an underfill sealant 245 may be formed between the bottom surface of the first redistribution structure 230 and the active surface 240a of the semiconductor chip 240. The underfill sealant 245 may fill any gap between the first redistribution structure 230 and the semiconductor chip 240 and optionally cover the lateral surface of the semiconductor chip 240. The underfill sealant 245 may include a polymer composite material, such as an epoxy resin, epoxy acrylate, or a polymer with or without fillers. The underfill sealant 245 may provide mechanical support for the interconnection between the first redistribution structure 230 and the semiconductor chip 240, helping to reduce the risk of cracks or delamination due to the difference in thermal expansion between the first redistribution structure 230 and the semiconductor chip 240.

[0040] refer to Figure 3 , which shows an integrated package 300 according to another embodiment of the present application. The integrated package 300 may have Figure 2 The integrated package 300 has a similar structure and configuration to the integrated package 200 shown in FIG. The similar or identical parts between the integrated package 300 and the integrated package 200 will not be repeated here.

[0041] Figure 3 The integrated package 300 and Figure 2 The integrated package 200 is different in that the non-active surface 340 b of the semiconductor chip 340 is located above the bottom surface of the second encapsulant 350. That is, the non-active surface 340 b of the semiconductor chip 340 is covered by the second encapsulant 350, and at least a portion of the second encapsulant 350 is disposed between the semiconductor chip 350 and the second redistribution structure 360.

[0042] refer to Figures 4A to 4E, which shows the steps of a method for forming an antenna module according to an embodiment of the present application. For example, the method can be used to form Figure 1 The antenna module 110 is shown. Figures 4A to 4E The method is described in more detail.

[0043] like Figure 4A As shown, a blanket molded substrate 414 is provided. The molded substrate 414 may include a molding compound such as a polymer composite. For example, the molding compound may include an epoxy resin, an epoxy resin containing fillers, an epoxy acrylate containing fillers, or a polymer containing appropriate fillers. The molded substrate 414 may be formed using compression molding, transfer molding, liquid sealant molding, or other suitable molding processes. The molded substrate 414 may provide structural support for the antenna structure formed in subsequent steps.

[0044] like Figure 4B As shown, a bottom passivation layer 416 is formed on the molded substrate 414. The bottom passivation layer 416 may include silicon nitride, silicon oxynitride, tetraethyl fluoride orthosilicate (FTEOS), SiCOH, polyimide, benzocyclobutene (BCB) or other organic polymers, or a combination thereof, and may be formed by spraying, sputtering or any other suitable deposition process.

[0045] like Figure 4C As shown, one or more top antenna structures 412 may be formed on the bottom passivation layer 416. In some embodiments, a metal layer (e.g., Cu, Al, Sn, Ni, Au, Pd, Ag, Ti, TiW, or any other suitable conductive material) may be formed on the bottom passivation layer 416 by spraying, electroplating, sputtering, or any other suitable metal deposition process, and then the metal layer may be patterned into a desired shape by a photolithography process to form the antenna structure 412. However, the scope of the present application is not limited thereto, and other suitable processes may be used to form the top antenna structure 412. For example, one or more additional passivation layers and corresponding antenna structures may be formed above the top antenna structure 412.

[0046] like Figure 4D As shown, a cover passivation layer 418 is formed on the top antenna structure 412. The passivation layer 418 covers the top and side surfaces of the top antenna structure 412 and can environmentally protect the top antenna structure 412 from external elements and contaminants. The cover passivation layer 418 can have the same or different material as the bottom passivation layer 416.

[0047] like Figure 4EAs shown, the blanket molded substrate 414 is singulated to form a plurality of individual antenna modules 410. In some embodiments, a saw blade may be used to singulate the molded substrate 414 into the plurality of antenna modules 410. In some other examples, a laser cutting tool may also be used to singulate the molded substrate 414.

[0048] In some embodiments, the molded substrate 414 may be flipped over and a cover passivation layer 418 may be attached to a carrier before singulating the molded substrate 414. A back grinding process may then be performed to reduce the thickness of the molded substrate 414. After grinding, the molded substrate 414 may be removed from the carrier.

[0049] It should be understood that by changing the specific process or materials, reference Figures 4A to 4E The described method may also be used to form antenna modules having other configurations (eg, omitting the bottom passivation layer and / or the cover passivation layer), which will not be described in detail herein.

[0050] refer to Figures 5A to 5J , which shows the steps of a method for forming an integrated package according to an embodiment of the present application. For example, the method can be used to form Figure 1 The integrated package 100 shown in FIG. Figures 5A to 5J The method is described in more detail.

[0051] like Figure 5A As shown, at least one antenna module 510 is provided, and then the at least one antenna module 510 is bonded to a carrier 511 through an adhesive layer 513 .

[0052] In some embodiments, the antenna module 510 may be connected to Figure 1 The antenna module 110 is similar to that shown and can be referred to by reference Figures 4A to 4E The method is formed. For example, the antenna module 510 may include an antenna module substrate 514 and a top antenna structure 512 disposed on the antenna module substrate 514. Optionally, the antenna module 510 may further include a bottom passivation layer 516 between the antenna module substrate 514 and the top antenna structure 512, and a cover passivation layer 518 covering the top antenna structure 512. For example, the carrier 511 may be a glass carrier, a metal carrier, or any carrier suitable for the integrated package manufacturing method. The adhesive layer 513 may include a pre-made double-sided adhesive tape or sheet (e.g., a die attach tape), an adhesive paste layer, a liquid adhesive layer, a printed adhesive, etc.

[0053] like Figure 5BAs shown, a first sealant 520 is formed on the carrier 511 to seal the antenna module 510. The first sealant 520 may include epoxy resin, epoxy resin containing fillers, epoxy acrylate containing fillers, or a polymer containing appropriate fillers, but the scope of the present application is not limited thereto. In some embodiments, the first sealant 520 may be formed by using compression molding, transfer molding, liquid sealant molding, or other suitable molding processes.

[0054] Afterwards, if Figure 5C As shown, the carrier 511 and the adhesive layer 513 are removed from the first sealant 520. In one example, although Figure 5C Not shown, but the second carrier may be coupled with the first encapsulant 520 (eg, on a side opposite to the carrier 511 ), and then the carrier 511 and the adhesive layer 513 may be removed.

[0055] Afterwards, if Figure 5D As shown, flip Figure 5C and forming a first redistribution structure 530 on the first sealant 520.

[0056] In some embodiments, the first redistribution structure 530 can be formed according to a standard embedded wafer-level ball grid array (eWLB) process. The first redistribution structure 530 may include one or more dielectric layers and one or more conductive layers between and through the dielectric layers. The conductive layers may define pads, traces, and plugs through which electrical signals or voltages may be distributed horizontally and vertically across the first redistribution structure 530. For example, a first dielectric layer 531 may be formed over the first encapsulant 520, and then a first redistribution layer 532 may be formed in the first dielectric layer 531. A second dielectric layer 533 may be further formed on the first dielectric layer 531, and a second redistribution layer 534 may be formed in the second dielectric layer 533, and the second redistribution layer is electrically connected to the first redistribution layer 532. Figure 5D In the example shown, the first redistribution layer 532 may include a first portion 532a used as a bottom antenna structure and a second portion 532b used as an interconnect structure. The bottom antenna structure 532a is connected to the second redistribution layer 534 and is configured to couple electromagnetic energy with the top antenna structure 512 and transmit / receive communication signals to / from a semiconductor chip formed in a subsequent step.

[0057] In some embodiments, an under bump metallization (UBM) structure may be formed on the second redistribution layer 534 and / or the second dielectric layer 533 (e.g., on a peripheral portion of the second dielectric layer 533 surrounding an opening in the second dielectric layer 533 exposing the second redistribution layer 534). The UBM structure may include any of various materials (e.g., Ti, Cr, Al, Ti / W, Ti / Ni, Cu, alloys thereof, etc.) and may be formed in any of various manners (e.g., sputtering, electroless plating, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma vapor deposition, etc.).

[0058] Afterwards, if Figure 5E As shown, at least one conductive pillar 552 is formed on the first redistribution structure 530. The conductive pillar 552 is electrically connected to the second redistribution layer 534 of the first redistribution structure 530 and is used for vertical electrical interconnection.

[0059] In some embodiments, the conductive pillars 552 are formed by the following processes: forming a mask over the first redistribution structure 530; forming openings through the mask to expose the second redistribution layer 534 at locations where conductive pillars are needed; and depositing conductive material into the mask openings. In other embodiments, the conductive pillars 552 are formed using other additive, semi-additive, or subtractive metal deposition techniques. The conductive pillars 552 may include any of a variety of conductive materials (e.g., copper, aluminum, silver, gold, nickel, alloys thereof, etc.). For example, the conductive pillars 552 may include copper (e.g., pure copper, copper with some impurities, etc.), copper alloys, etc.

[0060] Afterwards, if Fig. 5F As shown, a semiconductor chip 540 is provided, and then the semiconductor chip 540 is bonded to the first redistribution structure 530 through an adhesive layer 542. The semiconductor chip 540 may include an integrated circuit chip for wireless communication. Fig. 5F In the example shown, the semiconductor chip 540 has an active surface 540 a and an inactive surface 540 b opposite to the active surface 540 a. A plurality of interconnect bumps (e.g., solder bumps, micro bumps, metal pillars, copper balls, etc.) 543 are formed on the active surface 540 a of the semiconductor chip 540, and the inactive surface 540 b is attached to the adhesive layer 542, wherein the plurality of interconnect bumps 543 are opposite to the first redistribution structure 530.

[0061] Afterwards, if Figure 5G As shown, a second encapsulant 550 is formed on the first redistribution structure 530 to encapsulate the semiconductor chip 540 (eg, including the interconnection bumps 543 ) and the conductive pillars 552 .

[0062] In some embodiments, the second sealant 550 can be formed on the first redistribution structure 530 using compression molding, transfer molding, liquid sealant molding, or other suitable molding processes, and can include epoxy resin, epoxy resin containing fillers, epoxy acrylate containing fillers, or polymers containing appropriate fillers, but the scope of the present application is not limited thereto. The second sealant 550 can share any or all properties with the first sealant 520. However, the scope of the present application is not limited thereto. For example, the second sealant 550 can be formed in a manner different from the first sealant, and / or the material of the second sealant 550 can be different from the material of the first sealant 520.

[0063] refer to Figure 5G and Figure 5H Both, the second encapsulant 550 is ground to expose the interconnection bumps 543 and the conductive pillars 552 on the semiconductor chip 540 .

[0064] In some embodiments, Figure 5H The grinder 557 is shown removing the upper portion of the second encapsulant 550. The grinding process may also planarize the top surface of the second encapsulant 550. After the grinding process, at least the respective top surfaces of the interconnect bumps 543 and the conductive pillars 552 are exposed from the top surface of the second encapsulant 550.

[0065] Afterwards, refer to Fig.5I , a second redistribution structure 560 is formed on the second encapsulant 550. The second redistribution structure 560 is electrically coupled with the interconnection bump 543 and the conductive pillar 552, so that the semiconductor chip 540 can be electrically coupled with the bottom antenna structure 532a in the first redistribution structure 530 through the second redistribution structure 560 and the interconnection bump 543.

[0066] In some embodiments, the second redistribution structure 560 may be formed by using steps similar to the steps for forming the first redistribution structure 530. For example, Fig.5IAs shown, the second redistribution structure 560 also includes two dielectric layers and two conductive layers formed in the two dielectric layers. However, the scope of the present application is not limited to this. For example, the formation method of the second redistribution structure 560 may be different from the formation method of the first redistribution structure 530, and / or the material of the second redistribution structure 560 may be different from the material of the first redistribution structure 530. In some embodiments, a plurality of contact pads or UBM structures may be formed on the second redistribution structure 560, and the plurality of contact pads or UBM structures may be electrically coupled to the redistribution layers therein. The UBM structure may include any of a variety of materials (e.g., Ti, Cr, Al, Ti / W, Ti / Ni, Cu, alloys thereof, etc.), and may be formed in any of a variety of ways (e.g., sputtering, electroless plating, CVD, PVD, ALD, plasma vapor deposition, etc.).

[0067] Finally, reference Figure 5J , a plurality of conductive bumps 570 are formed on the second redistribution structure 560 to be electrically coupled with the second redistribution structure 560 .

[0068] In some embodiments, the conductive bump material is deposited on the top redistribution layer of the second redistribution structure 560 and / or the UBM structure (if present) exposed from the top dielectric layer of the second redistribution structure 560 using one of the following processes or any combination thereof: evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The conductive bump material can be solder, Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, or a combination thereof, and an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high lead solder, or lead-free solder. The material can be reflowed by heating the bump material above its melting point to form an external interconnect bump 570. In some embodiments, the conductive bump 570 can be compression bonded or hot-pressed bonded to the second redistribution structure 560. Figure 5J The spherical bumps shown in FIG. 5 may represent one type of external conductive bumps that may be formed on the second redistribution structure 560. In other examples, the conductive bumps 570 may be stud bumps, micro bumps, or other electrical interconnects.

[0069] refer to Figures 6A to 6H , which shows a cross-sectional view of a method for forming an integrated package according to another embodiment of the present application. Figures 5A-5J Unlike the described embodiment, the active surface of the semiconductor chip in this embodiment is bonded to the first redistribution structure, rather than the inactive surface.

[0070] refer to Fig. 6A , a package 601 is provided. The package 601 includes at least one antenna module 610 and a first sealant 620 that seals the antenna module 610 . Fig. 6A The package 601 shown in FIG. Figure 5C The structure shown in is similar and will not be described in detail here.

[0071] Afterwards, refer to Figure 6B , flip Fig. 6A and forming a first redistribution structure 630 on the first sealant 620.

[0072] Specifically, a first dielectric layer 631 may be formed on the first sealant 620, and then a first redistribution layer 632 may be formed in the first dielectric layer 631. A second dielectric layer 633 may be further formed on the first dielectric layer 631, and a second redistribution layer 634 may be formed in the second dielectric layer 633, and the second redistribution layer 634 is electrically connected to the first redistribution layer 632. Figure 6B In the example shown, the first redistribution layer 632 may include a first portion 632a serving as a bottom antenna structure and a second portion 532b serving as an interconnect structure. Figure 5D Unlike the example shown, the second redistribution layer 634 is also formed in the area above the bottom antenna structure 632a where the semiconductor chip will be mounted in a subsequent step. A plurality of openings are formed in the second dielectric layer 633 to expose the top surface of the second redistribution layer 634. In some embodiments, a UBM structure may be formed within and around the openings of the second dielectric layer 633 through which the second redistribution layer 634 is exposed.

[0073] refer to Figure 6C At least one conductive pillar 652 is formed on the first redistribution structure 630. The conductive pillar 652 is electrically connected to the second redistribution layer 634 of the first redistribution structure 630 and is used for vertical electrical interconnection.

[0074] refer to Fig.6D , a semiconductor chip 640 is provided, and then the semiconductor chip is mounted on the first redistribution structure 630. The interconnect bumps 643 on the active surface of the semiconductor chip 640 are electrically connected to the second redistribution layer 634 of the first redistribution structure 630. For example, solder paste can be deposited or printed on the exposed second redistribution layer 634 on which the semiconductor chip 640 is to be mounted. The semiconductor chip 640 can then be placed on the top surface of the first redistribution structure 630, with the interconnect bumps 643 in contact with and located above the solder paste. The solder paste can be reflowed to mechanically and electrically couple the interconnect bumps 643 to the second redistribution layer 634 of the first redistribution structure 630. In Fig.6D In the example shown, after the semiconductor chip 640 is mounted on the first redistribution structure 630 , the top surface of the semiconductor chip 640 may be higher than the top surface of the conductive pillar 652 .

[0075] In some embodiments, an underfill sealant 645 is further formed between the semiconductor chip 640 and the first redistribution structure 630. The underfill sealant 645 can fill any gap between the semiconductor chip 640 and the first redistribution structure 630, and optionally cover the lateral surface of the semiconductor chip 640. The underfill sealant 645 may include a polymer composite material, such as an epoxy resin, epoxy acrylate, or a polymer with or without a filler. For example, the underfill sealant 645 is formed by depositing a fluid material at a position close to the semiconductor chip 640 on the first redistribution structure 630, and allowing capillary action to draw the fluid material into the space between the semiconductor chip 640 and the first redistribution structure 630. The underfill sealant 645 can provide mechanical support for the interconnection between the semiconductor chip 640 and the first redistribution structure 630, helping to reduce the risk of cracks or delamination due to the difference in thermal expansion between the semiconductor chip 640 and the first redistribution structure 630.

[0076] refer to Fig. 6E , a second sealant 650 is formed on the first redistribution structure 630 to seal the semiconductor chip 640 and the conductive pillars 652 .

[0077] refer to Fig. 6F , for example, the second encapsulant 650 is ground by a grinder 657 to expose the conductive pillars 652. The grinding process may remove an upper portion of the second encapsulant 650, as well as an upper portion of the semiconductor chip 640. After the grinding process, at least the respective top surfaces of the conductive pillars 652 and the semiconductor chip 640 are substantially flush or coplanar with each other.

[0078] refer to Figure 6G A second redistribution structure 660 is formed on the second sealant 650 . The second redistribution structure 660 (eg, a redistribution layer therein) is electrically coupled to the conductive pillar 652 .

[0079] Finally, if Figure 6H As shown, a plurality of conductive bumps 670 are formed on the second redistribution structure 660 to be electrically coupled with the second redistribution structure 660 .

[0080] refer to Figures 7A to 7F , which shows a cross-sectional view of a method for forming an integrated package according to another embodiment of the present application. Figures 6A-6H Different from the above-mentioned embodiment, in this embodiment, the top surface of the semiconductor chip mounted on the first redistribution structure is lower than the top surface of the conductive pillar.

[0081] refer to Fig. 7A, a package 701 is provided. The package 701 includes at least one antenna module 710 and a first sealant 720 that seals the antenna module 710. A first redistribution structure 730 is formed on the first sealant 720, and at least one conductive pillar 752 is formed on the first redistribution structure 730. Fig. 7A The package 701 shown in FIG. Figure 6C The structure shown in is similar and will not be described in detail here.

[0082] refer to Figure 7B , a semiconductor chip 740 is mounted on the first redistribution structure 730. The interconnect bumps 743 on the active surface of the semiconductor chip 740 are electrically connected to the first redistribution structure 730. In some embodiments, an underfill sealant 745 is further formed between the semiconductor chip 740 and the first redistribution structure 730. The underfill sealant 745 can fill any gap between the semiconductor chip 740 and the first redistribution structure 730, and optionally cover the lateral surface of the semiconductor chip 740. Figure 7B In the example shown, after the semiconductor chip 740 is mounted on the first redistribution structure 730 , the top surface of the semiconductor chip 740 may be lower than the top surface of the conductive pillar 752 .

[0083] refer to Figure 7C , a second sealant 750 is formed on the first redistribution structure 730 to seal the semiconductor chip 740 and the conductive pillars 752 .

[0084] refer to Fig.7D , for example, the second encapsulant 750 is ground by a grinder 757 to expose the conductive pillar 752. The grinding process may remove an upper portion of the second encapsulant 750. After the grinding process, the top surface of the conductive pillar 752 is exposed from the second encapsulant 750. Since the top surface of the semiconductor chip 740 is lower than the top surface of the conductive pillar 752, a portion of the second encapsulant 750 may remain above the semiconductor chip 740.

[0085] refer to Fig. 7E A second redistribution structure 760 is formed on the second sealant 750 . The second redistribution structure 760 is electrically coupled to the conductive pillars 752 .

[0086] Finally, reference Figure 7F , a plurality of conductive bumps 770 are formed on the second redistribution structure 760 to be electrically coupled with the second redistribution structure 760 .

[0087] Although combined Figures 5A-5J , Figures 6A-6H and Figures 7A-7FDifferent processes for forming the integrated package are described, but those skilled in the art will appreciate that modifications and adaptations may be made to the processes without departing from the scope of the present invention.

[0088] For example, although in Figures 5A-5J , Figures 6A-6H and Figures 7A-7F The steps in this section only describe the integration of a single unit of the package, but using Figures 5A-5J , Figures 6A-6H and Figures 7A-7F The process shown can produce a strip type integrated package, that is, a plurality of integrated packages formed in a substrate strip. Figure 5J , Figure 6H and Figure 7F After the steps shown for forming the conductive bumps, a further singulation step may be performed on the substrate strip.

[0089] The discussion herein includes a number of illustrative drawings that illustrate various parts of an integrated package and methods for making an integrated package. For clarity of description, such figures do not illustrate all aspects of each example package. Any example package and / or method provided herein may share any or all characteristics with any or all other devices and / or methods provided herein.

[0090] Various embodiments have been described herein with reference to the accompanying drawings. However, it will be apparent that various modifications and changes may be made thereto, and additional embodiments may be implemented, without departing from the broader scope of the invention as set forth in the appended claims. Further, other embodiments will be apparent to those skilled in the art by considering the specification and practice of one or more embodiments of the invention disclosed herein. Therefore, the present application and the examples herein are intended to be considered as exemplary only, with the true scope and spirit of the invention being indicated by the following list of exemplary claims.

Claims

1. An integrated package, characterized in that: The integrated package comprises: An antenna module, the antenna module comprising: an antenna module substrate; and a top antenna structure, the top antenna structure being disposed on the antenna module substrate; a first sealant, the first sealant sealing the antenna module; a first redistribution structure disposed on a bottom surface of the first encapsulant, the first redistribution structure comprising a bottom antenna structure configured to electromagnetically couple energy with the top antenna structure; and A semiconductor chip is mounted on a bottom surface of the first redistribution structure and is electrically coupled to the bottom antenna structure.

2. The integrated package according to claim 1, characterized in that: The integrated package further comprises: a second sealant disposed on the bottom surface of the first redistribution structure and sealing the semiconductor chip; at least one conductive pillar extending through the second encapsulant and electrically coupled to the first redistribution structure; and A second redistribution structure is disposed on a bottom surface of the second encapsulant and is electrically coupled to the conductive pillar.

3. The integrated package according to claim 2, characterized in that: The integrated package further comprises: A plurality of interconnection bumps are disposed between the first redistribution structure and the semiconductor chip to electrically couple the semiconductor chip with the first redistribution structure.

4. The integrated package according to claim 3, characterized in that: At least a portion of the second encapsulant is disposed between the semiconductor chip and the second redistribution structure.

5. The integrated package according to claim 2, characterized in that: The integrated package further comprises: A plurality of interconnection bumps are disposed between the second redistribution structure and the semiconductor chip to electrically couple the semiconductor chip with the second redistribution structure.

6. The integrated package according to claim 2, characterized in that: The integrated package further comprises: A plurality of conductive bumps are disposed on a bottom surface of the second redistribution structure and electrically coupled with the second redistribution structure.

7. The integrated package according to claim 1, characterized in that: The antenna module substrate includes a molding compound.

8. The integrated package according to claim 7, characterized in that: The antenna module further comprises: A cover passivation layer is disposed on the antenna module substrate and covers the top antenna structure.

9. The integrated package according to claim 7, characterized in that: The antenna module further comprises: A bottom passivation layer is disposed between the antenna module substrate and the top antenna structure.

10. The integrated package according to claim 1, characterized in that: The distance between the top antenna structure and the bottom antenna structure is determined based on patterns of the top antenna structure and the bottom antenna structure, and a dielectric constant and a dissipation factor of a dielectric material between the top antenna structure and the bottom antenna structure.

11. A method for manufacturing an integrated package, characterized in that: The method comprises: Providing an antenna module, wherein the antenna module includes an antenna module substrate and a top antenna structure disposed on the antenna module substrate; attaching the antenna module to a carrier; forming a first sealant on the carrier to seal the antenna module; removing the carrier to expose a bottom surface of the first encapsulant; forming a first redistribution structure on a bottom surface of the first encapsulant, wherein the first redistribution structure comprises a bottom antenna structure configured to electromagnetically couple energy with the top antenna structure; and A semiconductor chip is mounted on the first redistribution structure, wherein the semiconductor chip is electrically coupled to the bottom antenna structure.

12. The method according to claim 11, characterized in that The method further comprises: forming at least one conductive pillar on the first redistribution structure; forming a second sealant on the first redistribution structure to seal the semiconductor chip; and A second redistribution structure is formed on the second encapsulant, wherein the second redistribution structure is electrically coupled to the first redistribution structure through the conductive pillars.

13. The method according to claim 12, characterized in that Mounting the semiconductor chip on the first redistribution structure comprises: forming a plurality of interconnect bumps on an active surface of the semiconductor chip; and The semiconductor chip is mounted on the first redistribution structure through the plurality of interconnection bumps.

14. The method according to claim 13, characterized in that At least a portion of the second encapsulant is formed between the semiconductor chip and the second redistribution structure.

15. The method according to claim 12, characterized in that Mounting the semiconductor chip on the first redistribution structure comprises: forming a plurality of interconnect bumps on an active surface of the semiconductor chip; and The semiconductor chip is attached to the first redistribution structure, wherein the plurality of interconnection bumps are opposite to the first redistribution structure.

16. The method according to claim 12, characterized in that The method further comprises: A plurality of conductive bumps are formed on the second redistribution structure to be electrically coupled with the second redistribution structure.

17. The method according to claim 12, characterized in that Providing the antenna module includes: providing a molded substrate comprising a molding compound; and The top antenna structure is formed on the molded substrate.

18. The method according to claim 17, characterized in that Providing the antenna module further comprises: Before forming the top antenna structure on the molded substrate, a bottom passivation layer is formed on the molded substrate.

19. The method according to claim 17, characterized in that Providing the antenna module further comprises: A cover passivation layer is formed on the top antenna structure.

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