Multi-phase integrated phase shifter and phase shifter for achieving 22.5°, 45° and 67.5° phase shifts

Abstract

This invention relates to a multi-phase integrated phase shifter unit and phase shifter for implementing 22.5°, 45°, and 67.5° phase shifts, belonging to the field of radio frequency integrated circuit technology. It solves the problem of large volume in existing phase shifter units for implementing 22.5°, 45°, and 67.5° phase shifts. The multi-phase integrated phase shifter unit includes a high-pass circuit, a first low-pass circuit, and a second low-pass circuit connected in parallel. The on / off states of the first low-pass circuit and the second low-pass circuit are opposite. By controlling the on / off states of the high-pass circuit, the first low-pass circuit, and the second low-pass circuit, the multi-phase integrated phase shifter unit can achieve the following four phase shift states: reference phase shift state, 22.5° phase shift state, 45° phase shift state, and 67.5° phase shift state. The phase shifter unit implementing 22.5°, 45°, and 67.5° phase shifts has a small volume and saves costs.

Description

Technical Field

[0001] This invention relates to the field of radio frequency integrated circuit technology, and in particular to a multi-phase integrated phase shifter and phase shifter for realizing 22.5°, 45° and 67.5° phase shifts. Background Technology

[0002] With the continuous development of communication technology, in the military field, phased array radar, due to its strong anti-jamming capability and high reliability, is gradually replacing traditional mechanical radar, which suffers from slow scanning speed and inflexible scanning direction. Simultaneously, with the continuous breakthroughs in 5G technology, the application of automotive radar systems in autonomous driving technology is becoming increasingly widespread. Among these technologies, the phased array radar system is a crucial component. Within a phased array radar system, the T / R (Transmitter and Receiver) transceiver module is the core architecture, and the phase shifter is a vital component of the T / R transceiver module, directly affecting the performance of the entire phased array system, such as phase accuracy and insertion loss. The entire phased array system has tens of thousands of T / R transceiver modules, and each T / R transceiver module requires at least one phase shifter, which occupies a considerable area within the T / R transceiver module.

[0003] In existing technologies, phase shift units for 22.5° and 45° are typically implemented using T-shaped structures based on capacitors or inductors. When 67.5° is required, the two phase shift units for 22.5° and 45° are connected in series to achieve a 67.5° phase shift. However, this implementation method occupies a large volume and is increasingly unable to meet the demands of current technological miniaturization.

[0004] Therefore, there is an urgent need for a phase shifting unit that occupies a small volume to achieve 22.5°, 45° and 67.5°. Summary of the Invention

[0005] Based on the above analysis, the present invention aims to provide a multi-phase integrated phase shifting unit and phase shifter for realizing 22.5°, 45° and 67.5° phase shifts, in order to solve the problem of large volume occupied by the phase shifting unit for realizing 22.5°, 45° and 67.5° phase shifts in the prior art.

[0006] On one hand, embodiments of the present invention provide a multi-phase integrated phase shifting unit for realizing 22.5°, 45° and 67.5° phase shifts, wherein the multi-phase integrated phase shifting unit includes a high-pass circuit, a first low-pass circuit and a second low-pass circuit connected in parallel;

[0007] The on / off states of the first low-pass circuit and the second low-pass circuit are opposite; by controlling the on / off states of the high-pass circuit, the first low-pass circuit, and the second low-pass circuit, the multi-phase integrated phase shift unit can achieve the following four phase shift states:

[0008] When only the first low-pass circuit is in the conducting state, a reference phase shift state is formed for the multi-phase integrated phase shift unit;

[0009] When only the second low-pass circuit is in the conducting state, a 22.5° phase shift state is formed in the multi-phase integrated phase shift unit;

[0010] When only the high-pass circuit and the first low-pass circuit are in the conducting state, a 45° phase shift state is formed in the multi-phase integrated phase shift unit;

[0011] When only the high-pass circuit and the second low-pass circuit are in the conducting state, a 67.5° phase shift state is formed in the multi-phase integrated phase shift unit.

[0012] Based on the further improvement of the above-mentioned multi-phase integrated phase shifter, the high-pass circuit includes a first NMOS transistor, a first capacitor, a first inductor, a second capacitor, and a second NMOS transistor connected in series.

[0013] The gates of the first NMOS transistor and the second NMOS transistor are simultaneously connected to a first voltage. The first voltage is used to control the on / off state of the first NMOS transistor and the second NMOS transistor, thereby controlling the on / off state of the high-pass circuit.

[0014] The source of the first NMOS transistor serves as the signal input terminal of the multi-phase integrated phase-shifting unit;

[0015] The drain of the first NMOS transistor is connected to one end of the first capacitor; the other end of the first capacitor is connected to one end of the second capacitor and one end of the first inductor; the other end of the first inductor is grounded.

[0016] The other end of the second capacitor is connected to the source of the second NMOS transistor, and the drain of the second NMOS transistor serves as the signal output terminal of the multi-phase integrated phase shifter.

[0017] Based on the further improvement of the multi-phase integrated phase shifting unit mentioned above, the capacitance values ​​of the first capacitor and the second capacitor are equal.

[0018] Based on the further improvement of the above-mentioned multi-phase integrated phase shifting unit, the first low-pass circuit and the second low-pass circuit have the same structure, both including a third NMOS transistor, a third capacitor, a second inductor, a fourth capacitor and a fourth NMOS transistor connected in series.

[0019] The gates of the third NMOS transistor and the fourth NMOS transistor are simultaneously connected to a second voltage. The second voltage is used to control the on / off state of the third NMOS transistor and the fourth NMOS transistor, thereby controlling the on / off state of the first low-pass circuit and the second low-pass circuit.

[0020] The source of the third NMOS transistor serves as the signal input terminal of the multi-phase integrated phase shift unit;

[0021] The drain of the third NMOS transistor is connected to one end of the third capacitor and one end of the second inductor, and the other end of the third capacitor is grounded; the other end of the second inductor is connected to one end of the fourth capacitor and the source of the fourth NMOS transistor, and the other end of the fourth capacitor is grounded.

[0022] The drain of the fourth NMOS transistor serves as the signal output terminal of the multi-phase integrated phase shifter unit.

[0023] Based on the further improvement of the above-mentioned multi-phase integrated phase shifting unit, the capacitance values ​​of the third capacitor and the fourth capacitor in the first low-pass circuit are equal, and the capacitance values ​​of the third capacitor and the fourth capacitor in the second low-pass circuit are equal.

[0024] The inductive reactance values ​​of the second inductors in the first low-pass circuit and the second low-pass circuit are not equal;

[0025] The capacitance values ​​of the third capacitor in the first low-pass circuit and the second low-pass circuit are not equal.

[0026] The capacitance values ​​of the fourth capacitor in the first low-pass circuit and the second low-pass circuit are not equal.

[0027] Based on the further improvement of the above-mentioned multi-phase integrated phase shifting unit, the multi-phase integrated phase shifting unit also includes an inverter;

[0028] One end of the inverter is connected to the gate of the third NMOS transistor and the fourth NMOS transistor of the first low-pass circuit.

[0029] The other end of the inverter is connected to the gate of the third NMOS transistor and the fourth NMOS transistor of the second low-pass circuit.

[0030] Based on the further improvements of the aforementioned multi-phase integrated phase-shifting unit, the capacitance values ​​of the first capacitor, the second capacitor, the third capacitor and the fourth capacitor in the first low-pass circuit and the second low-pass circuit, as well as the inductive reactance values ​​of the first inductor, the second inductor of the first low-pass circuit, and the second inductor of the second low-pass circuit are determined in the following manner:

[0031] The circuit equivalent models of the multi-phase integrated phase shift unit are determined in four phase shift states respectively; based on the circuit equivalent models in each state, the amplitude ratio of the output signal to the input signal and the phase change of the output signal to the input signal are determined in each state.

[0032] Constraint equations are constructed for four phase shift states. Solving the constraint equations yields the capacitance values ​​of the first capacitor, the second capacitor, the third capacitor in the first low-pass circuit, and the fourth capacitor in the second low-pass circuit, as well as the inductive reactance values ​​of the first inductor, the second inductor in the first low-pass circuit, and the second inductor in the second low-pass circuit.

[0033] Based on the further improvement of the aforementioned multi-phase integrated phase shifter, the step of determining the amplitude ratio of the output signal to the input signal and the phase change of the output signal to the input signal in each state according to the circuit equivalent model in each state includes:

[0034] Determine the cascade matrix of the circuit equivalent model for each state, and convert the cascade matrix into the admittance matrix for that state.

[0035] Based on the admittance matrix under this condition, determine the insertion loss under this condition;

[0036] Based on the insertion loss in this state, determine the ratio of the amplitude of the output signal to that of the input signal, as well as the phase change between the output signal and the input signal in this state.

[0037] Based on the further improvements to the aforementioned multi-phase integrated phase-shifting unit, the constraint equations for constructing four phase-shifting states include:

[0038] Phase LP2 -Phase LP1 =22.5°;

[0039] Phase HP+LP1 -Phase LP1 =45°;

[0040] phase HP+LP2 -Phase LP1 =67.5°;

[0041]

[0042]

[0043]

[0044]

[0045] Among them, Phase LP1 Phaswe LP2 Phase HP+LP1 and phase HP+LP2 These represent the phase changes between the output and input signals in the reference phase-shifted state, the 22.5° phase-shifted state, the 45° phase-shifted state, and the 67.5° phase-shifted state, respectively.

[0046] real(S21 LP1 ), real(S21) LP2 ), real(S21) HP+LP1 ) and real(S21 HP+LP2 Let f(x) represent the real part of the insertion loss in the reference phase shift state, the 22.5° phase shift state, the 45° phase shift state, and the 67.5° phase shift state, respectively.

[0047] imag(S21 LP1 ), imag(S21) LP2 ), imag(S21) HP+LP1 ) and imag (S21 HP+LP2 ) represent the imaginary parts of the insertion loss in the reference phase shift state, 22.5° phase shift state, 45° phase shift state, and 67.5° phase shift state, respectively.

[0048] On the other hand, embodiments of the present invention provide a phase shifter, the phase shifter including the above-mentioned multi-phase integrated phase shifting unit, and the phase shifter further including one or more of the following phase shifting units:

[0049] 5.625° phase shifting unit;

[0050] 11.25° phase shifting unit;

[0051] 90° phase shifting unit;

[0052] 180° phase shifting unit;

[0053] The phase-shifting unit is connected in series with the multi-phase integrated phase-shifting unit.

[0054] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0055] 1. A phase shifting unit that achieves 22.5°, 45° and 67.5° is formed by combining a high-pass circuit and two low-pass circuits with a double-pole triple-throw switch, which occupies a small size and saves costs;

[0056] 2. By determining the circuit equivalent model of the multi-phase integrated phase shift unit under four phase shift states, the amplitude ratio of the output signal to the input signal and the phase change of the output signal to the input signal under each state are further determined. Constraint equations are constructed under the four phase shift states. Solving the constraint equations yields the capacitance values ​​of the first capacitor, the second capacitor, the third capacitor in the first low-pass circuit, and the fourth capacitor in the second low-pass circuit, as well as the inductive reactance values ​​of the first inductor, the second inductor in the first low-pass circuit, and the second inductor in the second low-pass circuit. This further reduces the volume of the multi-phase integrated phase shift unit and saves costs.

[0057] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description

[0058] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0059] Figure 1 A schematic diagram of the structure of a multi-phase integrated phase-shifting unit for implementing 22.5°, 45° and 67.5° phase shifts provided in an embodiment of the present invention;

[0060] Figure 2 A comparison chart showing the volume occupied by the multi-phase integrated phase shifting unit for implementing 22.5°, 45° and 67.5° phase shifting provided in the embodiments of the present invention and the combined phase shifting unit of 22.5° and 45° in the prior art.

[0061] Figure label:

[0062] ① High-pass circuit; ② First low-pass circuit; ③ Second low-pass circuit. Detailed Implementation

[0063] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.

[0064] In a first aspect, a specific embodiment of the present invention discloses a multi-phase integrated phase-shifting unit for realizing 22.5°, 45°, and 67.5° phase shifts, such as... Figure 1 As shown, the multi-phase integrated phase shifting unit includes a high-pass circuit ①, a first low-pass circuit ②, and a second low-pass circuit ③ connected in parallel.

[0065] The on / off states of the first low-pass circuit ② and the second low-pass circuit ③ are opposite; by controlling the on / off states of the high-pass circuit ①, the first low-pass circuit ②, and the second low-pass circuit ③, the multi-phase integrated phase shift unit can achieve the following four phase shift states:

[0066] When only the first low-pass circuit ② is in the conducting state, a reference phase shift state of the multi-phase integrated phase shift unit is formed;

[0067] When only the second low-pass circuit ③ is in the conducting state, a 22.5° phase shift state is formed in the multi-phase integrated phase shift unit;

[0068] When only the high-pass circuit ① and the first low-pass circuit ② are in the conducting state, a 45° phase shift state is formed in the multi-phase integrated phase shift unit;

[0069] When only the high-pass circuit ① and the second low-pass circuit ③ are in the conducting state, a 67.5° phase shift state is formed in the multi-phase integrated phase shift unit.

[0070] Specifically, such as Figure 1 As shown, the multi-phase integrated phase shifter provided in this embodiment of the invention for implementing 22.5°, 45°, and 67.5° phase shifts has an IN terminal on the left as the signal input terminal and an OUT terminal on the right as the signal output terminal. The signal is input from the IN terminal, passes through a high-pass circuit ①, a first low-pass circuit ②, and a second low-pass circuit ③ connected in parallel, and is finally output from the OUT terminal.

[0071] Specifically, the on / off states of the first low-pass circuit ② and the second low-pass circuit ③ are opposite. That is, if the first low-pass circuit ② is in the on state, the second low-pass circuit ③ is in the off state; if the first low-pass circuit ② is in the off state, the second low-pass circuit ③ is in the on state.

[0072] Specifically, the on / off state of the Qualcomm circuit ① is controlled independently.

[0073] It is worth noting that by controlling the on / off states of the high-pass circuit ①, the first low-pass circuit ②, and the second low-pass circuit ③, the multi-phase integrated phase shifter unit can achieve four on / off states, which is a 2-bit phase shifter.

[0074] The first type: When the first low-pass circuit ② is in the on state and the high-pass circuit ① and the second low-pass circuit ③ are in the off state, this state serves as the reference phase shift state of the multi-phase integrated phase shift unit.

[0075] The second type: When the second low-pass circuit ③ is in the on state, and the high-pass circuit ① and the first low-pass circuit ② are in the off state, this state is the 22.5° phase shift state of the multi-phase integrated phase shift unit;

[0076] The third type: When the high-pass circuit ① and the first low-pass circuit ② are in the on state, and the second low-pass circuit ③ is in the off state, this state is the 45° phase shift state of the multi-phase integrated phase shift unit.

[0077] The fourth type: When the high-pass circuit ① and the second low-pass circuit ③ are in the on state, and the first low-pass circuit ② is in the off state, this state is the 67.5° phase shift state of the multi-phase integrated phase shift unit.

[0078] It is worth noting that when using the multi-phase integrated phase shifting unit provided in this embodiment of the invention for implementing 22.5°, 45°, and 67.5° phase shifts, the number of multi-phase integrated phase shifting units can be selected according to actual needs. For example, if only 22.5°, 45°, or 67.5° phase shifts are needed, two multi-phase integrated phase shifting units can be selected. One multi-phase integrated phase shifting unit is kept in the reference phase shift state, while the other multi-phase integrated phase shifting unit is kept in the 22.5°, 45°, or 67.5° phase shift state. This allows the phase difference of the output signals of the two multi-phase integrated phase shifting units to be 22.5°, 45°, or 67.5°, meaning the phase difference is relative to the reference phase shift state.

[0079] Preferably, such as Figure 1 As shown, the high-pass circuit ① includes a first NMOS transistor, a first capacitor, a first inductor, a second capacitor, and a second NMOS transistor connected in series.

[0080] The gates of the first NMOS transistor and the second NMOS transistor are simultaneously connected to a first voltage. The first voltage is used to control the on / off state of the first NMOS transistor and the second NMOS transistor, thereby controlling the on / off state of the high-pass circuit ①.

[0081] The source of the first NMOS transistor serves as the signal input terminal of the multi-phase integrated phase-shifting unit;

[0082] The drain of the first NMOS transistor is connected to one end of the first capacitor; the other end of the first capacitor is connected to one end of the second capacitor and one end of the first inductor; the other end of the first inductor is grounded.

[0083] The other end of the second capacitor is connected to the source of the second NMOS transistor, and the drain of the second NMOS transistor serves as the signal output terminal of the multi-phase integrated phase shifter.

[0084] Preferably, such as Figure 1 As shown, the capacitance values ​​of the first capacitor and the second capacitor are equal.

[0085] Specifically, such as Figure 1 As shown, the high-pass circuit ① includes, from left to right, a first NMOS transistor M51, a first capacitor C51, a first inductor L51, a second capacitor C51, and a second NMOS transistor M51. It is worth noting that the first NMOS transistor and the second NMOS transistor can be the same or different, as long as the first voltage VA can simultaneously control the on / off state of both NMOS transistors. Figure 1 As shown, the two first NMOS transistors and the second NMOS transistor are identical. When the first voltage VA is high, the first NMOS transistor and the second NMOS transistor are turned on simultaneously. When the first voltage VA is low, the first NMOS transistor and the second NMOS transistor are turned off simultaneously.

[0086] Specifically, the capacitance values ​​of the first capacitor and the second capacitor are equal, that is, as shown below. Figure 1 As shown, the first capacitor C51 and the second capacitor C51 are the same.

[0087] Specifically, when the first voltage VA is high, the first NMOS transistor and the second NMOS transistor are simultaneously turned on, causing the high-pass circuit ① to conduct. The signal is output from the left side to the high-pass circuit ①, and then output from the right side after passing through the high-pass circuit ①. When the first voltage VA is low, the first NMOS transistor and the second NMOS transistor are simultaneously turned off, causing the high-pass circuit ① to turn off, and the signal cannot pass through the high-pass circuit ①.

[0088] Preferably, such as Figure 1 As shown, the first low-pass circuit and the second low-pass circuit have the same structure, both including a third NMOS transistor, a third capacitor, a second inductor, a fourth capacitor and a fourth NMOS transistor connected in series.

[0089] The gates of the third NMOS transistor and the fourth NMOS transistor are simultaneously connected to a second voltage. The second voltage is used to control the on / off state of the third NMOS transistor and the fourth NMOS transistor, thereby controlling the on / off state of the first low-pass circuit and the second low-pass circuit.

[0090] The source of the third NMOS transistor serves as the signal input terminal of the multi-phase integrated phase shift unit;

[0091] The drain of the third NMOS transistor is connected to one end of the third capacitor and one end of the second inductor, and the other end of the third capacitor is grounded; the other end of the second inductor is connected to one end of the fourth capacitor and the source of the fourth NMOS transistor, and the other end of the fourth capacitor is grounded.

[0092] The drain of the fourth NMOS transistor serves as the signal output terminal of the multi-phase integrated phase shifter unit.

[0093] Preferably, the capacitance values ​​of the third capacitor and the fourth capacitor in the first low-pass circuit are equal, and the capacitance values ​​of the third capacitor and the fourth capacitor in the second low-pass circuit are equal.

[0094] The inductive reactance values ​​of the second inductors in the first low-pass circuit and the second low-pass circuit are not equal;

[0095] The capacitance values ​​of the third capacitor in the first low-pass circuit and the second low-pass circuit are not equal.

[0096] The capacitance values ​​of the fourth capacitor in the first low-pass circuit and the second low-pass circuit are not equal.

[0097] Specifically, such as Figure 1 As shown, the first low-pass circuit ② and the second low-pass circuit ③, from left to right, include a third NMOS transistor, a third capacitor, a second inductor, a fourth capacitor, and a fourth NMOS transistor connected in series. That is, the first low-pass circuit ② and the second low-pass circuit ③ have the same structure.

[0098] It is worth noting that, such as Figure 1 As shown, the capacitance values ​​of the third capacitor C52 and the fourth capacitor C52 in the first low-pass circuit ② are equal, and the capacitance values ​​of the third capacitor C53 and the fourth capacitor C53 in the second low-pass circuit ③ are equal. That is, the third capacitor C52 and the fourth capacitor C52 in the first low-pass circuit ② are the same, and the third capacitor C53 and the fourth capacitor C53 in the second low-pass circuit ③ are the same.

[0099] It is worth noting that, such as Figure 1 As shown, the inductive reactance values ​​of the second inductors in the first low-pass circuit ② and the second low-pass circuit ③ are not equal;

[0100] The capacitance values ​​of the third capacitor in the first low-pass circuit ② and the second low-pass circuit ③ are not equal.

[0101] The capacitance values ​​of the fourth capacitor in the first low-pass circuit ② and the second low-pass circuit ③ are not equal.

[0102] That is, the second inductor L52 of the first low-pass circuit ② and the second inductor L53 of the second low-pass circuit ③ are different; the third capacitor C52 of the first low-pass circuit ② and the third capacitor C53 of the second low-pass circuit ③ are different; and the fourth capacitor C52 of the first low-pass circuit ② and the fourth capacitor C53 of the second low-pass circuit ③ are different.

[0103] Specifically, such as Figure 1As shown, the first low-pass circuit ② includes, from left to right, a third NMOS transistor, a third capacitor C52, a second inductor L52, a fourth capacitor C52, and a fourth NMOS transistor connected in series. It is worth noting that the third and fourth NMOS transistors can be the same or different, as long as the second voltage VB can simultaneously control the on / off state of both NMOS transistors. Figure 1 As shown, the third and fourth NMOS transistors are identical. When the first voltage VB is high, both the third and fourth NMOS transistors are turned on simultaneously; when the first voltage VB is low, both the third and fourth NMOS transistors are turned off simultaneously. Specifically, when the second voltage VB is high, both the third and fourth NMOS transistors are turned on simultaneously, causing the first low-pass circuit ② to conduct. The signal is output from the left side to the first low-pass circuit ②, and then output from the right side after passing through the first low-pass circuit ②. When the second voltage VB is low, both the third and fourth NMOS transistors are turned off simultaneously, causing the first low-pass circuit ② to turn off, preventing the signal from passing through the first low-pass circuit ②.

[0104] Specifically, such as Figure 1 As shown, the second low-pass circuit ③, from left to right, includes a third NMOS transistor, a third capacitor C53, a second inductor L53, a fourth capacitor C53, and a fourth NMOS transistor connected in series. It is worth noting that the third and fourth NMOS transistors can be the same or different, as long as the second voltage VB can simultaneously control the on / off state of both NMOS transistors. Figure 1 As shown, the third and fourth NMOS transistors are identical. When the first voltage VB is high, both the third and fourth NMOS transistors are turned off simultaneously; when the first voltage VB is low, both the third and fourth NMOS transistors are turned on simultaneously. Specifically, when the second voltage VB is low, both the third and fourth NMOS transistors are turned on simultaneously, causing the second low-pass circuit ③ to conduct. The signal is output from the left side to the second low-pass circuit ③, and then output from the right side after passing through the second low-pass circuit ③. When the second voltage VB is high, both the third and fourth NMOS transistors are turned off simultaneously, causing the second low-pass circuit ③ to turn off, preventing the signal from passing through the second low-pass circuit ③.

[0105] Preferably, the multi-phase integrated phase shifting unit further includes an inverter;

[0106] One end of the inverter is connected to the gate of the third NMOS transistor and the fourth NMOS transistor of the first low-pass circuit.

[0107] The other end of the inverter is connected to the gate of the third NMOS transistor and the fourth NMOS transistor of the second low-pass circuit.

[0108] Specifically, one end of the inverter is connected to the gates of the third and fourth NMOS transistors of the first low-pass circuit ②, and the other end is connected to the gates of the third and fourth NMOS transistors of the second low-pass circuit ③, so that the second voltage VB can simultaneously control the on / off state of the first low-pass circuit ② and the second low-pass circuit ③, and make the on / off states of the first low-pass circuit ② and the second low-pass circuit ③ opposite.

[0109] Preferably, the capacitance values ​​of the first capacitor, the second capacitor, the third capacitor and the fourth capacitor in the first low-pass circuit and the second low-pass circuit, and the inductive reactance values ​​of the first inductor, the second inductor of the first low-pass circuit, and the second inductor of the second low-pass circuit are determined by the following method:

[0110] The circuit equivalent models of the multi-phase integrated phase shift unit are determined in four phase shift states respectively; based on the circuit equivalent models in each state, the amplitude ratio of the output signal to the input signal and the phase change of the output signal to the input signal are determined in each state.

[0111] Constraint equations are constructed for four phase shift states. Solving the constraint equations yields the capacitance values ​​of the first capacitor, the second capacitor, the third capacitor in the first low-pass circuit, and the fourth capacitor in the second low-pass circuit, as well as the inductive reactance values ​​of the first inductor, the second inductor in the first low-pass circuit, and the second inductor in the second low-pass circuit.

[0112] Preferably, determining the amplitude ratio of the output signal to the input signal and the phase change of the output signal to the input signal in each state based on the circuit equivalent model in each state includes:

[0113] Determine the cascade matrix of the circuit equivalent model for each state, and convert the cascade matrix into the admittance matrix for that state.

[0114] Based on the admittance matrix under this condition, determine the insertion loss under this condition;

[0115] Based on the insertion loss in this state, determine the ratio of the amplitude of the output signal to that of the input signal, as well as the phase change between the output signal and the input signal in this state.

[0116] Specifically, the multi-phase integrated phase shifting unit includes four phase shift states:

[0117] The first type: When the first low-pass circuit ② is in the on state and the high-pass circuit ① and the second low-pass circuit ③ are in the off state, this state serves as the reference phase shift state of the multi-phase integrated phase shift unit.

[0118] The second type: When the second low-pass circuit ③ is in the on state, and the high-pass circuit ① and the first low-pass circuit ② are in the off state, this state is the 22.5° phase shift state of the multi-phase integrated phase shift unit;

[0119] The third type: When the high-pass circuit ① and the first low-pass circuit ② are in the on state, and the second low-pass circuit ③ is in the off state, this state is the 45° phase shift state of the multi-phase integrated phase shift unit.

[0120] The fourth type: When the high-pass circuit ① and the second low-pass circuit ③ are in the on state, and the first low-pass circuit ② is in the off state, this state is the 67.5° phase shift state of the multi-phase integrated phase shift unit.

[0121] Determine the circuit equivalent model for each phase shift state, determine the cascade matrix of the circuit equivalent model for each state, and convert the cascade matrix of the circuit equivalent model for each state into the admittance matrix for that state.

[0122] Specifically, such as Figure 1 As shown, the cascade matrix of the first capacitor C51, the first inductor L51, and the second capacitor C51 in the multi-phase integrated phase shifter unit is as follows:

[0123] The cascade matrix of the first capacitor C51 is as follows:

[0124] The cascade matrix of the first inductor L51 is as follows:

[0125] The cascade matrix of the second capacitor C51 is as follows:

[0126] The cascade matrix of the high-pass circuit is: A HP =HP1*HP2*HP3.

[0127] Specifically, such as Figure 1 As shown, the cascade matrix of the third capacitor C52, the second inductor L52, and the fourth capacitor C52 in the first low-pass circuit of the multi-phase integrated phase shifter unit is as follows:

[0128] The cascade matrix of the third capacitor C52 in the first low-pass circuit is as follows:

[0129]

[0130] The cascade matrix of the second inductor L52 in the first low-pass circuit is as follows:

[0131]

[0132] The cascade matrix of the fourth capacitor C52 in the first low-pass circuit is as follows:

[0133]

[0134] That is, the cascade matrix of the first low-pass circuit is: A LP1 =LP1*LP2*LP3.

[0135] Specifically, such as Figure 1 As shown, the cascade matrix of the third capacitor C53, the second inductor L53, and the fourth capacitor C53 in the second low-pass circuit of the multi-phase integrated phase shifter unit is as follows:

[0136] The cascade matrix of the third capacitor C53 in the second low-pass circuit is as follows:

[0137]

[0138] The cascade matrix of the second inductor L53 in the second low-pass circuit is as follows:

[0139]

[0140] The cascade matrix of the fourth capacitor C53 in the second low-pass circuit is as follows:

[0141]

[0142] That is, the cascade matrix of the second low-pass circuit is: A LP2 =LP4*LP5*LP6.

[0143] Where j is the imaginary unit, and w represents the angular frequency of the input signal.

[0144] Specifically, the cascade matrix of the high-pass circuit, the first low-pass circuit, and the second low-pass circuit is converted into an admittance matrix:

[0145] The admittance matrix of a high-pass circuit is:

[0146]

[0147] The admittance matrix of the first low-pass circuit is:

[0148]

[0149] The admittance matrix of the second low-pass circuit is:

[0150]

[0151] The admittance matrices of the multi-phase integrated phase-shifting unit under the four phase-shifting states are:

[0152] In the first reference phase-shift state, only the first low-pass circuit is conducting, and the circuit equivalent model only includes the first low-pass circuit. The admittance matrix for the first reference phase-shift state is:

[0153]

[0154] In the second 22.5° phase shift state, only the second low-pass circuit is conducting, and the circuit equivalent model only includes the second low-pass circuit. The admittance matrix for the second 22.5° phase shift state is:

[0155]

[0156] In the third 45° phase-shift state, only the high-pass circuit and the first low-pass circuit are conducting. The circuit equivalent model only includes the high-pass circuit and the first low-pass circuit. The admittance matrix of the third 45° phase-shift state is:

[0157]

[0158] In the fourth 67.5° phase shift state, only the high-pass circuit and the second low-pass circuit are conducting. The circuit equivalent model only includes the high-pass circuit and the second low-pass circuit. The admittance matrix for the fourth 67.5° phase shift state is:

[0159]

[0160] Specifically, the insertion loss in this state is determined based on the admittance matrix under this condition:

[0161]

[0162] Where S21 represents the insertion loss, Y (1，1) Y (1，2) Y (2，1) and Y (2，2) These represent the elements in the admittance matrix for each phase shift state, and Z represents the characteristic impedance parameter of the circuit network.

[0163] Preferably, the construction of constraint equations for the four phase shift states includes:

[0164] Phase LP2 -Phase LP1 =22.5°;

[0165] Phase HP+LP1 -Phase LP1 =45°;

[0166] Phase HP+LP2 -Phase LP1 =67.5°;

[0167]

[0168]

[0169]

[0170]

[0171] Among them, Phase LP1 Phase LP2 Phase HP+LP1 and Phase HP+LP2 These represent the phase changes between the output and input signals in the reference phase-shifted state, the 22.5° phase-shifted state, the 45° phase-shifted state, and the 67.5° phase-shifted state, respectively.

[0172] real(S21 LP1 ), real(S21) LP2 ), real(S21) HP+LP1 ) and real(S21 HP+LP2 Let f(x) represent the real part of the insertion loss in the reference phase shift state, the 22.5° phase shift state, the 45° phase shift state, and the 67.5° phase shift state, respectively.

[0173] imag(S21 LP1 ), imag(S21) LP2 ), imag(S21) HP+LP1 ) and imag (S21 HP+LP2 ) represent the imaginary parts of the insertion loss in the reference phase shift state, 22.5° phase shift state, 45° phase shift state, and 67.5° phase shift state, respectively.

[0174] Specifically, solving the constraint equations is equivalent to solving a multi-objective problem. This can be achieved using the particle swarm optimization algorithm, which selects the final solution from the set of non-dominated solutions based on the specific problem. Alternatively, ant colony optimization, distribution estimation algorithms, co-evolutionary algorithms, or evolutionary algorithms can also be used to solve the constraint equations.

[0175] Specifically, such as Figure 2 As shown, the left figure represents the volume of the combination of the 22.5° phase shifting unit and the 45° phase shifting unit in the prior art, while the right figure represents the volume of the multi-phase integrated phase shifting unit provided by the embodiment of the present invention for realizing 22.5°, 45° and 67.5° phase shifts. It can be seen that the volume occupied is greatly reduced.

[0176] Secondly, in a specific embodiment of the present invention, a phase shifter is disclosed, the phase shifter comprising the above-mentioned multi-phase integrated phase shifting unit, and the phase shifter further comprising one or more of the following phase shifting units:

[0177] 5.625° phase shifting unit;

[0178] 11.25° phase shifting unit;

[0179] 90° phase shifting unit;

[0180] 180° phase shifting unit;

[0181] The phase-shifting unit is connected in series with the multi-phase integrated phase-shifting unit.

[0182] Specifically, the phase shifter may include one or more phase shifting units, which may be 5.625° phase shifting units, 11.25° phase shifting units, 90° phase shifting units or 180° phase shifting units, as well as the multi-phase integrated phase shifting unit provided in the first aspect of the present invention.

[0183] It is worth noting that the phase shifter provided in the second aspect embodiment of the present invention includes the multi-phase integrated phase shifting unit provided in the first aspect of the present invention, and the phase shifter provided in the second aspect embodiment of the present invention may also include the 5.625° phase shifting unit, 11.25° phase shifting unit, 90° phase shifting unit or 180° phase shifting unit in the prior art. The specific phase shifting unit used is selected according to the specific requirements. For example, when it is necessary to achieve a 28.125° phase shift, a 50.625° phase shift or a 73.125° phase shift, the phase shifter includes the multi-phase integrated phase shifting unit provided in the first aspect of the present invention and a 5.625° phase shifting unit.

[0184] Specifically, the multi-phase integrated phase shifting unit provided in this embodiment of the invention for realizing 22.5°, 45° and 67.5° phase shifts can be used in combination with one or more other phase shifting units, such as a 5.625° phase shifting unit, an 11.25° phase shifting unit, a 90° phase shifting unit and a 180° phase shifting unit. The multi-phase integrated phase shifting unit is connected in series with other phase shifting units to realize a multi-bit phase shifter.

[0185] When a 2-bit multi-phase integrated phase shifter is connected in series with a 5.625° phase shifter, an 11.25° phase shifter, a 90° phase shifter, and a 180° phase shifter, a 6-bit phase shifter can be formed. This 6-bit phase shifter can achieve phase shifts from 5.625° to 354.375°, realizing 64 phase shift states, with a 5.625° interval between each phase shift state.

[0186] For example: In a 6-bit phase shifter, a multi-phase integrated phase shifter unit, a 5.625° phase shifter unit, an 11.25° phase shifter unit, a 90° phase shifter unit, and a 180° phase shifter unit are connected in series. In this case, the 6-bit phase shifter contains:

[0187] The multi-phase integrated phase shifting unit exhibits a 0° reference phase shift state, a 22.5° phase shift state, a 45° phase shift state, and a 67.5° phase shift state.

[0188] The 5.625° phase shift unit has a 0° reference phase shift state and a 5.625° phase shift state;

[0189] The 11.25° phase shift unit has a 0° reference phase shift state and an 11.25° phase shift state;

[0190] A 90° phase-shifting unit exists in both a 0° reference phase-shifting state and a 90° phase-shifting state;

[0191] The 180° phase shift unit has a 0° reference phase shift state and a 180° phase shift state.

[0192] By controlling the state of each phase-shifting unit, phase shifts from 5.625° to 354.375° are achieved respectively:

[0193] When a 5.625° phase shift is required, control the 5.625° phase shift unit in one 6-bit phase shifter to be in the 5.625° phase shift state, and control the other phase shift units to be in the 0° reference phase shift state. Control all phase shift units in another 6-bit phase shifter to be in the 0° reference phase shift state to achieve a 5.625° phase shift.

[0194] When an 11.25° phase shift is required, control the 11.25° phase shift unit in one 6-bit phase shifter to be in the 11.25° phase shift state, and control the other phase shift units to be in the 0° reference phase shift state. Control all phase shift units in another 6-bit phase shifter to be in the 0° reference phase shift state to achieve an 11.25° phase shift.

[0195] When a 16.875° phase shift is required, control the 11.25° phase shift unit in one 6-bit phase shifter to be in the 11.25° phase shift state and the 5.625° phase shift unit to be in the 5.625° phase shift state, while the other phase shift units are in the 0° reference phase shift state. Control all phase shift units in another 6-bit phase shifter to be in the 0° reference phase shift state to achieve a 16.875° phase shift.

[0196] …

[0197] Similarly, when a 354.375° phase shift is required, the multi-phase integrated phase shifting unit in one 6-bit phase shifter is controlled to be in a 67.5° phase shift state, the 5.625° phase shifting unit is in a 5.625° phase shift state, the 11.25° phase shifting unit is in an 11.25° phase shift state, the 90° phase shifting unit is in a 90° phase shift state, and the 180° phase shifting unit is in a 180° phase shift state. At the same time, all phase shifting units in another 6-bit phase shifter are controlled to be in a 0° reference phase shift state, thus achieving a 354.375° phase shift.

[0198] Compared with existing technologies, the multi-phase integrated phase shifting unit for achieving 22.5°, 45°, and 67.5° phase shifts provided in this embodiment of the invention uses a high-pass circuit and two low-pass circuits, combined with a double-pole triple-throw switch, to form a phase shifting unit that achieves 22.5°, 45°, and 67.5° phase shifts. This results in a smaller footprint and lower cost. Furthermore, by determining the equivalent circuit model of the multi-phase integrated phase shifting unit under the four phase shift states, the amplitude ratio of the output signal to the input signal and the phase change of the output signal to the input signal are further determined for each state. Constraint equations are constructed for the four phase shift states, and solving these equations yields the capacitance values ​​of the first capacitor, the second capacitor, the third capacitor in the first low-pass circuit, and the fourth capacitor in the second low-pass circuit, as well as the inductive reactance values ​​of the first inductor, the second inductor in the first low-pass circuit, and the second inductor in the second low-pass circuit. This further reduces the size of the multi-phase integrated phase shifting unit and saves cost.

[0199] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A multi-phase integrated phase-shifting unit for achieving 22.5°, 45°, and 67.5° phase shifts, characterized in that, The multi-phase integrated phase shifting unit includes a high-pass circuit, a first low-pass circuit, and a second low-pass circuit connected in parallel. The on / off states of the first low-pass circuit and the second low-pass circuit are opposite; by controlling the on / off states of the high-pass circuit, the first low-pass circuit, and the second low-pass circuit, the multi-phase integrated phase shift unit can achieve the following four phase shift states: When only the first low-pass circuit is in the conducting state, a reference phase shift state is formed for the multi-phase integrated phase shift unit; When only the second low-pass circuit is in the conducting state, a 22.5° phase shift state is formed in the multi-phase integrated phase shift unit; When only the high-pass circuit and the first low-pass circuit are in the conducting state, a 45° phase shift state is formed in the multi-phase integrated phase shift unit; When only the high-pass circuit and the second low-pass circuit are in the conducting state, a 67.5° phase shift state is formed in the multi-phase integrated phase shift unit.

2. The multi-phase integrated phase shifting unit according to claim 1, characterized in that, The high-pass circuit includes a first NMOS transistor, a first capacitor, a first inductor, a second capacitor, and a second NMOS transistor connected in series. The gates of the first NMOS transistor and the second NMOS transistor are simultaneously connected to a first voltage. The first voltage is used to control the on / off state of the first NMOS transistor and the second NMOS transistor, thereby controlling the on / off state of the high-pass circuit. The source of the first NMOS transistor serves as the signal input terminal of the multi-phase integrated phase-shifting unit; The drain of the first NMOS transistor is connected to one end of the first capacitor; the other end of the first capacitor is connected to one end of the second capacitor and one end of the first inductor; the other end of the first inductor is grounded. The other end of the second capacitor is connected to the source of the second NMOS transistor, and the drain of the second NMOS transistor serves as the signal output terminal of the multi-phase integrated phase shifter.

3. The multi-phase integrated phase shifting unit according to claim 2, characterized in that, The first capacitor and the second capacitor have the same capacitance value.

4. The multi-phase integrated phase shifting unit according to claim 2, characterized in that, The first low-pass circuit and the second low-pass circuit have the same structure, both including a third NMOS transistor, a third capacitor, a second inductor, a fourth capacitor and a fourth NMOS transistor connected in series. The gates of the third NMOS transistor and the fourth NMOS transistor are simultaneously connected to a second voltage. The second voltage is used to control the on / off state of the third NMOS transistor and the fourth NMOS transistor, thereby controlling the on / off state of the first low-pass circuit and the second low-pass circuit. The source of the third NMOS transistor serves as the signal input terminal of the multi-phase integrated phase shift unit; The drain of the third NMOS transistor is connected to one end of the third capacitor and one end of the second inductor, and the other end of the third capacitor is grounded; the other end of the second inductor is connected to one end of the fourth capacitor and the source of the fourth NMOS transistor, and the other end of the fourth capacitor is grounded. The drain of the fourth NMOS transistor serves as the signal output terminal of the multi-phase integrated phase shifter unit.

5. The multi-phase integrated phase shifting unit according to claim 4, characterized in that, The capacitance values ​​of the third capacitor and the fourth capacitor in the first low-pass circuit are equal, and the capacitance values ​​of the third capacitor and the fourth capacitor in the second low-pass circuit are equal. The inductive reactance values ​​of the second inductors in the first low-pass circuit and the second low-pass circuit are not equal; The capacitance values ​​of the third capacitor in the first low-pass circuit and the second low-pass circuit are not equal. The capacitance values ​​of the fourth capacitor in the first low-pass circuit and the second low-pass circuit are not equal.

6. The multi-phase integrated phase shifting unit according to claim 4, characterized in that, The multi-phase integrated phase shifting unit also includes an inverter; One end of the inverter is connected to the gate of the third NMOS transistor and the fourth NMOS transistor of the first low-pass circuit. The other end of the inverter is connected to the gate of the third NMOS transistor and the fourth NMOS transistor of the second low-pass circuit.

7. The multi-phase integrated phase shifting unit according to claim 5, characterized in that, The capacitance values ​​of the first capacitor, the second capacitor, the third capacitor and the fourth capacitor in the first low-pass circuit and the second low-pass circuit, and the inductive reactance values ​​of the first inductor, the second inductor of the first low-pass circuit, and the second inductor of the second low-pass circuit are determined in the following manner: The circuit equivalent models of the multi-phase integrated phase shift unit are determined in four phase shift states respectively; based on the circuit equivalent models in each state, the amplitude ratio of the output signal to the input signal and the phase change of the output signal to the input signal are determined in each state. Constraint equations are constructed for four phase shift states. Solving the constraint equations yields the capacitance values ​​of the first capacitor, the second capacitor, the third capacitor in the first low-pass circuit, and the fourth capacitor in the second low-pass circuit, as well as the inductive reactance values ​​of the first inductor, the second inductor in the first low-pass circuit, and the second inductor in the second low-pass circuit.

8. The multi-phase integrated phase shifting unit according to claim 7, characterized in that, The determination of the amplitude ratio of the output signal to the input signal and the phase change of the output signal to the input signal under each state, based on the circuit equivalent model under each state, includes: Determine the cascade matrix of the circuit equivalent model for each state, and convert the cascade matrix into the admittance matrix for that state. Based on the admittance matrix under this condition, determine the insertion loss under this condition; Based on the insertion loss in this state, determine the ratio of the amplitude of the output signal to that of the input signal, as well as the phase change between the output signal and the input signal in this state.

9. The multi-phase integrated phase shifting unit according to claim 8, characterized in that, The construction of constraint equations for the four phase shift states includes: Phase LP2 -Phase LP1 =22.5°; Phase HP+LP1 -Phase LP1 =45°; phase HP+LP2 -Phase LP1 =67.5°; Among them, Phase LP1 Phase LP2 Phase HP+LP1 and phase HP+LP2 These represent the phase changes between the output and input signals in the reference phase-shifted state, the 22.5° phase-shifted state, the 45° phase-shifted state, and the 67.5° phase-shifted state, respectively. real(S21 LP1 ), real(S21) LP2 ), real(S21) HP+LP1 ) and real(S21 HP+LP2 Let f(x) represent the real part of the insertion loss in the reference phase shift state, the 22.5° phase shift state, the 45° phase shift state, and the 67.5° phase shift state, respectively. imag(S21 LP1 ), imag(S21) LP2 ), imag(S21) HP+LP1 ) and imag (S21 HP+LP2 ) represent the imaginary parts of the insertion loss in the reference phase shift state, 22.5° phase shift state, 45° phase shift state, and 67.5° phase shift state, respectively.

10. A phase shifter, characterized in that, The phase shifter includes the multi-phase integrated phase shifting unit according to any one of claims 1-9, and the phase shifter further includes one or more of the following phase shifting units: 5.625° phase shifting unit; 11.25° phase shifting unit; 90° phase shifting unit; 180° phase shifting unit; The phase-shifting unit is connected in series with the multi-phase integrated phase-shifting unit.

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