Zero-voltage start-up control module, drive circuit and active clamp converter

Abstract

This invention provides a zero-voltage turn-on control module, a drive circuit, and an active clamp converter, comprising: a timing unit for timing a first duration; a duration acquisition unit for acquiring the duration from the clamp transistor's turn-off to the complete release of the transformer's secondary inductor current, obtaining a second duration; a comparison unit for comparing the first duration with the second duration; and a dead-time adjustment unit for adjusting the clamp transistor's on-time and the first duration in the next cycle based on the comparison result of the current cycle, thereby achieving adaptive zero-voltage turn-on control. This invention employs digital circuitry, enabling accurate control, a wide control range, and dynamic zero-voltage turn-on control, improving system efficiency, reducing the use of capacitors in analog circuits, and lowering chip area costs.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, and in particular to a zero-voltage turn-on control module, a drive circuit, and an active clamp converter. Background Technology

[0002] The current energy shortage is driving the continued development of electronic technology, and further reducing the power consumption of electronic devices has always been a mission for electronic design engineers. In recent years, flyback converters, which have advantages in size, cost, and high reliability, have seen significant development. Among them, active clamp converters (such as active clamp flyback converters, ACF) use active components to recover (absorb) the energy in the leakage inductance of the transformer through a resonant process. Compared with traditional RCD clamp converters and LCD clamp converters, active clamp converters can meet the ZVS requirement of the primary-side power transistors. Therefore, they have higher switching frequencies and higher efficiency, and are widely used in the field of power isolation conversion.

[0003] Existing technologies often employ analog circuits to adjust the dead time between the clamping transistor and the main switching transistor. This approach cannot accurately control the dead time, has a narrow adjustable range, and cannot achieve zero-voltage turn-on control across the entire load range. It also suffers from drawbacks such as higher main switching transistor losses and lower system efficiency. Furthermore, some control schemes negatively impact system stability and lack practical applicability. One current solution uses a multiplexed auxiliary winding voltage sampling pin to determine whether the main switching transistor has achieved zero-voltage turn-on. However, this requires designing both a forward counter and a reversible counter internally, resulting in a complex circuit structure that is detrimental to integrated circuit fabrication and the requirements for miniaturization and low cost.

[0004] Therefore, improving the accuracy of zero-voltage turn-on control of the main switch, reducing costs, and minimizing circuit area have become urgent problems for those skilled in the art.

[0005] It should be noted that the above description of the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of the present invention and facilitating understanding by those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because they have been described in the background section of this invention. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a zero-voltage turn-on control module, a drive circuit, and an active clamp converter to solve the problems of poor accuracy, complex circuit structure, and high cost in the adjustment of dead time in analog circuits in the prior art.

[0007] To achieve the above and other related objectives, the present invention provides an adaptive zero-voltage turn-on control module applied to an active clamp converter, wherein the adaptive zero-voltage turn-on control module includes at least:

[0008] Timing unit, duration acquisition unit, comparison unit, and dead time adjustment unit;

[0009] The timing unit is connected to the output terminal of the dead time adjustment unit and times the first duration provided by the dead time adjustment unit. The first duration is the preset dead time between the clamping transistor being turned off and the main switch being turned on in the active clamping converter.

[0010] The duration acquisition unit acquires the duration from the turn-off of the clamping transistor in the active clamping converter to the complete release of the transformer secondary inductor current, and obtains the second duration.

[0011] The comparison unit is connected to the output of the timing unit and the duration acquisition unit, and compares the first duration with the second duration.

[0012] The dead time adjustment unit is connected to the output of the comparison unit. Based on the comparison result of the current cycle, it adjusts the on-time of the clamping transistor and the first duration for the next cycle, thereby realizing adaptive zero-voltage turn-on control. When the first duration is greater than the second duration, the on-time of the clamping transistor is reduced by a preset duration. When the first duration is less than the second duration, the on-time of the clamping transistor is increased by a preset duration. When the first duration is equal to the second duration, the on-time of the clamping transistor remains unchanged.

[0013] Optionally, the timing unit includes a timer that starts timing from when the clamping tube is turned off and outputs a timing end signal when the timing reaches the first duration.

[0014] Optionally, the duration acquisition unit includes a controller, a frequency divider, and a counter;

[0015] The controller receives the drive signal and zero current detection signal of the clamping transistor. When the clamping transistor is turned off, a timing start signal is triggered, and when the zero current detection signal is valid, a timing end signal is triggered.

[0016] The frequency divider is connected to the output of the controller and receives the working clock. When the timing start signal is valid, it sequentially performs a 2-step process on the working clock. i The frequency is divided by a factor to obtain the counting clock; where i = 1, 2...n, and n is the number of bits in the output signal of the duration acquisition unit, set to a natural number greater than 2;

[0017] The counter is connected to the output of the controller and the frequency divider. When the timing start signal is valid, timing starts based on the counting clock. When the timing end signal is valid, timing stops.

[0018] Alternatively, the controller is implemented using an RS flip-flop, wherein the set terminal of the RS flip-flop is connected to the drive signal of the clamping transistor, the reset terminal is connected to the zero current detection signal, and the controller outputs control signals for starting and ending the timing.

[0019] Alternatively, the frequency divider includes n cascaded D flip-flops, with the data input terminal of each D flip-flop connected to the inverted output terminal and the non-inverted output terminal outputting the frequency division signal; the clock terminal of the first-stage D flip-flop is connected to the operating clock, and the clock terminal of the subsequent D flip-flop is connected to the inverted output terminal of the preceding D flip-flop; the asynchronous reset terminal of the first-stage D flip-flop is connected to the output terminal of the controller, and the asynchronous reset terminals of the second to nth D flip-flops are connected to the inverted signal of the zero-current detection signal.

[0020] Alternatively, the counter includes n cascaded D flip-flops, with the asynchronous reset terminal of each D flip-flop connected to the delayed signal of the controller output signal, and the clock terminal of the i-th D flip-flop connected to 2 i The counting clock is divided by a factor of two; the data input of the first-stage D flip-flop is connected to a preset voltage, and the data input of the subsequent D flip-flop is connected to the positive output of the previous D flip-flop; the inverted output of each D flip-flop outputs the timing result.

[0021] Alternatively, the comparison unit includes n comparison sub-units, each of which includes an XOR gate, a first NAND gate, a second NAND gate, and a third NAND gate;

[0022] The input terminals of the XOR gate are respectively connected to the output signal of the timing unit and the corresponding bit output signal of the counter. The input terminals of the first NAND gate are respectively connected to the corresponding bit output signal of the counter and the output signal of the XOR gate, and output a first comparison result. The input terminals of the second NAND gate are respectively connected to the output signal of the timing unit and the output signal of the XOR gate, and output a second comparison result. The input terminals of the third NAND gate are respectively connected to the output signal of the timing unit and the corresponding bit output signal of the counter, and output a third comparison result.

[0023] Alternatively, the dead time adjustment unit includes a time adjustment subunit and n control subunits;

[0024] Each control subunit is connected to the output terminal of each comparison subunit. Each adjustment subunit includes a first enable transistor, a second enable transistor, a third enable transistor, a first transistor, a second transistor, and a third transistor. One end of each enable transistor is connected to a preset voltage, and the other end is connected to the control terminal of the corresponding transistor. When the enable signal is invalid, each enable transistor is turned on to control each transistor to turn off. One end of the first transistor is connected to the preset voltage, and the other end generates a control signal to reduce the conduction time of the clamping transistor. The control terminal is connected to the corresponding first comparison result. One end of the second transistor is connected to the preset voltage, and the other end generates a control signal to increase the conduction time of the clamping transistor. The control terminal is connected to the corresponding second comparison result. One end of the third transistor is connected to the preset voltage, and the other end generates a control signal to maintain the conduction time of the clamping transistor. The control terminal is connected to the corresponding third comparison result.

[0025] The time adjustment subunit is connected to the output terminal of each control subunit and receives the working clock. Based on the control signals output by each control subunit, the working clock is used to generate a counting time, thereby adjusting the conduction time of the clamping transistor.

[0026] To achieve the above and other related objectives, the present invention also provides a driving circuit, the driving circuit comprising at least:

[0027] The logic control module, the power-on reset module, and the aforementioned adaptive zero-voltage turn-on control module;

[0028] The adaptive zero-voltage turn-on control module generates and adjusts the dead time between the turn-off of the clamping transistor and the turn-on of the main switch transistor in the next cycle based on the drive signal and zero-current detection signal of the clamping transistor.

[0029] The power-on reset module is used to reset the logic control module when the active clamp converter is powered on;

[0030] The logic control module is connected to the output terminals of the adaptive zero-voltage turn-on control module and the power-on reset module, and receives the zero-voltage detection signal and output current sampling signal of the active clamp converter, which are used to generate drive signals for the clamping transistor and the main switching transistor.

[0031] Optionally, the driving circuit further includes an oscillator that provides an operating clock for the driving circuit.

[0032] To achieve the above and other related objectives, the present invention also provides an active clamp converter, the active clamp converter comprising at least:

[0033] Active clamping conversion circuit and the aforementioned driving circuit;

[0034] The driving circuit obtains feedback signals from the active clamping conversion circuit and generates driving signals for the clamping transistor and the main switching transistor based on the feedback signals.

[0035] The active clamping converter circuit converts the input voltage into the output voltage based on the control of the driving circuit.

[0036] As described above, the zero-voltage turn-on control module, drive circuit, and active clamp converter of the present invention have the following beneficial effects:

[0037] 1. The zero-voltage turn-on control module, drive circuit, and active clamp converter of the present invention introduce dynamic dead-time adjustment control technology to achieve zero-voltage adaptive control of the main switch, enabling the system to quickly reach the optimal working state, reducing the switching loss of the main switch, and improving the efficiency of the active clamp converter.

[0038] 2. The zero-voltage turn-on control module, drive circuit and active clamp converter of the present invention use digital circuits to adjust the dead time between the clamping transistor and the main switching transistor, which can avoid the use of large capacitors in analog circuits, thereby greatly reducing the circuit size and reducing costs.

[0039] 3. The zero-voltage turn-on control module of the present invention is implemented using digital circuits, which has a simple circuit structure, high accuracy, and no impact on system stability.

[0040] 4. The zero-voltage turn-on control module, drive circuit, and active clamp converter of the present invention can achieve zero-voltage turn-on control across the entire load range and can operate at a higher frequency range, further improving the system efficiency. At the same time, the circuit has good portability and meets the application scenarios of ordinary Si transistors and third-generation semiconductor GaN. Attached Figure Description

[0041] Figure 1 The diagram shows the control waveforms of an active clamp flyback converter.

[0042] Figure 2 The diagram shown is a structural schematic of the adaptive zero-voltage turn-on control module of the present invention.

[0043] Figure 3 The diagram shown is a schematic of the adaptive zero-voltage start-up control module of the present invention.

[0044] Figure 4 The diagram shown is a schematic representation of the driving circuit of the present invention.

[0045] Figure 5 The diagram shown is a structural schematic of the active clamp converter of the present invention.

[0046] Component designation explanation

[0047] 1-Drive circuit; 11-Adaptive zero-voltage turn-on control module; 111-Timing unit; 112-Duration acquisition unit; 112a-Controller; 112b-Frequency divider; 112c-Counter; 113-Comparison unit; 113a-Comparison subunit; 114-Dead time adjustment unit; 114a-Adjustment subunit; 12-Power-on reset module; 13-Logic control module; 14-Oscillator; 2-Active clamping conversion circuit; 21-Voltage input module; 22-Output module; 23-Zero current detection module. Detailed Implementation

[0048] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0049] Please see Figures 1-5 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0050] Taking an active clamp flyback converter as an example, to achieve zero-voltage turn-on control of the main switch in an active clamp flyback converter, a complementary conduction control mode is typically adopted between the main switch and the clamping transistor; for example... Figure 1 The diagram shows the control waveforms of an active clamp flyback converter, where V DS PWM_C is the drain-source voltage of the main switching transistor, PWM_P is the drive signal for the clamping transistor, and PWM_C is the drive signal for the main switching transistor. i m This refers to the primary inductance current of the transformer. In an active clamp flyback converter, the main switch transistor can be controlled based on its drain-source voltage V. DS The output power is used to control the switching on and off. After the main switch is turned on, the transformer primary inductor current... i m It shows a linear increasing trend (at this time, the transformer primary inductance current flows through the main switching transistor, denoted as I). P When the output current sampling signal reaches the preset reference value (the preset reference value is adjustable and corresponds to different values ​​at different stages), the control system turns off the main switch, and the energy stored in the primary inductance of the transformer is instantly coupled to the secondary side. At the same time, the clamping transistor, after a delay T after the main switch is turned off, DP_CAfter opening (at this time, the primary inductance current of the transformer flows through the clamping transistor, denoted as...), i clamp The drain-source voltage V of the main switch transistor N0 DS Given Vin + mVo, where Vin is the input voltage, Vo is the output voltage, and m is the turns ratio of the primary winding to the secondary winding in the transformer, the energy in the leakage inductance can be recovered through the clamping resistor and clamping capacitor after the clamping transistor is turned on. Because the clamping transistor is open, the primary inductor current of the transformer... i m The voltage dipped momentarily, but due to the parasitic capacitance between the drain and source of the main switch, the transformer capacitance, and the capacitance of the secondary rectifier diode, the primary inductor current of the transformer was reduced. i m There will be an increasing process. Based on the above analysis, in order to achieve zero-voltage turn-on control of the main switch, the following zero-voltage turn-on conditions need to be met:

[0051] (1)

[0052] Among them, L M i is the inductance value of the primary side of the transformer. clamp- direction and i clamp The directions are opposite, but the sizes are equal; similarly i m- direction and i m The specified currents are in opposite directions but equal in magnitude; C eq The drain-source equivalent capacitance of the main switching transistor; due to the leakage inductance L K The leakage inductance is very small, and some of the leakage inductance energy has already been recovered, so formula (1) no longer considers the leakage inductance energy. From the above formulas, it can be seen that the equivalent capacitance C of the drain-source of the main switch needs to be utilized. eq Clamping capacitor C RD In addition, the parasitic capacitance between the drain and source of the clamping transistor discharges until a zero-voltage detection signal is detected. Therefore, in order to achieve zero-voltage turn-on control, the turn-on time of the clamping transistor needs to be continuously and adaptively adjusted, thereby adjusting the dead time between the turn-off of the clamping transistor and the turn-on of the main switch.

[0053] like Figure 2 As shown, the present invention provides an adaptive zero-voltage turn-on control module 11, applied to an active clamp converter, the adaptive zero-voltage turn-on control module 11 comprising:

[0054] The system includes a timing unit 111, a duration acquisition unit 112, a comparison unit 113, and a dead time adjustment unit 114.

[0055] like Figure 2As shown, the timing unit 111 is connected to the output terminal of the dead time adjustment unit 114 and times the first duration T1 provided by the dead time adjustment unit 114. The first duration T1 is the preset dead time between the clamping transistor being turned off and the main switch being turned on in the active clamping converter.

[0056] Specifically, in the initial state, the timing unit 111 acquires the first duration T1 based on the zero-voltage detection signal ZVS. At this time, the first duration T1 is the duration from the clamping transistor being turned off to the main switch being turned on (actual measured value). Subsequently, the timing unit 111 acquires the continuously updated first duration T1 (calculated preset value) based on the dead-time adjustment unit 114. In this embodiment, the timing unit 111 is implemented using a timer. The count value of the timer is set based on the first duration T1. The timer starts counting from the time the clamping transistor is turned off. When the count value is reached, it is determined that the first duration T1 has ended, and a corresponding count end signal is output (for example, high level is active). As the dead-time adjustment unit 114 continuously adjusts the first duration T1, the set count value of the timer is also continuously updated.

[0057] It should be noted that any circuit structure capable of timing the first duration T1 and outputting a corresponding signal is applicable to the present invention, and is not limited to this embodiment.

[0058] like Figure 2 As shown, the duration acquisition unit 112 acquires the duration from the turn-off of the clamping transistor in the active clamping converter to the complete release of the transformer secondary inductor current, thus obtaining the second duration t2. Figure 3 As shown, in this embodiment, the duration acquisition unit 112 includes a controller 112a, a frequency divider 112b, and a counter 112c.

[0059] Specifically, such as Figure 3As shown, in this embodiment, the controller 112a receives the drive signal PWM_C of the clamping transistor and the zero-current detection signal ZCD. When the clamping transistor is turned off, a timing start signal is triggered; when the zero-current detection signal ZCD is valid, a timing end signal is triggered. As an example, the controller 112a is implemented using an RS flip-flop. The set terminal s of the RS flip-flop is connected to the drive signal PWM_C of the clamping transistor, and the reset terminal is connected to the zero-current detection signal ZCD. It outputs control signals for timing start and end. When the drive signal PWM_C of the clamping transistor goes low, the output signal CTR of the RS flip-flop goes high (i.e., the timing start signal). When the zero-current detection signal ZCD is valid at a high level, the output signal CTR of the RS flip-flop goes low (i.e., the timing end signal). In practical use, any circuit structure that satisfies the above logic is applicable to this invention and is not limited to this embodiment.

[0060] Specifically, such as Figure 3 As shown, in this embodiment, the frequency divider 112b is connected to the output terminal of the controller 112a and receives the working clock OSC. When the timing start signal is valid, the working clock OSC is sequentially processed by 2... i The frequency is divided by a factor of 1 to obtain the counting clock; where i = 1, 2...n, and n is the number of bits in the output signal of the duration acquisition unit 112, set to a natural number greater than 2, and can be set to the appropriate value as needed in actual use. As an example, the frequency divider 112b includes n cascaded D flip-flops, the data input terminal D of each D flip-flop is connected to the inverting output terminal Q-, and the non-inverting output terminal Q+ outputs the frequency division signal, wherein the first stage D flip-flop outputs a frequency division signal of 2clk by 2, the second stage D flip-flop outputs a frequency division signal of 4clk by 4, and so on, with the nth stage D flip-flop outputting 2clk by 4clk. n Frequency division signal 2 n clk; The clock input clk of the first-stage D flip-flop is connected to the operating clock OSC, and the clock input clk of the subsequent-stage D flip-flop is connected to the inverted output Q- of the preceding-stage D flip-flop; The asynchronous reset input Clr of the first-stage D flip-flop is connected to the output of the controller 112a, and the asynchronous reset input Clr of the second to nth-stage D flip-flops is connected to the inverted signal ZCD_N of the zero-current detection signal; When the output signal CTR of the RS flip-flop jumps to a high level and the inverted signal ZCD_N of the zero-current detection signal is high, the frequency divider 112b starts frequency division; When the output signal CTR of the RS flip-flop jumps to a low level and the inverted signal ZCD_N of the zero-current detection signal is low, the frequency divider 112b is reset; In practical use, any circuit structure that can satisfy the above logic is applicable to this invention, and is not limited to this embodiment.

[0061] Specifically, such as Figure 3 As shown, in this embodiment, the counter 112c is connected to the output terminals of the controller 112a and the frequency divider 112b. When the timing start signal is valid, timing begins based on the counting clock; when the timing end signal is valid, timing stops. As an example, the counter 112c includes n cascaded D flip-flops. The asynchronous reset terminal Clr of each D flip-flop is connected to the delayed signal CTR_D of the controller output signal, and the clock terminal of the i-th D flip-flop is connected to the 2... i The counting clock is divided by a factor of two (i.e., the clock input of the first-stage D flip-flop receives a divided-by-two signal 2clk, the clock input of the second-stage D flip-flop receives a divided-by-four signal 4clk, and so on, with the clock input of the nth-stage D flip-flop receiving 2clk). n Frequency division signal 2 n clk); the data input terminal D of the first-stage D flip-flop is connected to the preset voltage LV; the data input terminal D of the subsequent-stage D flip-flop is connected to the non-inverting output terminal Q+ of the preceding-stage D flip-flop; the inverting output terminal Q- of each D flip-flop outputs the timing result, and each D flip-flop outputs one bit of signal (t). 2_DET1 t 2_DET2 …t 2_DETn The timing result is composed of n-bit signals (high level is active as an example); when the delay signal CTR_D of the controller output signal jumps to a high level and the corresponding counting clock is received, the counter 112c starts counting; when the delay signal CTR_D of the controller output signal jumps to a low level or the corresponding counting clock is not received, the counter 112c stops working; in actual use, any circuit structure that can satisfy the above logic is applicable to the present invention, and is not limited to this embodiment.

[0062] like Figure 2 As shown, the comparison unit 113 is connected to the output terminals of the timing unit 111 and the duration acquisition unit 112, and compares the first duration T1 with the second duration t2.

[0063] Specifically, such as Figure 3 As shown, in this embodiment, the comparison unit 113 includes n comparison subunits 113a, each of which includes an XOR gate, a first NAND gate (nand1), a second NAND gate (nand2), and a third NAND gate (nand3). The input of the XOR gate is connected to the output signal of the timing unit 111 and the corresponding bit output signal of the counter 112c (denoted as t). 2_DET1 t 2_DET2 …t 2_DETnThe input terminals of the first NAND gate (nand1) are respectively connected to the corresponding bit output signals of the counter (112c) and the output signal of the XOR gate (XOR), and output the first comparison result (denoted as P11, P12...P1n). The input terminals of the second NAND gate (nand2) are respectively connected to the output signal of the timing unit (111) and the output signal of the XOR gate (XOR), and output the second comparison result (denoted as P21, P22...P2n). The input terminals of the third NAND gate (nand3) are respectively connected to the output signal of the timing unit (111) and the corresponding bit output signal of the counter, and output the third comparison result (denoted as P31, P32...P3n). Specifically, when the duration represented by the corresponding bit output signal of the counter 112c is less than the first duration T1, the first comparison result of the corresponding comparison subunit 113a jumps to a low level; when the duration represented by the corresponding bit output signal of the counter 112c is greater than the first duration T1, the second comparison result of the corresponding comparison subunit 113a jumps to a low level; when the duration represented by the corresponding bit output signal of the counter 112c is equal to the first duration T1, the third comparison result of the corresponding comparison subunit 113a jumps to a low level; in this example, taking the nth comparison unit 113a as an example, the first duration T1 and the nth bit output signal t of the counter 112c... 2_DETn The high-level signal, arriving first, is the one with the shorter duration. By combining the comparison results P11, P12…P1n, P21, P22…P2n, P31, P32…P3n, we can determine which duration, the first time T1 or the second time t2, is longer. The corresponding truth table is as follows:

[0064] T1 <![CDATA[t 2_DETn ]]> XOR output P1n P2n P3n 0 0 0 1 1 1 0 1 1 0 1 1 <![CDATA[T1>t 2_DETn ]]> 1 0 1 1 0 1 <![CDATA[T1<t 2_DETn ]]> 1 1 0 0 0 1 <![CDATA[T1= t 2_DETn ]]>

[0065] In practical applications, any circuit structure that can compare two signals representing durations and obtain a comparison result is applicable to this invention, and is not limited to this embodiment.

[0066] like Figure 2 As shown, the dead time adjustment unit 114 is connected to the output of the comparison unit 113. Based on the comparison result of the current cycle, it adjusts the on-time of the clamping transistor and the first duration in the next cycle, thereby realizing adaptive zero-voltage turn-on control. When the first duration T1 is greater than the second duration t2, the on-time T of the clamping transistor is adjusted. H_ON Reduce the preset duration Δt; when the first duration T1 is less than the second duration t2, reduce the conduction time T of the clamping tube. H_ON Increase the preset duration Δt; when the first duration T1 is equal to the second duration t2, the conduction time T of the clamping transistor is... H_ON It remains unchanged.

[0067] Specifically, such as Figure 3 As shown, in this embodiment, the dead time adjustment unit 114 includes a time adjustment subunit 114b and n control subunits 114a, each control subunit 114a being connected one-to-one with the output terminal of each comparison subunit 113a. Each control subunit 114a includes a first enable transistor M1, a second enable transistor M2, a third enable transistor M3, a first transistor M4, a second transistor M5, and a third transistor M6. One end of each enable transistor is connected to a preset voltage LV, and the other end is connected to the control terminal of each transistor. When the enable signal T... SSE When invalid, each enable transistor is turned on to control the turn-off of each transistor; wherein, the first enable transistor M1 is connected to the control terminal of the first transistor M4, the second enable transistor M2 is connected to the control terminal of the second transistor M5, and the third enable transistor M3 is connected to the control terminal of the third transistor M6. As an example, each enable transistor and transistor is a PMOS transistor. When the enable signal T... SSE When the signal transitions to a low level (invalid), all enable transistors are turned on, thereby causing the control terminals of each transistor to be connected to the preset voltage LV (high level) and turned off. At this time, the dead time adjustment unit 114 does not work; when the enable signal T... SSE When the signal transitions to a high level (active), all enable transistors are turned off, and the control terminals of each transistor are connected to the corresponding comparison results. At this time, the dead time adjustment unit 114 is in operation. One end of the first transistor M4 is connected to the preset voltage LV, and its control terminal is connected to the corresponding first comparison result. The other end generates a signal that reduces the conduction time T of the clamping transistor. H_ON The control signal; one end of the second transistor M5 is connected to the preset voltage LV, the control end is connected to the corresponding second comparison result, and the other end generates an increase in the conduction time T of the clamping transistor. H_ON The control signal; one end of the third transistor M6 is connected to the preset voltage LV, the control terminal is connected to the corresponding third comparison result, and the other end generates the control signal to maintain the conduction time T of the clamping transistor. H_ON The control signal; when the corresponding comparison result jumps to a low level, the corresponding transistor is turned on, and a control signal for adjusting the conduction time of the clamping transistor is output. The time adjustment subunit 114b is connected to the output terminal of each control subunit 114a and receives the working clock OSC. Based on the control signal output by each control subunit 114a, it uses the working clock OSC to generate a counting time, thereby realizing the adjustment of the conduction time T of the clamping transistor. H_ON Adjustments.

[0068] It should be noted that, in this embodiment, during the circuit startup phase, the enable signal T SSE Invalid; the adaptive zero-voltage turn-on control module 11 is not working; when the circuit starts, the enable signal T... SSEUpon the transition becoming valid, the adaptive zero-voltage turn-on control module 11 begins operation. Furthermore, any circuit structure capable of adjusting the conduction time of the clamping transistor and the first duration based on the output signal of the comparison unit 113 is applicable to this invention and is not limited to this embodiment.

[0069] It should be noted that the preset duration Δt is not greater than the clamping transistor's on-time. To improve the adjustment accuracy, the preset duration Δt should be set to a smaller value; to improve the adjustment efficiency, the preset duration Δt should be set to a larger value. The specific value of the preset duration Δt is set according to the actual design requirements, as long as it can achieve adaptive changes in the dead time of each cycle. As an example, the preset duration Δt is configured as n working clock cycles, where n is a natural number greater than or equal to 1, including but not limited to 1 to 10.

[0070] like Figure 4 As shown, the present invention also provides a driving circuit 1, the driving circuit 1 comprising:

[0071] The adaptive zero-voltage turn-on control module 11, power-on reset module 12, and logic control module 13 are described.

[0072] like Figure 4 As shown, the adaptive zero-voltage turn-on control module 11 generates and adjusts the dead time between the turn-off of the clamping transistor and the turn-on of the main switch transistor in the next cycle based on the drive signal PWM_C of the clamping transistor and the zero-current detection signal ZCD.

[0073] Specifically, the structure and working principle of the adaptive zero-voltage turn-on control module 11 are described above and will not be repeated here.

[0074] like Figure 4 As shown, the power-on reset module 12 is used to reset the logic control module 13 when the active clamp converter is powered on.

[0075] Specifically, the structure of the power-on reset module 12 is not limited, and any circuit structure that can achieve power-on reset is applicable to the present invention.

[0076] like Figure 4 As shown, the logic control module 13 is connected to the output terminals of the adaptive zero-voltage turn-on control module 11 and the power-on reset module 12, and receives the zero-voltage detection signal ZVS and the output current sampling signal Vcs of the active clamp converter, which are used to generate the drive signal PWM_C of the clamping transistor and the drive signal PWM_P of the main switching transistor.

[0077] Specifically, as an example, when the clamping transistor's off-time in the current cycle reaches the set first duration T1 and the zero-voltage detection signal ZVS is valid, the main switch is turned on; when the output current of the active clamp converter reaches a limited threshold (as an example, during the circuit startup phase, the output current sampling signal Vcs is determined to have reached the limited threshold when it reaches the overcurrent protection point; after circuit startup, the output current sampling signal Vcs is determined to have reached the limited threshold when it reaches a preset reference value, at which point the output current sampling signal Vcs reaches its maximum value; the limited threshold values ​​for the two phases are different and can be set as needed), the main switch is driven to turn off. After the main switch is turned off for a set duration, the clamping transistor is turned on; when the clamping transistor's on-time reaches the duration adjusted by the adaptive zero-voltage turn-on control module 11, the clamping transistor is turned off. In practical use, the clamping transistor and the main switch can be switched on and off according to different strategies combined with the feedback signals of the active clamp converter.

[0078] like Figure 4 As shown, in another implementation of the present invention, the driving circuit 1 further includes an oscillator 14, which provides a working clock for the driving circuit 1 (including a clock of at least one frequency, and clocks of different frequencies can meet the needs of different circuits). The uses of the working clock include, but are not limited to, counting, adjusting the conduction time of the clamping transistor, and adjusting the first duration. All clock signals required in the driving circuit 1 can be provided by the oscillator 14, which will not be described in detail here.

[0079] like Figure 5 As shown, the present invention also provides an active clamp converter, the active clamp converter comprising:

[0080] Drive circuit 1 and active clamping conversion circuit 2.

[0081] like Figure 5 As shown, the driving circuit 1 obtains feedback signals from the active clamping conversion circuit and generates driving signals for the clamping transistor and the main switching transistor based on the feedback signals.

[0082] Specifically, the feedback signals include, but are not limited to, the current sampling signal Vcs of the main switch transistor, the zero-voltage detection signal ZVS, and the zero-current detection signal ZCD. Any feedback signal that can be used to control the clamping transistor and the main switch transistor is applicable to this invention, and will not be described in detail here. The structure and principle of the drive circuit 1 are described above.

[0083] like Figure 5 As shown, the active clamping conversion circuit 2 converts the input voltage Vin into the output voltage Vo based on the control of the driving circuit 1.

[0084] Specifically, in this embodiment, the active clamping converter circuit 2 adopts a flyback topology and includes a voltage input module 21, a clamping transistor Nc, a main switching transistor N0, and a leakage inductance L. K Transformer T, clamping resistor R1, clamping capacitor C RD The system includes a sampling resistor Rs, an output module 22, and a zero-current detection module 23. As an example, the clamping transistor Nc and the main switching transistor N0 are GaN semiconductor power devices. The voltage input module 21 converts the AC voltage AC into a DC input voltage Vin. As an example, the voltage input module 21 includes a rectifier bridge and an input capacitor Ci; one end of the input capacitor Ci is connected to the output terminal of the rectifier bridge, and the other end is grounded. The leakage inductance L... K One end is connected to the output terminal of the voltage input module 21, and the other end is connected to the first terminal of the primary inductance of the transformer T. The second terminal of the primary inductance of the transformer T is grounded via the main switch N0 and the sampling resistor Rs. The clamping resistor R1 and the clamping capacitor C RD One end of the parallel connection is connected to the output terminal of the voltage input module 21, and the other end is connected to the second terminal of the primary inductance of the transformer T via the clamping transistor Nc. The output module 22 is connected to the secondary inductance of the transformer T to generate the output voltage Vo; as an example, the output module 22 includes a diode Do, an output capacitor Co, and a load R. L The anode of diode Do is connected to the first terminal of the secondary inductance of transformer T, and the cathode is connected to the second terminal (grounded) of the secondary inductance of transformer T via the output capacitor Co; the load R L The zero-current detection module 23 is connected in parallel across the output capacitor Co. The zero-current detection module 23 achieves zero-current detection through an auxiliary inductor, obtaining a zero-current detection signal ZCD. As an example, the zero-current detection module 23 includes a transformer auxiliary winding, voltage divider resistors R2 and R3. One end of the transformer auxiliary winding is grounded, and the other end is grounded sequentially through voltage divider resistors R2 and R3. The zero-current detection signal ZCD is output between voltage divider resistors R2 and R3.

[0085] It should be noted that the active clamp converter 2 is not limited to the structure listed in this embodiment; any active clamp circuit structure is applicable, including but not limited to forward and flyback structures. Furthermore, the active clamp converter of this invention can achieve zero-voltage conduction control without additional components, has a simple structure, and a wide range of applications.

[0086] This invention introduces dynamic dead-time adjustment control technology. After the clamping transistor turns off at the pre-turn-off time, the system turns on the main switch when it detects a zero-voltage signal, ensuring zero-voltage conduction of the main power transistor. The zero-voltage turn-on control module starts working after the clamping transistor turns off, calculates the dead time from the clamping transistor turning off to the primary power transistor turning on, and samples the time from the clamping transistor turning off to the time when the system detects the complete release of the transformer secondary inductor current. By comparing the two times, the dead time between the clamping transistor and the main switch in the next cycle is dynamically adjusted, thereby realizing adaptive zero-voltage turn-on control of the main switch.

[0087] In summary, this invention provides a zero-voltage turn-on control module, a drive circuit, and an active clamp converter, including: a timing unit, a duration acquisition unit, a comparison unit, and a dead-time adjustment unit; the timing unit is connected to the output terminal of the dead-time adjustment unit and times a first duration provided by the dead-time adjustment unit, the first duration being a preset dead-time duration between the clamping transistor being turned off and the main switching transistor being turned on in the active clamp converter; the duration acquisition unit acquires the duration from the clamping transistor being turned off to the complete release of the transformer secondary inductor current in the active clamp converter to obtain a second duration; the comparison unit is connected to the output terminal of the dead-time adjustment unit, and the first duration is a preset dead-time duration between the clamping transistor being turned off and the main switching transistor being turned on in the active clamp converter; the duration acquisition unit acquires the duration from the clamping transistor being turned off to the complete release of the transformer secondary inductor current in the active clamp converter to obtain a second duration; the comparison unit is connected to the output terminal of the active clamp converter, and the second duration is a preset dead-time duration between the clamping transistor being turned off and the main switching transistor being turned on in the active clamp converter; the second duration is a preset dead-time duration between the clamping transistor being turned off and the main switching transistor being turned on in the active clamp converter, and the first duration is a preset dead-time duration between the clamping transistor being turned off and the main switching transistor being turned on in the active clamp converter, and the second ... The output terminals of the timing unit and the duration acquisition unit compare the first duration with the second duration. The dead time adjustment unit is connected to the output terminal of the comparison unit and adjusts the conduction time of the clamping transistor and the first duration in the next cycle based on the comparison result of the current cycle, thereby realizing adaptive zero-voltage turn-on control. When the first duration is greater than the second duration, the conduction time of the clamping transistor is reduced by a preset duration; when the first duration is less than the second duration, the conduction time of the clamping transistor is increased by a preset duration; when the first duration is equal to the second duration, the conduction time of the clamping transistor remains unchanged. The zero-voltage turn-on control module, drive circuit, and active clamp converter of the present invention use digital circuits to adaptively adjust the dead time between the clamping transistor and the main switching transistor, which has high accuracy and safety, and can realize zero-voltage turn-on control across the entire load range. The main switching transistor has low loss and high system efficiency. In addition, the circuit structure of the zero-voltage turn-on control module of the present invention is simple, which can effectively reduce the chip area occupied and reduce costs. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0088] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An adaptive zero-voltage turn-on control module, applied to an active clamp converter, characterized in that, The adaptive zero-voltage turn-on control module includes at least: Timing unit, duration acquisition unit, comparison unit, and dead time adjustment unit; The timing unit is connected to the output terminal of the dead time adjustment unit and times the first duration provided by the dead time adjustment unit. The first duration is the preset dead time between the clamping transistor being turned off and the main switch being turned on in the active clamping converter. The duration acquisition unit acquires the duration from the turn-off of the clamping transistor in the active clamping converter to the complete release of the transformer secondary inductor current, and obtains the second duration. The comparison unit is connected to the output of the timing unit and the duration acquisition unit, and compares the first duration with the second duration. The dead time adjustment unit is connected to the output of the comparison unit. Based on the comparison result of the current cycle, it adjusts the on-time of the clamping transistor and the first duration for the next cycle, thereby realizing adaptive zero-voltage turn-on control. When the first duration is greater than the second duration, the on-time of the clamping transistor is reduced by a preset duration. When the first duration is less than the second duration, the on-time of the clamping transistor is increased by a preset duration. When the first duration is equal to the second duration, the on-time of the clamping transistor remains unchanged.

2. The adaptive zero-voltage turn-on control module according to claim 1, characterized in that: The timing unit includes a timer that starts timing from when the clamping tube is turned off and outputs a timing end signal when the timing reaches the first duration.

3. The adaptive zero-voltage turn-on control module according to claim 1, characterized in that: The duration acquisition unit includes a controller, a frequency divider, and a counter; The controller receives the drive signal and zero current detection signal of the clamping transistor. When the clamping transistor is turned off, a timing start signal is triggered, and when the zero current detection signal is valid, a timing end signal is triggered. The frequency divider is connected to the output of the controller and receives the working clock. When the timing start signal is valid, it sequentially performs a 2-step process on the working clock. i The frequency is divided by a factor to obtain the counting clock; where i = 1, 2...n, and n is the number of bits in the output signal of the duration acquisition unit, set to a natural number greater than 2; The counter is connected to the output of the controller and the frequency divider. When the timing start signal is valid, timing starts based on the counting clock. When the timing end signal is valid, timing stops.

4. The adaptive zero-voltage turn-on control module according to claim 3, characterized in that: The controller is implemented using an RS flip-flop. The set terminal of the RS flip-flop is connected to the drive signal of the clamping transistor, and the reset terminal is connected to the zero current detection signal. It outputs control signals for starting and ending the timing.

5. The adaptive zero-voltage turn-on control module according to claim 3, characterized in that: The frequency divider includes n cascaded D flip-flops, with the data input terminal of each D flip-flop connected to the inverting output terminal, and the non-inverting output terminal outputting the frequency-divided signal. The clock input of the first-stage D flip-flop is connected to the working clock, and the clock input of the subsequent-stage D flip-flop is connected to the inverted output of the preceding-stage D flip-flop. The asynchronous reset terminal of the first-stage D flip-flop is connected to the output terminal of the controller, and the asynchronous reset terminals of the second to nth-stage D flip-flops are connected to the inverted signal of the zero-current detection signal.

6. The adaptive zero-voltage turn-on control module according to claim 3, characterized in that: The counter comprises n cascaded D flip-flops. The asynchronous reset terminal of each D flip-flop is connected to the delayed output signal of the controller. The clock terminal of the i-th D flip-flop is connected to 2... i A multiplier-based counting clock; the data input of the first-stage D flip-flop is connected to a preset voltage, and the data input of the subsequent D flip-flop is connected to the positive output of the preceding D flip-flop; The timing results are output at the inverted output terminals of each D flip-flop.

7. The adaptive zero-voltage turn-on control module according to claim 3, characterized in that: The comparison unit includes n comparison sub-units, and each comparison sub-unit includes an XOR gate, a first NAND gate, a second NAND gate and a third NAND gate; The input terminals of the XOR gate are respectively connected to the output signal of the timing unit and the corresponding bit output signal of the counter. The input terminals of the first NAND gate are respectively connected to the corresponding bit output signal of the counter and the output signal of the XOR gate, and output a first comparison result. The input terminals of the second NAND gate are respectively connected to the output signal of the timing unit and the output signal of the XOR gate, and output a second comparison result. The input terminals of the third NAND gate are respectively connected to the output signal of the timing unit and the corresponding bit output signal of the counter, and output a third comparison result.

8. The adaptive zero-voltage turn-on control module according to claim 7, characterized in that: The dead time adjustment unit includes a time adjustment subunit and n control subunits; Each control subunit is connected to the output terminal of each comparison subunit. Each control subunit includes a first enable transistor, a second enable transistor, a third enable transistor, a first transistor, a second transistor, and a third transistor. One end of each enable transistor is connected to a preset voltage, and the other end is connected to the control terminal of the corresponding transistor. When the enable signal is invalid, each enable transistor is turned on to control the transistor to turn off. One end of the first transistor is connected to the preset voltage, and the other end generates a control signal to reduce the conduction time of the clamping transistor. The control terminal is connected to the corresponding first comparison result. One end of the second transistor is connected to the preset voltage, and the other end generates a control signal to increase the conduction time of the clamping transistor. The control terminal is connected to the corresponding second comparison result. One end of the third transistor is connected to the preset voltage, and the other end generates a control signal to maintain the conduction time of the clamping transistor. The control terminal is connected to the corresponding third comparison result. The time adjustment subunit is connected to the output terminal of each control subunit and receives the working clock. Based on the control signals output by each control subunit, the working clock is used to generate a counting time, thereby adjusting the conduction time of the clamping transistor.

9. A driving circuit, characterized in that, The driving circuit includes at least: The logic control module, the power-on reset module, and the adaptive zero-voltage turn-on control module as described in any one of claims 1-8; The adaptive zero-voltage turn-on control module generates and adjusts the dead time between the turn-off of the clamping transistor and the turn-on of the main switch transistor in the next cycle based on the drive signal and zero-current detection signal of the clamping transistor. The power-on reset module is used to reset the logic control module when the active clamp converter is powered on; The logic control module is connected to the output terminals of the adaptive zero-voltage turn-on control module and the power-on reset module, and receives the zero-voltage detection signal and output current sampling signal of the active clamp converter, which are used to generate drive signals for the clamping transistor and the main switching transistor.

10. The driving circuit according to claim 9, characterized in that: The driving circuit also includes an oscillator that provides a working clock for the driving circuit.

11. An active clamp converter, characterized in that, The active clamp converter includes at least: An active clamping conversion circuit and a driving circuit as described in claim 9 or 10; The driving circuit obtains feedback signals from the active clamping conversion circuit and generates driving signals for the clamping transistor and the main switching transistor based on the feedback signals. The active clamping converter circuit converts the input voltage into the output voltage based on the control of the driving circuit.

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