Phase-shift discontinuous pulse width modulation method, three-phase converter and vehicle-mounted charger

Abstract

The invention discloses a phase shift discontinuous pulse width modulation method, a three-phase converter and a vehicle-mounted charger, and the phase shift discontinuous pulse width modulation method comprises the steps: dividing the alternating current period of the three-phase converter into a plurality of clamping intervals, each clamping interval at least comprises one switching period, and carrying out the clamping control of a phase bridge arm in any switching period, performing non-clamping control on the other two phases of bridge arms, and enabling the driving signals of the bridge arms in the two non-clamping phases to have a phase shifting ratio delta D; according to the amplitude Vm of the input voltage and the output voltage Vo which are obtained through detection and conversion, the optimal value range of the phase shift ratio delta D of the phase shift discontinuous pulse width modulation method is obtained through calculation, the optimal phase shift ratio delta D can be kept in any modulation degree and any sector, and the optimal phase shift modulation effect, namely the lowest common-mode voltage and common-mode current, is achieved; meanwhile, a modulation method matching mode between the intervals is reasonably set, and alternating current side inductive current distortion during interval switching is remarkably eliminated.

Description

Technical Field

[0001] The invention relates to the technical field of discontinuous pulse width modulation, in particular to a phase-shifted discontinuous pulse width modulation method, a three-phase converter and a vehicle-mounted charger. Background Art

[0002] AC / DC converters and DC / AC converters are key interface circuits that connect direct current networks with alternating current networks. In recent years, industry and academia have conducted in-depth research on these two types of converters, with efficiency and cost optimization becoming the main research directions.

[0003] In the prior art, the topology of three-phase AC / DC and DC / AC converters is as follows: Figure 1 As shown. In order to reduce energy loss and improve system efficiency, a discontinuous pulse width modulation (DPWM) strategy is usually adopted. However, this modulation method will generate a large common-mode voltage between the midpoint M of the DC side capacitor and the neutral point N of the AC side filter capacitor. This requires the addition of an isolation circuit between the DC side and the AC side sampling circuit to ensure the safe and stable operation of the hardware circuit. The additional cost brought by the isolation circuit undoubtedly limits the application of DPWM modulation technology in AC / DC converters and DC / AC converters.

[0004] Due to the current trend of high frequency and high power density of power electronic converters, processes such as metal casings and multi-layer PCB structures are commonly used in power electronic products. The journal article "Analysis and Improvement of the Effect of Distributed Parasitic Capacitance on High-Frequency High-Density Three-Phase Buck Rectifier" points out that these processes often lead to common-mode interference between the DC side and the AC side in three-phase AC / DC and DC / AC converters, which seriously affects the quality of the input current. In order to solve this problem, a common-mode filter is usually introduced, which includes common-mode filter capacitors (Cp, Cn) and common-mode suppression units (CMSU), such as Figure 2 However, when the traditional discontinuous pulse width modulation (DPWM) strategy is adopted, a significant common-mode voltage VMN will be generated between the midpoint M of the DC side capacitor and the neutral point N of the AC side filter capacitor. This common-mode voltage will generate a common-mode current in the common-mode suppression unit, forming a circulating current, thereby increasing system losses. Therefore, the DPWM modulation method must be improved to reduce the common-mode voltage and optimize the overall performance of the system.

[0005] Patent document "202410577519.X" provides a phase-shifted discontinuous pulse width modulation method and a three-phase converter. The patent points out that in the above background, by maintaining a certain phase shift ratio ΔΦ between the non-clamped phase bridge arm drive signals, the common-mode voltage v can be significantly reduced. MN , thereby simplifying the sampling circuit design, optimizing the cost, and suppressing the impact of common mode interference in three-phase AC / DC converters and DC / AC converters on the input current quality and EMC and EMI characteristics. However, the modulation method mentioned in the patent is only applicable when the sum of the non-clamped phase bridge arm drive signals satisfies a duty cycle of less than 100%, that is, as mentioned in the patent: at any time, the upper bridge arm switch devices of each phase bridge arm in the three-phase bridge arm are not turned on or off at the same time; when the modulation index m of the converter is low, the modulation method mentioned in the patent document is no longer applicable, so this method has certain modulation index limitations. Summary of the invention

[0006] In view of the problems existing in the prior art, the present invention proposes a phase-shift discontinuous pulse width modulation method and a three-phase converter.

[0007] The technical solution of the present invention is to design a phase-shift discontinuous pulse width modulation method, including: dividing the AC cycle of the three-phase converter into a plurality of clamping intervals, each of the clamping intervals includes at least one switching cycle, clamping control is performed on one phase bridge arm in any switching cycle, and non-clamping control is performed on the other two phase bridge arms, and a shift phase ΔD is made between the driving signals of the bridge arms in the two non-clamping phases; detecting the input voltage amplitude V of the three-phase converter m and output voltage V o , according to the input voltage amplitude V m and the output voltage V o Calculate the optimal range of the shift ratio ΔD.

[0008] Furthermore, the amplitude V of the input voltage detected m and output voltage V o The specific range of the calculated displacement ratio ΔD includes:

[0009] exist In this case, the optimal value range of the shift ratio ΔD should satisfy the following formula: 1 / 2-ΔD x / 2<ΔD<1 / 2+ΔD x / 2, where ΔD x There are two cases: When the clamp phase is clamped to 1, ΔD x =1-D1-D2, D1, D2 are the duty ratios of the upper equivalent switch drive signals of the two non-clamped phase bridge arms; when the clamped phase is clamped to 0, ΔD x =D1+D2-1;

[0010] exist In this case, the optimal value range of the shift ratio ΔD should satisfy the following formula: 1 / 2-ΔD y / 2<ΔD<1 / 2+ΔD y / 2, where ΔD y There are two cases: When the clamp phase is clamped to 0, ΔD y =1-D1-D2, D1, D2 are the duty ratios of the upper equivalent switch drive signals of the two non-clamped phase bridge arms; when the clamped phase is clamped to 1, ΔD y =D1+D2-1.

[0011] Furthermore, the value of the shift ratio ΔD is 0.5.

[0012] Furthermore, the phase-shifted discontinuous pulse width modulation method further includes: smoothly alternating between the first modulation method PSDPWM_1 and the second modulation method PSDPWM_2 in each clamping interval to eliminate the AC side inductor current distortion when the clamping interval is switched.

[0013] Furthermore, the first modulation method PSDPWM_1 is: the switch device of one phase bridge arm in the three-phase converter is kept on or turned off, and the middle time of the high level of the driving signal of the upper bridge arm switch device of the bridge arm with a larger phase voltage in the other two phase bridge arms is D1T s The middle time of the high level of the driving signal of the upper bridge arm switch device of the bridge arm with smaller phase voltage is D2T s , and the shift ratio ΔD=D2-D1>0; the second modulation method PSDPWM_2 is: the switch device of one phase bridge arm in the three-phase converter is kept on or turned off, and the high level middle time of the driving signal of the upper bridge arm switch device of the bridge arm with smaller phase voltage in the other two phase bridge arms is D1T s The middle time of the high level of the driving signal of the upper bridge arm switch device of the bridge arm with a larger phase voltage is D2T s , and the phase shift is ΔD=D2-D1>0; D2 and D1 are both phases, T s is the switching period, and the shift ratio ΔD is the difference between D2 and D1.

[0014] Furthermore, the phase-shifted discontinuous pulse width modulation method further includes: the switching moment between any two adjacent clamping intervals is the start moment or the end moment of the switching cycle of the driving signal.

[0015] Furthermore, the phase-shift discontinuous pulse width modulation method further includes: when the phase modulation signal of any phase bridge arm in the three phases is not clamped, the high level intermediate moment remains unchanged; when each phase modulation signal enters or exits its clamping interval, and when it is in the clamping interval, the high level intermediate moment position of the driving signal is changed;

[0016] When the AC cycle of the three-phase converter is divided into 6 clamping intervals, the switching moments of the 6 clamping intervals are t1, t2, t3, t4, t5, and t6 in sequence; the A-phase drive signal of the three-phase converter updates the high-level intermediate moment position at moments t1, t3, t4, and t6, the B-phase drive signal can update the high-level intermediate moment position at moments t2, t3, t5, and t6, and the C-phase drive signal can update the high-level intermediate moment position at moments t1, t2, t4, and t5;

[0017] When the AC cycle of the three-phase converter is divided into 12 clamping intervals, the switching times of the 12 clamping intervals are t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, t13, t14, t15, t16, t17, t18, t19, t2 10 ,t 11 The A phase drive signal of the three-phase converter is at t0, t1, t5, t6, t7, t 11 The high level intermediate time position is updated at all times, and the B phase drive signal is at t3, t4, t5, t9, t 10 ,t 11 The high level middle moment position is updated at all times, and the C-phase drive signal updates the high level middle moment position at t1, t2, t3, t7, t8, and t9.

[0018] Furthermore, the phase-shifted discontinuous pulse width modulation method further includes: in the interval where the modulation signal of any phase is in the rising stage and the modulation signal is in the falling stage, the high level intermediate moment position of the driving signal corresponding to the modulation signal is different.

[0019] The present invention also designs a three-phase converter, which includes: an A-phase bridge arm, a B-phase bridge arm, and a C-phase bridge arm. The control strategy for the A-phase bridge arm, the B-phase bridge arm, and the C-phase bridge arm adopts the phase-shifted discontinuous pulse width modulation method described in any one of the above items.

[0020] The present invention also provides a vehicle-mounted charger, which includes the above-mentioned three-phase converter.

[0021] Compared with the prior art, the present invention has at least the following beneficial effects:

[0022] The present invention detects and converts the input voltage amplitude V m and output voltage V oThe optimal value range of the phase shift ratio ΔD of the phase-shift discontinuous pulse width modulation method is calculated, and the optimal phase shift modulation effect, that is, the lowest common-mode voltage and common-mode current, is achieved; at the same time, the modulation method coordination mode between intervals is reasonably set, the complexity of phase shift modulation is simplified, and the AC side inductor current distortion when the interval is switched under the conditions of 6 interval division and 12 interval division is significantly eliminated. At the same time, a special phase shift ratio ΔD=0.5 is given. With this phase shift ratio, the optimal phase shift ratio ΔD can be maintained in any modulation index and in any sector, simplifying the phase shift modulation. The complexity of the control is reduced, and the shift phase is 0.5, which is also convenient for implementation using carrier interleaving; the common-mode voltage between the midpoint of the DC side capacitor and the neutral point of the AC side capacitor can be significantly reduced, and the common-mode current in the common-mode suppression unit can also be significantly reduced; due to the reduction of common-mode voltage and common-mode current, the common-mode filter can be conveniently applied to AC / DC converters and DC / AC converters, and the proposed modulation method improves the input current quality; due to the reduction of common-mode voltage, the sampling circuit does not require an additional isolation circuit to ensure the safe and stable operation of the controller, which simplifies the design of the sampling circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0024] Figure 1 It is a schematic diagram of the circuit topology of a three-phase converter;

[0025] Figure 2 It is a schematic diagram of the circuit topology of a three-phase converter with a CM suppression circuit;

[0026] Figure 3(a) to Figure 3(f) Schematic diagram of six existing DPWM modulation methods;

[0027] Figure 4 Schematic diagram of the 6-interval division method of the PSDPWM_1 modulation method of the present invention;

[0028] Figure 5 It is a schematic diagram of the topological structure of a three-phase VSR converter;

[0029] Figure 6(a), Figure 6(b) and Figure 6(c) are PWM timing and voltage v of DPWM1, PSDPWM_1 and PSDPWM_2 modulation methods in time interval X1 MN Compare the schematic diagrams;

[0030] Figure 6(d), Figure 6(e) and Figure 6(f) are PWM timing and voltage v of DPWM1, PSDPWM_1 and PSDPWM_2 modulation methods in the time interval X2 MN Compare the schematic diagrams;

[0031] Figure 7(a), Figure 7(b) and Figure 7(c) are PWM timing and voltage v of DPWM1, PSDPWM_1 and PSDPWM_2 modulation methods in time interval X1 MN Compare the schematic diagrams;

[0032] Figure 7(d), Figure 7(e) and Figure 7(f) are PWM timing and voltage v of DPWM1, PSDPWM_1 and PSDPWM_2 modulation methods in time interval X2 MN Compare the schematic diagrams;

[0033] Figure 8(a) and Figure 8(b) are PWM timing and voltage v of PSDPWM_1 and PSDPWM_2 modulation methods in time interval X1 MN Compare the schematic diagrams;

[0034] Figure 8(c) and Figure 8(d) are PWM timing and voltage v of PSDPWM_1 and PSDPWM_2 modulation methods in the time interval X2 MN Compare the schematic diagrams;

[0035] Figure 9(a) and Figure 9(b) show PWM timing and voltage v of PSDPWM_1 and PSDPWM_2 modulation methods in time interval X1 MN Compare the schematic diagrams;

[0036] Figure 9(c) and Figure 9(d) show PWM timing and voltage v of PSDPWM_1 and PSDPWM_2 modulation methods in the time interval X2 MN Compare the schematic diagrams;

[0037] Fig.10 It is the PWM timing diagram of the PSDPWM_SS1 modulation method in the X1 interval to the X3 interval;

[0038] Fig.11 It is the PWM timing diagram of the PSDPWM_SS2 modulation method in the X1 interval to the X3 interval;

[0039] FIG. 12( a ) and FIG. 12( b ) are simulation results of the 6-interval PSDPWM_1 and PSDPWM_SS1 modulation methods when the intervals are updated within the switching cycle;

[0040] Fig.13 The simulation results of the 6-interval PSDPWM_1 and PSDPWM_SS1 modulation methods when the intervals are updated at the beginning or end of the switching cycle;

[0041] Fig.14 It is a schematic diagram of the interval division method 12 of the DPWM1 modulation method of the present invention;

[0042] Fig.15 It is the PWM timing of the PSDPWM_TS1 modulation method in the interval S1 to S6;

[0043] Fig.16 It is the PWM timing of the PSDPWM_TS2 modulation method in the interval S1 to S6;

[0044] Figure 17(a) and Figure 17(b) are simulation results of the 12-interval PSDPWM_1 and PSDPWM_TS1 modulation methods when the intervals are updated within the switching cycle;

[0045] Fig.18 The simulation results of the 12-interval PSDPWM_1 modulation method when the interval is updated at the start of the switching cycle;

[0046] Fig.19 This is the overall control logic of the present invention. DETAILED DESCRIPTION

[0047] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0048] Thus, a feature indicated in this specification will be used to illustrate one of the features of an embodiment of the present invention, rather than implying that each embodiment of the present invention must have the described feature. In addition, it should be noted that this specification describes many features. Although some features can be combined together to illustrate possible system designs, these features can also be used in other combinations that are not explicitly described. Thus, unless otherwise stated, the described combinations are not intended to be limiting.

[0049] The principle and structure of the present invention are described in detail below with reference to the accompanying drawings and embodiments.

[0050] In the prior art, the three-phase converter topology can be simplified as Figure 1When the existing DPWM modulation method is used, there is a large common-mode voltage between the midpoint M of the DC side capacitor and the neutral point N of the AC side filter capacitor, which requires the use of an isolation circuit to isolate the DC side sampling circuit from the AC side sampling circuit to ensure safe and stable operation of the hardware circuit. The additional cost brought by the isolation circuit undoubtedly limits the application of DPWM modulation technology in three-phase converters.

[0051] The present invention proposes a phase-shift discontinuous pulse width modulation method. The control logic of this strategy is shown in Fig.19 First, the AC cycle is divided into multiple clamping intervals, the modulation calculation method is run, the discontinuous pulse width modulation method is generated, and the optimal value range of the phase shift ratio ΔD is calculated at the same time. The first modulation method PSDPWM_1 and the second modulation method PSDPWM_2 are smoothly used alternately in each clamping interval to perform modulation coordination between sectors, and finally form a complete phase-shifted discontinuous pulse width modulation method PSDPWM. The present invention reduces the voltage at both ends of the common-mode suppression unit and the current flowing through by controlling the phase shift ratio ΔD, and gives the optimal range of the phase shift ratio ΔD. Within this optimal range, the absolute value of the common-mode voltage at both ends of the common-mode suppression unit is the smallest, and the corresponding common-mode current is also the smallest. At the same time, a special phase shift ratio (ΔD=0.5) is given, which can maintain the optimal phase shift in any modulation index and in any sector, simplifying the complexity of phase shift modulation. The phase shift ratio of 0.5 is also convenient for realization by carrier interleaving. Thereby, the purpose of optimizing the efficiency of the three-phase converter is achieved on the basis of simplifying the sampling circuit design and optimizing the cost. The common mode suppression unit may be composed of components such as capacitors, inductors, resistors, etc., and may even be a wire.

[0052] in, Figure 3(a) to Figure 3(f) Six existing DPWM modulation methods are given as examples, and the improved method of the phase-shifted discontinuous pulse width modulation method proposed in the present invention is not limited to these six exemplified DPWMs. In the following, taking the DPWM1 modulation method in FIG3 (a) as an example, the specific implementation measures and theoretical derivation of the improved modulation method are described in detail.

[0053] Specifically, the present invention provides a phase-shifted discontinuous pulse width modulation method, comprising:

[0054] The AC cycle of the three-phase converter is divided into a plurality of clamping intervals, each of which includes at least one switching cycle. In any switching cycle, one phase bridge arm is clamped and the other two phase bridge arms are non-clamped, and a phase shift ΔD exists between the driving signals of the bridge arms in the two non-clamped phases. The input voltage amplitude V of the three-phase converter is detected. m and output voltage V o , according to the input voltage amplitude V m and the output voltage Vo Calculate the optimal range of shift ratio ΔD.

[0055] Here, the three-phase converter mentioned in this article is a three-phase AC / DC converter or a three-phase DC / AC converter, both of which can be applicable to the design concept of the present invention.

[0056] Furthermore, the amplitude V of the input voltage detected m and output voltage V o The specific range of the calculated displacement ratio ΔD includes:

[0057] exist In this case, when the modulation signal of one phase bridge arm is clamped to the interval of the carrier peak, the driving signal phases of the equivalent switches on the two non-clamped phases are staggered by 180 degrees. The optimal value range of the phase shift ratio ΔD should satisfy the following formula: 1 / 2-ΔD x / 2<ΔD<1 / 2+ΔD x / 2, that is, the formula T s / 2-ΔD x T s / 2<ΔDT s <T s / 2+ΔD x T s / 2, where T s is the switching period, ΔD x T s It is the interval when the upper equivalent switch drive signals of the two phase bridge arms in the two non-clamped phases are both low or high in the current state. ΔD x There are two cases: When the clamp phase is clamped to 1, ΔD x =1-D1-D2, D1 and D2 are the duty ratios of the upper equivalent switch drive signals of the two non-clamped phase bridge arms; when the clamped phase is clamped to 0, ΔD x =D1+D2-1.

[0058] exist In this case, when the modulation signal of one phase bridge arm is clamped to the interval of the carrier valley value, the driving signal phases of the equivalent switches on the two non-clamped phases are staggered by 180 degrees. The optimal value range of the phase shift ratio ΔD should satisfy the following formula: 1 / 2-ΔD y / 2<ΔD<1 / 2+ΔD y / 2, that is, the formula T s / 2-ΔD y T s / 2<ΔDT s <T s / 2+ΔD y T s / 2, where T s is the switching period, ΔDy T s It is the interval when the upper equivalent switch drive signals of the two phase bridge arms in the two non-clamped phases are both high or low in the current state. ΔD y There are two cases: When the clamp phase is clamped to 0, ΔD y =1-D1-D2, D1 and D2 are the duty ratios of the upper equivalent switch drive signals of the two non-clamped phase bridge arms; when the clamped phase is clamped to 1, ΔD y =D1+D2-1.

[0059] In a preferred embodiment, the shift ratio ΔD is set to 0.5.

[0060] Furthermore, the phase-shifted discontinuous pulse width modulation method further includes: smoothly alternating between the first modulation method PSDPWM_1 and the second modulation method PSDPWM_2 in each clamping interval to eliminate the AC side inductor current distortion when the clamping interval is switched.

[0061] Furthermore, the first modulation method PSDPWM_1 is: the switch device of one phase bridge arm in the three-phase converter is kept on or turned off, and the middle time of the high level of the driving signal of the upper bridge arm switch device of the bridge arm with a larger phase voltage in the other two phase bridge arms is D1T s The middle time of the high level of the driving signal of the upper bridge arm switch device of the bridge arm with smaller phase voltage is D2T s , and the shift ratio ΔD=D2-D1>0.

[0062] Furthermore, the second modulation method PSDPWM_2 is as follows: the switch device of one phase bridge arm in the three-phase converter is kept on or turned off, and the high level middle time of the drive signal of the upper bridge arm switch device of the bridge arm with smaller phase voltage in the other two phase bridge arms is D1T s The middle time of the high level of the driving signal of the upper bridge arm switch device of the bridge arm with a larger phase voltage is D2T s , and the phase shift is ΔD=D2-D1>0; D2 and D1 are both phases, T s is the switching period, and the shift ratio ΔD is the difference between D2 and D1.

[0063] See also Fig.19The overall control logic of the present invention is that when the three-phase converter is running, the AC cycle is divided into 3N clamping intervals, each of which includes at least one switching cycle, and one phase bridge arm is clamped in any switching cycle, and the modulation signal of the bridge arm is clamped to the carrier peak or carrier valley; the other two phase bridge arms are non-clamped, and the drive signals of the two phase bridge arms are shifted by ΔD; N is a positive integer. The first modulation method PSDPWM_1 and the second modulation method PSDPWM_2 are smoothly and alternately applied in each clamping interval.

[0064] like Figure 4 As shown in the figure, in the existing literature, a variety of clamping implementation methods of the DPWM1 modulation method have been given, mainly including: a clamping method based on sector division, a clamping method based on zero-sequence component injection, etc. The so-called clamping means that the switch tube of a certain phase bridge arm does not operate, and the modulation signal of this phase is clamped to the carrier peak value or carrier valley value.

[0065] The principle is explained by taking the clamping method of zero-sequence component injection as an example. The initial three-phase sinusoidal modulation wave m a 、m b 、m c The expression is:

[0066]

[0067] Where m (0≤m≤0.5) is the modulation index, α=ωt, ω is the angular frequency on the AC side, and t is time.

[0068] When the carrier is unipolar, the three-phase bridge arm modulation wave D a0 , D b0 , D c0 The expression is:

[0069]

[0070] Zero sequence component D z The expression is:

[0071]

[0072] Where D max D a0 , D b0 , D c0 The maximum value in D min D a0 , D b0 , D c0 The minimum value in .

[0073] The zero sequence component D zBy injecting it into the initial three-phase modulation wave, the modulation signal waveform of DPWM1 can be obtained. The calculation expression of the modulation signal is shown in formula (4). Figure 4 A schematic diagram of the DPWM1 modulation signal is given.

[0074] The final three-phase sinusoidal modulation wave expression is:

[0075]

[0076] With three-phase VSR rectifier (such as Figure 5 As shown in the figure, for the common mode voltage v of DPWM1 MN Conduct theoretical deduction.

[0077] To simplify the analysis, the unipolar binary logic switching function s of the three-phase VSR rectifier is defined as x for:

[0078]

[0079] Among them, "1" represents that the upper tube is turned on and the lower tube is turned off, and "0" represents that the upper tube is turned off and the lower tube is turned on. According to Kirchhoff's voltage law, the three-phase VSR voltage loop equation is established as:

[0080]

[0081] where v xE =s x V o (x=A, B, C).

[0082] Consider a three-phase symmetrical system,

[0083] v A +v B +v C =0,i A +i B +i C =0 (7)

[0084] Combining formulas (5), (6) and (7), we can obtain

[0085]

[0086] v ME is the capacitance C n The voltage across the two ends is generally considered

[0087] Taking the X1 interval as an example, in this interval the zero sequence component D z 1-D a0 , then the final sinusoidal modulation wave expression is:

[0088]

[0089] Therefore, in the X1 interval, D b +D c The expression is:

[0090] D b +D c =D b0 +1-D a0 +D c0 +1-D a0 =2-2m a +m b +m c (10)

[0091] Since the three-phase modulation wave is symmetrical, we have

[0092] m a +m b +m c =0 (11)

[0093] Substituting equation (11) into equation (10), we can obtain

[0094] D b +D c =2-3m a (12)

[0095] Let D b +D c =1, we get 3m a =1,m a =1 / 3.

[0096] In the X1 interval, at time t6, m a To obtain the minimum value, we can get D from formula (12): b +D c Get the maximum value. The corresponding ωt = π / 3 ± 2kπ at time t6, k = 0, 1, 2, 3... Therefore, from formula (1), we can get

[0097] For three-phase VSR rectifiers there are:

[0098] mV o =V m (12)

[0099] Where V m is the amplitude of the input voltage, V o is the output voltage.

[0100] Will Substituting into formula (12), we can get: In summary, in the X1 interval, when When Db +D c >1.

[0101] In the X2 interval, the zero sequence component D z -D c0 , then the final sinusoidal modulation wave expression is:

[0102]

[0103] Therefore, in the X2 interval, D a +D b The expression is:

[0104] D a +D b =D a0 -D c0 +D b0 -D c0 =m a +m b -2m c (14)

[0105] Substituting formula (11) into formula (14), we can obtain:

[0106] D a +D b =-3m c (15)

[0107] Let D a +D b =1 gives -3m a =1,m c =-1 / 3.

[0108] In the X2 interval, at time t1, m c To obtain the minimum value, we can get D from formula (15): a +D b Get the maximum value. The corresponding ωt at time t1 is 2π / 3±2kπ, k=0, 1, 2, 3… Therefore, from formula (1), we can get Will Substituting into formula (12), we can get:

[0109] In summary, in the X2 interval, when When D a +D b <1.

[0110] Therefore, for When one phase modulation signal is clamped to the carrier peak value, the sum of the duty cycles of the upper equivalent switch drive signals of the other two phase bridge arms is greater than 1; when one phase modulation signal is clamped to the carrier valley value, the sum of the duty cycles of the upper equivalent switch drive signals of the other two phase bridge arms is less than 1.

[0111] by Figure 4 Take the interval between X1 and X2 as an example, when The PWM timing diagrams of DPWM1 and the proposed PSDPWM modulation method are shown in Figure 7. Figures 7(a) and (d) show the PWM timing diagrams of the DPWM1 modulation method in the X1 and X2 intervals, respectively. In one switching cycle, the equivalent upper and lower switches of the A-phase bridge arm do not operate, and the high-level intermediate moments of the equivalent upper switch drive signals of the B-phase and C-phase bridge arms are both D m T s , usually D m =0.5. Figure 7(b) and Figure 7(c) respectively show the PWM timing diagrams of the two PSDPWM modulation methods in the X1 interval. As shown in Figure 7(b), within a switching cycle, the PWM timing of the PSDPWM_1 modulation method is: the equivalent upper and lower switches (S1 and S4) of the A-phase bridge arm do not act, and the high-level intermediate moment of the driving signal of the equivalent upper switch (S3) of the B-phase bridge arm is D1T s The middle time of the high level of the equivalent upper switch (S5) driving signal of the C-phase bridge arm is D2T s As shown in Figure 7(c), within a switching cycle, the PWM timing of the PSDPWM_2 modulation method is: the equivalent upper and lower switches of the A-phase bridge arm do not operate, and the high-level intermediate time of the equivalent upper switch driving signal of the C-phase bridge arm is D1T s The high level middle moment of the equivalent upper switch driving signal of the B phase bridge arm is D2T s , define ΔD = D2-D1>0. The PWM timing diagrams of the two PSDPWM modulation methods (PSDPWM_1 and PSDPWM_2) in the X2 interval are shown in Figures 7(e) and 7(f).

[0112] Similarly, when When the PWM timing diagram of DPWM1 and the proposed PSDPWM modulation method is shown in Figure 6, Figure 6 (a) and (d) respectively show the PWM timing diagram of the DPWM1 modulation method in the X1 and X2 intervals, and Figure 6 (b) and Figure 6 (c) respectively show the PWM timing diagrams of the two PSDPWM modulation methods in the X1 interval. The PWM timing diagrams of the two PSDPWM modulation methods (PSDPWM_1 and PSDPWM_2) in the X2 interval are shown in Figure 6 (e) and Figure 6 (f).

[0113] The equivalent upper and lower switch drive signals of the A, B, and C phase bridge arms are complementary. It is worth noting that there should be a certain dead time between the high levels of the upper and lower equivalent switch signals of the same phase to avoid the upper and lower equivalent switch devices being turned on at the same time during the turn-on and turn-off delay time of the switch devices, causing a capacitor short circuit fault.

[0114] In summary, at any time, the upper equivalent switch drive signal of the modulation wave clamp phase is always high or low. The equivalent switch drive signal of the remaining two phases: The PSDPWM_1 modulation method is defined as the high-level middle moment of the equivalent upper switch drive signal of the phase bridge arm with the larger phase voltage is D1T s The middle moment of the high level of the equivalent upper switch driving signal of the phase bridge arm with a smaller phase voltage is D2T s , and ΔD=D2-D1>0. Otherwise, it is PSDPWM_2 modulation method.

[0115] Similar to the patent document "202410577519.X", compared with the DPWM1 modulation method, the common mode voltage v of the PSDPWM_1 and PSDPWM_2 modulation methods is MN Figure 6 shows the voltage v of the DPWM1 and the proposed PSDPWM modulation method within a switching cycle. MN Schematic diagram. It is worth noting that the proposed PSDPWM modulation method voltage v MN The schematic diagrams are shown in Figure 6(b), (c), (e) and (f). MN The maximum voltage is ±V o / 6. Figure 7 shows the voltage v of DPWM1 and the proposed PSDPWM modulation method within a switching cycle. MN Schematic diagram of the proposed PSDPWM modulation method voltage v MN The schematic diagrams are shown in Figure 7(b), (c), (e) and (f). MN The maximum voltage is ±V o / 2, but v MN = ±V o / 2 time period is significantly reduced.

[0116] In a preferred embodiment, the phase-shifted discontinuous pulse width modulation method further includes: detecting the amplitude V of the input voltage of the three-phase converter m and output voltage V o , according to the detected input voltage amplitude V m and output voltage V o Calculate the range of the displacement ratio ΔD:

[0117] exist In this case, the value of the shift ratio ΔD should satisfy the following formula: 1 / 2-ΔD x / 2<ΔD<1 / 2+ΔD x / 2, that is, the formula T s / 2-ΔD x T s / 2<ΔDT s <T s / 2+ΔD x T s / 2, where T s is the switching period, ΔD x There are two cases: When the clamp phase is clamped to 1, ΔD x =1-D1-D2, D1 and D2 are the duty ratios of the upper equivalent switch drive signals of the two non-clamped phase bridge arms; when the clamped phase is clamped to 0, ΔD x =D1+D2-1.

[0118] exist In this case, the value of the shift ratio ΔD should satisfy the following formula: 1 / 2-ΔD y / 2<ΔD<1 / 2+ΔD y / 2, that is, the formula T s / 2-ΔD y T s / 2<ΔDT s <T s / 2+ΔD y T s / 2, where T s is the switching period, ΔD y There are two cases: When the clamp phase is clamped to 0, ΔD y =1-D1-D2, D1 and D2 are the duty ratios of the upper equivalent switch drive signals of the two non-clamped phase bridge arms; when the clamped phase is clamped to 1, ΔD y =D1+D2-1.

[0119] The following analysis shows how to achieve the optimal phase shift range of ΔD:

[0120] In one switching cycle, v MN The absolute value of the voltage volt-second product is used as the criterion, and the present invention provides and Optimal range of shift comparison in both cases.

[0121] In this case, when one phase modulation signal is clamped to the carrier peak, the other two non-clamped phase modulation signals are interleaved T s / 2, at this time, the interval in which the upper equivalent switch drive signals of the two-phase bridge arm are both low is ΔD x T s , ΔD xThe size is 1 and the difference between the duty cycle and the duty cycle of the upper equivalent switch drive signal of the two-phase bridge arm. When ΔD satisfies T s / 2-ΔD x T s / 2<ΔDT s <T s / 2+ΔD x T s / 2 when voltage v MN When one phase modulation signal is clamped to the carrier valley value, the other two non-clamped phase modulation signals are interleaved T s / 2, at this time, the interval in which the upper equivalent switch drive signals of the two-phase bridge arm are both high is ΔD x T s , ΔD x The size is the difference between the duty cycle of the upper equivalent switch drive signal of the two-phase bridge arm and 1. When ΔD satisfies T s / 2-ΔD x T s / 2<ΔDT s <T s / 2+ΔD x T s / 2 when voltage v MN The absolute value of the volt-second product is the smallest.

[0122] Take the X1 interval and X2 interval as examples to illustrate the optimal phase shift range. When D b +D c <1, voltage v MN The optimal condition should be met when the minimum is reached: the A phase modulation signal in the X1 interval is clamped to the carrier peak value, and the other B phase and C phase modulation signals are staggered T s / 2, as shown in Figure 8(a) and (b), the interval in which the upper equivalent switch drive signals of the two-phase bridge arms are both low is ΔD x T s (ΔD x =1-D b -D c >0), when ΔD satisfies T s / 2-ΔD x T s / 2<ΔDT s <T s / 2+ΔD x T s / 2 when voltage v MN The absolute value of the volt-second product is the smallest; in the X2 interval, the C phase modulation signal is clamped to the carrier valley value, and the A phase and B phase modulation signals are interleaved T s / 2, as shown in Figure 8(c) and (d), at this time, the interval in which the upper equivalent switch drive signals of the other two phase bridge arms are both high is ΔDx T s (ΔD x =1-D a –D b >0), when ΔD satisfies T s / 2-ΔD x T s / 2<ΔDT s <T s / 2+ΔD x T s / 2 when voltage v MN The absolute value of the volt-second product is the smallest.

[0123] When one phase modulation signal is clamped to the carrier peak, the other two phase modulation signals are interleaved T s / 2, at this time, the upper equivalent switch drive signals of the other two phase bridge arms are both high level in the interval ΔD y T s , ΔD y The size is the difference between the sum of the duty cycles of the upper equivalent switch drive signals of the other two phase bridge arms and 1. When ΔD satisfies T s / 2-ΔD y T s / 2<ΔDT s <T s / 2+ΔD y T s / 2 when voltage v MN When one phase modulation signal is clamped to the carrier valley value, the other two phase modulation signals are staggered T s / 2, at this time, the upper equivalent switch drive signals of the other two phase bridge arms are both low level in the interval ΔD y T s , ΔD y The size is the difference between the sum of the duty cycles of the upper equivalent switch drive signals of the other two phase bridge arms and 1. When ΔD satisfies T s / 2-ΔD y T s / 2<ΔDT s <T s / 2+ΔD y T s / 2 when voltage v MN Minimum.

[0124] Take the X1 interval and X2 interval as examples to illustrate the optimal phase shift range. When D b +D c >1, voltage v MNThe optimal condition should be met when the minimum is reached: the A phase modulation signal in the X1 interval is clamped to the carrier peak value, and the other B phase and C phase modulation signals are staggered T s / 2, as shown in Figure 9 (a) and (b), at this time, the interval in which the upper equivalent switch drive signals of the two-phase bridge arms are both high is ΔD y T s (ΔD y =D b +D c -1>0), when ΔD satisfies T s / 2-ΔD y T s / 2<ΔD <T s / 2+ΔD y T s / 2 when voltage v MN Minimum; in the X2 interval, the C phase modulation signal is clamped to the carrier valley value, and the A phase and B phase modulation signals are interleaved T s / 2, as shown in Figure 9(c) and (d), at this time, the interval in which the upper equivalent switch drive signals of the other two phase bridge arms are both low is ΔD y T s (ΔD y =D a +D b -1>0), when ΔD satisfies T s / 2-ΔD y T s / 2<ΔDT s <T s / 2+ΔD y T s / 2 when voltage v MN Minimum.

[0125] In a preferred embodiment, the shift ratio ΔD is set to 0.5. In any interval, still When the phase shift ratio ΔD of the upper equivalent switch drive signal of the two non-clamped phases is 0.5, it must be within the optimal phase shift range; in addition, the phase shift ratio of 0.5 can be conveniently realized by staggered carriers, which is convenient for engineering applications. Therefore, the phase shift ratio ΔD of 0.5 is a special phase shift ratio given by the present invention, which has the characteristics of being simple and easy to apply.

[0126] Furthermore, the phase-shifted discontinuous pulse width modulation method further includes: the switching moment between any two adjacent clamping intervals is the start moment or the end moment of the switching cycle of the driving signal.

[0127] Furthermore, the phase-shifted discontinuous pulse width modulation method further includes: when the switch drive signals of the three-phase bridge arms are in their respective non-clamping intervals, the intermediate moments of the high level of the drive signals remain unchanged; when the respective phase modulation signals enter or exit their clamping intervals, and when they are in the clamping intervals, the intermediate moments of the high level of the drive signals are changed;

[0128] When the AC cycle of the three-phase converter is divided into 6 clamping intervals, the switching moments of the 6 clamping intervals are t1, t2, t3, t4, t5, and t6 in sequence; the A-phase drive signal of the three-phase converter updates the high-level intermediate moment position at moments t1, t3, t4, and t6, the B-phase drive signal can update the high-level intermediate moment position at moments t2, t3, t5, and t6, and the C-phase drive signal can update the high-level intermediate moment position at moments t1, t2, t4, and t5;

[0129] The modulation improvement method under the condition of 6 interval division of the present invention is as follows Figure 4 As shown in the figure, the DPWM1 modulation method divides an input cycle into 6 clamping intervals (X1 to X6). According to the above improvement method, DPWM1 can be improved to PSDPWM modulation method. However, in order to reduce the inductor current distortion on the AC side, the modulation methods of adjacent intervals need to be coordinated to a certain extent.

[0130] Modulation method improvement method 1: The three-phase bridge arm switch driving signal remains unchanged at the high level middle moment in the corresponding specific interval (in the clamping interval or the non-clamping interval).

[0131] Only when the modulation wave enters or exits the clamping interval, the high level intermediate moment position of the phase drive signal is changed, that is, the A phase drive signal can update the high level intermediate moment position at t1, t3, t4, and t6, the B phase drive signal can update the high level intermediate moment position at t2, t3, t5, and t6, and the C phase drive signal can update the high level intermediate moment position at t1, t2, t4, and t5. In addition, in order to ensure the realization of PSDWPM, the high level intermediate moment position of the drive signal in the interval where the rising phase and the falling phase of the modulation wave of any phase are located should be different, that is, the high level intermediate moment position of the A phase drive signal in interval 2 and interval 3 should be different from that in interval 5 and interval 6, the high level intermediate moment position of the B phase drive signal in interval 1 and interval 2 should be different from that in interval 4 and interval 5, and the high level intermediate moment position of the C phase drive signal in interval 3 and interval 4 should be different from that in interval 1 and interval 6. If the high level intermediate moment of the drive signal in the rising phase interval is D1T s , then the middle moment of the high level in the descending phase is D2T s ;vice versa.

[0132] Based on the above ideas, it is obvious that there are multiple 6-interval-based overall modulation methods (hereinafter referred to as PSDPWM_SS modulation methods) within an input cycle. Two of the PSDPWM_SS modulation methods (PSDPWM_SS1 and PSDPWM_SS2) are given as examples below. Fig.10 (PWM timing diagram of PSDPWM_SS1 modulation method in the X1 interval to X3 interval) and Fig.11 (PWM timing diagram of PSDPWM_SS2 modulation method in the X1 interval to the X3 interval) as shown.

[0133] The PWM timings of the PSDPWM_SS1 modulation method in the X1 interval to the X3 interval are as follows: Fig.10 As shown; the PWM timing in the remaining intervals can be deduced by yourself according to the modulation improvement idea mentioned above, and the specific PWM timing diagram is not given here.

[0134] The PWM timings of the PSDPWM_SS2 modulation method in the X1 interval to the X3 interval are as follows: Fig.11 As shown; the PWM timing in the remaining intervals can be deduced by yourself according to the modulation improvement idea mentioned above, and the specific PWM timing diagram is not given here.

[0135] Figure 12(a) and Figure 12(b) show the simulation results of the PSDPWM_1 and PSDPWM_SS1 modulation methods in six intervals. As can be seen from Figure 12, the PSDPWM_SS1 modulation method does not change v MN and i MN On this basis, the AC side inductor current distortion during interval switching is eliminated.

[0136] Modulation method improvement method 2: When switching between intervals, it should be done at the end or beginning of the switching cycle.

[0137] The reason for the AC side inductor current distortion: the AC side inductor voltage is abnormal, resulting in an imbalance in the volt-second product of the AC side inductor in a short period of time, and the inductor current changes in one direction, resulting in distortion. Take the update from interval 1 to interval 2 as an example, Fig.13 The simulation results of the AC side inductor voltage and current are given when the interval is updated at the beginning or end of the switching cycle.

[0138] As shown in Figure 12(a), when the A-phase inductor voltage switches in the interval, there is an abnormality, which causes the volt-second product to be greater than 0 in a short period of time, and the inductor current increases rapidly, resulting in distortion. Fig.13 It can be seen that the A-phase inductor voltage also has abnormalities when switching between intervals, but the change in the volt-second product is significantly smaller than that in Figure 12(a), so the inductor current distortion is not obvious.

[0139] The modulation improvement method under the condition of 12 interval division of the present invention is as follows Fig.14 As shown in the figure: when the AC cycle of the three-phase converter is divided into 12 clamping intervals, the switching moments of the 12 clamping intervals are t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, t13, t14, t15, t16, t17, t18, t19, t20, t21, t22, t23, t24, t25, t26, t27, t28, t29, t30, t31, t32, t33, t34, t35, t36, t37, t38, t39, t40, t41, t42, t43, t44, 10 ,t 11 The A phase drive signal of the three-phase converter is at t0, t1, t5, t6, t7, t 11 The high level intermediate time position is updated at all times, and the B phase drive signal is at t3, t4, t5, t9, t 10 ,t 11 The high level middle moment position is updated at all times, and the C-phase drive signal updates the high level middle moment position at t1, t2, t3, t7, t8, and t9.

[0140] Modulation method improvement method 1: The three-phase bridge arm switch driving signal remains unchanged at the middle moment of the high level in the corresponding specific interval.

[0141] The idea of ​​solving the AC side inductor current distortion at the interval switching point in the 12 interval is similar to that in the 6 interval. The difference is that in addition to changing the high level middle moment position of the phase drive signal when the modulation wave enters or exits the clamping interval, the high level middle moment position of the phase drive signal can also be changed when switching from the clamping interval to the clamping interval. That is: the A phase drive signal can be Fig.10 t0, t1, t5, t6, t7, t 11 The high level intermediate time position is updated at all times. The B phase drive signal can be at t3, t4, t5, t9, t 10 ,t 11 The high-level intermediate moment position is updated at all times, and the C-phase drive signal can update the high-level intermediate moment position at t1, t2, t3, t7, t8, and t9. In addition, the idea of ​​the improvement measures in interval 6 is consistent with that: in order to ensure the realization of PSDWPM, the high-level intermediate moment position of the drive signal in the interval where the rising stage of the modulation wave of any phase and the falling stage of the modulation wave are located should be different, please refer to the above for details.

[0142] Taking phase A as an example, if phase A is driven at t1, t5, t7, t 11 When the A-phase drive is updated at t0 or t6, the 12-interval modulation method improvement measures are equivalent to the 6-interval improvement measures, which will not be repeated here; if the A-phase drive is updated at t0 or t6, there are two modulation methods in the 12-interval (hereinafter referred to as PSDPWM_TS1 and PSDPWM_TS2 modulation methods) that can eliminate the AC side inductor current interval switching point distortion.

[0143] The PWM timings of the PSDPWM_TS1 modulation method in the S1 to S6 intervals are as follows: Fig.15 As shown; the PWM timing in the remaining intervals can be deduced by yourself according to the modulation improvement idea mentioned above, and the specific PWM timing diagram is not given here.

[0144] The PWM timings of the PSDPWM_TS2 modulation method in the S1 to S6 intervals are as follows: Fig.16 As shown; the PWM timing in the remaining intervals can be deduced by yourself according to the modulation improvement idea mentioned above, and the specific PWM timing diagram is not given here.

[0145] Figure 17(a) and Figure 17(b) show the simulation results of the PSDPWM_1 and PSDPWM_TS1 modulation methods in 12 intervals respectively. As can be seen from Figure 17, the PSDPWM_SS1 modulation method does not change v MN and i MN On this basis, the AC side inductor current distortion during interval switching is eliminated.

[0146] Modulation method improvement method 2: When switching between intervals, it should be done at the end or beginning of the switching cycle, that is:

[0147] Both the 12-interval and 6-interval division methods can be used to switch between intervals at the end or beginning of the switching cycle to eliminate the distortion of the AC side inductor current sector switching point. When updating from interval 2 to interval 3, the inductor L a For example, the voltage Fig.18 The simulation results of the AC side inductor voltage and current when the interval is updated at the beginning of the switching cycle are given.

[0148] As shown in Figure 17(a), when the A-phase inductor voltage switches in the interval, there is an abnormality, which causes the volt-second product to be greater than 0 in a short period of time, and the inductor current increases rapidly, resulting in distortion. Fig.18 It can be seen that the A-phase inductor voltage also has abnormalities when switching between intervals, but the change in the volt-second product is smaller than that in Figure 17(a), so the inductor current distortion is not obvious.

[0149] Furthermore, the phase-shifted discontinuous pulse width modulation method further includes: in the interval where the modulation signal of any phase is in the rising stage and the modulation signal is in the falling stage, the high level intermediate moment position of the driving signal corresponding to the modulation signal is different.

[0150] Among them, in the above control logic, the driving signals of the upper arm switch device and the lower arm switch device of any phase bridge arm in the three-phase converter are complementary, and a dead time is set when the upper arm switch device and the lower arm switch device of the same bridge arm switch state.

[0151] It is used to avoid the situation where the upper and lower equivalent switching devices are turned on at the same time during the turn-on and turn-off delay time of the switching device, causing a capacitor short circuit fault.

[0152] The present invention also discloses a three-phase converter, which includes: an A-phase bridge arm, a B-phase bridge arm, and a C-phase bridge arm. The control strategy for the A-phase bridge arm, the B-phase bridge arm, and the C-phase bridge arm adopts the above-mentioned phase-shifted discontinuous pulse width modulation method.

[0153] The invention also discloses a vehicle-mounted charger, which comprises the above-mentioned three-phase converter.

[0154] Compared with the prior art, the present invention has at least the following beneficial effects:

[0155] The present invention is applicable to AC / DC converters and DC / AC converters. Within a switching cycle, the modulation method changes the PWM timing on the basis of the existing DPWM modulation, and adds a phase shift between the equivalent switch drive signals of the two non-clamped phases; within the AC cycle, two improvement measures are adopted: the two modulation methods are used alternately between adjacent intervals, and the intervals are updated at the beginning and end of the switching cycle, which significantly eliminates the AC side inductor current distortion when the intervals are switched under the conditions of 6-interval division and 12-interval division. In addition, the optimal range of the phase shift ratio for the proposed modulation method is given, and it is demonstrated that within the optimal range, the absolute value volt-second product of the common-mode voltage is the smallest. At the same time, a special phase shift ratio (ΔD=0.5) is given, which can maintain the optimal phase shift under any modulation degree and in any sector, simplifying the complexity of the phase shift modulation. The phase shift ratio of 0.5 is also convenient for implementation using carrier interleaving. The proposed new phase-shifted discontinuous pulse width modulation method retains the advantages of patent document "202410577519.X", which can significantly reduce the common-mode voltage between the midpoint of the DC side capacitor and the neutral point of the AC side capacitor; when a common-mode filter is applied in the converter, the proposed modulation method can also significantly reduce the common-mode current in the common-mode suppression unit; due to the reduction of common-mode voltage and common-mode current, the common-mode filter can be conveniently applied to AC / DC converters and DC / AC converters, and the proposed modulation method improves the input current quality; due to the reduction of common-mode voltage, the sampling circuit does not require an additional isolation circuit to ensure the safe and stable operation of the controller, which simplifies the design of the sampling circuit.

[0156] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A phase-shift discontinuous pulse width modulation method, characterized in that: include: The AC cycle of the three-phase converter is divided into a plurality of clamping intervals, each of which includes at least one switching cycle, and one phase bridge arm is clamped and the other two phase bridge arms are non-clamped in any switching cycle, and a phase shift ΔD exists between the driving signals of the bridge arms in the two non-clamped phases; Detect the input voltage amplitude V of the three-phase converter m and output voltage V o , according to the input voltage amplitude V m and the output voltage V o Calculate the optimal range of shift ratio ΔD.

2. The phase-shifted discontinuous pulse width modulation method according to claim 1, characterized in that: The amplitude V of the input voltage m and the output voltage V o The optimal value range of calculating the shift ratio ΔD specifically includes: exist In this case, the optimal value range of the shift ratio ΔD should satisfy the following formula: 1 / 2-ΔD x / 2<ΔD<1 / 2+ΔD x / 2, where ΔD x There are two cases: When the clamp phase is clamped to 1, ΔD x =1-D1-D2, D1, D2 are the duty ratios of the upper equivalent switch drive signals of the two non-clamped phase bridge arms; when the clamped phase is clamped to 0, ΔD x =D1+D2-1; exist In this case, the optimal value range of the shift ratio ΔD should satisfy the following formula: 1 / 2-ΔD y / 2<ΔD<1 / 2+ΔD y / 2, where ΔD y There are two cases: When the clamp phase is clamped to 0, ΔD y =1-D1-D2, D1, D2 are the duty ratios of the upper equivalent switch drive signals of the two non-clamped phase bridge arms; when the clamped phase is clamped to 1, ΔD y =D1+D2-1.

3. The phase-shifted discontinuous pulse width modulation method according to claim 2, characterized in that: The value of the shift ratio ΔD is 0.

5.

4. The phase-shifted discontinuous pulse width modulation method according to claim 2, characterized in that: The phase-shifted discontinuous pulse width modulation method further includes: smoothly alternating between the first modulation method PSDPWM_1 and the second modulation method PSDPWM_2 in each clamping interval to eliminate the AC side inductor current distortion when the clamping interval is switched.

5. The phase-shifted discontinuous pulse width modulation method according to claim 4, characterized in that: The first modulation method PSDPWM_1 is: the switch device of one phase bridge arm in the three-phase converter is kept on or turned off, and the middle time of the high level of the driving signal of the upper bridge arm switch device of the bridge arm with a larger phase voltage in the other two phase bridge arms is D1T s The middle time of the high level of the driving signal of the upper bridge arm switch device of the bridge arm with smaller phase voltage is D2T s , and the shift ratio is ΔD=D2-D1>0; The second modulation method PSDPWM_2 is: the switch device of one phase bridge arm in the three-phase converter is kept on or turned off, and the middle time of the high level of the drive signal of the upper bridge arm switch device of the bridge arm with smaller phase voltage in the other two phase bridge arms is D1T s The middle time of the high level of the driving signal of the upper bridge arm switch device of the bridge arm with a larger phase voltage is D2T s , and the shift ratio is ΔD=D2-D1>0; The D2 and D1 are both in phase, T s is the switching period, and the shift ratio ΔD is the difference between D2 and D1.

6. The phase-shifted discontinuous pulse width modulation method according to claim 5, characterized in that: The phase-shifted discontinuous pulse width modulation method further includes: the switching time between any two adjacent clamping intervals is the starting time or the ending time of the switching cycle of the driving signal.

7. The phase-shifted discontinuous pulse width modulation method according to claim 6, characterized in that: The phase-shift discontinuous pulse width modulation method further comprises: when the switch drive signal of the three-phase bridge arm is in the non-clamping interval of each phase, the high level intermediate moment of the drive signal remains unchanged; when the modulation signal of each phase enters or exits its clamping interval, and when it is in the clamping interval, the high level intermediate moment position of the drive signal is changed; When the AC cycle of the three-phase converter is divided into 6 clamping intervals, the switching moments of the 6 clamping intervals are t1, t2, t3, t4, t5, and t6 in sequence; the A-phase drive signal of the three-phase converter updates the high-level intermediate moment position at moments t1, t3, t4, and t6, the B-phase drive signal can update the high-level intermediate moment position at moments t2, t3, t5, and t6, and the C-phase drive signal can update the high-level intermediate moment position at moments t1, t2, t4, and t5; When the AC cycle of the three-phase converter is divided into 12 clamping intervals, the switching times of the 12 clamping intervals are t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, t13, t14, t15, t16, t17, t18, t19, t2 10 ,t 11 The A phase drive signal of the three-phase converter is at t0, t1, t5, t6, t7, t 11 The high level intermediate time position is updated at all times, and the B phase drive signal is at t3, t4, t5, t9, t 10 ,t 11 The high level middle moment position is updated at all times, and the C-phase drive signal updates the high level middle moment position at t1, t2, t3, t7, t8, and t9.

8. The phase-shifted discontinuous pulse width modulation method according to claim 7, characterized in that: In the interval where the arbitrary phase modulation signal is in the rising stage and the modulation signal is in the falling stage, the high level intermediate moment position of the driving signal corresponding to the modulation signal is different.

9. A three-phase converter, characterized in that: include: A phase bridge arm, B phase bridge arm, and C phase bridge arm, the control strategy for the A phase bridge arm, B phase bridge arm, and C phase bridge arm adopts the phase shift discontinuous pulse width modulation method as described in any one of claims 1 to 8.

10. A vehicle charger, characterized in that: Comprising the three-phase converter as claimed in claim 9.

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