Working mode switching circuit of direct-current converter

Abstract

A working mode switching circuit of a direct current converter is a control circuit which is used in a direct current converter chip and can rapidly detect output current and flexibly adjust mode switching points, and belongs to the technical field of analog integrated circuits. The circuit comprises a phase discriminator, an adjustable capacitor array and a phase inverter chain. On the basis of accurately detecting and sampling the output current of the BUCK chip, the mode switching point can be freely adjusted only by changing the capacitance value of the adjustable capacitor array, so that the mode switching from single-path output to double-path output is realized. According to the invention, the complexity of the circuit is reduced, the precision of mode switching is improved, and stable and efficient work of the BUCK chip within a total current output range is realized.

Description

Technical Field

[0001] The present invention is a control circuit used in a direct current converter chip, which can quickly detect output current and flexibly adjust a mode switching point, and belongs to the technical field of analog integrated circuits. Background Art

[0002] BUCK type DC converter has the advantages of high efficiency, low energy consumption, stable output, strong driving ability, etc., and is currently widely used in consumer electronics, communication and network equipment, industrial automation and control systems, new energy vehicles, medical equipment and other fields. In the future, BUCK type DC converter will continue to develop towards stronger driving ability and higher efficiency. When the DC converter outputs large current, if a single output is used, it will bring many problems: on the one hand, the power tube, inductor and other components inside the chip will be subjected to considerable current stress, which may cause the life of the components to be shortened or even directly damaged; on the other hand, when a single output current is large, the conduction loss of the DC converter will be greatly increased, which will bring a series of problems such as chip heating and reduced efficiency. In order to solve the above problems, multi-channel parallel technology can be used to share the current stress, that is, when the DC converter outputs a large current, it automatically switches to a multi-channel output mode, reduces the loss by reducing the current of each channel, and improves the DC converter's ability to withstand current.

[0003] In practical applications, due to the influence of the chip PVT characteristics, the mode switching point of the current detection circuit should not be fixed, but should be flexibly adjusted according to the actual situation to find the most efficient switching strategy. The existing mode switching method usually uses a comparator to detect the overcurrent of the BUCK chip output current and output a mode switching signal. The user can only adjust the mode switching point by changing the reference voltage at the input end of the comparator. However, this method is difficult to operate, mainly for two reasons: first, the user needs to design a variety of reference voltages for the mode switching circuit, which will greatly increase the complexity of the circuit; second, the mode switching point often only needs to be adjusted within a very small range, which places high demands on the accuracy of the reference voltage. In response to this practical need, the present invention proposes a novel mode switching circuit, which only requires a simple adjustable capacitor array to adjust the BUCK chip mode switching point and achieve efficient output in the full range. It is worth noting that the above switching strategy is based on the accurate detection of the output current. Therefore, the present invention also provides a current detection circuit that matches the mode switching circuit. Summary of the invention

[0004] In view of practical application requirements, the present invention proposes a mode switching circuit with flexible adjustable switching points. Based on accurate detection of output current, the circuit can adjust the mode switching point according to user requirements to achieve efficient operation of the BUCK chip.

[0005] The present invention adopts the following technical solutions. The first aspect of the present invention provides an output current detection circuit of a BUCK chip, such as Figure 1 As shown, it includes: an operational amplifier, a source follower, a switch NMOS tube, an inductor current sampling resistor, and a PMOS current mirror.

[0006] The inductor L0 and the capacitor Cout are both external components of the BUCK chip. S1 and S2 are chip switches. The BUCK chip driver module Driver is connected to the gate terminals of the switches S1 and S2. The drain terminal of the upper switch S2 is connected to the input voltage VIN of the BUCK chip, and the source terminal is connected to the drain terminal of the lower switch S1. The source terminal of the lower switch S1 is grounded. The gate terminal of the BUCK chip switch NMOS tube NM1 is connected to the gate terminal of the lower switch S1 of the BUCK chip, the drain terminal is connected to the current output terminal LX of the BUCK circuit, and the source terminal is connected to the The lower end of the sampling resistor Rsense is connected; the positive input end of the operational amplifier A1 is grounded, the output end is connected to the gate end of the source follower NM2, and the negative input end is connected to the source end of the source follower and the upper end of the sampling resistor Rsense; the drain end of the source follower NM2 is connected to the drain end of the first PMOS tube PM1, the source end of the first PMOS tube is connected to the internal power supply voltage VDD of the chip, the drain end is short-circuited with the gate end, and the gate end of the first PMOS tube is connected to the gate end of the second PMOS tube PM2 of the mode switching circuit as the output port Vsense.

[0007] The second aspect of the present invention provides a mode switching circuit of a BUCK chip, which is connected to the output current detection circuit through a port Vsense. Figure 2 As shown, it includes: phase detector, current mirror, inverter, switch NMOS tube, adjustable capacitor array, etc. The VIP terminal of the phase detector is connected to the waveform output terminal Wave_1 of the detection signal circuit, and the VIN terminal is connected to the waveform output terminal Wave_2 of the reference signal circuit. By comparing the phase of the detection signal waveform and the reference signal waveform, the mode switching signal is output to control the working mode of the BUCK chip.

[0008] The detection signal circuit includes: a second PMOS transistor PM2, an inverter chain INV_1, an adjustable capacitor array Cap_bank_1, and a switch NMOS transistor NM3. The gate end of the second PMOS transistor PM2 is connected to the gate end of the first PMOS transistor of the current detection circuit, the source end of PM2 is connected to the internal power supply of the chip, and the drain end is connected to the input end of the inverter chain INV_1; the input end of INV_1 is connected to the A end of the adjustable capacitor array Cap_bank_1, and the output end is connected to the positive input end VIP of the phase detector; the B end of the adjustable capacitor array Cap_bank_1 is grounded, and the A end is connected to the drain end of the switch NMOS transistor NM3; the source end of the switch NMOS transistor NM3 is grounded, and the drain end is connected to the control signal CLK_RST_B, and CLK_RST_B is the inverted signal of the external reset signal CLK_RST.

[0009] The reference signal circuit includes: a third PMOS transistor PM3, a fourth PMOS transistor PM4, an inverter chain INV_2, an adjustable capacitor array Cap_bank_2, and a switch NMOS transistor NM4. The source terminal of the third PMOS transistor is connected to the internal power supply of the chip, the drain terminal is short-circuited with the gate terminal and connected to the chip reference current Iref, and the gate terminal is short-circuited with the gate terminal of the fourth PMOS transistor PM4; the source terminal of PM4 is connected to the internal power supply of the chip, and the drain terminal is connected to the input terminal of the inverter chain INV_2; the input terminal of INV_2 is connected to the A terminal of the adjustable capacitor array Cap_bank_2, and the output terminal is connected to the negative input terminal VIN of the phase detector; the B terminal of the adjustable capacitor array Cap_bank_2 is grounded, and the A terminal is connected to the drain terminal of the switch NMOS transistor NM4; the source terminal of the switch NMOS transistor NM4 is grounded, and the drain terminal is connected to the control signal CLK_RST_B.

[0010] The adjustable capacitor array is as follows Figure 3 As shown, it includes capacitors and switch NMOS tubes. The drain terminals of the switch NMOS tubes NM5, NM6, and NM7 are connected to the lower plates of C1, C2, and C3 respectively, and the gate terminals are connected to the switch control signal CADD respectively. <1> 、CADD <2> 、CADD <3> The upper plate of the fixed capacitor C0 is connected to the upper plates of C1, C2, and C3 and connected to the A port of the adjustable capacitor array, and the lower plate is connected to the source end of the switch NMOS tubes NM5, NM6, and NM7 and grounded.

[0011] The phase detector used in the mode switching circuit is as follows: Figure 4As shown, it includes: a fifth PMOS tube PM5, a sixth PMOS tube PM6, a seventh PMOS tube PM7, an eighth PMOS tube PM8, a ninth PMOS tube PM9, an eighth NMOS tube NM8, a ninth NMOS tube NM9, a tenth NMOS tube NM10, an eleventh NMOS tube NM11 and an inverter INV_3. Among them, the source terminals of PM6, PM7, PM8 and PM9 are connected to the internal power supply of the chip, the gate terminals of PM6 and PM9 are connected to the external reset signal CLK_RST, and the drain terminals are connected to the drain terminals of PM7 and PM8 respectively; the gate terminal of PM7 is connected to the drain terminal of PM8, and the gate terminal of PM8 is connected to the drain terminal of PM7; the gate terminal of PM5 is connected to the CLK_RST signal, the drain terminal is connected to the gate terminal of NM10, and the source terminal is connected to the gate terminal of NM11; the drain terminal of NM10 is connected to the drain terminals of PM6 and PM7, and the source terminal is connected to the drain terminal of NM8. The drain end of NM11 is connected to the drain ends of PM8 and PM9, and thus connected to the input end of the inverter INV_3. The output end of INV_3 is the phase detector output end Mode_change, which is used to output the mode switching signal; the gate end of NM9 is the positive input end VIP of the phase detector, which is connected to the waveform output end Wave_1 of the detection signal circuit. The gate end of NM8 is the negative input end VIN of the phase detector, which is connected to the waveform output end Wave_2 of the reference signal circuit. The source ends of NM8 and NM9 are grounded.

[0012] The user can adjust the capacitance by controlling the on and off of the adjustable capacitor array switch NMOS tube, change the speed of capacitor charging, thereby adjusting the phase of the square wave received by the phase detector and changing the mode switching point of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is the output current detection circuit of the present invention.

[0014] Figure 2 This is the mode switching circuit of the present invention.

[0015] Figure 3 This is the adjustable capacitor array circuit of the present invention.

[0016] Figure 4 This is the phase detector circuit of the present invention.

[0017] Figure 5 It is a signal timing diagram of the present invention. DETAILED DESCRIPTION

[0018] In order to make the purpose and technical advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and examples. The implementation described in this application is only a part of the embodiments of the present invention, not all embodiments.

[0019] like Figure 1 The current detection circuit used in the present invention is shown. When the BUCK chip is working, the switch tubes S1 and S2 are turned on alternately, the sampling switch NMOS1 and the switch tube S1 are controlled by the same drive signal, and when the switch tube S1 is turned on, the sampling switch NMOS1 is also turned on, and the current detection circuit samples the output current of the BUCK chip. At this time, since the current flows from the source end of the switch tube S1 to the drain end, and the source end is grounded, the node LX is a negative voltage V LX , V LX It can be expressed as:

[0020] V LX =-I OUT ×R ONS1 (1)

[0021] Among them I OUT is the chip output current, R ONS1 is the on-resistance of switch tube S1.

[0022] The detection circuit is mainly composed of operational amplifier A1 and source follower NM0S2. Operational amplifier A1 can adopt a folded common source and common gate structure to provide high DC gain. Since it has only one circuit and only produces one main pole, it has high stability. The output terminal V0 of source follower NM0S2 is connected to the inverting terminal INN of operational amplifier A1, and the inverting terminal INP of operational amplifier A1 is grounded. Due to the high gain of A1, the output terminal VO of source follower is zero potential. When switch tube S1 and sampling switch NMOS1 are turned on, current Isense flows from node V0 through sampling resistor Rsense and sampling switch tube NMOS1 to node LX. Current Isense can be expressed as:

[0023]

[0024] Where R sense is the sampling resistor, R ONNM1 is the on-resistance of the sampling switch tube NMOS1. ONNM1 Compared with the sampling resistor R sense It is usually small, so users can ignore its impact based on actual conditions.

[0025] like Figure 2 The figure shows the mode switching circuit proposed by the present invention, wherein the second PMOS transistor PM2 and the first PMOS transistor PM1 of the current detection circuit form a sampling PMOS current mirror, which replicates the sampling current Isense in a 1:1 ratio. The third PMOS transistor PM3 and the fourth PMOS transistor PM4 form a reference PMOS current mirror, which replicates the reference current Iref in a 1:1 ratio. The reference current Iref can be designed by the user according to actual needs, and the mode switching point can also be changed by adjusting the reference current Iref.

[0026] When a sampling cycle starts, the CLK_RST_B signal turns off the charging switch tubes NMOS3 and NMOS4, and the current mirror copies the current Icharge_1 to charge the adjustable capacitor array Cap_bank_1 to obtain the charging voltage Vcharge_1. Icharge_1 copies the Isense current 1:1 through the PMOS current mirror, which is proportional to the output current of the BUCK chip. At the same time, the reference PMOS current mirror copies the reference current Iref 1:1 to obtain the current Icharge_2 to charge the adjustable capacitor array Cap_bank_2 to obtain the charging voltage Vcharge_2.

[0027] When the charging voltages Vcharge_1 and Vcharge_2 reach the flip threshold Vth of the inverter chain, the inverter chain outputs square wave signals Wave_1 and Wave_2 respectively. The phase detector compares the phases of Wave_1 and Wave_2 to determine whether the output current exceeds the mode switching point threshold set by the user. When the output current exceeds the mode switching point threshold, the sampling circuit charging voltage Vcharge_1 rises faster than the reference circuit charging voltage Vcharge_2. In other words, Vcharge_1 can reach the flip threshold Vth of the inverter chain in a shorter time. At this time, the phase detector will output a high level, causing the BUCK chip to switch from single-channel output to multi-channel output.

[0028] The time for Vcharge_1 to charge from 0 to Vth is represented by t_sense, and the time for Vcharge_2 to charge from 0 to Vth is represented by t_ref, which can be expressed as:

[0029]

[0030] Since the current mirror uses 1:1 replication, the above equation holds true. sense and C ref Respectively represent the capacitance array values ​​of the sampling circuit and the reference circuit. Users can adjust the capacitance value according to actual needs, thereby changing the time to charge to Vth and further changing the mode switching point.

[0031] The phase detector circuit used in the present invention is as follows: Figure 4 When the sampling cycle starts, the CLK_RST signal pulls the output signal low. When the phase detector VIP signal phase leads the VIN signal, that is, t sense <t ref , the output Mode_change signal is pulled high, and this signal can be used for mode switching of the BUCK chip.

[0032] The key signal waveforms of the circuit proposed by the present invention are as follows: Figure 5 As shown. When the chip output current increases and exceeds the preset mode switching point, the phase of Wave_1 leads Wave_2, the Mode_change signal is pulled high, and the BUCK chip enters the dual-channel output mode. By adjusting the capacitance value of the capacitor array, the slope of Vcharge_1 and Vcharge_2 can be changed, thereby affecting the phase of Wave_1 and Wave_2 and changing the mode switching point of the BUCK chip.

[0033] The beneficial effects of the present invention include at least: adjusting the working mode of the BUCK chip by adjusting the capacitor array, and the user can find the most suitable mode switching point according to actual needs, so that the BUCK chip can work more efficiently and stably.

Claims

1. A DC converter operating mode switching circuit, characterized in that: Including: phase detector, current mirror, inverter, switch NMOS tube, adjustable capacitor array; The output terminal of the detection signal circuit is connected to the positive input terminal VIP of the phase detector, and the output terminal of the reference signal circuit is connected to the negative input terminal VIN of the phase detector. By judging the phase of the detection signal and the reference signal, a mode switching signal is output to control the working mode of the BUCK chip. The detection signal circuit includes: a second PMOS transistor PM2, an inverter chain INV_1, an adjustable capacitor array Cap_bank_1, and a switch NMOS transistor NM3; wherein the gate end of the second PMOS transistor PM2 is connected to the gate end of the first PMOS transistor of the current detection circuit, the source end of PM2 is connected to the internal power supply of the chip, and the drain end is connected to the input end of the inverter chain INV_1; the input end of INV_1 is connected to the A end of the adjustable capacitor array Cap_bank_1, and the output end is connected to the positive input end VIP of the phase detector; the B end of the adjustable capacitor array Cap_bank_1 is grounded, and the A end is connected to the drain end of the switch NMOS transistor NM3; the source end of the switch NMOS transistor NM3 is grounded, and the drain end is connected to the control signal CLK_RST_B, and CLK_RST_B is the inverted signal of the external reset signal CLK_RST; The reference signal circuit includes: a third PMOS tube PM3, a fourth PMOS tube PM4, an inverter chain INV_2, an adjustable capacitor array Cap_bank_2, and a switch NMOS tube NM4; wherein the source terminal of the third PMOS tube is connected to the internal power supply of the chip, the drain terminal is short-circuited with the gate terminal and is connected to the chip reference current Iref, and the gate terminal is short-circuited with the gate terminal of the fourth PMOS tube PM4; the source terminal of PM4 is connected to the internal power supply of the chip, and the drain terminal is connected to the input terminal of the inverter chain INV_2; the input terminal of INV_2 is connected to the A terminal of the adjustable capacitor array Cap_bank_2, and the output terminal is connected to the negative input terminal VIN of the phase detector; the B terminal of the adjustable capacitor array Cap_bank_2 is grounded, and the A terminal is connected to the drain terminal of the switch NMOS tube NM4; the source terminal of the switch NMOS tube NM4 is grounded, and the drain terminal is connected to the control signal CLK_RST_B.

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