Demodulation Circuit and Rotary Digital Converter

Abstract

The present application discloses a demodulation circuit and a rotary digital converter, relating to the technical field of rotary digital converters. The demodulation circuit is composed of a peak detection circuit and a phase-locked loop. The peak detection circuit is used to extract the envelope waveform in the incoming resolver input signal and demodulate the envelope waveform to obtain rotor information. The phase-locked loop is used to identify the phase information of the accessed resolver input signal. After determining the offset error, a sampling clock and a synchronization clock are generated according to the offset error, and the sampling clock and the synchronization clock are transmitted to the peak detection circuit to correct the envelope waveform. The phase-locked loop assists the peak detection circuit to improve the gain of the envelope waveform extracted by the peak detection circuit, thereby improving the signal-to-noise ratio and further improving the demodulation effect and demodulation accuracy of the envelope waveform.

Description

Technical Field

[0001] The present application relates to the technical field of rotary digital converters, and particularly to a demodulation circuit and a rotary digital converter. Background Art

[0002] Inside a rotary digital converter, to achieve demodulation, the maximum amplitudes within one excitation period of the sine signal and the cosine signal are extracted respectively, and thus an envelope signal with the best signal-to-noise ratio is extracted. The input shaft angle related to the demodulation result is obtained through this envelope signal.

[0003] However, the extraction of the maximum amplitude of the signal in one excitation period is related to the position of the zero-crossing point of one excitation period. If the zero-crossing point data obtained at the zero moment in one excitation period is positive or negative, that is, the position of the zero-crossing point data obtained in one excitation period on the excitation period does not correspond to the zero position of the excitation period, it indicates that there is a deviation in one excitation period. There are problems of low signal-to-noise ratio of the extracted envelope signal and inaccurate demodulation result when collecting the sine signal and cosine signal corresponding to this one excitation period. Summary of the Invention

[0004] The main purpose of the present application is to provide a demodulation circuit and a rotary digital converter, aiming to solve the technical problem of low signal-to-noise ratio of the extracted envelope signal when there is a deviation in one excitation period.

[0005] To achieve the above object, the present application proposes a demodulation circuit, which is composed of a peak detection circuit and a phase-locked loop;

[0006] The peak detection circuit is used to extract the envelope waveform from the incoming resolver input signal and demodulate the envelope waveform to obtain rotor information;

[0007] The phase-locked loop is used to identify the phase information of the incoming resolver input signal. After determining the offset error, a sampling clock and a synchronization clock are generated according to the offset error, and the sampling clock and the synchronization clock are sent to the peak detection circuit to correct the envelope waveform;

[0008] Among them, the peak detection circuit includes a first analog-to-digital converter, a second analog-to-digital converter, an envelope extractor, and a four-quadrant arctangent module;

[0009] The input end of the first analog-to-digital converter is connected to the sine resolver input signal, and the sine resolver input digital signal is output to the envelope extractor. The input end of the second analog-to-digital converter is connected to the cosine resolver input signal, and the cosine resolver input digital signal is output to the envelope extractor;

[0010] The envelope extractor outputs a sine envelope waveform based on the incoming sine resolver input digital signal, and outputs a cosine envelope waveform based on the incoming cosine resolver input digital signal;

[0011] The four - quadrant arctangent module outputs the quadrant phase of the sine envelope waveform and the cosine envelope waveform according to the accessed sine envelope waveform and cosine envelope waveform, and the rotor information is obtained according to the quadrant phase;

[0012] The phase - discrimination loop includes a first phase discriminator, a second phase discriminator, a four - quadrant adder, a sampling phase accumulator, and a clock generation module;

[0013] Both the first phase discriminator and the second phase discriminator are connected to the output ends of the first analog - to - digital converter and the second analog - to - digital converter, and are used for phase - identifying the sine resolver input digital signal and the cosine resolver input signal, and outputting phase information;

[0014] The first phase discriminator and the second phase discriminator are connected to the four - quadrant adder, and the four - quadrant adder outputs phase error information according to the phase information;

[0015] The first phase discriminator and the second phase discriminator are also connected to the sampling phase accumulator, the four - quadrant adder is connected to the sampling phase accumulator, and the sampling phase accumulator is used for outputting a phase offset according to the phase information and the phase error information;

[0016] The sampling phase accumulator is connected to the clock generation module, and the clock generation module outputs a sampling clock and a synchronization clock to the envelope extractor according to the accessed phase offset.

[0017] In one embodiment, the four - quadrant adder includes a multiplexer, a first inverter, a second inverter, a first adder, and a gain device;

[0018] The first input end of the multiplexer is connected to the output end of the first phase discriminator, and the second input end of the multiplexer is connected to the output end of the first phase discriminator via the first inverter;

[0019] The third input end of the multiplexer is connected to the output end of the second phase discriminator, and the fourth input end of the multiplexer is connected to the output end of the second phase discriminator via the second inverter;

[0020] The output end of the multiplexer is connected to the first adder, and the output end of the first adder is connected to the gain device.

[0021] In one embodiment, the sampling phase accumulator includes a second adder and a unit delay;

[0022] The input end of the second adder is connected to the output end of the gain device, and the output end of the second adder is connected to the input end of the unit delay;

[0023] The output end of the unit delay is respectively connected to the input end of the clock generation module and the input end of the second adder.

[0024] In one embodiment, the clock generation module includes a plurality of phase branches and an OR gate, and the plurality of phase branches form an excitation period;

[0025] Each phase branch is respectively connected to a phase offset amount, and the phase offset amount is compared with the phase points in each phase branch. When it is compared that the phase offset amount is equal to the phase amount corresponding to any phase branch, the comparison result of the phase branch to which the phase amount equal to the phase offset amount belongs is output as a sampling clock through the OR gate.

[0026] In one embodiment, if there is a phase offset amount equal to any zero crossing point, the comparison result of the phase branch where any zero crossing point is located is output as a synchronization clock.

[0027] In one embodiment, the demodulation circuit is specifically configured to:

[0028] Perform equidistant sampling operation or non-equidistant sampling operation on one excitation period according to the sampling clock through the peak detection circuit to obtain a plurality of initial sampling signals, where the plurality of initial sampling signals include sampling signals at the zero moment;

[0029] Based on the phase-locked loop, the difference is made on the sampling signal at the zero moment to obtain phase information. According to the positive and negative conditions reflected by the phase information, the position information between the sampling position corresponding to the sampling signal at the zero moment and the zero position on one excitation period is obtained;

[0030] Adjust the sampling clock according to the position information to obtain a target sampling clock. Based on the target sampling clock, perform multiple samplings on one excitation period to obtain a plurality of target sampling signals, and then extract the sine envelope waveform and cosine envelope waveform of the electromagnetic induction differential output signal belonging to one excitation period according to the target sampling signals.

[0031] In one embodiment, the demodulation circuit is specifically configured to:

[0032] In the case where it is determined according to the positive and negative conditions that the phase information is a positive difference, a first position relationship that the sampling position lags behind the zero crossing position of one excitation period is obtained according to the positive difference, and a first distance relationship between the sampling position and the zero crossing position is obtained according to the first absolute value of the positive difference, where the first position relationship and the first distance relationship are position information.

[0033] According to the first position relationship and the first distance relationship, advance the time period reflected by the first time interval on the basis of the sampling clock to obtain the sine envelope waveform and the cosine envelope waveform.

[0034] In one embodiment, the demodulation circuit is specifically configured to:

[0035] In the case where the phase information is determined to be a negative difference according to the positive and negative conditions, a second position relationship between the sampling position and the zero-crossing position that is ahead of an excitation period is obtained based on the negative difference, and a second distance relationship between the sampling position and the zero-crossing position is obtained based on the second absolute value of the negative difference, where the second position relationship and the second distance relationship are position information.

[0036] Based on the second position relationship and the second distance relationship, a period reflected by delaying a second time interval is adjusted on the basis of a sampling clock to obtain a sine envelope waveform and a cosine envelope waveform.

[0037] In one embodiment, the demodulation circuit is specifically configured to:

[0038] Calculate the sum of the sampling signal at the target zero-crossing moment and the sampling signal at the target non-zero-crossing moment, and output to obtain a sine envelope waveform and a cosine envelope waveform; or, calculate the sum of the sampling signals at the target non-zero-crossing moments, and output to obtain a sine envelope waveform and a cosine envelope waveform.

[0039] In addition, to achieve the above object, the present application further provides a rotational digital converter, and the rotational digital converter includes the demodulation circuit as described above.

[0040] One or more technical solutions proposed by the present application have at least the following technical effects:

[0041] A demodulation circuit is proposed. The demodulation circuit consists of a peak detection circuit and a phase discrimination loop. The peak detection circuit is used to extract the envelope waveform from the incoming resolver input signal and demodulate the envelope waveform to obtain rotor information. The phase discrimination loop is used to identify the phase information of the accessed resolver input signal. After determining the offset error, a sampling clock and a synchronization clock are generated according to the offset error, and the sampling clock and the synchronization clock are sent to the peak detection circuit to correct the envelope waveform. Among them, the peak detection circuit includes a first analog-to-digital converter, a second analog-to-digital converter, an envelope extractor, and a four-quadrant arctangent module. The input end of the first analog-to-digital converter is connected to the sine resolver input signal, and the sine resolver input digital signal is output to the envelope extractor. The input end of the second analog-to-digital converter is connected to the cosine resolver input signal, and the cosine resolver input digital signal is output to the envelope extractor. The envelope extractor outputs a sine envelope waveform based on the accessed sine resolver input digital signal and a cosine envelope waveform based on the accessed cosine resolver input digital signal. The four-quadrant arctangent module outputs the quadrant phase of the sine envelope waveform and the cosine envelope waveform according to the accessed sine envelope waveform and cosine envelope waveform. Among them, the rotor information is obtained according to the quadrant phase. The phase discrimination loop includes a first phase discriminator, a second phase discriminator, a four-quadrant adder, a sampling phase accumulator, and a clock generation module. The first phase discriminator and the second phase discriminator are both connected to the output end of the first analog-to-digital converter and the output end of the second analog-to-digital converter, and are used to identify the phase of the sine resolver input digital signal and the cosine resolver input signal and output phase information. The first phase discriminator and the second phase discriminator are connected to the four-quadrant adder, and the four-quadrant adder outputs phase error information according to the phase information. The first phase discriminator and the second phase discriminator are also connected to the sampling phase accumulator, the four-quadrant adder is connected to the sampling phase accumulator, and the sampling phase accumulator is used to output a phase offset according to the phase information and the phase error information. The sampling phase accumulator is connected to the clock generation module, and the clock generation module outputs a sampling clock and a synchronization clock to the envelope extractor according to the accessed phase offset.

[0042] Through a demodulation circuit designed by this application, the phase discrimination loop assists the peak detection circuit to improve the gain of the envelope waveform extracted by the peak detection circuit, thereby improving the signal-to-noise ratio and further improving the demodulation effect and demodulation accuracy of the envelope waveform. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings here are incorporated into the specification and form a part of this specification, showing embodiments consistent with this application, and are used together with the specification to explain the principles of this application.

[0044] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0045] Figure 1 It is a schematic structural diagram of the demodulation circuit of the present application;

[0046] Figure 2 It is a schematic diagram of the correct waveform of the rotor position phase detection output;

[0047] Figure 3 It is a schematic diagram of the correct waveform of the detection output after the rotor position phase is corrected;

[0048] Figure 4 It is a schematic structural diagram of the four-quadrant adder of the present application;

[0049] Figure 5 It is a schematic structural diagram of the sampling phase accumulator of the present application;

[0050] Figure 6 It is a schematic structural diagram of the clock generation module of the present application;

[0051] Figure 7 It is a schematic diagram of the waveform of equally spaced sampling in one excitation period;

[0052] Figure 8 It is a schematic diagram of the waveform of non-equally spaced sampling in one excitation period;

[0053] Figure 9 It is a schematic diagram of the waveform of one excitation period with different phases on the coordinate axis.

[0054] The realization of the purpose, functional characteristics and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. Detailed implementation manners

[0055] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0056] To better understand the technical solutions of the present application, the following will be described in detail in combination with the drawings of the specification and the specific implementation manners.

[0057] The main solution of the embodiment of the present application is: a demodulation circuit is proposed, which is composed of a peak detection circuit and a phase discrimination loop; the peak detection circuit is used to extract the envelope waveform in the incoming resolver input signal and demodulate the envelope waveform to obtain rotor information; the phase discrimination loop is used to identify the phase information of the accessed resolver input signal, generate a sampling clock and a synchronization clock according to the offset error after determining the offset error, and transmit the sampling clock and the synchronization clock to the peak detection circuit to correct the envelope waveform; wherein, the peak detection circuit includes a first analog-to-digital converter, a second analog-to-digital converter, an envelope extractor and a four-quadrant arctangent module; the input end of the first analog-to-digital converter is connected to the sine resolver input signal, and outputs the sine resolver input digital signal to the envelope extractor, and the input end of the second analog-to-digital converter is connected to the cosine resolver input signal, and outputs the cosine resolver input digital signal to the envelope extractor; the envelope extractor outputs a sine envelope waveform based on the accessed sine resolver input digital signal, and outputs a cosine envelope waveform based on the accessed cosine resolver input digital signal; the four-quadrant arctangent module outputs the quadrant phase of the sine envelope waveform and the cosine envelope waveform according to the accessed sine envelope waveform and cosine envelope waveform, wherein the rotor information is obtained according to the quadrant phase; the phase discrimination loop includes a first phase discriminator, a second phase discriminator, a four-quadrant adder, a sampling phase accumulator and a clock generation module; both the first phase discriminator and the second phase discriminator are connected to the output end of the first analog-to-digital converter and the output end of the second analog-to-digital converter, and are used to perform phase discrimination on the sine resolver input digital signal and the cosine resolver input signal, and output phase information; the first phase discriminator and the second phase discriminator are connected to the four-quadrant adder, and the four-quadrant adder outputs phase error information according to the phase information; the first phase discriminator and the second phase discriminator are also connected to the sampling phase accumulator, the four-quadrant adder is connected to the sampling phase accumulator, and the sampling phase accumulator is used to output a phase offset according to the phase information and the phase error information; the sampling phase accumulator is connected to the clock generation module, and the clock generation module outputs a sampling clock and a synchronization clock to the envelope extractor according to the accessed phase offset.

[0058] Inside the rotary digital converter, to achieve demodulation, the maximum amplitude within one excitation period of the sine signal and the cosine signal is extracted respectively, and thus an envelope signal with the best signal-to-noise ratio is extracted. The input shaft angle related to the demodulation result is obtained through this envelope signal. However, to extract the maximum amplitude of the signal in one excitation period is related to the position of the zero-crossing point of one excitation period. If the zero-crossing point data obtained at the zero moment in one excitation period is positive or negative, that is, the position of the zero-crossing point data obtained in one excitation period corresponding to the excitation period is not the zero position of the excitation period, it indicates that there is a deviation in one excitation period, and there are problems such as low signal-to-noise ratio of the extracted envelope signal and inaccurate demodulation result for the collected sine signal and cosine signal corresponding to this one excitation period.

[0059] The present application provides a solution, which uses a phase discrimination loop to assist a peak detection circuit, thereby enhancing the gain of the envelope waveform extracted by the peak detection circuit, improving the signal-to-noise ratio, and further enhancing the demodulation effect and demodulation accuracy of the envelope waveform.

[0060] It should be noted that the execution subject of this embodiment can be a computing service device with data processing, network communication, and program running functions, such as a tablet computer, a personal computer, a mobile phone, etc., or an electronic device capable of implementing the above functions. Hereinafter, a rotary digital converter will be used as an example to illustrate this embodiment and the following embodiments.

[0061] An embodiment of the present application proposes an envelope signal extraction method, referring to Figure 1 as shown in Figure 1 The demodulation circuit of the present application is composed of a peak detection circuit and a phase discrimination loop;

[0062] The peak detection circuit is used to extract the envelope waveform from the incoming resolver input signal and demodulate the envelope waveform to obtain rotor information; the phase discrimination loop is used to identify the phase information of the accessed resolver input signal. After determining the offset error, a sampling clock and a synchronization clock are generated according to the offset error, and the sampling clock and the synchronization clock are transmitted to the peak detection circuit to correct the envelope waveform.

[0063] Among them, the peak detection circuit includes a first analog-to-digital converter (i.e., Figure 1 the ADC1 in Figure 1the ADC2), envelope extractor, and four-quadrant arctangent module therein; the input end of the first analog-to-digital converter is connected to the sine resolver input signal, and outputs the sine resolver input digital signal to the envelope extractor, and the input end of the second analog-to-digital converter is connected to the cosine resolver input signal, and outputs the cosine resolver input digital signal to the envelope extractor; the envelope extractor outputs the sine envelope waveform based on the accessed sine resolver input digital signal, and outputs the cosine envelope waveform based on the accessed cosine resolver input digital signal; the four-quadrant arctangent module outputs the quadrant phase of the sine envelope waveform and the cosine envelope waveform according to the accessed sine envelope waveform and cosine envelope waveform, wherein the rotor information is obtained according to the quadrant phase. Among them, in addition to the SAR ADC (Successive Approximation Register Analog-to-Digital Converter), the first analog-to-digital converter and the second analog-to-digital converter can also use the Incremental Delta-Sigma ADC (incremental delta-sigma analog-to-digital converter), etc. The four-quadrant arctangent module can be implemented by quadrant judgment plus arctangent CORDIC (Coordinate Rotation Digital Computer), or can be implemented by four-quadrant arctangent CORDIC. The present application does not limit the implementation manner of the four-quadrant arctangent module.

[0064] The phase-locked loop includes a first phase detector, a second phase detector, a four-quadrant adder, a sampling phase accumulator, and a clock generation module; both the first phase detector and the second phase detector are connected to the output end of the first analog-to-digital converter and the output end of the second analog-to-digital converter, and are used for phase identification of the sine resolver input digital signal and the cosine resolver input signal, and output phase information; the first phase detector and the second phase detector are connected to the four-quadrant adder, and the four-quadrant adder outputs phase error information according to the phase information; the first phase detector and the second phase detector are also connected to the sampling phase accumulator, the four-quadrant adder is connected to the sampling phase accumulator, and the sampling phase accumulator is used for outputting a phase offset according to the phase information and the phase error information; the sampling phase accumulator is connected to the clock generation module, and the clock generation module outputs a sampling clock and a synchronization clock to the envelope extractor according to the accessed phase offset.

[0065] According to Figure 1 It can be seen from the shown demodulation circuit that the demodulation circuit proposed in the present application is composed of a peak detection circuit and a phase-locked loop. Among them, the peak detection circuit can demodulate and obtain rotor information such as the phase and speed of the rotor by extracting the envelope waveform of the resolver input signal. The phase-locked loop identifies the offset error situation of phase information such as zero-crossing points, and generates a sampling clock and a synchronization clock for correcting the envelope waveform in the peak detection circuit.

[0066] It should be noted that the resolver input signal includes a sine signal and a cosine signal , and their expressions respectively correspond to Expression ① and Expression ②.

[0067] ————Expression ①

[0068] ————Expression ②

[0069] Among them, is the input shaft angle, is the angular frequency parameter. The two electromagnetic induction differential output signals generated on the secondary winding are modulated by the corresponding input shaft angle. Specifically, the sine signal, the cosine signal, the excitation signal, and the sine envelope signal and the cosine envelope signal respectively extracted based on the sine signal and the cosine signal and the cosine envelope signal such as Figure 2 and Figure 3 are shown.

[0070] Among them, Figure 2 when the excitation phase is 0°, the rotor position phase output is correct. It can be seen from the topmost figure that since the position of the zero crossing point is relatively accurate, the output amplitude of the analog-to-digital converter can match the input amplitude of the analog-to-digital converter at this time. Therefore, the amplitude of the obtained envelope signal is large and the signal-to-noise ratio is high (the middle figure). The rotor position phase detection output obtained thereby is correct, that is, the demodulation effect is good. It should be noted that Figure 2 the topmost figure in Figure 2 is the verification diagram of the ADC input / output amplitude matching when the excitation phase is 0°; Figure 2 the middle figure in

[0071] Figure 3 is the demodulation effect diagram of the high signal-to-noise ratio envelope signal; Figure 3 the bottommost figure in Figure 3The middle figure is the verification diagram of the envelope signal dynamic correction effect; Figure 3 The bottom figure is the comparison diagram of the rotor phase closed-loop correction.

[0072] Refer to Figure 4 As shown, the four-quadrant adder includes a multiplexer, a first inverter (i.e., Figure 4 ① in Figure 4 ), a second inverter (i.e., Figure 4 ② in Figure 4 ), a first adder (i.e., ③ in

[0073] ), and a gain device (i.e., ④ in

[0074] Figure 4 );

[0075] Figure 1 The first input terminal of the multiplexer is connected to the output terminal of the first phase detector, and the second input terminal of the multiplexer is connected to the output terminal of the first phase detector via the first inverter; the third input terminal of the multiplexer is connected to the output terminal of the second phase detector, and the fourth input terminal of the multiplexer is connected to the output terminal of the second phase detector via the second inverter; the output terminal of the multiplexer is connected to the first adder, and the output terminal of the first adder is connected to the gain device.

[0076] Refer to Figure 5 As shown, the sampling phase accumulator includes a second adder (i.e., Figure 5 ⑤ in Figure 5

[0077] ), and a unit delay element (i.e., ⑥ in

[0078] ); Figure 6 The input terminal of the second adder is connected to the output terminal of the gain device, and the output terminal of the second adder is connected to the input terminal of the unit delay element; the output terminal of the unit delay element is respectively connected to the input terminal of the clock generation module and the input terminal of the second adder. That is, the phase error can be obtained as a phase offset by means of shift addition. Figure 6in 、...、 、 and ), and an OR gate (i.e., Figure 6 ⑦ in ), where multiple phase branches form an excitation period. Among them,

[0079] Each phase branch is respectively connected to a phase offset, and the phase offset is compared with the phase points in each phase branch. When it is compared and the phase offset is equal to the phase amount corresponding to any phase branch, the comparison result of the phase branch to which the phase amount equal to the phase offset belongs is output as a sampling clock through the OR gate.

[0080] If there is a phase offset equal to any zero-crossing point, the comparison result of the phase branch where any zero-crossing point is located is output as a synchronization clock.

[0081] The clock generation module is a phase branch that equally divides the signal of an excitation period, and compares the phase offset with the equally divided phase points. The outputs of n phase branches will be used as the inputs of the OR gate, and the output of the OR gate is the sampling clock. Among them, the output of the phase branch at the 0° phase point is the synchronization clock.

[0082] It should be noted that since both the 0° phase point and the 180° phase point are zero-crossing points. If synchronized once within an excitation period, the output of the phase branch at the 0° phase point can be taken as the synchronization clock; or the output of the phase branch at the 180° phase point can be taken as the synchronization clock. If synchronized twice within an excitation period, the outputs of the phase branches at the 0° phase point and the 180° phase point can be ORed as the synchronization clock. The present invention does not limit the selection of the synchronization clock.

[0083] The embodiment of this clock generation module mainly compares the phase offset with the equally divided phase points of n phase branches. When the phase offset is equal to a certain phase point of the equal division, this branch will output a high level, and the OR gate will also output a high level. At this time, the sampling clock becomes high level, so the signal within an excitation period is sampled at equal intervals with n equal divisions.

[0084] When n = 8, the phase offset needs to be compared with 0°, 45°, 90°, 135°, 180°, 225°, 270°, 315°. When the phase offset is exactly equal to the above 8 phase points, a sampling clock will be output to sample the signal within an excitation period, as Figure 7 shown. When the phase offset is equal to 0° and 180°, the corresponding S0 and S4 are zero-crossing signals.

[0085] It should be noted that equal sampling intervals are not necessary. Sampling can be concentrated near 0°, 90°, 180°, and 270°; sampling can also be concentrated near 90° and 270°, as Figure 8 shown, and the present invention is not limited thereto.

[0086] Furthermore, the demodulation circuit is specifically configured to:

[0087] perform equidistant sampling operations or non-equidistant sampling operations on a single excitation period according to the sampling clock through a peak detection circuit to obtain a plurality of initial sampling signals, where the plurality of initial sampling signals include sampling signals at the zero point moment;

[0088] obtain phase information by taking the difference of the sampling signals at the zero point moment based on a phase-locked loop, and obtain the position information between the sampling position corresponding to the sampling signal at the zero point moment and the zero position on a single excitation period according to the positive or negative situation reflected by the phase information;

[0089] adjust the sampling clock according to the position information to obtain a target sampling clock, and based on the target sampling clock, perform multiple samplings on a single excitation period to obtain a plurality of target sampling signals, and then extract the sine envelope waveform and cosine envelope waveform of the electromagnetic induction differential output signal belonging to a single excitation period according to the target sampling signals.

[0090] For the convenience of subsequent description and understanding, the principle of the rotary digital converter and relevant information on the extraction of envelope signals based on the rotary digital converter will be described first.

[0091] First of all, the rotary digital converter realizes an interface between the resolver and the system microprocessor, and demodulates by collecting sine signals and cosine signals to obtain the angular position and rotational speed of the motor shaft.

[0092] For the resolver, it excites the primary winding by using an excitation signal with a single excitation period to generate two electromagnetic induction differential output signals on the secondary winding, namely the sine signal and the cosine signal , and their expressions respectively correspond to Expression ① and Expression ②.

[0093] ————Expression ①

[0094] ————Expression ②

[0095] Among them, is the input shaft angle, is the angular frequency parameter. The two electromagnetic induction differential output signals generated on the secondary winding are modulated by the corresponding input shaft angle. Specifically, the sine signal, cosine signal, excitation signal, and envelope signals respectively extracted based on the sine signal and cosine signal and such as Figure 1 shown.

[0096] may be referred to Figure 7 shown. In the early stage, directly based on the sampling clock, a magnetic excitation period is sampled multiple times to obtain multiple initial sampling signals. In this embodiment, the magnetic excitation period is sampled 8 times to obtain the initial sampling signals as shown in Expression ③.

[0097] ————Expression ③

[0098] Among them, represents the set of initial sampling signals, s represents the initial sampling signal, and its subscript represents the sampling point number. According to Figure 7 it can be known that and are the signals at the zero point moment of a magnetic excitation period, that is, the sampling signals at the zero point moment of a magnetic excitation period, ~ and ~ are the sampling signals at the non-zero point moments of a magnetic excitation period.

[0099] Based on the sampling clock, directly sample a magnetic excitation period to obtain the sampling signal at the zero point moment of a magnetic excitation period, and thereby judge the corresponding relationship between the sampling signal at the zero point moment and the zero-crossing position of a magnetic excitation period.

[0100] It should be noted that the zero point moment in the sampling signal at the zero point moment of a magnetic excitation period refers to the zero point moment of a magnetic excitation period, and this zero point moment is related to the sampling clock.

[0101] Furthermore, Expression ③ only expresses the case where the number of initial sampling signals is 8. Specifically, it can also be other sampling times as shown in Expression ④.

[0102] ————Expression ④

[0103] Among them, represents the set of initial sampling signals, s represents the initial sampling signal, and its subscript represents the sampling point number.

[0104] It should be noted that because the excitation signal of a magnetic excitation period excites the primary winding, a sine signal and a cosine signal , while the sine signal and the cosine signal both have corresponding input shaft angles. Therefore, in this application, it is necessary to separately sample the first excitation period corresponding to the sine signal and the second excitation period corresponding to the cosine signal multiple times according to the sampling clock. The zero-crossing moment sampling signals on the first excitation period and the zero-crossing moment sampling signals on the second excitation period are obtained, so as to respectively adjust the sampling clocks of the first excitation period and the second excitation period based on the zero-crossing moment sampling signals, so that the envelope signals extracted based on the first excitation period and the second excitation period can both improve the demodulation accuracy.

[0105] Referring to Expression ⑤, Expression ⑤ is the calculation formula for phase information.

[0106] ————Expression ⑤

[0107] Among them, represents the phase information. In the expression, represents the initial sampling signal of the 4th sampling times, represents the zero-crossing moment sampling signal. In the specific implementation process, it can be set as the zero-crossing moment sampling signal with other subscripts.

[0108] Because within half of an excitation period, and have equal amplitude magnitudes but opposite directions. Therefore, if effective phase information is to be extracted based on and , a subtraction operation needs to be performed. Based on this subtraction operation, the positional relationship and distance magnitude between and the zero-crossing position within an excitation period can be obtained, and further, it can be determined whether the zero-crossing moment sampling signal sampled based on the sampling clock is the signal at the zero-crossing position of an excitation period.

[0109] The reason for judging based on the zero-crossing moment sampling signal instead of the non-zero-crossing moment sampling signal is that the zero-crossing moment sampling signal can better determine the position compared to the non-zero-crossing moment sampling signal. As long as it is determined that the zero-crossing moment sampling signal corresponds to the zero-crossing position of an excitation period, it can be directly deduced that the non-zero-crossing moment sampling signal does not correspond to the zero-crossing position of an excitation period, and subsequently, an envelope signal with a higher signal-to-noise ratio can be directly extracted based on the non-zero-crossing moment sampling signal.

[0110] In other implementation processes, the calculation formula for phase information can be further Expression ⑥.

[0111] ————Expression ⑥

[0112] Among them, represents phase information. In the expression, represents the initial sampling signal of the 2n-th sampling point number, represents the sampling signal at the zero point moment.

[0113] In this embodiment, the first phase information obtained by taking the difference between the sampling signals at the first zero point moment in the first excitation period and the second phase information obtained by taking the difference between the sampling signals at the second zero point moment in the second excitation period can both reflect whether the sampling signals at the zero point moment in the first excitation period and the second excitation period obtained based on the sampling clock are signals at the zero crossing position of one excitation period. Accordingly, the sampling clocks of the first excitation period and the sampling clock of the second excitation period are adjusted correspondingly to ensure that the envelope signals extracted in the first excitation period and the second excitation period both have good signal-to-noise ratios.

[0114] After obtaining the position information between the sampling position of the sampling signal at the zero point moment in one excitation period mapped on one excitation period and the zero crossing position in one excitation period, at this time, the sampling clock can be adjusted according to the position information to change the sampling time of the sampling signal in one excitation period based on the sampling clock, so that the target sampling signal sampled in one excitation period based on the adjusted sampling clock, that is, the target sampling clock, includes the signal at the zero crossing position in one excitation period. Therefore, other signals in the target sampling signal at this time will surely not be at the zero crossing position in one excitation period. Therefore, the target envelope signals (i.e., the sine envelope waveform and the cosine envelope waveform) extracted based on other signals in the target sampling signal will surely have better signal-to-noise ratios and can achieve a high-accuracy demodulation effect.

[0115] The demodulation circuit is further configured to: in the case of determining that the phase information is a positive difference according to the positive and negative situations, obtain a first position relationship that the sampling position lags behind the zero crossing position of one excitation period according to the positive difference, and obtain a first distance relationship between the sampling position and the zero crossing position according to the first absolute value of the positive difference, where the first position relationship and the first distance relationship are position information.

[0116] According to the first position relationship and the first distance relationship, advance the time period reflected by the first time interval on the basis of the sampling clock to obtain the sine envelope waveform and the cosine envelope waveform.

[0117] Specifically, as Figure 9 shown, an example of one excitation period is used for illustration.

[0118] Figure 9 One excitation period in As a control group, it is used to represent the standard wave, whose phase is neither leading nor lagging, and one excitation period The zero-crossing position on exactly coincides with the zero position on one excitation period (i.e., Figure 9 the position marked "0" in).

[0119] When, according to the positive and negative situations, the phase information is determined to be a positive difference, its phase situation reflected on one excitation period is as shown on one excitation period as shown. Figure 9 The zero moment in (i.e., the zero position of one excitation period) is a certain sampling moment in the sampling clock. It can be seen from the figure that when the phase information is a positive difference, it means that the sampling signal at the zero moment sampled on one excitation period is located in the second half period of one excitation period The phase is leading and the sampling clock is lagging, making the sampling signal at the zero moment of one excitation period mapped to a sampling position on one excitation period lagging behind the zero-crossing position of one excitation period The first positional relationship.

[0120] Since one excitation period repeats periodically at a certain frequency, the difference between the sampling signals at the zero moment sampled on one excitation period, that is, the absolute value of the positive difference reflected by the phase information, can reflect the first distance relationship between the sampling position and the zero-crossing position of one excitation period

[0121] After determining the first positional relationship and the first distance relationship, the sampling clock can be directly adjusted accordingly. According to the first positional relationship obtained above, it can be known that the sampling moment of the sampling clock is lagging, so an operation of advancing the sampling clock needs to be performed. According to the first distance relationship obtained above, it can be known the distance relationship between the sampling position and the zero-crossing position reflected on the X-axis (i.e., the time axis) of one excitation period. Therefore, the adjustment operation of the initial sampling clock at this time is to advance the sampling clock by the first time interval.

[0122] Among them, the first time interval corresponds to the first distance relationship, and the first distance relationship can reflect the time interval between the sampling moment of the sampling position on one excitation period and the first moment of the zero-crossing position on one excitation period.

[0123] The demodulation circuit is further configured to: in the case where, according to the positive and negative situations, the phase information is determined to be a negative difference, obtain a second positional relationship that the sampling position is ahead of the zero-crossing position of one excitation period according to the negative difference, and obtain a second distance relationship between the sampling position and the zero-crossing position according to the second absolute value of the negative difference, where the second positional relationship and the second distance relationship are position information.​​

[0124] According to the second positional relationship and the second distance relationship, delay the period reflected by the second time interval based on the sampling clock to obtain the sine envelope waveform and the cosine envelope waveform.

[0125] When determining that the phase information is a negative difference according to the positive or negative situation, the phase situation reflected on an excitation period is like an excitation period as shown. Figure 9 The 0 moment in (i.e., the zero moment of an excitation period) is a certain sampling moment in the sampling clock. It can be seen from the figure that when the phase information is a negative difference, it means that the sampling signal at the zero moment sampled on an excitation period is located in the first half period of an excitation period After the phase occurs, the sampling clock is advanced, so that the sampling signal at the zero moment of an excitation period is mapped to a sampling position on an excitation period that is ahead of the zero-crossing position of an excitation period in the second positional relationship.

[0126] Since an excitation period repeats periodically at a certain frequency, the difference between the sampling signals at the zero moment sampled on an excitation period , that is, the absolute value of the negative difference reflected by the phase information, can reflect the second distance relationship between the sampling position and the zero-crossing position of an excitation period .

[0127] After determining the second positional relationship and the second distance relationship, the sampling clock can be directly adjusted accordingly. According to the second positional relationship obtained above, it can be known that the sampling moment of the sampling clock is advanced, so an operation of delaying the sampling clock needs to be performed. According to the second distance relationship obtained above, it can be known the distance relationship between the sampling position and the zero-crossing position reflected on the X-axis (i.e., the time axis) of an excitation period. Therefore, the adjustment operation of the initial sampling clock at this time is to delay the sampling clock by the second time interval.

[0128] Among them, the second time interval corresponds to the second distance relationship, and the second distance relationship can reflect the time interval between the sampling moment of the sampling position on an excitation period and the second moment of the zero-crossing position on an excitation period.

[0129] It should be noted that based on Figure 2 and Figure 3It can be seen that the envelope signal has sine and cosine characteristics. Therefore, when the amplitude of the sine envelope signal is the smallest, the amplitude of the cosine envelope signal is the largest; when the amplitude of the cosine envelope signal is the smallest, the amplitude of the sine envelope signal is the largest. However, when the amplitudes differ greatly, there is a large error in the extracted phase information. Therefore, to avoid this situation, this embodiment proposes to superimpose the phase information of the sine envelope signal and the cosine envelope signal to solve the problem of large phase information error caused by too small amplitude of a single sine envelope signal or cosine envelope signal.

[0130] Specifically, still according to Figure 2 and Figure 3 It can be known that in the phase range of 0° to 90°, the amplitudes of both the sine envelope signal and the cosine envelope signal are positive; in the phase range of 90° to 180°, the amplitude of the sine envelope signal is positive and the amplitude of the cosine envelope signal is negative; in the phase range of 180° to 270°, the amplitudes of both the sine envelope signal and the cosine envelope signal are negative; in the phase range of 270° to 360°, the amplitude of the sine envelope signal is negative and the amplitude of the cosine envelope signal is positive. Therefore, the sine envelope signal and the cosine envelope signal can be divided into four quadrants. The first quadrant is the phase range of 0° to 90°; the second quadrant is the phase range of 90° to 180°; the third quadrant is the phase range of 180° to 270°; the fourth quadrant is the phase range of 270° to 360°. Thus, the superimposed formula of the phase information of the sine envelope signal and the phase information of the cosine envelope signal as shown in Expression ⑦ can be obtained.

[0131] ————Expression ⑦

[0132] Among them, is the target phase information of the phase information of the sine envelope signal and the phase information of the cosine envelope signal in the first quadrant, is the target phase information of the phase information of the sine envelope signal and the phase information of the cosine envelope signal in the second quadrant, is the target phase information of the phase information of the sine envelope signal and the phase information of the cosine envelope signal in the third quadrant, is the target phase information of the phase information of the sine envelope signal and the phase information of the cosine envelope signal in the fourth quadrant, represents the phase information of the sine envelope signal and the phase information of the cosine envelope signal in the first quadrant, represents the phase information of the sine envelope signal and the phase information of the cosine envelope signal in the second quadrant, represents the phase information of the sine envelope signal and the phase information of the cosine envelope signal in the third quadrant, represents the phase information of the sine envelope signal and the phase information of the cosine envelope signal in the fourth quadrant.

[0133] After obtaining the corresponding target phase information according to Expression ⑦, calculate the arctangent of the target phase information, and the specific degree within the phase range of 0° to 360° (i.e., one excitation period) of the target phase information can be obtained.

[0134] It should be noted that the arctangent operation in this embodiment is performed using the CORDIC method.

[0135] In order to further improve the accuracy of the obtained phase information and further improve the accuracy of the extracted envelope signal, this embodiment proposes to adjust the sampling clock based on the obtained degree and position information together, so as to reduce the large phase information error caused by too small amplitude based on a single sine envelope signal or cosine envelope signal, and further reduce the low accuracy of the existing position information, resulting in a situation where the signal-to-noise ratio of the extracted envelope signal of the adjusted target sampling clock is still relatively low.

[0136] Furthermore, the demodulation circuit is specifically configured to:

[0137] Calculate the sum of the target zero-point moment sampling signal and the target non-zero-point moment sampling signal, and output to obtain a sine envelope waveform and a cosine envelope waveform; or, calculate the sum of the target non-zero-point moment sampling signals, and output to obtain a sine envelope waveform and a cosine envelope waveform.

[0138] Specifically, Expression ⑧ calculates the sum of the target zero-point moment sampling signal and the target non-zero-point moment sampling signal, and outputs to obtain the target envelope signal.

[0139] ————Expression ⑧

[0140] Wherein, represents the signal sum from the first target zero-point moment sampling signal to the previous target non-zero-point moment sampling signal before the second target zero-point moment sampling signal, represents the signal sum from the second target zero-point moment sampling signal to the last target non-zero-point moment sampling signal, represents the target envelope signal.

[0141] Expression ⑨ calculates the sum of the target non-zero-point moment sampling signals, and outputs to obtain the target envelope signal.

[0142] ————Expression ⑨

[0143] Wherein, represents the signal sum from the next target non-zero-point moment sampling signal after the first target zero-point moment sampling signal to the previous target non-zero-point moment sampling signal before the second target zero-point moment sampling signal, It represents the sum of the sampled signals from the next target non-zero time instance sampling signal of the sampled signal at the second target zero time instance to the last target non-zero time instance sampling signal. It represents the target envelope signal.

[0144] Since the sampled signal at the target zero time instance obtained by sampling over an excitation period based on the target sampling clock is necessarily located at the zero-crossing position of an excitation period, it can be determined at this time that the sampled signal at the target non-zero time instance not only includes the peak value of an excitation period but also contains other amplitude components. Therefore, the signal-to-noise ratio of the envelope signal calculated based on this is improved.

[0145] It should be noted that the reason why the sampled signal at the target zero time instance is included in Expression ⑧ is that although the sampled signal at the target zero time instance is a useless signal, it will not affect the calculation result. Therefore, calculating the sampled signal at the target zero time instance and the sampled signal at the non-target zero time instance will not have a negative impact on the output envelope signal.

[0146] This application also proposes a rotational digital converter, which includes the demodulation circuit as described above.

[0147] The above are only partial embodiments of this application, and do not limit the patent scope of this application. Any equivalent structural transformation made under the technical concept of this application by using the content of the specification and drawings of this application, or direct / indirect application in other related technical fields, is included in the patent protection scope of this application.

Claims

1. A demodulation circuit, characterized in that, The demodulation circuit consists of a peak detection circuit and a phase-locked loop; The peak detection circuit is used to extract the envelope waveform in the incoming resolver input signal and demodulate the envelope waveform to obtain rotor information; The phase-locked loop is used to identify the phase information of the accessed resolver input signal. After determining the offset error, a sampling clock and a synchronization clock are generated according to the offset error, and the sampling clock and the synchronization clock are sent to the peak detection circuit to correct the envelope waveform; Among them, the peak detection circuit includes a first analog-to-digital converter, a second analog-to-digital converter, an envelope extractor, and a four-quadrant arctangent module; The input end of the first analog-to-digital converter accesses the sine resolver input signal, and outputs the sine resolver input digital signal to the envelope extractor. The input end of the second analog-to-digital converter accesses the cosine resolver input signal, and outputs the cosine resolver input digital signal to the envelope extractor; The envelope extractor outputs a sine envelope waveform based on the accessed sine resolver input digital signal, and outputs a cosine envelope waveform based on the accessed cosine resolver input digital signal; The four-quadrant arctangent module outputs the quadrant phase of the sine envelope waveform and the cosine envelope waveform according to the accessed sine envelope waveform and cosine envelope waveform. Among them, the rotor information is obtained according to the quadrant phase; The phase-locked loop includes a first phase detector, a second phase detector, a four-quadrant adder, a sampling phase accumulator, and a clock generation module; Both the first phase detector and the second phase detector are connected to the output end of the first analog-to-digital converter and the output end of the second analog-to-digital converter, and are used to identify the phase of the sine resolver input digital signal and the cosine resolver input signal, and output the phase information; The first phase detector and the second phase detector are connected to the four-quadrant adder, and the four-quadrant adder outputs phase error information according to the phase information; The first phase detector and the second phase detector are also connected to the sampling phase accumulator. The four-quadrant adder is connected to the sampling phase accumulator. The sampling phase accumulator is used to output a phase offset according to the phase information and the phase error information; The sampling phase accumulator is connected to the clock generation module, and the clock generation module outputs the sampling clock and the synchronization clock to the envelope extractor according to the accessed phase offset; 2. The demodulation circuit according to claim 1, wherein The four-quadrant adder includes a multiplexer, a first inverter, a second inverter, a first adder, and a gain device; The first input end of the multiplexer is connected to the output end of the first phase detector, and the second input end of the multiplexer is connected to the output end of the first phase detector via the first inverter; The third input end of the multiplexer is connected to the output end of the second phase detector, and the fourth input end of the multiplexer is connected to the output end of the second phase detector via the second inverter; The output end of the multiplexer is connected to the first adder, and the output end of the first adder is connected to the gain device.

3. The demodulation circuit according to claim 2, characterized in that The sampling phase accumulator includes a second adder and a unit delay; The input end of the second adder is connected to the output end of the gain device, and the output end of the second adder is connected to the input end of the unit delay; The output end of the unit delay is respectively connected to the input end of the clock generation module and the input end of the second adder.

4. The demodulation circuit according to claim 3, wherein The clock generation module includes a plurality of phase branches and an OR gate, and the plurality of phase branches form an excitation period; Each of the phase branches is respectively input with the phase offset, and the phase offset is compared with the phase points in each of the phase branches. When it is obtained through comparison that the phase offset is equal to the phase amount corresponding to any phase branch, the comparison result of the phase branch to which the phase amount equal to the phase offset belongs is output as a sampling clock through the OR gate.

5. The demodulation circuit according to claim 4, wherein If there is a phase offset equal to any zero crossing point, the comparison result of the phase branch where any zero crossing point is located is output as the synchronization clock.

6. The demodulation circuit according to claim 5, wherein, The demodulation circuit is specifically configured to: Perform an equidistant sampling operation or a non-equidistant sampling operation on the one excitation period according to the sampling clock through the peak detection circuit to obtain a plurality of initial sampling signals, where the plurality of initial sampling signals include a sampling signal at the zero moment; Based on the phase-locked loop, the phase information is obtained by taking the difference of the sampling signal at the zero moment, and according to the positive or negative situation reflected by the phase information, the position information between the sampling position corresponding to the sampling signal at the zero moment and the zero position on the one excitation period is obtained; Adjust the sampling clock according to the position information to obtain a target sampling clock. Based on the target sampling clock, multiple samplings are performed on the one excitation period to obtain a plurality of target sampling signals, and then the sine envelope waveform and the cosine envelope waveform of the electromagnetic induction differential output signal belonging to the one excitation period are extracted according to the target sampling signals.

7. The demodulation circuit according to claim 6, wherein, The demodulation circuit is specifically configured to: In the case where it is determined according to the positive or negative situation that the phase information is a positive difference value, a first position relationship that the sampling position lags behind the zero crossing position of the one excitation period is obtained according to the positive difference value, and a first distance relationship between the sampling position and the zero crossing position is obtained according to the first absolute value of the positive difference value, where the first position relationship and the first distance relationship are the position information; According to the first position relationship and the first distance relationship, the time period reflected by the first time interval is advanced on the basis of the sampling clock to obtain the sine envelope waveform and the cosine envelope waveform.

8. The demodulation circuit according to claim 7, wherein, The demodulation circuit is specifically configured to: In the case where it is determined according to the positive or negative situation that the phase information is a negative difference value, a second position relationship that the sampling position is ahead of the zero crossing position of the one excitation period is obtained according to the negative difference value, and a second distance relationship between the sampling position and the zero crossing position is obtained according to the second absolute value of the negative difference value, where the second position relationship and the second distance relationship are the position information; Based on the second positional relationship and the second distance relationship, delay the period reflected by the second time interval on the basis of the sampling clock to obtain the sine envelope waveform and the cosine envelope waveform.

9. The demodulation circuit according to claim 6, characterized in that, The demodulation circuit is specifically configured to: calculate the sum of the sampling signal at the target zero-crossing moment and the sampling signal at the target non-zero-crossing moment, and output to obtain the sine envelope waveform and the cosine envelope waveform; or, calculate the sum of the sampling signals at the target non-zero-crossing moments, and output to obtain the sine envelope waveform and the cosine envelope waveform.

10. A rotary digital converter, characterized in that, The rotation digital converter includes the demodulation circuit according to any one of claims 1 to 9.

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