Current mirror type gain bootstrap operational transconductance amplifier

Abstract

The present application proposes a current mirror type gain bootstrap operational transconductance amplifier, comprising: an input circuit receiving a differential input and providing an input transconductance; the current mirror circuit is used for amplifying the gain of the amplifier according to the mirror image proportion; the cascode gain bootstrap circuit is used for improving the output resistance of the current source mirror circuit, so that the gain of the amplifier is further expanded; and the tail current source is connected with the input circuit to provide stable reference current. The amplifier gain can be effectively improved, and the amplifier can be applied to various operational amplifier scenes.

Description

Technical Field

[0001] The invention relates to the field of integrated circuit applications, and in particular to a current mirror type gain bootstrap operational transconductance amplifier. Background Art

[0002] The traditional operational transconductance amplifier is an amplifier that converts voltage into current. It has a dual-end input and a single-end output. It can convert differential signals into single-end output signals. It is widely used in analog circuits such as analog-to-digital converters, filters, buffers, and linear regulators. It is one of the most important modules in analog circuits. The typical operational transconductance amplifier is a five-tube operational transconductance amplifier, which consists of five transistors. The input pair provides transconductance, the output resistance is small, and the total gain is small. The current mirror type operational transconductance amplifier adds a current mirror structure to its basis, which makes its gain increase by k times (k is the mirror ratio of the current mirror) with almost no loss of bandwidth. However, the gain of the traditional current mirror type operational transconductance amplifier is still relatively low, generally 30dB to 50dB. The insufficient gain of the operational amplifier will bring many problems to the circuit, such as introducing a large offset voltage and affecting the output accuracy of the circuit. Summary of the invention

[0003] In view of the above problems existing in the prior art, the present invention proposes a current mirror type gain bootstrap operational transconductance amplifier, which mainly solves the problem of low gain of the existing operational transconductance amplifier.

[0004] In order to achieve the above purpose and other purposes, the technical solution adopted by the present invention is as follows.

[0005] The present application proposes a current mirror type gain bootstrap operational transconductance amplifier, comprising: an input circuit, which receives a differential input and provides an input transconductance; a current mirror circuit, which is used to expand the amplifier gain according to the mirror ratio; a common source and common gate gain bootstrap circuit, which is used to increase the output resistance of the current source mirror circuit, so that the amplifier gain is further expanded; a tail current source, which is connected to the input circuit to provide a stable reference current.

[0006] In an embodiment of the present application, the tail current source includes: a first transistor, a drain of the first transistor is connected to the reference end of the input circuit, a source is grounded, and a gate is connected to a bias voltage.

[0007] In one embodiment of the present application, the common-source common-gate gain bootstrap circuit includes: a first gain bootstrap auxiliary circuit and a second gain bootstrap auxiliary circuit, the first gain bootstrap auxiliary circuit and the second gain bootstrap auxiliary circuit are respectively connected to the current mirror circuit, wherein the first gain bootstrap auxiliary circuit is an N-tube input type folded common-source common-gate circuit, and the second gain bootstrap auxiliary circuit is a P-tube input type folded common-source common-gate circuit.

[0008] In one embodiment of the present application, the input circuit includes a second transistor, a third transistor, a fourth transistor and a fifth transistor; the gate of the second transistor serves as the first input terminal of the input circuit, the gate of the third transistor serves as the second input terminal of the input circuit, the source of the second transistor is connected to the source of the third transistor as the reference terminal of the input circuit; the gate and drain of the fourth transistor are connected and then connected to the drain of the second transistor; the gate and drain of the fifth transistor are connected and then connected to the drain of the third transistor; the source of the fourth transistor is connected to the source of the fifth transistor and connected to the power supply voltage, wherein the input signals of the first input terminal and the second input terminal are differential signals.

[0009] In one embodiment of the present application, the current mirror circuit includes a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor and a thirteenth transistor; the source of the sixth transistor is connected to the source of the seventh transistor and connected to the power supply voltage; the gate of the sixth transistor is connected to the gate of the fourth transistor, and the gate of the seventh transistor is connected to the gate of the fifth transistor; the drain of the sixth transistor is connected to the source of the eighth transistor; the drain of the eighth transistor is connected to the drain of the tenth transistor, the source of the tenth transistor is connected to the drain of the twelfth transistor, the source of the twelfth transistor is connected to the source of the thirteenth transistor and then connected to ground; the gate of the twelfth transistor is connected to the gate of the thirteenth transistor and then connected to the drain of the eighth transistor; the source of the eleventh transistor is connected to the drain of the thirteenth transistor The drain of the ninth transistor is connected to the drain of the eleventh transistor as the output end of the amplifier, and the drain of the seventh transistor is connected to the source of the ninth transistor; the drain of the sixth transistor is connected to the inverting input end of the first gain bootstrap auxiliary circuit, the drain of the seventh transistor is connected to the non-inverting input end of the first gain bootstrap auxiliary circuit, the gate of the eighth transistor is connected to the positive power supply end of the first gain bootstrap auxiliary circuit, and the gate of the ninth transistor is connected to the negative power supply end of the first gain bootstrap auxiliary circuit; the gate of the tenth transistor is connected to the negative power supply end of the second gain bootstrap auxiliary circuit, and the gate of the eleventh transistor is connected to the positive power supply end of the second gain bootstrap auxiliary circuit; the drain of the twelfth transistor is connected to the non-inverting input end of the second gain bootstrap auxiliary circuit, and the drain of the thirteenth transistor is connected to the inverting input end of the second gain bootstrap auxiliary circuit.

[0010] In one embodiment of the present application, the first gain bootstrap auxiliary circuit includes: a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor and a twenty-fourth transistor; the gate of the fourteenth transistor is connected to a first bias voltage, the source is grounded, and the drain is connected to the sources of the fifteenth transistor and the sixteenth transistor; the gate of the fifteenth transistor serves as an inverting input terminal of the first gain bootstrap auxiliary circuit; the gate of the sixteenth transistor serves as a non-inverting input terminal of the first gain bootstrap auxiliary circuit; the drain of the fifteenth transistor is connected to the drain of the seventeenth transistor; the drain of the sixteenth transistor is connected to the drain of the eighteenth transistor; the source of the seventeenth transistor is connected to the source of the eighteenth transistor and connected to the power supply voltage; the gate of the seventeenth transistor is connected to the source of the seventeenth transistor and connected to the power supply voltage; The gate of the eighteenth transistor is connected; the drain of the seventeenth transistor is connected to the source of the nineteenth transistor, and the drain of the eighteenth transistor is connected to the source of the twentieth transistor; the gate of the nineteenth transistor is connected to the gate of the twentieth transistor; the drain of the nineteenth transistor is connected to the drain of the twenty-first transistor as the positive power supply terminal of the first gain bootstrap auxiliary circuit; the drain of the twentieth transistor is connected to the drain of the twenty-second transistor as the negative power supply terminal of the first gain bootstrap auxiliary circuit; the source of the twenty-first transistor is connected to the drain of the twenty-third transistor, and the source of the twenty-second transistor is connected to the drain of the twenty-fourth transistor; the gate of the twenty-first transistor is connected to the gate of the twenty-second transistor; the source of the twenty-third transistor is connected to the source of the twenty-fourth transistor and is grounded; the gate of the twenty-third transistor is connected to the gate of the twenty-fourth transistor.

[0011] In one embodiment of the present application, the second gain bootstrap auxiliary circuit includes: a twenty-fifth transistor, a twenty-sixth transistor, a twenty-seventh transistor, a twenty-eighth transistor, a twenty-ninth transistor, a thirtieth transistor, a thirty-first transistor, a thirty-second transistor, a thirty-third transistor, a thirty-fourth transistor and a thirty-fifth transistor; the gate of the twenty-fifth transistor is connected to the second bias voltage, the source is connected to the power supply voltage, and the drain is connected to the source of the twenty-sixth transistor and the twenty-seventh transistor; the gate of the twenty-sixth transistor serves as the non-inverting input terminal of the second gain bootstrap auxiliary circuit; the gate of the twenty-seventh transistor serves as the inverting input terminal of the second gain bootstrap auxiliary circuit; the drain of the twenty-sixth transistor is connected to the drain of the twenty-eighth transistor, and the drain of the twenty-seventh transistor is connected to the drain of the twenty-ninth transistor; the source of the twenty-eighth transistor is connected to the source of the twenty-ninth transistor and is grounded; the gate of the twenty-eighth transistor is connected to the second bias voltage, the source is connected to the power supply voltage, and the drain is connected to the source of the second transistor; The gate of the nineteenth transistor is connected; the drain of the twenty-eighth transistor is connected to the source of the thirtieth transistor, the drain of the twenty-ninth transistor is connected to the source of the thirty-first transistor, and the gate of the thirtieth transistor is connected to the gate of the thirty-first transistor; the drain of the thirtieth transistor is connected to the drain of the thirty-second transistor as the positive power supply terminal of the second gain bootstrap auxiliary circuit; the drain of the thirty-first transistor is connected to the drain of the thirty-third transistor as the negative power supply terminal of the second gain bootstrap auxiliary circuit; the gate of the thirty-second transistor is connected to the gate of the thirty-third transistor, and the source of the thirty-second transistor is connected to the drain of the thirty-fourth transistor; the source of the thirty-third transistor is connected to the drain of the thirty-fifth transistor, the gate of the thirty-fourth transistor is connected to the gate of the thirty-fifth transistor, and the source of the thirty-fourth transistor is connected to the source of the thirty-fifth transistor and connected to the power supply voltage.

[0012] As described above, the current mirror type gain bootstrap operational transconductance amplifier proposed in the present application has the following beneficial effects.

[0013] This application introduces a common-source and common-gate gain bootstrap circuit to greatly increase the output resistance of the current mirror circuit, thereby obtaining an operational transconductance amplifier with greater gain and differential input and single-ended output, which meets the requirements of most circuits for operational amplifiers and can be applied to various operational amplification scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 Schematic diagram of the circuit structure of a traditional current mirror operational transconductance amplifier.

[0015] Figure 2 Schematic diagram of the circuit structure of a current mirror type gain bootstrap operational transconductance amplifier according to an embodiment of the present application.

[0016] Figure 3 1 is a circuit diagram of a current mirror type gain bootstrap operational transconductance amplifier in one embodiment of the present application.

[0017] Figure 4 1 is a circuit schematic diagram of a first gain bootstrap auxiliary circuit A1 in an embodiment of the present application.

[0018] Figure 5 2 is a circuit schematic diagram of a second gain bootstrap auxiliary circuit A2 in an embodiment of the present application.

[0019] Description of Figure Numbers:

[0020] 01-input circuit; 02-current mirror circuit; 03-common source and common gate gain bootstrap circuit; 04-tail current source; A1-first gain bootstrap auxiliary circuit; A2-second gain bootstrap auxiliary circuit; M1-first transistor; M2-second transistor; M3-third transistor; M4-fourth transistor; M5-fifth transistor; M6-sixth transistor; M7-seventh transistor; M8-eighth transistor; M9-ninth transistor; M10-tenth transistor; M11-eleventh transistor; M12-twelfth transistor; M13-thirteenth transistor; M14-fourteenth transistor; M15-fifteenth transistor; M16-sixteenth transistor; M17- The seventeenth transistor; M18-the eighteenth transistor; M19-the nineteenth transistor; M20-the twentieth transistor; M21-the twenty-first transistor; M22-the twenty-second transistor; M23-the twenty-third transistor; M24-the twenty-fourth transistor; M25-the twenty-fifth transistor; M26-the twenty-sixth transistor; M27-the twenty-seventh transistor; M28-the twenty-eighth transistor; M29-the twenty-ninth transistor; M30-the thirtieth transistor; M31-the thirty-first transistor; M32-the thirty-second transistor; M33-the thirty-third transistor; M34-the thirty-fourth transistor; M35-the thirty-fifth transistor; vdd-power supply voltage. DETAILED DESCRIPTION

[0021] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0022] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0023] The inventors have found that:

[0024] The typical operational transconductance amplifier is a five-transistor operational transconductance amplifier, which consists of five transistors. The input pair of transistors provides transconductance, the output resistance is small, and the circuit gain is small. See Figure 1 , Figure 1 The circuit structure diagram of the traditional current mirror operational transconductance amplifier is shown in Figure 2. The current mirror operational transconductance amplifier adds a current mirror structure to its basis, which makes its gain increase by k times (k is the mirror ratio of the current mirror) without losing bandwidth. Figure 1 As shown. The gain of the current mirror operational transconductance amplifier is approximately gm2*k*(ro7 / / ro13). Among them, gm2 is the transconductance of transistor M2, ro7 and ro13 are the equivalent resistances of transistors M7 and M13 respectively. However, the gain of the traditional current mirror operational transconductance amplifier is still relatively low, generally 30dB to 50dB. The insufficient gain of the operational amplifier will bring many problems to the circuit, such as introducing a large offset voltage and affecting the output accuracy of the circuit.

[0025] Based on the above shortcomings of traditional operational amplifiers, the present application proposes a current mirror type gain bootstrap operational transconductance amplifier. The technical solution of the present application is described in detail below in conjunction with specific embodiments.

[0026] See also Figure 2 , Figure 2 The circuit architecture diagram of a current mirror type gain bootstrap operational transconductance amplifier according to an embodiment of the present application is shown in FIG. The current mirror type gain bootstrap operational transconductance amplifier provided in the present application includes: an input circuit 01, which receives a differential input and provides an input transconductance; a current mirror circuit 02, which is used to expand the amplifier gain according to the mirror ratio; a common source and common gate gain bootstrap circuit 03, which is used to increase the output resistance of the current source mirror circuit so that the amplifier gain is further expanded; and a tail current source 04, which is connected to the input circuit 01 to provide a stable reference current.

[0027] See also Figure 3 , Figure 3 The circuit schematic diagram of the current mirror type gain bootstrap operational transconductance amplifier in one embodiment of the present application is shown in FIG. In one embodiment, the tail current source 04 includes: a first transistor M1, the drain of the first transistor M1 is connected to the reference terminal of the input circuit 01, the source is grounded gnd, and the gate is connected to the bias voltage.

[0028] In one embodiment, the common-source common-gate gain bootstrap circuit 03 includes: a first gain bootstrap auxiliary circuit A1 and a second gain bootstrap auxiliary circuit A2, wherein the first gain bootstrap auxiliary circuit A1 and the second gain bootstrap auxiliary circuit A2 are respectively connected to the current mirror circuit 02, wherein the first gain bootstrap auxiliary circuit A1 is an N-tube input type folded common-source common-gate circuit, and the second gain bootstrap auxiliary circuit A2 is a P-tube input type folded common-source common-gate circuit.

[0029] In one embodiment, the input circuit 01 includes a second transistor M2, a third transistor M3, a fourth transistor M4 and a fifth transistor M5; the gate of the second transistor M2 serves as the first input terminal of the input circuit 01, the gate of the third transistor M3 serves as the second input terminal of the input circuit 01, the source of the second transistor M2 is connected to the source of the third transistor M3 as the reference terminal of the input circuit 01; the gate and drain of the fourth transistor M4 are connected and then connected to the drain of the second transistor M2; the gate and drain of the fifth transistor M5 are connected and then connected to the drain of the third transistor M3; the source of the fourth transistor M4 is connected to the source of the fifth transistor M5 and connected to the power supply voltage vdd, wherein the input signals of the first input terminal Vp and the second input terminal Vn are differential signals.

[0030] In one embodiment, the current mirror circuit 02 includes a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12 and a thirteenth transistor M13; the source of the sixth transistor M6 is connected to the source of the seventh transistor M7 and connected to the power supply voltage vdd; the gate of the sixth transistor M6 is connected to the gate of the fourth transistor M4, and the gate of the seventh transistor M7 is connected to the gate of the fifth transistor M5; the drain of the sixth transistor M6 is connected to the source of the eighth transistor M8; the drain of the eighth transistor M8 is connected to the drain of the tenth transistor M10, the source of the tenth transistor M10 is connected to the drain of the twelfth transistor M12, the source of the twelfth transistor M12 is connected to the source of the thirteenth transistor M13 and then connected to the ground gnd; the gate of the twelfth transistor M12 is connected to the gate of the thirteenth transistor M13 and then connected to the drain of the eighth transistor M8; the source of the eleventh transistor M11 is connected to the drain of the eighth transistor M8; The drain of the thirteenth transistor M13 is connected; the drain of the ninth transistor M9 is connected to the drain of the eleventh transistor M11 as the output end of the amplifier, and the drain of the seventh transistor M7 is connected to the source of the ninth transistor M9; the drain of the sixth transistor M6 is connected to the inverting input end of the first gain bootstrap auxiliary circuit A1, the drain of the seventh transistor M7 is connected to the non-inverting input end of the first gain bootstrap auxiliary circuit A1, the gate of the eighth transistor M8 is connected to the positive power supply end of the first gain bootstrap auxiliary circuit A1, and the gate of the ninth transistor M9 is connected to the negative power supply end of the first gain bootstrap auxiliary circuit A1; the gate of the tenth transistor M10 is connected to the negative power supply end of the second gain bootstrap auxiliary circuit A2, and the gate of the eleventh transistor M11 is connected to the positive power supply end of the second gain bootstrap auxiliary circuit A2; the drain of the twelfth transistor M12 is connected to the non-inverting input end of the second gain bootstrap auxiliary circuit A2, and the drain of the thirteenth transistor M13 is connected to the inverting input end of the second gain bootstrap auxiliary circuit A2.

[0031] See also Figure 4 , Figure 41 is a circuit schematic diagram of the first gain bootstrap auxiliary circuit A1 in one embodiment of the present application. In one embodiment, the first gain bootstrap auxiliary circuit A1 includes: a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, a nineteenth transistor M19, a twentieth transistor M20, a twenty-first transistor M21, a twenty-second transistor M22, a twenty-third transistor M23 and a twenty-fourth transistor M24; the gate of the fourteenth transistor M14 is connected to the first bias voltage Vb1, the source is connected to the ground gnd, and the drain is connected to the source of the fifteenth transistor M15 and the sixteenth transistor M16. The gate of the fifteenth transistor M15 serves as the inverting input terminal Vp1 of the first gain bootstrap auxiliary circuit A1; the gate of the sixteenth transistor M16 serves as the non-inverting input terminal Vn1 of the first gain bootstrap auxiliary circuit A1; the drain of the fifteenth transistor M15 is connected to the drain of the seventeenth transistor M17; the drain of the sixteenth transistor M16 is connected to the drain of the eighteenth transistor M18; the source of the seventeenth transistor M17 is connected to the source of the eighteenth transistor M18 and is connected to the power supply voltage vdd; the gate of the seventeenth transistor M17 is connected to the drain of the seventeenth transistor M18 ...7; the gate of the seventeenth transistor M17 is connected to the drain of the seventeenth transistor M17; the gate of the seventeenth transistor M17 is connected to the drain of The gate of the eighteenth transistor M18 is connected; the drain of the seventeenth transistor M17 is connected to the source of the nineteenth transistor M19, and the drain of the eighteenth transistor M18 is connected to the source of the twentieth transistor M20; the gate of the nineteenth transistor M19 is connected to the gate of the twentieth transistor M20; the drain of the nineteenth transistor M19 and the drain of the twenty-first transistor M21 are connected as the positive power supply terminal Von1 of the first gain bootstrap auxiliary circuit A1; the drain of the twentieth transistor M20 and the drain of the twenty-second transistor M22 are connected As the negative power supply terminal Vop1 of the first gain bootstrap auxiliary circuit A1; the source of the 21st transistor M21 is connected to the drain of the 23rd transistor M23, the source of the 22nd transistor M22 is connected to the drain of the 24th transistor M24; the gate of the 21st transistor M21 is connected to the gate of the 22nd transistor M22; the source of the 23rd transistor M23 is connected to the source of the 24th transistor M24 and is grounded to gnd; the gate of the 23rd transistor M23 is connected to the gate of the 24th transistor M24. Among them, the first bias voltage can be configured and adjusted according to actual circuit requirements, and is not limited here.

[0032] See also Figure 5 , Figure 5The circuit schematic diagram of the second gain bootstrap auxiliary circuit A2 in an embodiment of the present application. The second gain bootstrap auxiliary circuit A2 includes: a twenty-fifth transistor M25, a twenty-sixth transistor M26, a twenty-seventh transistor M27, a twenty-eighth transistor M28, a twenty-ninth transistor M29, a thirtieth transistor M30, a thirty-first transistor M31, a thirty-second transistor M32, a thirty-third transistor M33, a thirty-fourth transistor M34 and a thirty-fifth transistor M35; the gate of the twenty-fifth transistor M25 is connected to the second bias voltage Vb2, the source is connected to the power supply voltage vdd, and the drain is connected to the source of the twenty-sixth transistor M26 and the twenty-seventh transistor M27; The gate of the 26th transistor M26 serves as the non-inverting input terminal Vp2 of the second gain bootstrap auxiliary circuit A2; the gate of the 27th transistor M27 serves as the inverting input terminal Vn2 of the second gain bootstrap auxiliary circuit A2; the drain of the 26th transistor M26 is connected to the drain of the 28th transistor M28, and the drain of the 27th transistor M27 is connected to the drain of the 29th transistor M29; the source of the 28th transistor M28 is connected to the source of the 29th transistor M29 and is grounded gnd; the gate of the 28th transistor M28 is connected to the 29th transistor M29 and is grounded gnd; the gate of the 28th transistor M28 is connected to the 29th transistor M29 and is grounded gnd. The drain of the 28th transistor M28 is connected to the source of the 30th transistor M30, the drain of the 29th transistor M29 is connected to the source of the 31st transistor M31, and the gate of the 30th transistor M30 is connected to the gate of the 31st transistor M31; the drain of the 30th transistor M30 is connected to the drain of the 32nd transistor M32 as the positive power supply terminal Von2 of the second gain bootstrap auxiliary circuit A2; the drain of the 31st transistor M31 is connected to the drain of the 33rd transistor M33 as The negative power supply terminal Vop2 of the second gain bootstrap auxiliary circuit A2 is connected; the gate of the thirty-second transistor M32 is connected to the gate of the thirty-third transistor M33, and the source of the thirty-second transistor M32 is connected to the drain of the thirty-fourth transistor M34; the source of the thirty-third transistor M33 is connected to the drain of the thirty-fifth transistor M35, the gate of the thirty-fourth transistor M34 is connected to the gate of the thirty-fifth transistor M35, and the source of the thirty-fourth transistor M34 is connected to the source of the thirty-fifth transistor M35 and connected to the power supply voltage vdd. The second bias voltage can be configured and adjusted according to actual circuit requirements, and is not limited here.

[0033] Specifically, the current mirror type gain bootstrap operational transconductance amplifier of the embodiment of the present application adds a common source and common gate circuit structure on the basis of the current mirror type operational transconductance amplifier to provide a high output resistance, and the output resistance is reduced from (r o7 / / ro13 ) increased to (g m9 r o9 r o7 ) / / (g m11 r o11 r o13 The core circuit of the gain bootstrap circuit is two gain bootstrap auxiliary circuits. Both gain bootstrap auxiliary circuits A1 and A2 are designed as folded cascode structures, so that the gain bootstrap auxiliary circuits have relatively high gain and bandwidth. A1 is an N-tube input type folded cascode circuit, and A2 is a P-tube input type folded cascode circuit. The gain bootstrap circuit increases the gain (A v1 / / A v2 ) times(A v1 and A v2 Auxiliary amplifier A 1 and A 2 The total gain of the final circuit is approximately g m2 *k*[(g m9 r o9 r o7 )A v1 / / (g m11 r o11 r o13 )A v2 ], and obtain an ultra-high gain differential input, single-ended output operational transconductance amplifier. Among them, g m2 , g m9 , g m11 The transistor M 2 , M 9 , M 11 The transconductance, r o7 , r o9 , r o11 , r o13 The transistor M 7 , M 9 , M 11 , M 13 The current mirror type gain bootstrap operational transconductance amplifier meets the requirements of most circuits for operational amplifiers and can be directly applied to various occasions.

[0034] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A current mirror type gain bootstrap operational transconductance amplifier, characterized in that: include: an input circuit that receives a differential input and provides an input transconductance; A current mirror circuit for amplifying the amplifier gain according to the mirror ratio; A cascode gain bootstrap circuit, which is used to increase the output resistance of the current source mirror circuit so that the amplifier gain is further increased; A tail current source is connected to the input circuit to provide a stable reference current.

2. The current mirror type gain bootstrap operational transconductance amplifier according to claim 1, characterized in that: The tail current source comprises: a first transistor, a drain of the first transistor is connected to the reference end of the input circuit, a source of the first transistor is grounded, and a gate of the first transistor is connected to a bias voltage.

3. The current mirror type gain bootstrap operational transconductance amplifier according to claim 1, characterized in that: The common-source common-gate gain bootstrap circuit includes: a first gain bootstrap auxiliary circuit and a second gain bootstrap auxiliary circuit, the first gain bootstrap auxiliary circuit and the second gain bootstrap auxiliary circuit are respectively connected to the current mirror circuit, wherein the first gain bootstrap auxiliary circuit is an N-tube input type folded common-source common-gate circuit, and the second gain bootstrap auxiliary circuit is a P-tube input type folded common-source common-gate circuit.

4. The current mirror type gain bootstrap operational transconductance amplifier according to claim 3, characterized in that: The input circuit includes a second transistor, a third transistor, a fourth transistor and a fifth transistor; the gate of the second transistor serves as the first input terminal of the input circuit, the gate of the third transistor serves as the second input terminal of the input circuit, the source of the second transistor is connected to the source of the third transistor as the reference terminal of the input circuit; the gate and drain of the fourth transistor are connected and then connected to the drain of the second transistor; the gate and drain of the fifth transistor are connected and then connected to the drain of the third transistor; the source of the fourth transistor is connected to the source of the fifth transistor and connected to the power supply voltage, wherein the input signals of the first input terminal and the second input terminal are differential signals.

5. The current mirror type gain bootstrap operational transconductance amplifier according to claim 4, characterized in that: The current mirror circuit includes a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor and a thirteenth transistor; The source of the sixth transistor is connected to the source of the seventh transistor and connected to the power supply voltage; the gate of the sixth transistor is connected to the gate of the fourth transistor, and the gate of the seventh transistor is connected to the gate of the fifth transistor; the drain of the sixth transistor is connected to the source of the eighth transistor; the drain of the eighth transistor is connected to the drain of the tenth transistor, the source of the tenth transistor is connected to the drain of the twelfth transistor, the source of the twelfth transistor is connected to the source of the thirteenth transistor and then connected to ground; the gate of the twelfth transistor is connected to the gate of the thirteenth transistor and then connected to the drain of the eighth transistor; the source of the eleventh transistor is connected to the drain of the thirteenth transistor; the drain of the ninth transistor is connected to the drain of the eleventh transistor as the amplifier The output end, the drain of the seventh transistor is connected to the source of the ninth transistor; the drain of the sixth transistor is connected to the inverting input end of the first gain bootstrap auxiliary circuit, the drain of the seventh transistor is connected to the non-inverting input end of the first gain bootstrap auxiliary circuit, the gate of the eighth transistor is connected to the positive power supply end of the first gain bootstrap auxiliary circuit, and the gate of the ninth transistor is connected to the negative power supply end of the first gain bootstrap auxiliary circuit; the gate of the tenth transistor is connected to the negative power supply end of the second gain bootstrap auxiliary circuit, and the gate of the eleventh transistor is connected to the positive power supply end of the second gain bootstrap auxiliary circuit; the drain of the twelfth transistor is connected to the non-inverting input end of the second gain bootstrap auxiliary circuit, and the drain of the thirteenth transistor is connected to the inverting input end of the second gain bootstrap auxiliary circuit.

6. The current mirror type gain bootstrap operational transconductance amplifier according to claim 5, characterized in that: The first gain bootstrap auxiliary circuit includes: a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor and a twenty-fourth transistor; The gate of the fourteenth transistor is connected to the first bias voltage, the source is grounded, and the drain is connected to the sources of the fifteenth transistor and the sixteenth transistor; the gate of the fifteenth transistor serves as the inverting input terminal of the first gain bootstrap auxiliary circuit; the gate of the sixteenth transistor serves as the non-inverting input terminal of the first gain bootstrap auxiliary circuit; the drain of the fifteenth transistor is connected to the drain of the seventeenth transistor; the drain of the sixteenth transistor is connected to the drain of the eighteenth transistor; the source of the seventeenth transistor is connected to the source of the eighteenth transistor and connected to the power supply voltage; the gate of the seventeenth transistor is connected to the gate of the eighteenth transistor; the drain of the seventeenth transistor is connected to the source of the nineteenth transistor, and the drain of the eighteenth transistor is connected to the source of the twenty-third transistor. The gate of the nineteenth transistor is connected to the gate of the twentieth transistor; the drain of the nineteenth transistor is connected to the drain of the twenty-first transistor as the positive power terminal of the first gain bootstrap auxiliary circuit; the drain of the twentieth transistor is connected to the drain of the twenty-second transistor as the negative power terminal of the first gain bootstrap auxiliary circuit; the source of the twenty-first transistor is connected to the drain of the twenty-third transistor, and the source of the twenty-second transistor is connected to the drain of the twenty-fourth transistor; the gate of the twenty-first transistor is connected to the gate of the twenty-second transistor; the source of the twenty-third transistor is connected to the source of the twenty-fourth transistor and is grounded; the gate of the twenty-third transistor is connected to the gate of the twenty-fourth transistor.

7. The current mirror type gain bootstrap operational transconductance amplifier according to claim 5, characterized in that: The second gain bootstrap auxiliary circuit includes: a twenty-fifth transistor, a twenty-sixth transistor, a twenty-seventh transistor, a twenty-eighth transistor, a twenty-ninth transistor, a thirtieth transistor, a thirty-first transistor, a thirty-second transistor, a thirty-third transistor, a thirty-fourth transistor and a thirty-fifth transistor; The gate of the twenty-fifth transistor is connected to the second bias voltage, the source is connected to the power supply voltage, and the drain is connected to the sources of the twenty-sixth transistor and the twenty-seventh transistor; the gate of the twenty-sixth transistor serves as the non-inverting input terminal of the second gain bootstrap auxiliary circuit; the gate of the twenty-seventh transistor serves as the inverting input terminal of the second gain bootstrap auxiliary circuit; the drain of the twenty-sixth transistor is connected to the drain of the twenty-eighth transistor, and the drain of the twenty-seventh transistor is connected to the drain of the twenty-ninth transistor; the source of the twenty-eighth transistor is connected to the source of the twenty-ninth transistor and is grounded; the gate of the twenty-eighth transistor is connected to the gate of the twenty-ninth transistor; the drain of the twenty-eighth transistor is connected to the source of the thirtieth transistor, and the drain of the twenty-ninth transistor is connected to the thirtieth transistor. The source of the 30th transistor is connected to the source of the 31st transistor, the gate of the 30th transistor is connected to the gate of the 31st transistor; the drain of the 30th transistor is connected to the drain of the 32nd transistor as the positive power terminal of the second gain bootstrap auxiliary circuit; the drain of the 31st transistor is connected to the drain of the 33rd transistor as the negative power terminal of the second gain bootstrap auxiliary circuit; the gate of the 32nd transistor is connected to the gate of the 33rd transistor, and the source of the 32nd transistor is connected to the drain of the 34th transistor; the source of the 33rd transistor is connected to the drain of the 35th transistor, the gate of the 34th transistor is connected to the gate of the 35th transistor, and the source of the 34th transistor is connected to the source of the 35th transistor and connected to the power supply voltage.

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