Ultrahigh voltage-resistant digital isolator, packaging structure and manufacturing method

Abstract

The invention provides an ultrahigh voltage-resistant digital isolator, a packaging structure and a manufacturing method, and belongs to the technical field of isolator packaging. The ultrahigh voltage-withstanding digital isolator comprises a quartz wafer substrate; the first digital isolation chip, the second digital isolation chip, the first coupling transmission unit and the second coupling transmission unit form a coupling transmission structure; a first interconnection structure and a second interconnection structure, and an insulating layer. The first coupling transmission unit, the first digital isolation chip and the first interconnection structure form a first power domain region, the second coupling transmission unit, the second digital isolation chip and the second interconnection structure form a second power domain region, and a high-voltage isolation gate is formed between the first power domain region and the second power domain region. Through a wafer reconstruction technology, quartz glass is adopted as a wafer substrate, the voltage withstanding capability is remarkably improved and reaches 50000 V or above, and compared with a winding transformer, on the premise that the ultrahigh voltage withstanding requirement is met, the size and the weight of a product are greatly reduced, and miniaturization and light weight of a terminal product are achieved.

Description

Technical Field

[0001] The present invention belongs to the technical field of isolator packaging, and in particular relates to an ultra-high withstand voltage digital isolator, a packaging structure, and a manufacturing method. Background Art

[0002] In the prior art, digital isolators are usually electromagnetically coupled and capacitively coupled. A wafer passivation layer or polyimide is used to isolate the voltage between the electromagnetic coil or the capacitor plates. The wafer passivation layer is usually silicon dioxide and silicon nitride. Due to process capability limitations, the processable thickness of the passivation layer and polyimide is limited. The current voltage withstand capability of the isolator is 5000V, which cannot meet the needs of some ultra-high voltage application environments.

[0003] Moreover, in the traditional ultra-high withstand voltage isolation application environment, the signal is isolated through a winding transformer, which is large in size and weight, and cannot achieve the miniaturization, lightweight and integration of the terminal product. Summary of the invention

[0004] The present disclosure aims to solve at least one of the technical problems existing in the prior art and provide an ultra-high withstand voltage digital isolator and a packaging structure and a manufacturing method.

[0005] In one aspect of the present disclosure, an ultra-high withstand voltage digital isolator is provided, comprising:

[0006] Quartz wafer substrate;

[0007] A first digital isolation chip and a second digital isolation chip are arranged on the first surface of the quartz wafer substrate with a relative spacing;

[0008] A first coupling transmission unit and a second coupling transmission unit, both of which are respectively arranged on the second surface and the first surface of the quartz wafer substrate, and the first coupling transmission unit and the second coupling transmission unit constitute a coupling transmission structure;

[0009] The first digital isolation chip and the second digital isolation chip realize isolated transmission of signals through the coupled transmission structure;

[0010] a first interconnection structure and a second interconnection structure, wherein the first interconnection structure is used to electrically connect the first digital isolation chip to the first coupling transmission unit and the first external circuit respectively, and the second interconnection structure is used to electrically connect the second digital isolation chip to the second coupling transmission unit and the second external circuit respectively;

[0011] An insulating layer is disposed on the first surface and the second surface of the quartz wafer substrate to wrap the first digital isolation chip, the second digital isolation chip, the first coupling transmission unit, the second coupling transmission unit, the first interconnection structure and the second interconnection structure;

[0012] The first coupling transmission unit, the first digital isolation chip and the first interconnection structure form a first power domain area, the second coupling transmission unit, the second digital isolation chip and the second interconnection structure form a second power domain area, and a high-voltage isolation barrier is formed between the first power domain area and the second power domain area.

[0013] Optionally, the first coupling transmission unit and the second coupling transmission unit are capacitor plates; or,

[0014] The first coupling transmission unit and the second coupling transmission unit are electromagnetic coils; or,

[0015] The first coupling transmission unit and the second coupling transmission unit are giant magnetoresistance.

[0016] Optionally, the insulating layer includes a plurality of upper insulating layers stacked on the first surface of the quartz wafer substrate, and at least one lower insulating layer disposed on the second surface of the quartz wafer substrate;

[0017] The first interconnect structure includes a first inner interconnect structure and a first outer interconnect structure; wherein the first inner interconnect structure is wrapped in the upper insulating layer, the quartz wafer substrate and the lower insulating layer and is used to electrically connect the first digital isolation chip and the first coupling transmission unit, and the first outer interconnect structure is wrapped in the upper insulating layer and is used to electrically connect the first digital isolation chip and the first external circuit;

[0018] The second interconnection structure includes a second inner interconnection structure and a second outer interconnection structure; wherein the second inner interconnection structure is wrapped in the upper insulating layer and is used to electrically connect the second digital isolation chip and the second coupling transmission unit, and the second outer interconnection structure is wrapped in the upper insulating layer and is used to electrically connect the second digital isolation chip and the second external circuit.

[0019] Optionally, the first internal interconnection structure includes a first internal conductive portion provided on the first digital isolation chip, the first surface and the second surface of the quartz wafer substrate, the upper insulating layer, and the lower insulating layer, and a first internal conductive column electrically connecting the first internal conductive portions and the first internal conductive portion and the first coupling transmission unit; wherein,

[0020] The first inner conductive portion located on the first surface of the quartz wafer substrate and the second coupling transmission unit form a lateral high-voltage isolation grid.

[0021] Optionally, a creepage extension structure is further provided between the first inner conductive portion on the first surface of the quartz wafer substrate and the second coupling transmission unit.

[0022] Optionally, the lateral pressure-resistant structure is at least one protruding structure disposed on the first surface of the quartz wafer substrate.

[0023] Optionally, one of the first digital isolation chip and the second digital isolation chip serves as a transmitting end, and the other of the first digital isolation chip and the second digital isolation chip serves as a receiving end; or, both the first digital isolation chip and the second digital isolation chip can serve as a transmitting end and a receiving end, and when one of the digital isolation chips serves as a receiving end, the other digital isolation chip serves as a transmitting end.

[0024] Optionally, the insulating layer is polyimide.

[0025] Another aspect of the present disclosure provides an ultra-high withstand voltage digital isolator packaging structure, the ultra-high withstand voltage digital isolator packaging structure comprising:

[0026] Package substrate,

[0027] The ultra-high withstand voltage digital isolator described above is arranged on the packaging substrate;

[0028] A packaging layer, used for packaging the ultra-high withstand voltage digital isolator on the packaging substrate;

[0029] Two electrical signal lead-out components, one of which is electrically connected to the first interconnection structure, and the other of which is electrically connected to the second interconnection structure.

[0030] Another aspect of the present disclosure provides a method for manufacturing an ultra-high withstand voltage digital isolator, the manufacturing method comprising:

[0031] Providing quartz wafer substrates;

[0032] Disposing a first digital isolation chip and a second digital isolation chip on the first surface of the quartz wafer substrate at intervals;

[0033] Forming a first metallization layer and a second metallization layer on the second surface and the first surface of the quartz wafer substrate respectively, and forming a first coupling transmission unit and a second coupling transmission unit respectively by etching;

[0034] forming an insulating layer on the first coupling transmission unit, the second coupling transmission unit, and the first surface and the second surface of the quartz wafer substrate;

[0035] A first interconnection structure and a second interconnection structure are formed in the insulating layer and the quartz wafer substrate, the first interconnection structure is used to electrically connect the first digital isolation chip with the first coupling transmission unit and the first external circuit respectively, and the second interconnection structure is used to electrically connect the second digital isolation chip with the second coupling transmission unit and the second external circuit respectively.

[0036] The present disclosure proposes an ultra-high withstand voltage digital isolator and packaging structure, and a manufacturing method. Among them, the ultra-high withstand voltage digital isolator includes: a quartz wafer substrate; a first digital isolation chip and a second digital isolation chip, a first coupling transmission unit and a second coupling transmission unit forming a coupling transmission structure; a first interconnection structure and a second interconnection structure, and an insulating layer. The first coupling transmission unit, the first digital isolation chip, and the first interconnection structure form a first power domain area, the second coupling transmission unit, the second digital isolation chip, and the second interconnection structure form a second power domain area, and a high-voltage isolation gate is formed between the first power domain area and the second power domain area. The present disclosure adopts quartz glass as a wafer substrate through wafer reconstruction technology, which can increase the processing thickness of the silicon dioxide dielectric layer, and has a significant improvement in the withstand voltage capability compared to conventional digital isolators, which can reach more than 50,000V, and under the premise of meeting the ultra-high withstand voltage, compared with the winding transformer, it can greatly reduce the product volume and weight, and realize the miniaturization and lightweight of the terminal product. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 Schematic diagram of an ultra-high withstand voltage digital isolator according to Embodiment 1 of the present disclosure;

[0038] Figure 2 A schematic diagram of dielectric distance in an ultra-high withstand voltage digital isolator according to Embodiment 2 of the present disclosure;

[0039] Figure 3 It is a schematic diagram of the ultra-high withstand voltage digital isolator packaging structure of Example 3 of the present disclosure;

[0040] Figure 4 A schematic diagram of the dielectric distance in the ultra-high withstand voltage digital isolator packaging structure of Embodiment 4 of the present disclosure;

[0041] Figure 5 Schematic diagram of a method for manufacturing an ultra-high withstand voltage digital isolator according to Embodiment 5 of the present disclosure;

[0042] Figure 6 This is a flowchart of a method for manufacturing an ultra-high withstand voltage digital isolator according to Embodiment 5 of the present disclosure. DETAILED DESCRIPTION

[0043] In order to enable those skilled in the art to better understand the technical solution of the present disclosure, the present disclosure is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. It should be understood that the specific embodiments described herein are only used to explain the present disclosure and are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0044] Example 1

[0045] This example shows the specific structure of an ultra-high voltage digital isolator. Figure 1 As shown, the ultra-high withstand voltage digital isolator includes: a quartz wafer substrate 102; a first digital isolation chip 101a and a second digital isolation chip 101b, which are arranged on the first surface of the quartz wafer substrate 102 at a relative interval; a first coupling transmission unit 106g and a second coupling transmission unit 106d, which are respectively arranged on the second surface and the first surface of the quartz wafer substrate 102, and the first coupling transmission unit 106g and the second coupling transmission unit 106d constitute a coupling transmission structure; the first digital isolation chip 101a and the second digital isolation chip 101b realize signal isolation transmission through the coupling transmission structure; a first interconnection structure and a second interconnection structure, the first interconnection structure is used to connect the first digital isolation chip 101a to the first coupling transmission unit 106g and the first external The first and second external circuits are electrically connected, and the second interconnection structure is used to electrically connect the second digital isolation chip 101b to the second coupling transmission unit 106d and the second external circuit respectively; the insulating layer is arranged on the first surface and the second surface of the quartz wafer substrate 102 to wrap the first digital isolation chip 101a, the second digital isolation chip 101b, the first coupling transmission unit 106g, the second coupling transmission unit 106d, the first interconnection structure and the second interconnection structure; the first coupling transmission unit 106g, the first digital isolation chip 101a and the first interconnection structure form a first power domain area, the second coupling transmission unit 106d, the second digital isolation chip 101b and the second interconnection structure form a second power domain area, and a high-voltage isolation barrier is formed between the first power domain area and the second power domain area.

[0046] In this embodiment 1, through wafer reconstruction technology and the use of quartz wafer substrate, the processing thickness of the silicon dioxide dielectric layer can be increased, thereby increasing the voltage resistance of the isolator, and realizing the packaging of ultra-high voltage digital isolators with a voltage resistance of more than 50,000V. At the same time, under the premise of meeting the ultra-high voltage resistance, compared with the winding transformer, the product volume and weight can be greatly reduced, thereby realizing the miniaturization and lightweight of the terminal product.

[0047] It should be noted that, in this embodiment, one of the first digital isolation chip and the second digital isolation chip can be used as a transmitter, and the other of the first digital isolation chip and the second digital isolation chip can be used as a receiver, so that the signal is transmitted unidirectionally from the transmitter to the receiver. For example, when the first digital isolation chip is used as a transmitter, the second digital isolation chip can be used as a receiver, and at this time, the signal is transmitted from the first digital isolation chip to the second digital isolation chip; for another example, when the second digital isolation chip is used as a transmitter, the first digital isolation chip can be used as a receiver, and at this time, the signal is transmitted from the second digital isolation chip to the first digital isolation chip.

[0048] It should be further explained that the first digital isolation chip and the second digital isolation chip in this embodiment can also be used as a transmitting end and a receiving end, and when one digital isolation chip is used as a receiving end, it corresponds to the other digital isolation chip as a transmitting end. In other words, both digital isolation chips can send and receive signals. At the same time, one chip sends a signal and the other chip receives a signal, forming a "one-send, one-receive" bidirectional transmission.

[0049] It should be understood that when the first digital isolation chip is used as a transmitting end, the first external circuit connected to the first interconnection structure should be an input signal source circuit, and when the second digital isolation chip is used as a receiving end, the second external circuit connected to the second interconnection structure should be an output signal receiving circuit. Similarly, when the first digital isolation chip is used as a receiving end, the first external circuit connected to the first interconnection structure should be an output signal receiving circuit, and when the second digital isolation chip is used as a transmitting end, the second external circuit connected to the second interconnection structure should be an input signal source circuit.

[0050] Furthermore, if Figure 1 As shown, in this embodiment, the first digital isolation chip 101a and the second digital isolation chip 101b are each one. Of course, this is only an exemplary description. In other embodiments, the first digital isolation chip and the second digital isolation chip can also be multiple, and the first digital isolation chip and the second digital isolation chip are arranged one by one. In addition, the first digital isolation chip and the second digital isolation chip themselves can be single isolation channels or multiple isolation channels to realize single-channel transmission or multi-channel transmission of data.

[0051] Furthermore, if Figure 1 As shown, the first digital isolation chip 101a and the second digital isolation chip 101b in this embodiment are arranged in the cavity of the quartz wafer substrate 102. Of course, the first digital isolation chip and the second digital isolation chip can also be directly arranged on the quartz wafer substrate.

[0052] It should be noted that the high-voltage isolation gate formed between the first power domain area and the second power domain area of ​​this embodiment includes a longitudinal high-voltage isolation gate and a transverse high-voltage isolation gate to increase the longitudinal and transverse breakdown voltages and enhance the withstand voltage capability of the isolator. Among them, the longitudinal high-voltage isolation gate is formed by a quartz wafer substrate longitudinally spaced between two coupled transmission units, and the transverse high-voltage isolation gate is formed by a dielectric laterally spaced between two power domain areas.

[0053] Specifically, Figure 1 As shown, a quartz wafer substrate 102 is arranged between the first coupling transmission unit 106g and the second coupling transmission unit 106d, thereby forming a longitudinal high-voltage isolation barrier between the first coupling transmission unit 106g and the second coupling transmission unit 106d. Compared with conventional digital isolators, the longitudinal insulating medium is replaced with quartz glass in this embodiment, which can be processed with increased thickness and significantly improved voltage resistance, which can reach more than 50,000V.

[0054] It should be understood that the first coupling transmission unit and the second coupling transmission unit may be capacitor plates to form capacitive coupling; may be electromagnetic coils to form inductive coupling; or may be giant magnetoresistance to form magnetic coupling.

[0055] like Figure 1 As shown, the first coupling transmission unit 106g and the second coupling transmission unit 106d in this embodiment 1 are capacitor plates, that is, the first coupling transmission unit 106g is one of the capacitor plates, and the second coupling transmission unit 106d is the other capacitor plate, forming a capacitive coupling structure to achieve isolated transmission of signals.

[0056] It should be noted that the first coupling transmission unit and the second coupling transmission unit given in this embodiment 1 are only exemplary illustrations. In other preferred embodiments, the first coupling transmission unit and the second coupling transmission unit are electromagnetic coils, that is, the first coupling transmission unit is one of the electromagnetic coils, and the second coupling transmission unit is the other electromagnetic coil, forming an inductive coupling structure to achieve isolated transmission of signals.

[0057] Furthermore, the insulating layer includes a plurality of upper insulating layers stacked on the first surface of the quartz wafer substrate, and at least one lower insulating layer arranged on the second surface of the quartz wafer substrate; the first interconnection structure includes a first inner interconnection structure and a first outer interconnection structure; wherein the first inner interconnection structure is wrapped in the upper insulating layer, the quartz wafer substrate and the lower insulating layer and is used to electrically connect the first digital isolation chip with the first coupling transmission unit, and the first outer interconnection structure is wrapped in the upper insulating layer and is used to electrically connect the first digital isolation chip with the first external circuit; the second interconnection structure includes a second inner interconnection structure and a second outer interconnection structure; wherein the second inner interconnection structure is wrapped in the upper insulating layer and is used to electrically connect the second digital isolation chip with the second coupling transmission unit, and the second outer interconnection structure is wrapped in the upper insulating layer and is used to electrically connect the second digital isolation chip with the second external circuit.

[0058] It should be noted that the lower insulating layer arranged on the second surface of the quartz wafer substrate can be arranged according to the type of the first coupling transmission unit. For example, when the first coupling transmission unit is a capacitor plate, the first internal interconnection structure can be arranged on the second surface of the quartz wafer substrate. At this time, only one lower insulating layer needs to be arranged to cover the first internal interconnection structure arranged on the second surface of the quartz wafer substrate. Of course, two lower insulating layers can also be arranged, and there is no specific limitation on this. It can prevent the first coupling transmission unit from passing through the second power domain area along the right side creepage in the horizontal direction. For another example, when the first coupling transmission unit is an electromagnetic coil, since the two joints of the electromagnetic coil are respectively located inside and outside the coil, an additional lower insulating layer needs to be arranged when the electromagnetic coil is led out to wire it to prevent the lead-out end from short-circuiting with other parts of the coil. Therefore, at this time, at least two lower insulating layers need to be arranged on the second surface of the quartz wafer substrate to prevent the inductor coil from passing through the second power domain area along the right side creepage in the horizontal direction. The implementation method of the above structure can effectively improve the lateral withstand voltage capability of the digital isolator by setting the lateral insulating medium to an insulating material with higher dielectric strength.

[0059] For example, Figure 1 As shown, two upper insulating layers, namely a first upper insulating layer 103a and a second upper insulating layer 103c, are stacked on the first surface of the quartz wafer substrate 102. Two lower insulating layers, namely a first lower insulating layer 103b and a second lower insulating layer 103d, are stacked on the second surface of the quartz wafer substrate 102.

[0060] Furthermore, if Figure 1As shown, the first inner interconnection structure includes a first inner conductive portion 106b arranged on the first digital isolation chip 101a, a first inner conductive portion 106c arranged on the first surface of the quartz wafer substrate 102, a first inner conductive portion arranged on the second surface of the quartz wafer substrate 102, a first inner conductive portion 106j arranged on the first upper insulating layer 103a, a first inner conductive portion 106n arranged on the first lower insulating layer 103b, and a first inner conductive column electrically connecting the above-mentioned first inner conductive portions, and a first inner conductive column electrically connecting the first inner conductive portion 106n and the first coupling transmission unit 106g; wherein a lateral high-voltage isolation gate is formed between the first inner conductive portion 106c located on the first surface of the quartz wafer substrate 102 and the second coupling transmission unit 106d.

[0061] In this embodiment, the first upper insulating layer, the second upper insulating layer and the first lower insulating layer and the second lower insulating layer are made of polyimide. By replacing the lateral insulating medium with polyimide, the lateral withstand voltage capability of the isolator is effectively improved.

[0062] Furthermore, if Figure 1 As shown, a creepage extension structure is further provided between the first inner conductive portion 106c and the second coupling transmission unit 106d on the first surface of the quartz wafer substrate 102 to increase the lateral creepage distance and further increase the lateral withstand voltage capability.

[0063] Please continue to refer to Figure 1 The creepage extension structure is four protruding structures 104c arranged on the first surface of the quartz wafer substrate 102. The creepage distance can be increased by creeping along the interface of the protruding structures. It should be noted that the number of protruding structures here should be designed according to actual needs and processes, and other numbers of protruding structures can also be set. Within the same distance, the more the number of protruding structures, the longer the creepage distance obtained and the better the withstand voltage effect.

[0064] Furthermore, if Figure 1 As shown, the first external interconnection structure includes a first external conductive portion 106a arranged on the first digital isolation chip 101a, a first external conductive portion 106h arranged on the first upper insulating layer 103a, a first external conductive portion 106p arranged on the second upper insulating layer 103c, and a first external conductive column electrically connecting the above-mentioned first external conductive portions, and the first external conductive portion 106p is used to be electrically connected to the first external circuit.

[0065] Furthermore, if Figure 1As shown, the second inner interconnection structure includes a second inner conductive portion 106e arranged on the second digital isolation chip 101b, a second inner conductive portion 106k arranged on the first upper insulating layer 103a, and a second inner conductive column electrically connecting the above-mentioned second inner conductive portions, and a second inner conductive column electrically connecting the second inner conductive portion 106k and the second coupling transmission unit 106d.

[0066] Furthermore, if Figure 1 As shown, the second external interconnection structure includes a second external conductive portion 106f arranged on the second digital isolation chip 101b, a second external conductive portion 106m arranged on the first upper insulating layer, a second external conductive portion 106q arranged on the second upper insulating layer, and a second external conductive column electrically connected between the above-mentioned second external conductive portions, and the second external conductive portion 106q is used to be electrically connected to the second external circuit.

[0067] Example 2

[0068] This example shows the physical distance of the ultra-high voltage digital isolator. Figure 2 As shown, the specific structure is the same as the ultra-high withstand voltage digital isolator given in Example 1. The above structure is to achieve internal ultra-high voltage isolation signal transmission (above 50000V) on both sides of the device, and a certain physical spacing needs to be met. The dielectric strength of the polyimide used in the upper insulating layer and the lower insulating layer is 300V / μm, the dielectric strength of the quartz glass used in the quartz wafer substrate is 600V / μm, and the dielectric strength of air is 3V / μm.

[0069] like Figure 2 As shown, in the single product 201 of the ultra-high withstand voltage digital isolator, the conductive structure in the circle indicated by A is the first power domain area, and the conductive structure in the circle indicated by B is the second power domain area. The middle is electrically isolated by quartz glass and polyimide. Figure 2 There are several locations of voltage-withstand bottlenecks in the structure, namely X1, Y1, and S1. The conventional values ​​of the thickness of the polyimide layers Y2, Y3, Y4, and Y5 can be selected as 20μm. The intermediate medium of X1 is polyimide inside and air outside. Under the premise that Y2 is 20μm, X1 is 12mm, X2 is polyimide inside and air outside, which can be selected as 20mm. The intermediate medium of Y1 and S1 is quartz glass, so in order to meet the internal ultra-high voltage isolation of more than 50000V, Y1 and S1 can be selected as 100μm, and the achievable dielectric breakdown voltage is 100*600=60000V>50000V.

[0070] Among them, X1: the shortest distance between the first power domain area and the second power domain area above the quartz glass along the length direction; X2: the shortest distance between the first power domain area and the second power domain area on the second upper insulating layer 103c along the length direction; Y1: the distance between the upper and lower coupling transmission units; S1: the shortest distance between the first coupling transmission unit 106g in the first power domain area and the second digital isolation chip 101b in the second power domain area; Y2-Y5 are all polyimide layer thicknesses, among which Y2 is the thickness of the second upper insulating layer, Y3 is the thickness of the first upper insulating layer, Y4 is the thickness of the first lower insulating layer, and Y5 is the thickness of the second lower insulating layer.

[0071] It should be understood that the values ​​of Y1, Y2, Y3, Y4, Y5, S1, X1, and X2 given in this embodiment are only preferred values ​​and are for illustrative purposes only. In fact, the values ​​of the above distances may be greater than or equal to the above preferred values ​​and are not listed one by one here.

[0072] Example 3

[0073] This example provides an ultra-high withstand voltage digital isolator packaging structure, wherein the ultra-high withstand voltage digital isolator has the same structure as the ultra-high withstand voltage digital isolator in Examples 1 and 2, such as Figure 3 As shown, the ultra-high withstand voltage digital isolator packaging structure includes: a packaging substrate 107, a packaging layer 111, two electrical signal lead-out components and the ultra-high withstand voltage digital isolator recorded above, wherein the ultra-high withstand voltage digital isolator is arranged on the packaging substrate 107, and the packaging layer 111 is used to package the ultra-high withstand voltage digital isolator in the packaging substrate 107, wherein one electrical signal lead-out component is electrically connected to the first interconnection structure in the ultra-high withstand voltage digital isolator, and the other electrical signal lead-out component is electrically connected to the second interconnection structure in the ultra-high withstand voltage digital isolator.

[0074] It should be noted that the encapsulation layer of this embodiment adopts plastic encapsulation compound.

[0075] It should be further explained that the present embodiment does not specifically limit the structure of the electrical signal lead-out component. Generally speaking, each electrical signal lead-out component includes at least two electrical signal lead-out parts. For example, one of the electrical signal lead-out parts is an input pin for receiving external signals, and the other electrical signal lead-out part is an output pin for outputting the signal generated or processed by the chip to the outside. Of course, other pins can be set according to the design and requirements of the chip to adapt to different application scenarios.

[0076] It is still necessary to explain that each electrical signal lead-out component includes at least two electrical signal lead-out parts, and the electrical signal lead-out parts include a first lead part passing through the packaging layer, a metal pad arranged on the side of the packaging substrate facing the packaging layer, and a second lead part passing through the packaging substrate or adhered to the outer surface of the packaging substrate and electrically connected to the first lead part; one end of the first lead part in one of the electrical signal lead-out components is electrically connected to the first interconnection structure, and one end of the first lead part in the other electrical signal lead-out component is electrically connected to the second interconnection structure; the metal pad is electrically connected to the other end of the first lead part, and the metal pad is also electrically connected to the second lead part through the line in the packaging substrate, and the other end of the second lead part is electrically connected to the external circuit to lead out the IO of the ultra-high withstand voltage digital isolator.

[0077] It should be noted that the first lead portion of this embodiment can use bonding wires, and the second lead portion can use ball planting, that is, the packaging substrate is provided with a through hole, a circuit is provided in the through hole, the pad is correspondingly arranged above the packaging substrate and electrically connected to the circuit in the packaging substrate, and a ball is planted below the packaging substrate as the second lead portion to realize the transmission of electrical signals.

[0078] For example, Figure 3 As shown, the ultra-high withstand voltage digital isolator packaging structure includes a first electrical signal lead-out component and a second electrical signal lead-out component, wherein the first electrical signal lead-out component includes two first electrical signal lead-out parts, and the second electrical signal lead-out component includes two second electrical signal lead-out parts. The first electrical signal lead-out part includes a first bonding wire 110a penetrating through the packaging layer 111, a first metal pad 108a disposed on the side of the packaging substrate 107 facing the packaging layer 111, and a first implant ball 109a / 109b electrically connected to the first metal pad 108a through the circuit in the packaging substrate 107. The second electrical signal lead-out part includes a second bonding wire 110b penetrating through the packaging layer 111, a second metal pad 108b disposed on the side of the packaging substrate 107 facing the packaging layer 111, and a second implant ball 109c / 109d electrically connected to the second metal pad 108b through the circuit in the packaging substrate 107.

[0079] Please continue to refer to Figure 3 For the first power domain area, the first external conductive portion 106p in the first interconnect structure is electrically connected to the first bonding wire 110a, and the IO is led out through the first pad 108a, the package substrate 107 and the two first planting balls 109a / 109b.

[0080] Please continue to refer to Figure 3 For the second power domain area, the second external conductive portion 106q in the second interconnect structure is electrically connected to the second bonding wire 110b, and the IO is led out through the second pad 108b, the package substrate 107 and the two second planting balls 109c / 109d.

[0081] For further information, please refer to Figure 3 An adhesive layer 112 is provided between the ultra-high withstand voltage digital isolator and the packaging substrate 107, and the adhesive layer may be made of adhesive tape or the like.

[0082] Example 4

[0083] This example also gives the physical distance of the ultra-high voltage digital isolator package structure, please refer to Figure 4 As shown, the specific structure is the same as the ultra-high withstand voltage digital isolator given in Example 3. The above packaging structure 301 needs to meet a certain physical spacing to realize internal ultra-high voltage isolation signal transmission (above 50000V) on both sides of the device, wherein the dielectric strength of the plastic sealing material of the plastic sealing layer 111 is 15V / μm, the dielectric strength of the polyimide used in the upper insulating layer and the lower insulating layer is 300V / μm, the dielectric strength of the quartz glass used in the quartz wafer substrate is 600V / μm, and the dielectric strength of air is 3V / μm.

[0084] like Figure 4 As shown, in the package structure 301, in addition to meeting the size requirements of Y1 and S1 in the single product of the ultra-high withstand voltage digital isolator shown in the above embodiment 2, the external medium of X1 is a plastic packaging material with a dielectric strength of 15V / μm, so the size of X1 can be selected as 2.5mm, and at the same time, Figure 4 The X2 size is sufficient, its medium is plastic packaging material, the X2 size can be 3.5mm, and the achievable dielectric breakdown voltage is 3500*15=52500>50000V.

[0085] It can be seen that by using the encapsulation layer 111 to encapsulate the ultra-high withstand voltage digital isolator, since the dielectric strength of the encapsulation layer material is greater than the dielectric strength of air, the ultra-high withstand voltage digital isolator in Examples 3 and 4 can use a smaller size than the ultra-high withstand voltage digital isolator in Examples 1 and 2. For example, the size of X1 in Example 4 is 2.5 mm and the size of X2 is 3.5 mm, both of which are smaller than the size of X1 of 12 mm and the size of X2 of 20 mm in Example 2 to obtain the same isolation withstand voltage value. Therefore, using the encapsulation layer 111 to encapsulate the ultra-high withstand voltage digital isolator can further reduce costs compared to the unencapsulated ultra-high withstand voltage digital isolator.

[0086] It should be understood that the values ​​of X1 and X2 given in this embodiment are only preferred values ​​and are only for illustrative purposes. In fact, the values ​​of the above distances can be greater than or equal to the above preferred values ​​and are not listed one by one here.

[0087] Example 5

[0088] like Figure 5 and Figure 6As shown, this example provides a method S200 for manufacturing an ultra-high withstand voltage digital isolator, and the specific steps include S210 to S250:

[0089] S210, providing a quartz wafer substrate.

[0090] Specifically, Figure 5 As shown in (a) in the figure, a quartz glass wafer 100 is taken, and the quartz glass wafer 100 is composed of a plurality of quartz wafer substrates 102 arrays. The subsequent process steps are all illustrated with the minimum unit quartz wafer substrate 102, and are actually processed as a whole on the quartz glass wafer 100.

[0091] S220, disposing a first digital isolation chip and a second digital isolation chip on a first surface of a quartz wafer substrate with an interval therebetween.

[0092] Specifically, Figure 5 As shown in (bd) in FIG. 1 , a first cavity 104a for placing a first digital isolation chip 101a, a second cavity 104b for placing a second digital isolation chip 101b, a plurality of protruding structures 104c, and a through hole 104d are etched on the first surface of the quartz wafer substrate 102, wherein the plurality of protruding structures 104c form a creepage extension structure. Afterwards, the first digital isolation chip 101a and the second digital isolation chip 101b are bonded to the first cavity 104a and the second cavity 104b, respectively.

[0093] S230, forming a first metallization layer and a second metallization layer on the second surface and the first surface of the quartz wafer substrate respectively, and forming a first coupling transmission unit and a second coupling transmission unit respectively by etching.

[0094] Specifically, Figure 5 As shown in (e), a first metallization layer is formed on the first surface of the quartz wafer substrate 102 and on the surfaces of the first digital isolation chip 101a and the second digital isolation chip 101b, a second metallization layer is formed on the second surface of the quartz wafer substrate 102, a first coupling transmission unit 106g and a first inner conductive portion are formed on the second surface of the quartz wafer substrate 102 by etching, a second coupling transmission unit 106d and a first inner conductive portion 106c are formed on the first surface of the quartz wafer substrate 102, a first inner conductive portion 106b and a first outer conductive portion 106a are formed on the first digital isolation chip 101a, and a second inner conductive portion 106e and a second outer conductive portion 106f are formed on the second digital isolation chip 101b.

[0095] S240: Form an insulating layer on the first coupling transmission unit, the second coupling transmission unit, and the first surface and the second surface of the quartz wafer substrate.

[0096] Specifically, Figure 5 As shown in (fg) in FIG. 1 , polyimide is covered on the first surface and the second surface of the quartz wafer substrate 102 to form a first upper insulating layer 103a and a first lower insulating layer 103b, and via holes 105a to 105h are etched. Afterwards, metallization is performed on the surfaces and vias of the first upper insulating layer 103a and the first lower insulating layer 103b to form a third metallization layer and a fourth metallization layer. By etching, a first outer conductive portion 106h, a first inner conductive portion 106j, a second inner conductive portion 106k, and a second outer conductive portion 106m are formed in the first upper insulating layer 103a, and a first inner conductive portion 106n is formed in the first lower insulating layer 103b, as well as a first inner conductive column connecting each first inner conductive portion, the first inner conductive portion 106n and the first coupling transmission unit 106g, a first outer conductive column connecting each first outer conductive portion, a second inner conductive column connecting each second inner conductive portion, the second inner conductive portion 106k and the second coupling transmission unit 106d, and a second outer conductive column connecting the second outer conductive portion.

[0097] Furthermore, if Figure 5 As shown in (hi), the first upper insulating layer 103a and the first lower insulating layer 103b are covered with polyimide to form the second upper insulating layer 103c and the second lower insulating layer 103d, respectively, and the vias 105j and 105k are etched. Afterwards, the surfaces and vias of the second upper insulating layer 103c and the second lower insulating layer 103d are metallized to form the fifth metallization layer and the sixth metallization layer. By etching, the first outer conductive part 106p and the second outer conductive part 106q are formed in the second upper insulating layer 103c, and the first outer conductive column connecting the first outer conductive part 106h and the first outer conductive part 106p, and the second outer conductive column connecting the second outer conductive part 106m and the second outer conductive part 106q are formed.

[0098] It should be understood that if Figure 5As shown, the first outer conductive part 106p, the first outer conductive pillar disposed in the second upper insulating layer 103c, the first outer conductive part 106h, the first outer conductive pillar disposed in the first upper insulating layer 103a, and the first outer conductive part 106a are sequentially electrically connected to form a first outer interconnection structure, wherein in the first outer interconnection structure, the first outer conductive part 106p is used to be electrically connected to the first external circuit, and the first outer conductive part 106a is used to be electrically connected to the first digital isolation chip 101a. Secondly, the first inner conductive part 106j, the two first inner conductive pillars located in the first upper insulating layer 103a, the first inner conductive part 106b, the first inner conductive part 106c located on the first surface of the quartz wafer substrate 102, the first inner conductive pillar located in the quartz wafer substrate 102, the first inner conductive part located on the second surface of the quartz wafer substrate 102, the two first inner conductive pillars located in the first lower insulating layer 103b, and the first inner conductive part 106n are electrically connected to form a first inner interconnection structure. In the first inner interconnection structure, the first inner conductive portion 106b is electrically connected to the first digital isolation chip 101a, and the first inner conductive column disposed in the first lower insulating layer 103b is electrically connected to the first coupling transmission unit 106g.

[0099] Similarly, the second outer conductive portion 106q, the second outer conductive column disposed in the second upper insulating layer 103c, the second outer conductive portion 106m, the second outer conductive column disposed in the first upper insulating layer 103a, and the second outer conductive portion 106f are sequentially electrically connected to form a second outer interconnection structure, wherein, in the second outer interconnection structure, the second outer conductive portion 106q is used to be electrically connected to an external circuit, and the second outer conductive portion 106f is used to be electrically connected to the second digital isolation chip 101b. Secondly, the second inner conductive portion 106e, the two second inner conductive columns located in the first upper insulating layer 103a, and the second inner conductive portion 106k are electrically connected to form a second inner interconnection structure. In the second inner interconnection structure, the second inner conductive portion 106e is electrically connected to the second digital isolation chip 101b, and the second inner conductive column is electrically connected to the second coupling transmission unit 106d.

[0100] S250. Form a first interconnection structure and a second interconnection structure in the insulating layer and the quartz wafer substrate, the first interconnection structure being used to electrically connect the first digital isolation chip to the first coupling transmission unit and the first external circuit respectively, and the second interconnection structure being used to electrically connect the second digital isolation chip to the second coupling transmission unit and the second external circuit respectively.

[0101] It should be understood that step S250 is performed simultaneously with step S240. For the specific process, please refer to the above description, that is, the first interconnection structure includes a first inner interconnection structure and a first outer interconnection structure, the first inner interconnection structure is used to electrically connect the first digital isolation chip and the first coupling transmission unit, and the first outer interconnection structure is used to electrically connect the first digital isolation chip and the first external circuit. The second interconnection structure includes a second inner interconnection structure and a second outer interconnection structure, the second inner interconnection structure is used to electrically connect the second digital isolation chip and the second coupling transmission unit, and the second outer interconnection structure is used to electrically connect the second digital isolation chip and the second external circuit.

[0102] It should also be understood that if Figure 5 As shown in (j), after the quartz glass wafer 100 has completed the above process, it can be diced along the cutting path to separate the ultra-high withstand voltage digital isolator single product 201. The structure of the single product 201 is as shown in FIG. Figure 5 As shown in (i), the ultra-high withstand voltage digital isolator single product 201 can be directly welded as an isolator product and applied to the terminal product, or it can be used as a bare core and produced into other packaging structures, such as Figure 5 As shown in (m) in .

[0103] Furthermore, the specific steps of producing a single product of ultra-high withstand voltage digital isolator into other packaging structures are as follows: Figure 5 In (km):

[0104] A packaging substrate 107 is obtained, wherein the packaging substrate 107 has a through hole, in which a circuit is arranged, and a first solder pad 108a and a second solder pad 108b are arranged on the packaging substrate 107, wherein the first solder pad 108a and the second solder pad 108b are connected correspondingly to the circuit in the through hole, and an ultra-high withstand voltage digital isolator single product 201 is bonded to the packaging substrate 107 using adhesive, that is, an adhesive layer 112 is formed between the packaging substrate 107 and the ultra-high withstand voltage digital isolator single product 201.

[0105] Furthermore, a first bonding wire 110a is used to electrically connect the first interconnect structure in the ultra-high voltage digital isolator single product to the first pad 108a, and a second bonding wire 110b is used to electrically connect the second interconnect structure in the ultra-high voltage digital isolator single product to the second pad 108b, and a plastic encapsulation material is used to perform molding protection on the packaging substrate 107 to form a packaging layer 111.

[0106] Furthermore, a ball is planted at the through hole corresponding to the first pad 108a on the back side of the packaging substrate 107 to form a first ball 109a / 109b, and a ball is planted at the through hole corresponding to the second pad 108b on the back side of the packaging substrate 107 to form a second ball 109c / 109d to obtain a packaging body.

[0107] The present invention discloses an ultra-high withstand voltage digital isolator, a packaging structure, and a manufacturing method. Compared with conventional digital isolators in which the lateral isolation medium is a plastic packaging material, and the longitudinal isolation medium is generally a thin layer of silicon dioxide and polyimide, which have limited processing thickness and limited withstand voltage capability and cannot meet the ultra-high withstand voltage application environment, the present invention has the following beneficial effects: through wafer reconstruction technology, the lateral insulating medium is replaced with polyimide, and the longitudinal insulating medium is replaced with quartz glass, which has significantly improved the withstand voltage capability compared with conventional digital isolators and can reach more than 50,000V. Moreover, under the premise of meeting the ultra-high withstand voltage, compared with winding transformers, the product volume and weight can be greatly reduced, thereby realizing miniaturization and lightweight of terminal products.

[0108] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. An ultra-high withstand voltage digital isolator, characterized in that: include: Quartz wafer substrate; A first digital isolation chip and a second digital isolation chip are arranged on the first surface of the quartz wafer substrate with a relative spacing; A first coupling transmission unit and a second coupling transmission unit, both of which are respectively arranged on the second surface and the first surface of the quartz wafer substrate, and the first coupling transmission unit and the second coupling transmission unit constitute a coupling transmission structure; The first digital isolation chip and the second digital isolation chip realize isolated transmission of signals through the coupled transmission structure; a first interconnection structure and a second interconnection structure, wherein the first interconnection structure is used to electrically connect the first digital isolation chip to the first coupling transmission unit and the first external circuit respectively, and the second interconnection structure is used to electrically connect the second digital isolation chip to the second coupling transmission unit and the second external circuit respectively; An insulating layer is disposed on the first surface and the second surface of the quartz wafer substrate to wrap the first digital isolation chip, the second digital isolation chip, the first coupling transmission unit, the second coupling transmission unit, the first interconnection structure and the second interconnection structure; The first coupling transmission unit, the first digital isolation chip and the first interconnection structure form a first power domain area, the second coupling transmission unit, the second digital isolation chip and the second interconnection structure form a second power domain area, and a high-voltage isolation barrier is formed between the first power domain area and the second power domain area.

2. The ultra-high withstand voltage digital isolator according to claim 1, characterized in that: The first coupling transmission unit and the second coupling transmission unit are capacitor plates; or, The first coupling transmission unit and the second coupling transmission unit are electromagnetic coils; or, The first coupling transmission unit and the second coupling transmission unit are giant magnetoresistance.

3. The ultra-high withstand voltage digital isolator according to claim 1, characterized in that: The insulating layer includes a plurality of upper insulating layers stacked on the first surface of the quartz wafer substrate, and at least one lower insulating layer disposed on the second surface of the quartz wafer substrate; The first interconnect structure includes a first inner interconnect structure and a first outer interconnect structure; wherein the first inner interconnect structure is wrapped in the upper insulating layer, the quartz wafer substrate and the lower insulating layer and is used to electrically connect the first digital isolation chip and the first coupling transmission unit, and the first outer interconnect structure is wrapped in the upper insulating layer and is used to electrically connect the first digital isolation chip and the first external circuit; The second interconnection structure includes a second inner interconnection structure and a second outer interconnection structure; wherein the second inner interconnection structure is wrapped in the upper insulating layer and is used to electrically connect the second digital isolation chip and the second coupling transmission unit, and the second outer interconnection structure is wrapped in the upper insulating layer and is used to electrically connect the second digital isolation chip and the second external circuit.

4. The ultra-high withstand voltage digital isolator according to claim 3, characterized in that: The first internal interconnect structure includes a first internal conductive portion disposed on the first digital isolation chip, the first surface and the second surface of the quartz wafer substrate, the upper insulating layer, and the lower insulating layer, and a first internal conductive column electrically connecting the first internal conductive portions and the first internal conductive portion and the first coupling transmission unit; wherein, The first inner conductive portion located on the first surface of the quartz wafer substrate and the second coupling transmission unit form a lateral high-voltage isolation grid.

5. The ultra-high withstand voltage digital isolator according to claim 4, characterized in that: A creepage extension structure is also provided between the first inner conductive portion on the first surface of the quartz wafer substrate and the second coupling transmission unit.

6. The ultra-high withstand voltage digital isolator according to claim 5, characterized in that: The creepage extension structure is at least one protruding structure disposed on the first surface of the quartz wafer substrate.

7. The ultra-high withstand voltage digital isolator according to any one of claims 1 to 6, characterized in that: One of the first digital isolation chip and the second digital isolation chip serves as a transmitting end, and the other of the first digital isolation chip and the second digital isolation chip serves as a receiving end; or, both the first digital isolation chip and the second digital isolation chip can serve as a transmitting end and a receiving end, and when one of the digital isolation chips serves as a receiving end, the other digital isolation chip serves as a transmitting end.

8. The ultra-high withstand voltage digital isolator according to any one of claims 1 to 6, characterized in that: The insulating layer is polyimide.

9. An ultra-high withstand voltage digital isolator packaging structure, characterized in that: The ultra-high withstand voltage digital isolator packaging structure comprises: Package substrate, The ultra-high withstand voltage digital isolator according to any one of claims 1 to 8, arranged on the packaging substrate; A packaging layer, used for packaging the ultra-high withstand voltage digital isolator on the packaging substrate; Two electrical signal lead-out components, one of which is electrically connected to the first interconnection structure, and the other of which is electrically connected to the second interconnection structure.

10. A method for manufacturing an ultra-high withstand voltage digital isolator, characterized in that: The manufacturing method comprises: Providing quartz wafer substrates; Disposing a first digital isolation chip and a second digital isolation chip on the first surface of the quartz wafer substrate at intervals; Forming a first metallization layer and a second metallization layer on the second surface and the first surface of the quartz wafer substrate respectively, and forming a first coupling transmission unit and a second coupling transmission unit respectively by etching; forming an insulating layer on the first coupling transmission unit, the second coupling transmission unit, and the first surface and the second surface of the quartz wafer substrate; A first interconnection structure and a second interconnection structure are formed in the insulating layer and the quartz wafer substrate, the first interconnection structure is used to electrically connect the first digital isolation chip with the first coupling transmission unit and the first external circuit respectively, and the second interconnection structure is used to electrically connect the second digital isolation chip with the second coupling transmission unit and the second external circuit respectively.

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