Delay-locked loop system and memory

Abstract

The invention provides a delay phase-locked loop system and a memory, the delay phase-locked loop system comprises a state indication circuit, a state broadening circuit and a delay phase-locked loop circuit, the circuit is simple in design and easy to realize, and the state indication circuit can generate a refresh state signal according to a refresh command to indicate that the memory is performing refresh operation. The state broadening circuit can generate a state control signal broadened relative to a refresh state signal, so that the delay phase-locked loop circuit can increase and adjust the step length of delay relative to before the refresh operation during the refresh operation of the memory and within a period of time after the refresh operation is finished, the internal clock signal offset output by the memory is quickly adjusted, and the memory performance is improved. Therefore, the locking speed of the delay phase-locked loop circuit is increased, and finally, the internal clock signal output by the memory is aligned with the external clock signal received by the memory before the memory receives the next effective operation command, so that the problem of errors in operations such as reading and writing after the refreshing operation of the memory is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of delay locked loops, and in particular to a delay locked loop system and a memory. Background Art

[0002] Dynamic Random Access Memory (DRAM) has the characteristics of being able to read and write at any time and at a high speed. It is usually used as a temporary data storage medium for operating systems or other running programs.

[0003] DRAM generally uses capacitors as storage units. The amount of charge in the capacitor can represent the stored data "0" or "1". Due to the leakage phenomenon, in the absence of any DRAM operation, the leakage current will also cause the charge in the capacitor to slowly lose over time. When the amount of charge is lower than the threshold, DRAM will not be able to correctly read the stored data. Therefore, in order to prevent data from being damaged due to leakage, DRAM needs to be refreshed (i.e., DRAM performs a refresh operation) at regular intervals to replenish the charge in the capacitor, thereby ensuring the correctness of the data.

[0004] However, the DRAM refresh operation consumes a lot of power and may cause a large change in the power supply voltage, which in turn causes DQS offset. If the DQS offset is not adjusted back in time, it may cause errors in subsequent operations such as DRAM reading and writing data. Summary of the invention

[0005] The object of the present invention is to provide a delay phase-locked loop system and a memory, which can timely adjust the internal clock signal offset output by the memory during the refresh operation performed by the memory after receiving a refresh command and after the refresh operation is completed, so as to avoid errors in subsequent operations such as reading and writing data of the memory.

[0006] To achieve the above object, the present invention provides a delay locked loop system, which includes:

[0007] A status indication circuit, configured to output a valid refresh status signal upon receiving a refresh command to indicate that the memory is undergoing a refresh operation, wherein the refresh command comes from outside the memory;

[0008] A state stretching circuit, coupled to the state indicating circuit, and used to generate a state control signal according to the effective refresh state signal, wherein a second edge of the state control signal is delayed relative to a second edge of the effective refresh state signal;

[0009] A delay locked loop circuit is used to receive an external clock signal and adjust its delay with a first step size before the state indication circuit receives the refresh command, and then lock after outputting an internal clock signal that is phase-aligned with the external clock signal;

[0010] Wherein, the delay locked loop circuit is also coupled to the state broadening circuit, and is further configured to re-operate under the control of the state control signal, and adjust its delay with a second step size that is greater than the first step size.

[0011] Optionally, a first edge of the state control signal is aligned with a first edge of the valid refresh state signal.

[0012] Optionally, the state broadening circuit includes a delay circuit and an OR logic circuit. An input end of the delay circuit and a first input end of the OR logic circuit are both coupled to the valid refresh state signal. An output end of the delay circuit is coupled to a second input end of the OR logic circuit, and an output end of the OR logic circuit outputs the state control signal.

[0013] Optionally, the second step size is a fixed step size, or the second step size decreases as a phase offset of the internal clock signal relative to the external clock signal decreases.

[0014] Optionally, the delay locked loop circuit is further configured to continue to operate under the control of the state control signal after the valid refresh state signal ends and before the state control signal ends, and adjust its delay with a third step size that is greater than the first step size. The third step size is a fixed step size or decreases as a phase offset of the internal clock signal relative to the external clock signal decreases; and / or,

[0015] The delay locked loop circuit is further configured to resume adjusting its delay with the first step size after the state control signal ends and before the next valid operation command is sent to the memory, so that the internal clock signal is phase-aligned with the external clock signal again.

[0016] Optionally, the third step size is the same as the second step size, or the third step size is less than the second step size.

[0017] Optionally, a minimum time interval between the refresh command and the next valid operation command is tRFC, a duration of the valid refresh state signal is t1, and t1 < tRFC; a duration by which a second edge of the state control signal lags behind a second edge of the valid refresh state signal is less than tRFC - t1.

[0018] Optionally, the delay locked loop circuit includes:

[0019] A signal receiver, used for receiving the external clock signal;

[0020] A controllable delay chain, used to delay the clock signal output by the signal receiver before outputting it;

[0021] a clock tree coupled to the controllable delay chain and outputting a clock signal output by the controllable delay chain as the internal clock signal;

[0022] A clock feedback circuit, coupled to the controllable delay chain and configured to generate a feedback clock signal according to a clock signal output by the controllable delay chain;

[0023] a phase detector, coupled to the clock feedback circuit and the signal receiver, and used to detect the phases of the clock signal output by the signal receiver and the feedback clock signal;

[0024] A controller is coupled to the state stretching circuit, the phase detector and the controllable delay chain, and is used to adjust the delay of the controllable delay chain according to the state control signal and the phase detection result of the phase detector, so as to adjust the phase difference between the internal clock signal and the external clock signal.

[0025] Optionally, a state machine is provided inside the controller, and the state machine is used to output and update a control code according to the state control signal and a phase detection result of the phase detector, so as to adjust the delay of the controllable delay chain with a corresponding step size.

[0026] Optionally, the state machine updates the control code at fixed time intervals during the locking process of the delay locked loop circuit.

[0027] Based on the same inventive concept, the present invention further provides a memory, which includes a storage array and the delay locked loop system as described in the present invention.

[0028] Optionally, the memory receives an operation command, an external clock signal and an address signal from a memory controller, and outputs an internal clock signal and data to the memory controller.

[0029] Compared with the prior art, the delay locked loop system of the present invention includes a state indication circuit, a state widening circuit and a delay locked loop circuit. The circuit design is simple and easy to implement. The state indication circuit can generate a refresh state signal according to a refresh command to indicate that the memory is undergoing a refresh operation. The state widening circuit can generate a state control signal that is widened relative to the refresh state signal, so that during the memory refresh operation and a period of time after the refresh operation, the delay locked loop circuit can increase the step size of the adjustment delay relative to before the refresh operation, quickly adjust the internal clock signal offset output by the memory, thereby accelerating the locking speed of the delay locked loop circuit, and finally, before the memory receives the next valid operation command, the internal clock signal output by the memory is aligned in phase with the external clock signal it receives, thereby avoiding errors in the reading and writing operations of the memory after the refresh operation.

[0030] The memory of the present invention has improved performance due to the use of the delay phase-locked loop system of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0032] Figure 1 This is a schematic diagram of embedding DLL in existing DRAM.

[0033] Figure 2 This is a signal timing diagram of an existing DRAM.

[0034] Figure 3 Schematic diagram of the architecture of a delay-locked loop system according to a specific embodiment of the present invention.

[0035] Figure 4 It is a schematic diagram of the architecture of a state stretching circuit in a delay locked loop system in a specific embodiment of the present invention.

[0036] Figure 5 It is a schematic diagram of an exemplary architecture of a DLL in a delay-locked loop system in a specific embodiment of the present invention.

[0037] Figure 6 yes Figure 3 The working timing diagram of the delay locked loop system is shown.

[0038] Figure 7 1 is another exemplary architecture diagram of a DLL in a delay-locked loop system in a specific embodiment of the present invention.

[0039] Figure 8 The specific embodiment of the present invention has Figure 7 The working timing diagram of the delay locked loop system of the DLL is shown.

[0040] Fig. 9 It is a schematic diagram of an exemplary architecture of a memory according to a specific embodiment of the present invention.

[0041] Fig.10 FIG. 4 is another exemplary architecture diagram of a memory according to a specific embodiment of the present invention. DETAILED DESCRIPTION

[0042] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features known in the art are not described. It should be understood that the present invention can be implemented in different forms and should not be interpreted as being limited to the embodiments proposed here. On the contrary, providing these embodiments will make the disclosure thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. The same reference numerals represent the same elements from beginning to end. It should be understood that when an element is referred to as "connected to", "coupled" other elements, it can be directly connected to other elements, or there can be intervening elements. On the contrary, when an element is referred to as "directly connected to" other elements, there is no intervening element. When used here, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0043] Please refer to Figure 1 At present, the delay of the internal circuit of DRAM will cause the problem of clock skew (i.e., phase misalignment) between the external clock signal PAD_CLK input to DRAM and the internal clock signal DQS output by DRAM, which will cause DRAM read and write data errors. Therefore, a delay-locked loop (DLL) circuit will be further embedded in the internal circuit of DRAM. The DLL can provide a controllable delay to achieve synchronization of DQS and PAD_CLK (or "phase alignment"), and when the phases of DQS and PAD_CLK are aligned, the DLL will be locked (i.e., the delay provided by the DLL will be locked).

[0044] Please refer to Figure 2In order to prevent data from being damaged due to leakage, DRAM needs to be refreshed (Refresh) every once in a while (that is, DRAM will respond to the refresh command REF (which is a command CMD) sent by the host or user to perform a refresh operation) to replenish the charge in the capacitor, thereby ensuring the correctness of the data. After the refresh operation is completed, DRAM responds to the activation command (Active) ACT (which is another command CMD) to select the storage block (Bank) and row (Row) address of the DRAM to access, and perform data read (Read) or write (Write) operations on the address.

[0045] Please combine Figure 1 and Figure 2 During the refresh operation, the DRAM storage array consumes a large amount of current, which causes the power supply voltage VDD to decrease. The change in the power supply voltage VDD causes DQS to shift relative to PAD_CLK (such as Figure 2 At this point, the DLL begins to adjust the delay to realign DQS with PAD_CLK, and the DLL relocks (as shown in A in Figure 1). Figure 2 After the refresh operation is completed, the power supply voltage VDD is restored, and the change of the power supply voltage VDD will cause DQS to shift relative to PAD_CLK again (as shown in B in FIG. Figure 2 At this point, the DLL works again and continues to adjust the delay to realign DQS with PAD_CLK.

[0046] Since the refresh operation consumes a lot of current (hundreds of mA level), the power supply voltage VDD changes a lot, the DQS offset may reach hundreds of ps, and the DLL adjustment delay step is very small (for example, 1F, 2F or 5ps to 10ps per step, where F is the unit fine adjustment step of DLL), so it takes a long time for DLL to re-lock. After the refresh operation is completed, DRAM may soon perform a read or write operation, but at this time DLL has not yet reached the locked state (that is, DQS and PAD_CLK are not aligned), which may cause DRAM read and write data errors.

[0047] Based on this, the present invention provides a delay phase-locked loop circuit and a memory, which can widen the falling edge of a refresh status signal originally used to indicate that the memory is undergoing a refresh operation (i.e., extend the high level phase of the refresh status signal) during the refresh operation of the memory, and during the period when the widened refresh status signal is high, the DLL increases the step size of the delay adjustment (for example, from 1F, 2F to 4F, 8F...), so as to speed up the phase adjustment speed of the internal clock signal DQS output by the DLL to the memory, thereby realizing the rapid locking of the DLL after the refresh operation is completed, avoiding the problem of errors in subsequent operations such as reading and writing data of the subsequent memory.

[0048] The following is combined with Figures 3 to 10 The technical solution of the present invention is described in detail with reference to the accompanying drawings and specific embodiments.

[0049] Please refer to Figure 3 An embodiment of the present invention provides a delay locked loop system, which includes a state indication circuit 10, a state widening circuit 11 and a delay locked loop circuit DLL.

[0050] Among them, the status indication circuit 10 is used to output a valid refresh status signal REF_STA when receiving a refresh command REF to indicate that the memory (such as DRAM, etc.) is undergoing a refresh operation (for example, REF_STA is high and represents that the memory is in the refresh operation stage).

[0051] The refresh command REF usually comes from a memory controller outside the memory (such as Fig.10 2 in FIG. 1 ). In one example, the refresh command REF may be periodic, for example, the memory controller sends the refresh command REF to the memory at intervals of an average period. That is, the memory controller periodically (for example, in milliseconds) cyclically sends the refresh command REF to the memory, so that the memory refreshes all rows or all columns at regular intervals, replenishes the charge lost over time, and prevents data from being damaged by leakage.

[0052] In another example, the refresh command REF may also be random, and the corresponding host or user may generate and send the refresh command REF to the memory through the memory controller, so as to refresh the memory as needed and replenish the charge lost over time to prevent the data from being damaged by leakage. In this case, there also needs to be a certain time interval between two refresh commands REF, and the corresponding host or user shall ensure that the average time between the refresh commands REF is certain.

[0053] It should be noted that the interval time between two adjacent refresh commands REF (which can also be said to be the period of the refresh command) cannot be too long. If the interval time is too long, it may lead to the inability to recognize the data level during the refresh. At the same time, the interval time cannot be too short either, because the memory cannot perform normal read and write operations during the refresh. Too frequent refreshing will cause the throughput performance of the memory to decline. Generally speaking, the minimum value of the interval time between two adjacent refresh commands is determined by attributes such as the capacity density, operating frequency, and working temperature of the memory, while the maximum value of the interval time between two adjacent refresh commands is determined by the requirements of the memory throughput performance. In addition, the minimum time from any refresh command REF to the next valid operation command CMD immediately following it is tRFC (Refresh Cycle Time). tRFC is related to the DRAM capacity density and working frequency. During tRFC, the memory controller cannot send any valid command CMD to the memory. The time t1 required for the memory to perform the refresh operation needs to be less than tRFC, that is, t1 < tRFC. The minimum interval between two adjacent REF commands (this period is used to wait for the completion of the refresh operation) also needs to be greater than tRFC.

[0054] It should also be noted that the refresh operation described in the present invention is different from the self-refresh operation of the memory. This refresh operation is also called the "normal refresh operation", which requires the participation of the external clock signal PAD_CLK. That is, during this refresh operation, the external clock signal PAD_CLK is normally input to the memory. It can also be a periodic refresh operation or a random refresh operation generated according to the needs of the user or host. The self-refresh operation of the memory is a refresh operation independently performed by the memory in the low-power mode, which does not require the participation of the external clock signal PAD_CLK. That is, during the self-refresh operation, the external clock signal PAD_CLK is continuously low. In another embodiment, the refresh status signal REF_STA can also be further used to instruct the DLL to turn off the output path of the internal clock signal DQS. Since there is no need to output DQS during the execution of the refresh operation phase, the DLL can turn off the output path of the internal clock signal DQS according to the refresh status signal REF_STA to further reduce the power consumption.

[0055] The status indication circuit 10 can adopt any suitable circuit design such as a conventional pulse generator (not shown) in the art or a circuit composed of elements such as flip-flops and counters (not shown), etc., which will not be elaborated here. As long as it can output a high-level pulse signal with a corresponding width as a valid refresh status signal REF_STA when receiving the refresh command REF to indicate that the memory is performing a refresh operation, and the width (i.e., the duration) of the valid refresh status signal REF_STA (i.e., the high-level pulse signal) is the time t1 required for the memory to perform the refresh operation.

[0056] The state broadening circuit 11 is coupled to the state indication circuit 10 and is configured to generate a state control signal REF_STA_DLY according to the valid refresh state signal REF_STA output by the state indication circuit 10.

[0057] In one example, the state control signal REF_STA_DLY can also be a high-level pulse signal, whose rising edge serves as its first edge and is aligned with the rising edge of the valid refresh state signal REF_STA (i.e., the first edge of REF_STA), and the falling edge of the state control signal REF_STA_DLY serves as its second edge and is delayed relative to the falling edge of the valid refresh state signal REF_STA (i.e., the second edge of REF_STA). Thus, the state control signal REF_STA_DLY is broadened relative to the valid refresh state signal REF_STA output by the state indication circuit 10.

[0058] In other examples, the state control signal REF_STA_DLY can also be a high-level pulse signal, whose rising edge serves as its first edge and can be delayed relative to the rising edge of the valid refresh state signal REF_STA (i.e., the first edge of REF_STA).

[0059] Furthermore, in various examples of the present invention, the duration (which can be referred to as the "broadening amount") td by which the falling edge of REF_STA_DLY (i.e., the second edge of REF_STA_DLY) is delayed relative to the falling edge of REF_STA (i.e., the second edge of REF_STA) is greater than 0 and less than <tRFC - t1>, thereby ensuring that REF_STA_DLY does not overlap with the next valid operation command CMD received by the memory (this operation command is the next command relative to the refresh command REF that triggers this refresh operation, such as a read command RD or a write command, etc.), avoiding errors in reading and writing data by the memory. The magnitude of td is sufficient to enable the delay locked loop circuit DLL to realign DQS with PAD_CLK and complete locking after the refresh operation ends and before the next valid operation command received by the memory.

[0060] In addition, the state broadening circuit 11 can be implemented using any suitable circuit design, and the present invention does not make specific limitations on this, as long as the above effects can be achieved.

[0061] As an example, please refer to Figure 4The state widening circuit 11 includes an OR logic circuit OR and a delay circuit 110. The input end of the delay circuit 110 and the first input end of the OR logic circuit OR are both coupled to the refresh state signal REF_STA. The output end of the delay circuit 110 is coupled to the second input end of the OR logic circuit OR, and the output end of the OR logic circuit OR outputs the state control signal REF_STA_DLY. The rising edge of REF_STA_DLY output by the state widening circuit 11 of this example is aligned with the rising edge of the valid refresh state signal REF_STA, and the falling edge of REF_STA_DLY is delayed by td relative to the falling edge of REF_STA.

[0062] Please combine Figure 3 and Figure 5 The delay locked loop circuit DLL is coupled to the state widening circuit 11 and the external clock signal PAD_CLK. The main function of the delay locked loop circuit DLL is to adjust the delay by adjusting the delay of the controllable delay chain 121 inside it, so as to output the internal clock signal DQS that is phase-aligned with the external clock signal PAD_CLK to ensure that the operations such as reading and writing data of the memory are correct. After DQS is adjusted to be phase-aligned with PAD_CLK, the delay locked loop circuit DLL is locked.

[0063] In this embodiment, the delay phase-locked loop circuit DLL not only uses the first step length to adjust the delay of its internal controllable delay chain 121 before the state indication circuit 10 receives the current refresh command REF (i.e., before the memory executes the current refresh operation), so that the output DQS is phase-aligned with the external clock signal PAD_CLK and then locked, but also further restarts under the control of the state control signal REF_STA_DLY during the refresh operation of the memory (because when the refresh operation Refresh starts, the power supply voltage VDD decreases and the DQS will have a phase shift), and before the effective refresh state signal REF_STA ends (i.e., before REF_STA becomes low), uses a second step length greater than the above-mentioned first step length to adjust the delay of its internal controllable delay chain 121, so as to quickly reduce or eliminate the phase shift of DQS relative to PAD_CLK caused by the refresh operation.

[0064] The first step length is, for example, 1F, 2F, or about 5ps to 10ps, where F is the unit fine-tuning step length of the DLL. The second step length can be a fixed step length, such as 8F, 4F, etc., or can be reduced as the phase offset of DQS relative to PAD_CLK decreases, for example, 8F first, then 4F, then 2F, and finally 1F.

[0065] In one example, the delay locked loop circuit DLL can re-align the phase of DQS with PAD_CLK before the effective refresh state signal REF_STA ends (ie, before REF_STA becomes low), such as Figure 6 In another example, please combine Figure 5 and Figure 6 , the delay locked loop circuit DLL can only reduce the phase offset of DQS relative to PAD_CLK before the effective refresh state signal REF_STA ends (ie, before REF_STA becomes low).

[0066] After the refresh operation Refresh is completed, the power supply voltage VDD is restored, and the phase shift of DQS may occur again. Therefore, in order to eliminate the shift, the delay locked loop circuit DLL is further used to continue to work under the control of the state control signal REF_STA_DLY after the effective REF_STA ends (that is, after REF_STA becomes low) and before REF_STA_DLY becomes low, and uses a third step length greater than the first step length to adjust the delay of the controllable delay chain 121 inside it, so as to further speed up the speed of re-aligning the phase of DQS with PAD_CLK. Further, the delay locked loop circuit DLL is further used to resume using the first step length to adjust the delay of the controllable delay chain 121 inside it after REF_STA_DLY becomes low and before the next valid operation command (such as a read command RD) is sent to the memory, until DQS is re-aligned with PAD_CLK in phase.

[0067] Among them, the third step length can be a fixed step length, for example, the third step length can be equal to the second step length. In this case, after REF_STA_DLY is pulled low, REF_STA_DLY is still high, and DLL still uses the second step length that is larger than the first step to adjust the delay; the third step length can also be larger than the first step length and smaller than the second step length, for example, the first step length is 1F, the second step length is 8F or 4F, and the third step length is 2F, so that DLL is smoother in the process of switching step lengths to adjust the delay. In other cases, the third step length can also be reduced as the phase offset of DQS relative to PAD_CLK decreases, for example, the second step length is 8F or 4F, the first step length is 1F, and the third step length can be 8F first, then changed to 4F, and then changed to 2F.

[0068] The delay locked loop circuit DLL can be implemented by any suitable circuit design, and the present invention does not make any specific limitation on this, as long as the above-mentioned effect can be achieved.

[0069] As an example, see Figure 5The delay locked loop circuit DLL includes a signal receiver 120 , a controllable delay chain 121 , a clock tree 122 , a clock feedback circuit 123 , a phase detector 124 and a controller 125 .

[0070] The signal receiver 120 is used to receive an external clock signal PAD_CLK. The controllable delay chain 121 is coupled to the signal receiver 120, and is used to delay the clock signal CLK_RCV output by the signal receiver 102 and then output it as the clock signal CLK_OUT. The clock tree 122 is coupled to the controllable delay chain 121, and outputs the clock signal CLK_OUT output by the controllable delay chain 121 as the internal clock signal DQS. The clock feedback circuit 123 is a replica circuit of the clock tree 122 and the signal receiver 120. The clock feedback circuit 123 is coupled to the output end of the controllable delay chain 121, and is used to generate a feedback clock signal CLK_FB according to the clock signal CLK_OUT output by the controllable delay chain 121. The phase detector 124 is coupled to the clock feedback circuit 123 and the signal receiver 121, and is used to detect the phase of the clock signal CLK_RCV output by the signal receiver 121 and the feedback clock signal CLK_FB. The controller 125 is coupled to the state stretching circuit 11, the phase detector 124 and the controllable delay chain 121, and is used to output and update the control code DLL code according to the state control signal REF_STA_DLY and the phase detection result of the phase detector 124, so as to adjust the delay of the controllable delay chain 121 (i.e., the controllable delay chain 121 adjusts the delay with a corresponding step size), thereby adjusting the phase difference between the internal clock signal DQS and the external clock signal PAD_CLK.

[0071] Please combine Figure 3 and Figure 6 , the working sequence of the delay phase-locked loop system of this embodiment is as follows:

[0072] First, before the status indication circuit 10 receives the refresh command REF, the DLL is locked, and the locked step is a small step, that is, the first step (for example, 1F), that is, the DLL adjusts the delay of its internal controllable delay chain with the first step to align the phases of DQS and PAD_CLK;

[0073] Then, when the status indication circuit 10 receives the refresh command REF, its output REF_STA becomes high level, and the memory refresh operation Refresh starts. At this time, due to the decrease of the power supply voltage VDD, the delay phase-locked loop circuit DLL loses lock, and the DQS phase of the DLL output shifts to Figure 6 At A in the figure, the state stretching circuit 11 stretches the falling edge of REF_STA and outputs a high-level state control signal REF_STA_DLY whose rising edge is aligned with REF_STA and whose falling edge is delayed by td relative to REF_STA.

[0074] During the refresh operation, REF_STA is high, and REF_STA_DLY is also high. The DLL adjusts the delay of its controllable delay chain with a second step size (e.g., 4F or 8F...) that is larger than the first step size. The purpose is to speed up the phase adjustment speed of DQS so that DQS can be aligned with PAD_CLK more quickly. At this stage, the DLL can make DQS and PAD_CLK in such a way that Figure 6 The DLL can also only make the phase difference between DQS and PAD_CLK smaller by aligning the phase at B in the figure and relocking it, but the two are still not aligned;

[0075] After that, the refresh operation Refresh ends, REF_STA becomes low, the power supply voltage VDD recovers, and due to the change of VDD (DLL may lose lock again), the DQS phase shifts to Figure 6 At C in the figure, since REF_STA_DLY is still at a high level at this time, the DLL continues to adjust the delay of its controllable delay chain with a third step size that is larger than the first step size (which is also a large step size and can be equal to or smaller than the second step size), thereby speeding up the phase alignment of DQS and PAD_CLK.

[0076] After REF_STA_DLY is pulled low (i.e. after REF_STA_DLY ends), DLL can resume the first step to continue adjusting the delay of its controllable delay chain, and finally align the DQS with PAD_CLK phase (such as before the next valid operation command (such as read command RD) is sent to the memory). Figure 6 ), the DLL is locked again.

[0077] Optionally, after REF_STA_DLY is pulled low and before the next valid operation command is sent to the memory, the DLL can be re-locked. Therefore, during this period, the memory controller can first send an activation command ACT to the memory, and the memory responds to the activation command ACT to select the address to be accessed by the next valid operation command, including the storage block (Bank) and row (Row) address, etc. Therefore, when the memory receives the next valid operation command, since the DLL has been re-locked, valid operations such as data read (Read) or write (Write) can be directly performed on the activated address.

[0078] In an example, see Figure 7The controller 125 of the delay locked loop circuit DLL further includes a state machine 125a, which is used to output and update the control code DLL code according to the state control signal REF_STA_DLY and the phase detection result of the phase detector 124, so as to adjust the delay of the controllable delay chain 121 with a corresponding step length. The update of the control code DLL code can, on the one hand, realize that the delay adjustment under the same step length is executed for at least one step (i.e., at least one working beat), and on the other hand, can realize the conversion between different step lengths.

[0079] Optionally, the state machine 125a updates the output control code DLL code at a fixed time interval during the delay locked loop circuit DLL locking process. For example, the clock signal of the state machine 125 updating the control code DLL code is Update clk, and its period is n*Tck, which means that the state machine 125a updates the DLL code once every n Tcks.

[0080] For example, please combine Figure 7 and Figure 8 During the operation of the delay-locked loop system, when REF_STA is high, the memory performs a refresh operation, and when REF_STA is low, the memory ends the refresh operation. During the period when REF_STA_DLY is high, the state machine 125a first outputs the control code Code1, updates the control code to Code2 after the first time interval (which is equal to n Tcks), updates the control code to Code3 after the second time interval (which is also equal to n Tcks), updates the control code to Code4 after the third time interval (which is also equal to n Tcks), and updates the control code to Code5 after the fourth time interval (which is also equal to n Tcks). Moreover, the updates of Code1 to Code5 all make the DLL use a larger second step size (such as 4F or 8F, etc.) to adjust the delay of the controllable delay chain to reduce or even eliminate the phase offset of DQS relative to PAD_CLK. Figure 8In the embodiment, the duration of REF_STA being high is close to 3*n*Tck, and the duration of REF_STA_DLY being high is close to 5*n*Tck. In the fourth time interval, REF_STA becomes low, and the DLL continues to use the larger second step size to adjust the delay of the controllable delay chain. After that, the state machine 125a updates the control code to Code5, and the DLL continues to adjust the delay of the controllable delay chain with the third step size (which is larger than the first step size and may be less than or equal to the second step size). In addition, the state machine 125a updates the control code to Code6 after the fifth time interval (which is also equal to n Tcks), and in the fifth time interval, REF_STA_DLY becomes low, and the state machine 125a updates the control code to Code7 after the sixth time interval (which is also equal to n Tcks), and so on. Moreover, the update of control codes such as Code6~Code7 can enable the DLL to resume using the first step length (such as 1F or 2F, etc.) to continue adjusting the delay of the controllable delay chain, and before the next valid operation command CMD (such as the read command RD) arrives, the DQS and PAD_CLK phases are realigned to complete the re-locking of the DLL.

[0081] In summary, the delay locked loop system of the present invention includes a state indication circuit, a state widening circuit and a delay locked loop circuit. The circuit design is simple and easy to implement. The state indication circuit can generate a refresh state signal according to a refresh command to indicate that the memory is undergoing a refresh operation. The state widening circuit can generate a state control signal that is widened relative to the refresh state signal, so that during the memory refresh operation and a period of time after the refresh operation, the delay locked loop circuit can increase the step size of the adjustment delay relative to before the refresh operation, quickly adjust the internal clock signal offset output by the memory, thereby accelerating the locking speed of the delay locked loop circuit, and finally aligning the phase of the internal clock signal output by the memory with the external clock signal received by the memory before the memory receives the next valid operation command, thereby avoiding the problem of errors in the read and write operations after the memory refresh operation.

[0082] Based on the same invention concept, please refer to Fig. 9 and Fig.10 An embodiment of the present invention further provides a memory, which includes a storage array 14 and a delay locked loop system as described in the present invention (which includes a state indication circuit 10, a state widening circuit 11 and a DLL).

[0083] Optionally, refer to Fig.10The storage array and the delay locked loop system are integrated in a memory 1, which may be a DRAM. The memory is also coupled to a corresponding memory controller 2, and the memory 1 can receive various commands CMD, an external clock signal PAD_CLK and an address signal ADD sent by the memory controller 2, and output an internal clock signal DQS and data DQ to the memory controller 2.

[0084] As an example, see Fig.10 , the memory 1 also has:

[0085] The command decoder 13 is coupled to the memory controller 2 and is used to receive and decode various commands CMD sent by the memory controller 2 to the memory 1. These commands CMD may include a row address selection command RAS, a column address selection command CAS, an activation command ACT, a chip selection command CS, a refresh command REF, a read command RD, a write command WR, etc. After decoding these commands CMD, it can generate a row decoder control signal R_CTRL, a column decoder control signal C_CTRL, etc., so the status indication circuit 10 can be integrated in the command decoder 13.

[0086] The address decoder 15 (which may include a row decoder and a column decoder) is coupled to the memory controller 2 and the memory array 14, and is used to receive and decode the address signal ADD sent by the memory controller 2 to the memory 1, so as to activate the corresponding address of the memory array 14 (including the storage block address, row address, column address, etc.);

[0087] The data input / output circuit 16 is coupled to the memory controller 2 and the memory array 14 , and is used to write data DQ into the activated address of the memory array 14 or read data DQ from the activated address of the memory array 14 .

[0088] The memory of the present invention adopts the delay phase-locked loop system of the present invention. During the memory refresh operation and a period of time after the refresh operation, the delay phase-locked loop circuit can increase the step size of the delay adjustment relative to before the refresh operation, quickly adjust the internal clock signal offset output by the memory, thereby accelerating the locking speed of the delay phase-locked loop circuit, and finally aligning the phase of the internal clock signal output by the memory with the external clock signal received by the memory before the memory receives the next valid operation command, thereby avoiding errors in valid operations such as reading and writing after the refresh operation of the memory, and improving performance.

[0089] The above description is only a description of the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A delay locked loop system, characterized in that: Comprising: A status indication circuit for outputting a valid refresh status signal when receiving a refresh command to indicate that the memory is performing a refresh operation, where the refresh command comes from outside the memory; A status broadening circuit coupled to the status indication circuit and for generating a status control signal according to the valid refresh status signal, where the second edge of the status control signal is delayed relative to the second edge of the valid refresh status signal; A delay locked loop circuit for receiving an external clock signal and adjusting its delay with a first step size before the status indication circuit receives the refresh command, and then locking after outputting an internal clock signal phase-aligned with the external clock signal; Wherein, the delay locked loop circuit is further coupled to the status broadening circuit and is further used to work again under the control of the status control signal and adjust its delay with a second step size greater than the first step size.

2. The delay locked loop system according to claim 1, characterized in that: The first edge of the status control signal is aligned with the first edge of the valid refresh status signal.

3. The delay locked loop system according to claim 1, wherein: The status broadening circuit includes a delay circuit and an OR logic circuit. The input end of the delay circuit and the first input end of the OR logic circuit are both coupled to the valid refresh status signal. The output end of the delay circuit is coupled to the second input end of the OR logic circuit, and the output end of the OR logic circuit outputs the status control signal.

4. The delay locked loop system according to claim 1, wherein: The second step size is a fixed step size, or the second step size decreases as the phase offset of the internal clock signal relative to the external clock signal decreases.

5. The delay locked loop system according to claim 1, wherein: The delay locked loop circuit is further used to continue working under the control of the status control signal after the valid refresh status signal ends and before the status control signal ends, and adjust its delay with a third step size greater than the first step size. The third step size is a fixed step size or decreases as the phase offset of the internal clock signal relative to the external clock signal decreases; and / or, The delay locked loop circuit is further used to resume adjusting its delay with the first step size after the status control signal ends and before the next valid operation command is sent to the memory, so that the internal clock signal is phase-aligned with the external clock signal again.

6. The delay locked loop system as claimed in claim 5, characterized in that: The third step size is the same as the second step size, or the third step size is less than the second step size.

7. The delay-locked loop system according to claim 5, characterized in that: The minimum time interval between the refresh command and the next valid operation command is tRFC, the duration of the valid refresh status signal is t1, and t1 < tRFC; the duration by which the second edge of the status control signal is delayed relative to the second edge of the valid refresh status signal is less than tRFC - t1.

8. The delay-locked loop system according to any one of claims 1 to 7, characterized in that: The delay locked loop circuit includes: A signal receiver for receiving the external clock signal; A controllable delay chain for delaying the clock signal output by the signal receiver and then outputting it; A clock tree coupled to the controllable delay chain and outputting the clock signal output by the controllable delay chain as the internal clock signal; A clock feedback circuit, coupled to the controllable delay chain and configured to generate a feedback clock signal according to a clock signal output by the controllable delay chain; a phase detector, coupled to the clock feedback circuit and the signal receiver, and used to detect the phases of the clock signal output by the signal receiver and the feedback clock signal; A controller is coupled to the state stretching circuit, the phase detector and the controllable delay chain, and is used to adjust the delay of the controllable delay chain according to the state control signal and the phase detection result of the phase detector, so as to adjust the phase difference between the internal clock signal and the external clock signal.

9. The delay locked loop system as claimed in claim 8, characterized in that: A state machine is provided inside the controller, and the state machine is used to output and update a control code according to the state control signal and the phase detection result of the phase detector, so as to adjust the delay of the controllable delay chain with a corresponding step length.

10. The delay locked loop system according to claim 9, characterized in that: The state machine updates the control code at fixed time intervals during the locking process of the delay locked loop circuit.

11. A memory, characterized in that: The invention comprises a storage array and a delay-locked loop system as claimed in any one of claims 1 to 10.

12. The memory according to claim 11, wherein: The memory receives an operation command, an external clock signal, and an address signal from a memory controller, and outputs an internal clock signal and data to the memory controller.

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