Dynamic comparator offset voltage calibration method applied to SAR ADC upper pole plate sampling

Abstract

The invention relates to a dynamic comparator offset voltage calibration method applied to SAR ADC upper pole plate sampling, and belongs to the field of digital-analog hybrid integrated circuit design. According to the method, the offset voltage of the comparator is calibrated by adjusting the switching voltage of a lower polar plate of a capacitor in the sampling stage of the successive approximation analog-to-digital converter; the quantization process of the digital-to-analog converter of the successive approximation analog-to-digital converter comprises a calibration mode and a normal working mode. In the calibration mode, common-mode voltage is sampled by using a successive approximation analog-to-digital converter and then quantized to obtain an offset code. And in a normal working mode, switching of a capacitor lower polar plate in the capacitor array is controlled according to the offset code during sampling, and then normal quantization is performed to obtain an output quantization code for eliminating the offset voltage of the comparator. According to the invention, a series of problems of narrowing of an input signal window caused by the offset voltage of the comparator can be eliminated, the logic is simple and easy to realize, the calibration precision is high, and real-time refreshing is not needed.

Description

Technical Field

[0001] The invention belongs to the technical field of digital-analog hybrid integrated circuit design, and relates to a dynamic comparator offset voltage calibration method applied to SAR ADC upper plate sampling. Background Art

[0002] In today's electronic systems, analog-to-digital converters (ADCs) play an important role in digital signal processing (DSP), especially in portable devices, where data processing is mainly performed in the digital domain. However, ADCs are the bottleneck of DSP-based systems. In order to improve the performance of ADCs, the speed of analog-to-digital converters (ADCs) is getting higher and higher, and the power consumption is getting lower and lower. Compared with traditional high-speed and high-precision pipeline ADCs, successive approximation register (SAR) ADCs have the characteristics of simple structure, small area, low power consumption, and low cost. The continuous reduction of process feature size and the application of some technologies (such as time interleaving, multi-bit shifting, etc.) also make SAR ADCs possible to achieve high-speed conversion. Therefore, SAR ADCs have great potential in the application field of high speed and low power consumption.

[0003] The main modules in SAR ADC include: comparator, digital-to-analog converter (DAC), register unit and logic control unit. Among them, the comparator is the core circuit of SAR ADC, which determines the speed, accuracy and power consumption of ADC and plays a very important role. When the input of an ideal comparator is equal, it has the same probability of high and low level output; for an actual comparator, due to process mismatch, there is a comparator offset voltage V offset , only when the input difference is equal to the offset voltage V offset When the output is equal, the probability of outputting high and low levels is equal. A single-channel SAR ADC generally uses one comparator, so the comparator offset voltage mainly causes DC offset error, resulting in a reduction in the quantization range of the ADC, and also causes the input signal window to narrow. For SAR ADCs that use multiple comparators, comparator offset causes nonlinear errors, resulting in a decrease in ADC performance. Comparator offset is mainly caused by the mismatch between the threshold voltage and size of the input pair tube, so the offset effect can be reduced by increasing the size of the input tube, but a large size will inevitably lead to high power consumption. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide a dynamic comparator offset voltage calibration method applied to SAR ADC upper plate sampling, so as to solve the problems of reduced quantization range, narrowed input signal window and performance degradation caused by the dynamic comparator offset voltage during upper plate sampling in a successive approximation analog-to-digital converter.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] A dynamic comparator offset voltage calibration method for SAR ADC upper plate sampling, wherein the digital-to-analog converter of the SAR ADC includes two capacitor arrays, one of which is connected to one input end of the SAR ADC comparator, and the other is connected to the other input end of the SAR ADC comparator. In the capacitor array, the upper plate of each capacitor is used for sampling, and the lower plate of each capacitor is connected to a switching switch.

[0007] The method for implementing dynamic comparator offset voltage calibration comprises the following steps:

[0008] In the calibration mode of the SAR ADC digital-to-analog converter quantization process, the lower plate of each capacitor in the capacitor array is connected to the common mode voltage, and the upper plate samples the common mode voltage;

[0009] After sampling is completed, the upper plates of each capacitor in the capacitor array are disconnected from the common mode voltage, and the comparator starts to compare and switches the potential connected to the lower plates of each capacitor in the capacitor array one by one according to the comparison result. After quantization is completed, an output quantization code is obtained, that is, an offset code of the comparator offset voltage;

[0010] After the offset code is obtained, the SAR ADC digital-to-analog converter enters a normal working mode, and the upper plates of each capacitor in the capacitor array sample the input signal. During the sampling process, the potential connected to the lower plates of each capacitor is reversely switched according to the offset code;

[0011] After sampling is completed, the upper plates of each capacitor in the capacitor array are disconnected from the input signal, and the lower plates of each capacitor are connected to the common mode voltage, and quantization begins; wherein the comparator starts to compare and replaces the potential connected to the lower plates of each capacitor in the capacitor array one by one according to the comparison result, until the lower plate of the lowest-order capacitor in the capacitor array is switched, and a quantization code is output, and the obtained quantization code is the result of eliminating the influence of the comparator offset voltage.

[0012] Furthermore, the SAR ADC is a single-ended sampling digital-to-analog converter, wherein one input of the comparator is connected to a capacitor array, and the other input of the comparator is connected to a positive reference voltage, and when sampling the common-mode voltage, the lower plates of each capacitor in the capacitor array are connected to the common-mode voltage.

[0013] Furthermore, the SAR ADC can also be a two-terminal sampling digital-to-analog converter, wherein both input terminals of the comparator are connected to a capacitor array, and when sampling the common-mode voltage, the lower plates of each capacitor in the capacitor array are connected to the common-mode voltage.

[0014] The beneficial effects of the present invention are as follows: the present invention can eliminate the influence of the comparator offset voltage in the output quantization code obtained by the SAR ADC, and can eliminate a series of problems of narrowing the input signal window caused by the comparator offset voltage. The logic is simple and easy to implement. Except for a small part of the implementation logic, no additional circuit module needs to be added. The calibration accuracy is high and no real-time refresh is required.

[0015] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0017] Figure 1 It is a schematic diagram of the process of the method of the present invention;

[0018] Figure 2 It is a SAR ADC capacitor array based on upper plate sampling;

[0019] Figure 3 Schematic diagram of the capacitor array switch during sampling in the calibration phase;

[0020] Figure 4 Schematic diagram of capacitor array switches during quantization in the calibration phase;

[0021] Figure 5 This is a schematic diagram of the capacitor array switch during sampling during the normal working phase;

[0022] Figure 6 This is a schematic diagram of the capacitor array switch during quantization in the normal working stage. DETAILED DESCRIPTION

[0023] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0024] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0025] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0026] The present invention provides a dynamic comparator offset voltage calibration method, which is applicable to a successive approximation analog-to-digital converter in the form of upper plate sampling. The method realizes the calibration of the comparator offset voltage by adjusting the switch switching voltage of the lower plate of the capacitor during the sampling phase of the successive approximation analog-to-digital converter. The quantization process of the digital-to-analog converter of the successive approximation analog-to-digital converter includes a calibration mode and a normal working mode. In the calibration mode, the common mode voltage V is calibrated by using the successive approximation analog-to-digital converter. cm Sampling is performed, and then quantization is performed to obtain an offset code. In normal working mode, the switch switching of the lower plate of the capacitor in the capacitor array is controlled according to the offset code during sampling, and then normal quantization is performed to obtain an output quantization code that eliminates the offset voltage of the comparator. The method proposed by the present invention can eliminate the relevant influence of the offset voltage of the comparator in the output quantization code obtained by the successive approximation analog-to-digital converter, and can eliminate a series of problems caused by the offset voltage of the comparator that narrows the input signal window. The logic is simple and easy to implement. No additional circuit module needs to be added except for a small part of the implementation logic, and the calibration accuracy is high, and no real-time refresh is required.

[0027] The DAC in the successive approximation ADC is divided into single-ended sampling and double-ended sampling. Figure 2 The working process of the present invention is described in detail by taking the double-ended sampling of the digital-to-analog converter shown in FIG. Figure 1 As shown, the method is specifically:

[0028] In calibration mode, Figure 3 As shown, during the sampling phase, the lower plates of the upper and lower capacitor arrays are connected to the common mode voltage V cm , the upper plate samples the common-mode voltage.

[0029] The sampling completed digital-to-analog converter is quantized normally, such as Figure 4 As shown, the comparator starts to compare and switches the potential connected to the lower plate of the capacitor successively according to the comparison result. The output quantization code obtained after quantization is completed is the offset code of the comparator offset voltage.

[0030] After the offset code is obtained, the calibration phase ends and the normal working phase begins. During sampling, the potential connected to the lower plate of the capacitor is reversely switched according to the offset code obtained, and the upper plate of the capacitor samples the input signal, such as Figure 5 As shown, at this time, after the sampling of the sampled signal is completed, when all the lower plates are connected to the common mode voltage, the maintained signal will rise or fall a DC voltage according to the obtained offset code to resist the influence of the comparator offset voltage.

[0031] After sampling is completed, the upper plate of the capacitor array is disconnected from the input signal, and the lower plates are all connected to the common mode voltage, such as Figure 6 As shown, the quantization stage begins, the comparator starts to compare and replaces the potential connected to the lower plate of the capacitor array one by one according to the comparison result, until the lower plate of the lowest capacitor in the capacitor array is switched, all quantization codes are output, and the work is completed. The obtained quantization code is the result of eliminating the influence of the comparator offset voltage.

[0032] The working principle of the method described in the present invention is: the SAR ADC samples the input signal through the upper plate of the CDAC capacitor array, and completes the quantization process in combination with the comparator. Before the normal working mode, the digital code of the offset voltage of the comparator in the CDAC capacitor array is first collected, and the common mode voltage is sampled, and then the quantization process is performed normally, so that the digital code corresponding to the offset voltage can be obtained.

[0033] When the DAC is single-ended, one input of the comparator is connected to the capacitor array, and the other input of the comparator is connected to the positive reference voltage, so that the quantization range of the single-ended SAR ADC is -V cm ~+V cm , for the common mode voltage V cm When sampling, connect the upper plates of all capacitors of CDAC to the common mode voltage, that is, switch the input voltage to the common mode voltage. When the digital-to-analog converter samples at both ends, due to the differential structure of the SAR ADC, if the input is V ip ~V in , then the sampling voltages on both sides are V cm -V ip and V cm -V in In the sampling phase of the normal working mode of the SAR ADC, according to the offset code obtained in the calibration phase, the potential of the lower plate of the capacitor array that should be connected to the common mode voltage is switched to a high level or a low level to compensate the input signal, thereby achieving the purpose of offset calibration.

[0034] Taking a dual-ended sampling 5-bit SAR ADC as an example, according to the working principle of SAR ADC, in the calibration mode, the sampled charge of the CDAC capacitor array is:

[0035]

[0036] Among them, Q p Q is the charge on the upper plate of the capacitor array connected to the positive terminal of the comparator CDAC. n is the charge on the upper plate of the capacitor array connected to the negative terminal of the comparator CDAC, V cm is the common mode voltage, V ip 、V in are the input voltage sampled at both ends of the differential CDAC, C t is the total capacitance of CDAC. At this time, due to the sampling common mode voltage V cm , so at this moment V in =V ip =V cm , and Q p =Q n =0.

[0037] At the beginning of the calibration phase, the input voltage switch is disconnected, and the lower plate of the capacitor array is connected to V cm At this time, the voltage across the comparator is V cm , due to the comparator offset voltage V offset , the quantized result will not be 10000 or 01111, but a result containing the comparator offset voltage, such as 10011, 01100, etc. In this way, the equivalent offset code of the comparator offset voltage in CDAC can be obtained, such as 00011.

[0038] After the offset code is obtained, the normal working mode is entered. During the sampling phase, the corresponding capacitor in CDAC is connected to V according to the offset code. cm The lower plate is reversely connected to the high reference level V refp Or low reference level V refn , to counteract the impact of the comparator offset voltage. At this time, the CDAC capacitor array sampling charge is:

[0039]

[0040] Among them, C i is the i-th capacitor in the capacitor array from large to small; V ci is the potential of the lower plate of the i-th capacitor, which is V refp or V refn , V ci The reverse potential, such as Vci V refp hour V refn .

[0041] After sampling, the holding phase begins. At this time, the lower plates of all capacitors in the capacitor array are connected to V cm , the input voltage of the comparator is:

[0042]

[0043] According to the sampling result of formula (3), the method of the present invention introduces a certain amount of charge to counteract the influence of the dynamic comparator offset voltage by switching the potential connected to the lower plate of the capacitor, so that the calibration accuracy can be achieved within 1 LSB.

[0044] After that, the SAR ADC enters the quantization process, and the comparator starts to compare and replaces the potential connected to the lower plate of the capacitor array one by one according to the comparison result, until the lower plate of the lowest capacitor in the capacitor array is switched, and all quantization codes are output. The work is completed, and the obtained quantization code is the result of eliminating the influence of the comparator offset voltage.

[0045] In summary, the present invention proposes a dynamic comparator offset voltage calibration method for SAR ADC applied to upper plate sampling, which can be achieved by adding a small part of logic switching circuit on the basis of the traditional digital-to-analog converter CDAC. The calibration has high accuracy, does not require an additional calibration capacitor array and does not require periodic refresh, and can be used after calibration once.

[0046] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. A dynamic comparator offset voltage calibration method for SAR ADC upper plate sampling, wherein the SAR ADC includes two capacitor arrays, one of which is connected to one input end of the SAR ADC comparator, and the other is connected to the other input end of the SAR ADC comparator; in the capacitor array, the upper plate of each capacitor is used for sampling, and the lower plate of each capacitor is connected to a switch; characterized in that: The method includes: In the calibration mode of the SAR ADC digital-to-analog converter quantization process, the lower plate of each capacitor in the capacitor array is connected to the common mode voltage, and the upper plate samples the common mode voltage; After sampling is completed, the upper plates of each capacitor in the capacitor array are disconnected from the common mode voltage, and the comparator starts to compare and switches the potential connected to the lower plates of each capacitor in the capacitor array one by one according to the comparison result. After quantization is completed, an output quantization code is obtained, that is, an offset code of the comparator offset voltage; After the offset code is obtained, the SAR ADC digital-to-analog converter enters a normal working mode, and the upper plates of each capacitor in the capacitor array sample the input signal. During the sampling process, the potential connected to the lower plates of each capacitor is reversely switched according to the offset code; After sampling is completed, the upper plates of each capacitor in the capacitor array are disconnected from the input signal, and the lower plates of each capacitor are connected to the common mode voltage, and quantization begins; wherein the comparator starts to compare and replaces the potential connected to the lower plates of each capacitor in the capacitor array one by one according to the comparison result, until the lower plate of the lowest-order capacitor in the capacitor array is switched, and a quantization code is output, and the obtained quantization code is the result of eliminating the influence of the comparator offset voltage.

2. The method according to claim 1, characterized in that: The SAR ADC is a single-ended sampling digital-to-analog converter, wherein one input end of the comparator is connected to the capacitor array, and the other input end of the comparator is connected to the positive reference voltage. When sampling the common-mode voltage, the lower plates of each capacitor in the capacitor array are connected to the common-mode voltage.

3. The method according to claim 1, characterized in that: The SAR ADC is a double-ended sampling digital-to-analog converter, wherein both input terminals of the comparator are connected to a capacitor array, and when sampling the common-mode voltage, the lower plates of each capacitor in the capacitor array are connected to the common-mode voltage.

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