Clock generation device

Abstract

The invention discloses a clock generation device, which belongs to the technical field of clock generation and comprises an inductance-capacitance clock generator, a resistance-capacitance clock generator, an inductance-capacitance clock generator control voltage detection module, an inductance-capacitance clock generator coarse tuning module and a self-detection module. At the beginning, the self-detection module generates a first starting control signal and outputs the first starting control signal to the inductance-capacitance clock generator, and meanwhile, the self-detection module also generates a second starting control signal and outputs the second starting control signal to the resistance-capacitance clock generator; and the inductor-capacitor clock generator coarse tuning module starts to work and outputs a control word to the inductor-capacitor clock generator and the self-detection module. According to comparison between the working range of the clock generator and the working condition, the proper clock generator is selected as a clock source of the serdes, and it is guaranteed that the jitter requirement can be met at different rates.

Description

Technical Field

[0001] The invention belongs to the technical field of clock generation, and in particular relates to a clock generation device. Background Art

[0002] In the application of serial / serial-to-parallel converters (serdes) with data rates ranging from a few G to more than ten G, a clock generator with a wide range of output frequencies is required. Usually, the frequency range of the output of a common single clock generator is narrow and cannot meet the requirements. Multiple clock generators are needed to achieve a wide range of output frequencies. However, in the current situation, since multiple clock generators are in different individuals, most applications need to know the specific conditions through register configuration, which greatly reduces the convenience of use. At the same time, if the specific conditions are unknown, the system may fail to work directly. How to solve the problem of different clock generators adapting to different working conditions has become a difficult problem. Summary of the invention

[0003] In view of the shortcomings of the prior art, the present invention provides a clock generating device which can select a suitable clock generator as a clock source of a serial / serial-to-parallel converter (serdes) according to the working range of the clock generator and the comparison of the working conditions.

[0004] The technical solution of the present invention is as follows: A clock generating device, comprising an inductor-capacitor clock generator, a resistor-capacitor clock generator, an inductor-capacitor clock generator control voltage detection module, an inductor-capacitor clock generator coarse adjustment module, and a self-detection module; Initially, the self-detection module generates a first start-up control signal and outputs it to the inductor and capacitor clock generator. At the same time, the self-detection module also generates a second start-up control signal and outputs it to the resistor and capacitor clock generator; the inductor and capacitor clock generator coarse adjustment module starts working and outputs the control word to the inductor and capacitor clock generator and the self-detection module; The LC clock generator starts to work after receiving the first start control signal and generates a clock corresponding to the current control word and a current control voltage VCNTL corresponding to the current control word under the control of the current control word; When the control voltage detection module of the inductor and capacitor clock generator detects the current control voltage VCNTL, it compares the current control voltage VCNTL with the first reference voltage and the second reference voltage; when the current control voltage VCNTL is less than the first reference voltage, the control voltage detection module of the inductor and capacitor clock generator outputs a first voltage indication signal; when the current control voltage VCNTL is greater than or equal to the first reference voltage and less than or equal to the second reference voltage, the control voltage detection module of the inductor and capacitor clock generator outputs a second voltage indication signal; when the current control voltage VCNTL is greater than the second reference voltage, the control voltage detection module of the inductor and capacitor clock generator outputs a third voltage indication signal; wherein, the first reference voltage is less than the second reference voltage; The method for the coarse adjustment module of the inductor and capacitor clock generator to find the upper limit of the control word that makes the inductor and capacitor clock generator lock is: using the binary method to determine the current control word bit by bit from the high bit to the low bit; first determine the highest bit of the current control word, and when the coarse adjustment module of the inductor and capacitor clock generator receives the first voltage indication signal, the highest bit of the current control word is set to 0; when the coarse adjustment module of the inductor and capacitor clock generator receives the second voltage indication signal, the highest bit of the current control word is set to 1; when the coarse adjustment module of the inductor and capacitor clock generator receives the third voltage indication signal, the highest bit of the current control word is set to 1; then according to the method of setting the highest bit in the process of finding the upper limit of the current control word that makes the inductor and capacitor clock generator lock, determine the second highest bit of the current control word; and so on, until the lowest bit of the current control word is determined; The method for the coarse adjustment module of the inductor and capacitor clock generator to find the lower limit of the control word that makes the inductor and capacitor clock generator lock is: using the binary method to determine the current control word bit by bit from the high bit to the low bit; first determine the highest bit of the current control word, and when the coarse adjustment module of the inductor and capacitor clock generator receives the first voltage indication signal, the highest bit of the current control word is set to 0; when the coarse adjustment module of the inductor and capacitor clock generator receives the second voltage indication signal, the highest bit of the current control word is set to 0; when the coarse adjustment module of the inductor and capacitor clock generator receives the third voltage indication signal, the highest bit of the current control word is set to 1; then according to the method of setting the highest bit in the process of finding the lower limit of the current control word that makes the inductor and capacitor clock generator lock, determine the second highest bit of the current control word; and so on, until the lowest bit of the current control word is determined; When the upper limit of the control word and the lower limit of the control word are found, the coarse adjustment module of the LC clock generator sets the coarse adjustment end indication signal CAL_DONE to 1, otherwise the coarse adjustment end indication signal CAL_DONE is set to 0 and the above-mentioned method of finding the upper limit of the control word that makes the LC clock generator lock and the method of finding the lower limit of the control word that makes the LC clock generator lock are repeated until the upper limit of the control word and the lower limit of the control word are found; When the upper limit of the control word and the lower limit of the control word are found, the coarse adjustment module of the inductor and capacitor clock generator takes the arithmetic mean of the upper limit of the control word and the lower limit of the control word as the control signal CRS_SET[6:0] and outputs it; at the same time, if the voltage indication signal received by the coarse adjustment module of the inductor and capacitor clock generator at this time is the second voltage indication signal, the coarse adjustment module of the inductor and capacitor clock generator sets the lock indication signal LOCK to 1, otherwise, the lock indication signal LOCK is set to 0; The self-detection module starts working when it detects that the coarse adjustment end indication signal CAL_DONE is 1; the self-detection module generates a first shutdown control signal and a second start control signal when it detects that all bits of the control signal are all zero; the self-detection module generates a first start control signal and a second shutdown control signal when it detects that all bits of the control signal are not all zero and the lock indication signal LOCK is 1; the self-detection module generates a first shutdown control signal and a second shutdown control signal when it detects that all bits of the control signal are not all zero and the lock indication signal LOCK is 0; Among them, the inductor and capacitor clock generator is turned off when it receives the first shutdown control signal, and the inductor and capacitor clock generator outputs the clock when it receives the first startup control signal; the resistor and capacitor clock generator is turned off when it receives the second shutdown control signal, and outputs the clock when it receives the second startup control signal.

[0005] The first reference voltage and the second reference voltage are generated by an inductor-capacitor clock generator controlling a voltage detection module.

[0006] The self-detection module starts to work when detecting that the coarse adjustment end indication signal CAL_DONE is 1.

[0007] If the LC clock generator coarse adjustment module uses the successive approximation method to find the upper limit of the control word that locks the LC clock generator, initially, the LC clock generator coarse adjustment module sets the control word to 1000000; wherein 1000000 is the middle value of the control word.

[0008] If the LC clock generator coarse adjustment module uses the successive approximation method to find the lower limit of the control word that locks the LC clock generator, initially, the LC clock generator coarse adjustment module sets the control word to 1000000; wherein 1000000 is the middle value of the control word.

[0009] The beneficial effects of the present invention are as follows: The present invention adopts two structural clock generators: one is a resistor-capacitor clock generator using a ring oscillator, and the other is an inductor-capacitor clock generator using an inductor-capacitor oscillator. When the parallel-to-serial / serial-to-parallel converter (SERDES) works at a lower data rate, the resistor-capacitor clock generator is used, and when the parallel-to-serial converter / serial-to-parallel (SERDES) works at a higher data rate, the inductor-capacitor clock generator is used. The advantage of the resistor-capacitor clock generator is that the operating frequency range is relatively wide, and the disadvantage is that the noise characteristics are poor. The inductor-capacitor clock generator has a narrow operating frequency range, but has better noise characteristics. In general, which clock generator to use will be configured according to the data rate, but due to the deviation between the simulation results and the manufacturing, and the different output frequency ranges of each clock generator under different process angles, the configuration of which clock generator to use according to the data rate cannot fully utilize the advantages of the noise characteristics of the inductor-capacitor clock generator.

[0010] The present invention realizes automatic selection of different clock generators by adding detection of different working conditions, wherein the detection of different working conditions is as follows: according to the comparison between the working range of the clock generator and the working conditions, a suitable clock generator is selected as the clock source of the parallel-to-serial / serial-to-parallel converter (serdes) to ensure that the jitter requirements can be met at different rates. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a logical structure diagram of the present invention; Figure 2 It is a flow chart of the present invention. DETAILED DESCRIPTION

[0012] The present invention is further described below by means of specific examples, but is not limited thereto.

[0013] See also Figure 1 , Figure 2 A clock generating device in many embodiments of the present invention includes an inductor-capacitor clock generator, a resistor-capacitor clock generator, an inductor-capacitor clock generator control voltage detection module, an inductor-capacitor clock generator coarse adjustment module, and a self-detection module.

[0014] Initially, the self-detection module generates a first start-up control signal and outputs it to the LC clock generator. At the same time, the self-detection module also generates a second start-up control signal and outputs it to the RC clock generator. The LC clock generator coarse adjustment module starts to work and outputs the control word to the LC clock generator and the self-detection module. When LC_CK_PD=0, it is the first start-up control signal, and when RC_CK_PD=0, it is the second start-up control signal, that is, when the self-detection module sets the current first control signal LC_CK_PD to 0, the current first control signal LC_CK_PD is the first start-up control signal, and when the self-detection module sets the current second control signal RC_CK_PD to 0, the current second control signal RC_CK_PD is the second start-up control signal.

[0015] The LC clock generator starts to work after receiving the first start control signal and generates a clock corresponding to the current control word and a current control voltage VCNTL corresponding to the current control word under the control of the current control word.

[0016] When the control voltage detection module of the inductor and capacitor clock generator detects the current control voltage VCNTL, the current control voltage VCNTL is compared with the first reference voltage and the second reference voltage. When the current control voltage VCNTL is less than the first reference voltage, the control voltage detection module of the inductor and capacitor clock generator outputs a first voltage indication signal, indicating that the oscillation frequency corresponding to the current control word is too high, and the adjustment direction of the loop is to reduce the oscillation frequency. When the current control voltage VCNTL is greater than or equal to the first reference voltage and less than or equal to the second reference voltage, the control voltage detection module of the inductor and capacitor clock generator outputs a second voltage indication signal, indicating that the oscillation frequency corresponding to the current control word can lock the loop. When the current control voltage VCNTL is greater than the second reference voltage, the control voltage detection module of the inductor and capacitor clock generator outputs a third voltage indication signal, indicating that the oscillation frequency corresponding to the current control word is too low, and the adjustment direction of the loop is to increase the oscillation frequency. Among them, the first reference voltage is less than the second reference voltage, the first reference voltage is used as the lower limit of the control voltage for controlling the oscillation of the inductor and capacitor clock generator, and the second reference voltage is used as the upper limit of the control voltage for controlling the oscillation of the inductor and capacitor clock generator.

[0017] The LC clock generator control voltage detection module is used to detect the current control voltage VCNTL of the LC clock generator, and the voltage indication signal VCNTL_DET[1:0] output by the module is used to indicate the state of the control voltage VCNTL.

[0018] When the current control voltage VCNTL is high, the oscillation frequency of the LC clock generator is high. When the current control voltage VCNTL is low, the oscillation frequency of the LC clock generator is low.

[0019] The voltage indication signal VCNTL_DET[1:0] includes a first voltage indication signal, a second voltage indication signal, and a third voltage indication signal. VCNTL_DET[1] is a comparison result between the control voltage VCNTL and the second reference voltage. When VCNTL_DET[1] is 0, it indicates that the control voltage VCNTL is higher than the second reference voltage. When VCNTL_DET[1] is 0, VCNTL_DET[1] is used as the third voltage indication signal; when VCNTL_DET[1] is 1, it indicates that the control voltage VCNTL is lower than the second reference voltage. VCNTL_DET[0] is a comparison result between the control voltage VCNTL and the first reference voltage. When VCNTL_DET[0] is 1, it indicates that the control voltage VCNTL is higher than the first reference voltage. When VCNTL_DET[0] is 0, it indicates that the control voltage VCNTL is lower than the first reference voltage. When VCNTL_DET[0] is 0, VCNTL_DET[0] is used as the first voltage indication signal. When both VCNTL_DET[1] and VCNTL_DET[0] are 1, they are used as the second voltage indication signal. In this way, the voltage indication signal VCNTL_DET[1:0] reflects three states of the control voltage VCNTL: 1) VCNTL_DET[1:0]=10, indicating that the control voltage VCNTL at this time is lower than the first reference voltage; 2) VCNTL_DET[1:0]=11, indicating that the control voltage VCNTL at this time is between the second reference voltage and the first reference voltage; 3) VCNTL_DET[1:0]=01, indicating that the control voltage VCNTL at this time is higher than the second reference voltage. Among them, VCNTL_DET[1] is the high bit of the voltage indication signal VCNTL_DET[1:0], and VCNTL_DET[0] is the low bit of the voltage indication signal VCNTL_DET[1:0].

[0020] The first reference voltage and the second reference voltage may be, but are not limited to, generated by an LC clock generator controlling a voltage detection module.

[0021] The method for the coarse adjustment module of the inductor and capacitor clock generator to find the upper limit of the control word that locks the inductor and capacitor clock generator is: using the binary method to determine the current control word bit by bit from the high bit to the low bit; first determine the highest bit of the current control word, and when the coarse adjustment module of the inductor and capacitor clock generator receives the first voltage indication signal, the highest bit of the current control word is set to 0; when the coarse adjustment module of the inductor and capacitor clock generator receives the second voltage indication signal, the highest bit of the current control word is set to 1; when the coarse adjustment module of the inductor and capacitor clock generator receives the third voltage indication signal, the highest bit of the current control word is set to 1; then according to the method of setting the highest bit in the process of finding the upper limit of the current control word that locks the inductor and capacitor clock generator, determine the second highest bit of the current control word; and so on, until the lowest bit of the current control word is determined.

[0022] For example, in the process of finding the upper limit of the control word that locks the inductor and capacitor clock generator, taking the successive approximation method as an example, initially the coarse adjustment module of the inductor and capacitor clock generator first sets the control word to 1000000, and 1000000 is the middle value of the control word; then the binary method is used to determine the current control word bit by bit from high bit to low bit, first determine the highest bit of the current control word, and determine whether the highest bit of the current control word is maintained at 1 or set to 0 according to the voltage indication signal VCNTL_DET[1:0] output by the inductor and capacitor voltage detection module; then determine the second highest bit of the current control word until the lowest bit is determined. Specifically, 1) when VCNTL_DET[1:0]=10, VCNTL_DET[1:0] is used as the first voltage indication signal, indicating that the control voltage VCNTL is lower than the first reference voltage, and the adjustment direction of the loop is to reduce the oscillation frequency, indicating that the oscillation frequency corresponding to the current control word is too high, and the current bit of the current control word needs to be set to 0; 2) when VCNTL_DET[1:0]=11, VCNTL_DET[1:0] is used as the second voltage indication signal, indicating that the control voltage VCNTL is between the second reference voltage and the first reference voltage, indicating that the oscillation frequency corresponding to the current control word can lock the loop, and keep the current bit of the current control word at 1; 3) when VCNTL_DET[1:0]=01, VCNTL_DET[1:0] is used as the third voltage indication signal, indicating that the control voltage VCNTL is higher than the upper limit of the control voltage, and the adjustment direction of the loop is to increase the oscillation frequency, indicating that the oscillation frequency corresponding to the current control word is too low, and the current bit of the current control word needs to be kept at 1. You can also use the enumeration method. The successive approximation method only makes 7 comparisons, while the enumeration method needs to do it 128 times. That is, the current control word ranges from 0000000 to 1111111. The frequency corresponding to each value will be calculated and then the maximum value will be confirmed.

[0023] The method for the coarse adjustment module of the inductor and capacitor clock generator to find the lower limit of the control word that locks the inductor and capacitor clock generator is as follows: the current control word is determined bit by bit from high bit to low bit by using the binary method; firstly, the highest bit of the current control word is determined, and when the coarse adjustment module of the inductor and capacitor clock generator receives the first voltage indication signal, the highest bit of the current control word is set to 0; when the coarse adjustment module of the inductor and capacitor clock generator receives the second voltage indication signal, the highest bit of the current control word is set to 0; when the coarse adjustment module of the inductor and capacitor clock generator receives the third voltage indication signal, the highest bit of the current control word is set to 1; then, according to the method of setting the highest bit in the process of finding the lower limit of the current control word that locks the inductor and capacitor clock generator, the second highest bit of the current control word is determined; and so on, until the lowest bit of the current control word is determined.

[0024] For example, in the process of finding the lower limit of the control word locked by the inductor and capacitor clock generator, taking the successive approximation method as an example, initially the coarse adjustment module of the inductor and capacitor clock generator sets the control word to an intermediate value of 1000000, and 1000000 is the intermediate value of the control word; then the binary method is used to determine the current control word bit by bit from high bit to low bit, first determine the highest bit of the current control word, and determine whether the highest bit of the current control word is maintained at 1 or set to 0 according to the voltage indication signal VCNTL_DET[1:0] output by the inductor and capacitor voltage detection module; then determine the second highest bit of the current control word until the lowest bit is determined. Specifically, 1) when VCNTL_DET[1:0]=10, VCNTL_DET[1:0] is used as the first voltage indication signal, indicating that the control voltage VCNTL is lower than the first reference voltage, and the adjustment direction of the loop is to reduce the oscillation frequency, indicating that the oscillation frequency corresponding to the current control word is too high, and the current bit of the current control word needs to be set to 0; 2) when VCNTL_DET[1:0]=11, VCNTL_DET[1:0] is used as the second voltage indication signal, indicating that the control voltage VCNTL is between the second reference voltage and the first reference voltage, indicating that the oscillation frequency corresponding to the current control word can lock the loop, and the current bit of the current control word needs to be set to 0; 3) when VCNTL_DET[1:0]=01, VCNTL_DET[1:0] is used as the third voltage indication signal, indicating that the control voltage VCNTL is higher than the upper limit of the control voltage, and the adjustment direction of the loop is to increase the oscillation frequency, indicating that the oscillation frequency corresponding to the current control word is too low, and the current bit of the current control word needs to be kept at 1. You can also use the enumeration method. The successive approximation method only makes 7 comparisons, while the enumeration method needs to do it 128 times. That is, the current control word ranges from 0000000 to 1111111. The frequency corresponding to each value will be calculated and then the minimum value will be confirmed.

[0025] When the upper limit of the control word and the lower limit of the control word are found, the coarse adjustment module of the LC clock generator sets the coarse adjustment end indication signal CAL_DONE to 1, otherwise the coarse adjustment end indication signal CAL_DONE is set to 0 and the above-mentioned method of finding the upper limit of the control word that makes the LC clock generator lock and the method of finding the lower limit of the control word that makes the LC clock generator lock are repeated until the upper limit of the control word and the lower limit of the control word are found. When the coarse adjustment end indication signal CAL_DONE is 1, it indicates that the coarse adjustment is finished.

[0026] When the upper limit of the control word and the lower limit of the control word are found, the coarse adjustment module of the inductor and capacitor clock generator takes the arithmetic mean of the upper limit of the control word and the lower limit of the control word as the control signal CRS_SET[6:0] and outputs it; at the same time, if the voltage indication signal VCNTL_DET[1:0] received by the coarse adjustment module of the inductor and capacitor clock generator is the second voltage indication signal, the coarse adjustment module of the inductor and capacitor clock generator sets the lock indication signal LOCK to 1, otherwise, sets the lock indication signal LOCK to 0. When the lock indication signal LOCK is 1, it indicates that the loop of the inductor and capacitor clock generator is locked.

[0027] The LC clock generator coarse adjustment module is used to find the control signal CRS_SET[6:0] that makes the LC clock generator lock. When the control signal is larger, the oscillation frequency is higher, and when the control signal is smaller, the oscillation frequency is lower.

[0028] The self-detection module generates a first shutdown control signal and a second start control signal when it detects that all bits of the control signal CRS_SET[6:0] are all zero; the self-detection module generates a first start control signal and a second shutdown control signal when it detects that all bits of the control signal CRS_SET[6:0] are not all zero and the lock indication signal LOCK is 1; the self-detection module generates a first shutdown control signal and a second shutdown control signal when it detects that all bits of the control signal CRS_SET[6:0] are not all zero and the lock indication signal LOCK is 0. Among them, LC_CK_PD=1 is the first shutdown control signal, and RC_CK_PD=1 is the second shutdown control signal.

[0029] Specifically, if all bits of the control signal CRS_SET[6:0] are 0, it indicates that the frequency locked by the inductor-capacitor clock generator is lower than or at the edge of the lower limit of the oscillation frequency of the inductor-capacitor clock generator. The clock generation module is switched to the resistor-capacitor clock generator, and LC_CK_PD=1 and RC_CK_PD=0 are set. At this time, LC_CK_PD is used as the first shutdown control signal and RC_CK_PD is used as the second start control signal to shut down the inductor-capacitor clock generator and keep the resistor-capacitor clock generator turned on. When the control signal CRS_SET[6:0] is not 0, if LOCK=1, it indicates that the frequency locked by the inductor-capacitor clock generator is within the oscillation frequency range of the inductor-capacitor clock generator. LC_CK_PD=0 and RC_CK_PD=1 are set. At this time, LC_CK_PD is used as the first start control signal and RC_CK_PD is used as the second shutdown control signal to shut down the resistor-capacitor clock generator and keep the inductor-capacitor clock generator turned on. If LOCK=0, it indicates that the frequency locked by the clock generator has exceeded the oscillation frequency range of the LC clock generator and the RC clock generator. Set LC_CK_PD=1, RC_CK_PD=1. At this time, LC_CK_PD is used as the first shutdown control signal and RC_CK_PD is used as the second shutdown control signal to shut down the RC clock generator and the LC clock generator.

[0030] The inductor and capacitor clock generator is turned off when receiving the first shutdown control signal, and outputs the clock when receiving the first start control signal; the resistor and capacitor clock generator is turned off when receiving the second shutdown control signal, and outputs the clock when receiving the second start control signal.

[0031] The self-detection module may start working only when the coarse adjustment end indication signal CAL_DONE is 1.

[0032] The upper limit of the control word mentioned above refers to the maximum value of the control word when the PLL is locked, and the lower limit of the control word refers to the minimum value of the control word when the PLL is locked.

Claims

1. A clock generating device, characterized in that: It includes an inductor and capacitor clock generator, a resistor and capacitor clock generator, an inductor and capacitor clock generator control voltage detection module, an inductor and capacitor clock generator coarse adjustment module, and a self-detection module; Initially, the self-detection module generates a first start-up control signal and outputs it to the inductor and capacitor clock generator. At the same time, the self-detection module also generates a second start-up control signal and outputs it to the resistor and capacitor clock generator; the inductor and capacitor clock generator coarse adjustment module starts working and outputs the control word to the inductor and capacitor clock generator and the self-detection module; The LC clock generator starts to work after receiving the first start control signal and generates a clock corresponding to the current control word and a current control voltage VCNTL corresponding to the current control word under the control of the current control word; When the control voltage detection module of the LC clock generator detects the current control voltage VCNTL, it compares the current control voltage VCNTL with the first reference voltage and the second reference voltage; When the current control voltage VCNTL is less than the first reference voltage, the LC clock generator controls the voltage detection module to output a first voltage indication signal; When the current control voltage VCNTL is greater than or equal to the first reference voltage and less than or equal to the second reference voltage, the LC clock generator controls the voltage detection module to output a second voltage indication signal; When the current control voltage VCNTL is greater than the second reference voltage, the LC clock generator controls the voltage detection module to output a third voltage indication signal; wherein the first reference voltage is less than the second reference voltage; The method for the coarse adjustment module of the inductor and capacitor clock generator to find the upper limit of the control word that makes the inductor and capacitor clock generator lock is: using the binary method to determine the current control word bit by bit from the high bit to the low bit; first determine the highest bit of the current control word, and when the coarse adjustment module of the inductor and capacitor clock generator receives the first voltage indication signal, the highest bit of the current control word is set to 0; when the coarse adjustment module of the inductor and capacitor clock generator receives the second voltage indication signal, the highest bit of the current control word is set to 1; when the coarse adjustment module of the inductor and capacitor clock generator receives the third voltage indication signal, the highest bit of the current control word is set to 1; then according to the method of setting the highest bit in the process of finding the upper limit of the current control word that makes the inductor and capacitor clock generator lock, determine the second highest bit of the current control word; and so on, until the lowest bit of the current control word is determined; The method for the coarse adjustment module of the inductor and capacitor clock generator to find the lower limit of the control word that makes the inductor and capacitor clock generator lock is: using the binary method to determine the current control word bit by bit from the high bit to the low bit; first determine the highest bit of the current control word, and when the coarse adjustment module of the inductor and capacitor clock generator receives the first voltage indication signal, the highest bit of the current control word is set to 0; when the coarse adjustment module of the inductor and capacitor clock generator receives the second voltage indication signal, the highest bit of the current control word is set to 0; when the coarse adjustment module of the inductor and capacitor clock generator receives the third voltage indication signal, the highest bit of the current control word is set to 1; then according to the method of setting the highest bit in the process of finding the lower limit of the current control word that makes the inductor and capacitor clock generator lock, determine the second highest bit of the current control word; and so on, until the lowest bit of the current control word is determined; When the upper limit of the control word and the lower limit of the control word are found, the coarse adjustment module of the LC clock generator sets the coarse adjustment end indication signal CAL_DONE to 1, otherwise the coarse adjustment end indication signal CAL_DONE is set to 0 and the above-mentioned method of finding the upper limit of the control word that makes the LC clock generator lock and the method of finding the lower limit of the control word that makes the LC clock generator lock are repeated until the upper limit of the control word and the lower limit of the control word are found; When the upper limit of the control word and the lower limit of the control word are found, the coarse adjustment module of the inductor and capacitor clock generator takes the arithmetic mean of the upper limit of the control word and the lower limit of the control word as the control signal CRS_SET[6:0] and outputs it; at the same time, if the voltage indication signal received by the coarse adjustment module of the inductor and capacitor clock generator at this time is the second voltage indication signal, the coarse adjustment module of the inductor and capacitor clock generator sets the lock indication signal LOCK to 1, otherwise, the lock indication signal LOCK is set to 0; The self-detection module starts working when it detects that the coarse adjustment end indication signal CAL_DONE is 1; the self-detection module generates a first shutdown control signal and a second start control signal when it detects that all bits of the control signal are all zero; the self-detection module generates a first start control signal and a second shutdown control signal when it detects that all bits of the control signal are not all zero and the lock indication signal LOCK is 1; the self-detection module generates a first shutdown control signal and a second shutdown control signal when it detects that all bits of the control signal are not all zero and the lock indication signal LOCK is 0; Among them, the inductor and capacitor clock generator is turned off when it receives the first shutdown control signal, and the inductor and capacitor clock generator outputs the clock when it receives the first startup control signal; the resistor and capacitor clock generator is turned off when it receives the second shutdown control signal, and outputs the clock when it receives the second startup control signal.

2. The clock generating device according to claim 1, characterized in that: The first reference voltage and the second reference voltage are generated by an inductor-capacitor clock generator controlling a voltage detection module.

3. The clock generating device according to claim 1, characterized in that: The self-detection module starts to work when detecting that the coarse adjustment end indication signal CAL_DONE is 1.

4. The clock generating device according to claim 1, characterized in that: If the LC clock generator coarse adjustment module uses the successive approximation method to find the upper limit of the control word that locks the LC clock generator, initially, the LC clock generator coarse adjustment module sets the control word to 1000000; wherein 1000000 is the middle value of the control word.

5. The clock generating device according to claim 1, characterized in that: If the LC clock generator coarse adjustment module uses the successive approximation method to find the lower limit of the control word that locks the LC clock generator, initially, the LC clock generator coarse adjustment module sets the control word to 1000000; wherein 1000000 is the middle value of the control word.

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