Frequency domain equalization method based on PD-DD-LMS architecture, medium and equipment

Abstract

The invention discloses a frequency domain equalization method based on a PD-DD-LMS architecture, a medium and equipment, and relates to the field of coherent optical communication system digital signal processing. The frequency domain equalization method based on the PD-DD-LMS architecture mainly comprises the following steps: converting an input sequence into a plurality of data blocks by using an odd-even separation and serial-parallel conversion method, carrying out fast Fourier transform to obtain a plurality of frequency domain input block vectors, obtaining a frequency domain output block vector by using a multi-input multi-output frequency domain equalizer, and carrying out inverse fast Fourier transform to obtain a plurality of frequency domain output block vectors; discarding the previous preset number of elements to obtain a time domain output block vector; and according to the time domain output block vector, updating the tap weight of the filter by using a phase correlation decision oriented least mean square algorithm and a gradient descent algorithm. By implementing the frequency domain equalization method based on the PD-DD-LMS architecture, the medium and the equipment provided by the invention, the calculation complexity can be reduced while the phase noise resistance and the frequency offset resistance are not reduced.

Description

Technical Field

[0001] The present invention relates to the field of digital signal processing in coherent optical communication systems, and more specifically, to a frequency domain equalization method, medium and device based on a PD-DD-LMS architecture. Background Art

[0002] With the rapid development of communication technology, fiber-optic communication systems have become the mainstream transmission method of modern communication networks due to their advantages such as large bandwidth, high transmission rate, and strong anti-interference ability. However, as the scale and transmission rate of fiber-optic communication networks continue to increase, the performance and transmission quality of the system face increasingly complex challenges. In coherent optical communication systems, signals will encounter problems such as dispersion, nonlinear effects, and frequency offset after being transmitted through optical fibers. These problems will cause serious degradation of signal quality, especially in high-speed and large-capacity systems. This effect is particularly obvious.

[0003] In order to overcome the negative effects of various types of impairments in coherent optical transmission systems, adaptive FIR filters play a very important role in coherent optical transmission systems. The tap coefficients of the FIR filter are updated through a tap adaptive algorithm. When the phase noise of the transmitter laser and the local oscillator laser (LO) and the frequency offset between them cause large carrier phase fluctuations during the delay time, the performance of the FIR filter with long delay taps will be severely degraded.

[0004] A new structure of the finite impulse response (FIR) filter of a digital coherent optical receiver based on the phase-dependent decision-directedleast-meansquare (PD-DD-LMS) algorithm removes fast phase fluctuations from the error signal that updates the FIR filter tap coefficients by introducing a two-stage decision-guided carrier phase estimator, thereby achieving stable adaptation of the filter tap coefficients for high-order quadrature amplitude modulation (QAM) signals. It has better resistance to phase noise and frequency offset than the traditional DD-LMS method.

[0005] However, the computational complexity of the FIR filter increases with the number of delay taps, and it is difficult to implement an FIR filter with a large number of delay taps in an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA) due to high power consumption and high gate density. Therefore, a new equalization method that can reduce the computational complexity is needed. Summary of the invention

[0006] The object of the present invention is to provide a frequency domain equalization method, medium and device based on the PD-DD-LMS architecture, which can effectively reduce the computational complexity without reducing the anti-phase noise and anti-frequency offset performance.

[0007] The present invention provides a frequency domain equalization method based on the PD-DD-LMS architecture, comprising the following steps: S1: obtaining a plurality of data blocks according to an input sequence by using a parity separation and a serial-to-parallel conversion method; S2: Based on the multiple data blocks, use fast Fourier transform to obtain multiple frequency domain input block vectors; S3: Based on the multiple frequency domain input block vectors, use a multi-input multi-output frequency domain equalizer to obtain a frequency domain output block vector; S4: Perform inverse fast Fourier transform on the frequency domain output block vector, and discard the first preset number of elements to obtain a time domain output block vector; S5: Based on the time domain output block vector, use a phase-related decision-directed least mean square algorithm and a gradient descent algorithm to update the filter tap weights.

[0008] Further, step S1 specifically includes: S11: performing parity separation on the input sequence to obtain Polarization even sequence, Odd sequence, Polarization even sequence, Polarization odd sequence; the input sequence includes Polarization input sequence and Polarization input sequence; S12: using a serial-to-parallel conversion method, according to a preset number, the Polarization even sequence, the Polarization odd sequence, the Polarization even sequence, the The polarization odd-number sequences are divided into a plurality of data blocks respectively.

[0009] Further, step S2 specifically includes: according to the multiple data blocks, using fast Fourier transform, obtaining multiple frequency domain input block vectors, such as formula: , in, Indicates frequency domain input block vector, represents the fast Fourier transform, ; Indicates transposing the matrix.

[0010] Further, step S3 specifically includes: according to the multiple frequency domain input block vectors, using a multi-input multi-output frequency domain equalizer, obtaining a frequency domain output block vector, such as formula: , , in, for Polarization time domain output block vector, for Polarization time domain output block vector, , , , , , , and Respectively represent the tap coefficients of eight sub-equalizer frequency domain filters in the multiple-input multiple-output frequency domain equalizer; Represents the dot product operation between frequency domain vectors; , , , Represents the even sequence and odd sequence respectively and Polarization frequency domain input block vector.

[0011] Further, step S5 specifically includes: S51: according to the time domain output block vector, using the phase-related decision-oriented least mean square algorithm to obtain an error vector; S52: after filling the error vector with a preset number of 0s, using fast Fourier transform to obtain a frequency domain error vector; S53: according to the frequency domain error vector and the multiple frequency domain input block vectors, obtaining a gradient vector; S54: according to the gradient vector, updating the filter tap weights.

[0012] Further, step S51 specifically includes: according to the time domain output block vector, using the phase-related decision-oriented least mean square algorithm, to obtain an error vector, such as formula: , , , , , in, is the error vector, express polarization( represent and Polarization) desired signal in training mode or decoded signal in tracking mode; express The tap coefficient vector of the polarization first-stage phase estimator, express The tap coefficient vector of the polarization second-stage phase estimator, Indicates the equalizer Output block vector on polarization; is the step size parameter, symbol is to take its conjugate vector, is the tap coefficient vector controlling the first-stage phase estimator The error signal is the step size parameter, is the tap coefficient vector controlling the second-stage phase estimator The error signal.

[0013] Further, step S54 specifically includes: updating the filter tap weights according to the gradient vector, such as formula: , in, is the updated filter tap weight applied to the next data block, is the filter tap weight applied to the current data block before updating, is the step size parameter of stochastic gradient descent, is the gradient vector, Indicates Fill with 0s.

[0014] The present invention also provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the above-mentioned frequency domain equalization method based on the PD-DD-LMS architecture are implemented.

[0015] The present invention also provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above-mentioned frequency domain equalization method based on the PD-DD-LMS architecture when executing the program.

[0016] The present invention also provides a computer program product, including a computer program, which implements the steps of the above-mentioned frequency domain equalization method based on the PD-DD-LMS architecture when executed by a processor.

[0017] The frequency domain equalization method, medium and device based on the PD-DD-LMS architecture provided by the present invention have the following beneficial effects: The present invention uses odd-even separation and serial-to-parallel conversion methods to convert the input sequence into multiple data blocks and perform fast Fourier transform to obtain multiple frequency domain input block vectors, uses a multi-input multi-output frequency domain equalizer to obtain a frequency domain output block vector and performs fast Fourier inverse transform, discards the first preset number of elements to obtain a time domain output block vector; according to the time domain output block vector, the phase-related decision-oriented least mean square algorithm and the gradient descent algorithm are used to update the filter tap weights. The present invention is suitable for polarization multiplexing transmission systems, and while having the same anti-phase noise and anti-frequency offset performance as time domain equalization, it reduces the computational complexity through effective implementation of block-by-block signal processing and discrete Fourier transform (DFT). BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The present invention will be further described below with reference to the accompanying drawings and embodiments, in which: Figure 1 It is a flow chart of a frequency domain equalization method based on the PD-DD-LMS architecture provided by the present invention; Figure 2 It is an overall structural principle diagram of the frequency domain equalization method based on the PD-DD-LMS architecture provided by the present invention; Figure 3 It is a principle diagram of the phase-related decision-making directional least mean square algorithm provided by the present invention; Figure 4 This is a simulation result diagram showing the performance comparison between the present invention and time domain equalization; Figure 5 This is a performance comparison experiment result diagram of the present invention and time domain equalization; Figure 6 It is a comparison chart of the computational complexity of the time domain equalization provided by the present invention; Figure 7 It is a structural block diagram of the computer device provided by the present invention. DETAILED DESCRIPTION

[0019] In order to have a clearer understanding of the technical features, purposes and effects of the present invention, specific embodiments of the present invention are now described in detail with reference to the accompanying drawings.

[0020] Figure 1 A schematic diagram of a frequency domain equalization method based on the PD-DD-LMS architecture of this embodiment is shown. In this embodiment, the frequency domain equalization method based on the PD-DD-LMS architecture includes the following steps: S1: According to the input sequence, multiple data blocks are obtained by using the parity separation and serial-to-parallel conversion method; In an exemplary embodiment, step S1 specifically includes: S11: Separate the input sequence into odd and even parts, and get Polarization even sequence, Odd sequence, Polarization even sequence, Polarization odd sequence; the input sequence includes Polarization input sequence and Polarization input sequence; S12: Using a serial-to-parallel conversion method, according to a preset number, the Polarization even sequence, the Polarization odd sequence, the Polarization even sequence, the The polarization odd-number sequences are respectively divided into a plurality of data blocks; As an exemplary embodiment, in step S1, the input sequence , Each branch is further divided into many Point data block, is equal to the discrete frequency response of the frequency domain equalizer, that is, the preset number is the discrete frequency response of the frequency domain equalizer; Figure 2 The overall structural principle diagram of the frequency domain equalization method based on the PD-DD-LMS architecture of this embodiment is shown. and Polarized input sequence It is divided into odd-numbered sequences and even-numbered sequences. Since frequency domain equalization is processed by blocks, the sequence is further divided into The data block is Indicates The length is The input block vector of S2: according to the multiple data blocks, using fast Fourier transform to obtain multiple frequency domain input block vectors; In an exemplary embodiment, step S2 specifically includes: according to the multiple data blocks, using fast Fourier transform, obtaining multiple frequency domain input block vectors, such as formula: , in, Indicates frequency domain input block vector, represents the fast Fourier transform, ; Indicates transposing the matrix; As an exemplary embodiment, in step S2, a fast Fourier transform (FFT) is performed on the data block according to an overlap-preserving method with 50% overlap, that is, the frequency domain input block vector of the sub-equalizer (including the even sub-equalizer and the odd sub-equalizer) is represented as , by using an overlap factor of 50%, the input sequence includes L samples from the current data block and L samples from the previous data block; S3: Obtain a frequency domain output block vector using a multi-input multi-output frequency domain equalizer according to the multiple frequency domain input block vectors; In an exemplary embodiment, step S3 specifically includes: according to the multiple frequency domain input block vectors, using a multi-input multi-output frequency domain equalizer, obtaining a frequency domain output block vector, such as formula: , , in, for Polarization time domain output block vector, for Polarization time domain output block vector, , , , , , , and Respectively represent the tap coefficients of eight sub-equalizer frequency domain filters in the multiple-input multiple-output frequency domain equalizer; Represents the dot product operation between frequency domain vectors; , , , Represents the even sequence and odd sequence respectively and Polarization frequency domain input block vector; As an exemplary embodiment, in step S3, the data block is sent to a 2 × 2 butterfly structure finite impulse response (FIR) filter to achieve frequency domain adaptive equalization; the eight frequency domain filters are composed of even sub-equalizers and odd sub-equalizers; the four even sub-equalizers are in one 2 × 2 butterfly structure, and the four odd sub-equalizers are in another 2 × 2 butterfly structure; in the frequency domain, the output block vector is: , , It should be noted that, in step S3, the L tap coefficient vectors of the sub-equalizer are Filled with an equal number of 0s and subjected to a 2L-point FFT, the frequency domain tap coefficient vector of the sub-equalizer is represented as ,in , express or polarization, , Represents an even or odd sequence; S4: performing an inverse fast Fourier transform on the frequency domain output block vector and discarding a preset number of front elements to obtain a time domain output block vector; As an exemplary embodiment, in step S4, an inverse FFT (IFFT) is performed and the previous elements to obtain the output block vector in the time domain , , that is, perform an inverse fast Fourier transform (IFFT) on the frequency domain output block vector of the sub-equalizer and discard forward elements to get the output block vector in the time domain ; S5: updating the filter tap weights according to the time domain output block vector using a phase-related decision-oriented least mean square algorithm and a gradient descent algorithm; In an exemplary embodiment, step S5 specifically includes: S51: according to the time domain output block vector, using a phase-related decision-oriented least mean square algorithm to obtain an error vector; In an exemplary embodiment, step S51 specifically includes: according to the time domain output block vector, using the phase-related decision-oriented least mean square algorithm, to obtain an error vector, such as formula: , , , , , in, is the error vector, express polarization( represent and Polarization) desired signal in training mode or decoded signal in tracking mode; express The tap coefficient vector of the polarization first-stage phase estimator, express The tap coefficient vector of the polarization second-stage phase estimator, Indicates the equalizer Output block vector on polarization; is the step size parameter, symbol is to take its conjugate vector, is the tap coefficient vector controlling the first-stage phase estimator The error signal is the step size parameter, is the tap coefficient vector controlling the second-stage phase estimator The error signal S52: After filling the error vector with a preset number of zeros, a frequency domain error vector is obtained by fast Fourier transform; As an exemplary embodiment, in step S52, an equal number of Fill the error vector with zeros and perform Point FFT to get the frequency domain error vector , Indicates 0 padding; S53: Obtaining a gradient vector according to the frequency domain error vector and the multiple frequency domain input block vectors; As an exemplary embodiment, in step S53, according to the frequency domain error vector, the block vector is then input Take the conjugate, and finally Perform an inverse fast Fourier transform and discard After elements to get the gradient vector ; S54: updating the filter tap weights according to the gradient vector; In an exemplary embodiment, step S54 specifically includes: updating the filter tap weights according to the gradient vector, such as formula: , in, is the updated filter tap weight applied to the next data block, is the filter tap weight applied to the current data block before updating, is the step size parameter of stochastic gradient descent, is the gradient vector, Indicates 0 padding; As an exemplary embodiment, in step S5, the PD-DD-LMS algorithm is used to perform error calculation in the time domain, and the obtained error vector is supplemented with L zeros and then converted into a frequency domain vector with a length of 2L. Finally, the filter tap weights are updated in the frequency domain by using the gradient descent algorithm.

[0021] In one embodiment, the frequency domain equalization method based on the PD-DD-LMS architecture includes the following steps: in the digital signal processing part of the signal receiving end, the input sequence , Each of them is subjected to odd-even separation, thereby obtaining four odd / even sequences. Unlike time domain equalization which uses sample-by-sample processing, frequency domain equalization uses block processing. Using a serial-to-parallel (S / P) converter, each branch is further divided into many L-point data blocks, where L is equal to the discrete frequency response of the frequency domain equalizer. The data blocks are subjected to fast Fourier transform (FFT) according to the overlap-preserving method with 50% overlap, and then the data blocks are sent to a 2 × 2 butterfly structure finite impulse response (FIR) filter to achieve frequency domain adaptive equalization. The eight frequency domain filters consist of even sub-equalizers and odd sub-equalizers. The four even sub-equalizers are in a 2 × 2 butterfly structure, and the four odd sub-equalizers are in another 2 × 2 butterfly structure. In the frequency domain, the output block vector is: , , Perform an inverse FFT (IFFT) and discard the first L elements to obtain the output block vector in the time domain , , the PD-DD-LMS algorithm is used to calculate the error in the time domain, and the error vector is supplemented with L zeros to convert it into a frequency domain vector of length 2L. Finally, the filter tap weights are updated in the frequency domain by using the gradient descent algorithm. Figure 4 This is a simulation result diagram showing the performance comparison between the present invention and time domain equalization; Figure 5 This is a performance comparison experiment result diagram of the present invention and time domain equalization; Figure 6 It is a comparison chart of the computational complexity of the time domain equalization provided by the present invention; It can be seen that the technical solution of the present invention can achieve the same effect as time domain equalization after carrier phase estimation, but its calculation complexity is greatly reduced.

[0022] In one embodiment, the frequency domain equalization method based on the PD-DD-LMS architecture may be implemented in the following manner. Figure 2 The overall structural principle diagram of the embodiment of the present invention is as follows: It is divided into odd sequence and even sequence. Since frequency domain equalization is processed by block, the sequence is further divided into data blocks of length L. Represents the k-th input block vector of length L.

[0023] The frequency domain input block vector of the sub-equalizer (including the even sub-equalizer and the odd sub-equalizer) is expressed as: , By using an overlap factor of 50%, the input sequence includes L samples from the current data block and L samples from the previous data block.

[0024] The L tap coefficient vectors of the sub-equalizer Padding with an equal number of 0s and performing a 2L-point FFT, the frequency domain tap coefficient vector of the sub-equalizer is represented as: , Where p and q represent x or y polarization.

[0025] Perform an inverse fast Fourier transform (IFFT) on the frequency domain output block vector of the sub-equalizer and discard The first L elements get the output block vector in the time domain .

[0026] The tap coefficients of the sub-equalizer are updated in the frequency domain using the gradient descent algorithm, and the expression is: , in That is, the gradient vector is calculated as follows: first, the error vector is calculated in the time domain , then fill it with an equal number of L zeros and perform a 2L-point FFT to obtain: , Then enter the block vector Take the conjugate, and finally Perform an inverse fast Fourier transform and discard The last L elements of .

[0027] Error Vector Using the phase-related decision-making directional least mean square algorithm (the algorithm principle is as follows Figure 3 As shown in the figure), it is calculated in the time domain and its expression is: , in Represents the desired signal in p-polarization (p stands for x or y) training mode or the decoded signal in tracking mode. represents the tap coefficient vector of the first-stage phase estimator for p-polarization, represents the tap coefficient vector of the p-polarization second-stage phase estimator, represents the output block vector of the equalizer on the p-polarization.

[0028] The update expression of the tap coefficients of the first-stage phase estimator is: , is the step size parameter, symbol is to take its conjugate vector, is the tap coefficient vector controlling the first-stage phase estimator The error signal is expressed as: ; The update expression of the tap coefficients of the second-stage phase estimator is: , is the step size parameter, symbol is to take its conjugate vector, is the tap coefficient vector controlling the second-stage phase estimator The error signal is expressed as: .

[0029] This embodiment provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the frequency domain equalization method based on the PD-DD-LMS architecture are implemented. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory (Flash Memory), a hard disk (HDD) or a solid-state drive (SSD), etc.; the storage medium may also include a combination of the above-mentioned types of memory.

[0030] This embodiment provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, the steps of the above-mentioned frequency domain equalization method based on the PD-DD-LMS architecture are implemented.

[0031] like Figure 7As shown, the computer device 120 may include: at least one processor 121, such as a central processing unit (CPU), at least one communication interface 123, a memory 124, and at least one communication bus 122. Among them, the communication bus 122 is used to realize the connection and communication between these components. Among them, the communication interface 123 may include a display screen (Display), a keyboard (Keyboard), and the optional communication interface 123 may also include a standard wired interface and a wireless interface. The memory 124 may be a high-speed random access memory (Random Access Memory, RAM), or a non-volatile memory (non-volatile memory), such as at least one disk storage. The memory 124 may also be at least one storage device located away from the aforementioned processor 121. Among them, the memory 124 stores an application program, and the processor 121 calls the program code stored in the memory 124 to perform any of the above method steps. Among them, the communication bus 122 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The communication bus 122 can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 7Only one line is used to represent it, but it does not mean that there is only one bus or one type of bus. Among them, the memory 124 may include a volatile memory (volatile memory), such as a random-access memory (random-access memory, RAM); the memory may also include a non-volatile memory (non-volatile memory), such as a flash memory (flash memory), a hard disk drive (hard disk drive, HDD) or a solid-state drive (solid-state drive, SSD); the memory 124 may also include a combination of the above-mentioned types of memory. Among them, the processor 121 may be a central processing unit (central processing unit, CPU), a network processor (network processor, NP) or a combination of CPU and NP. Among them, the processor 121 may further include a hardware chip. The above-mentioned hardware chip may be an application-specific integrated circuit (application-specific integrated circuit, ASIC), a programmable logic device (programmable logic device, PLD) or a combination thereof. The above-mentioned PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (field-programmable gate array, FPGA), a generic array logic (generic array logic, GAL) or any combination thereof. Optionally, the memory 124 is also used to store program instructions. The processor 121 can call the program instructions to implement the frequency domain equalization method based on the PD-DD-LMS architecture as in this embodiment.

[0032] This embodiment provides a computer program product, including a computer program. When the computer program is executed by a processor, the steps of the above-mentioned frequency domain equalization method based on the PD-DD-LMS architecture are implemented.

[0033] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A frequency domain equalization method based on PD-DD-LMS architecture, characterized in that: The following steps are involved: S1: According to the input sequence, multiple data blocks are obtained by using parity separation and serial-to-parallel conversion methods; S2: according to the multiple data blocks, using fast Fourier transform to obtain multiple frequency domain input block vectors; S3: Obtain a frequency domain output block vector using a multi-input multi-output frequency domain equalizer according to the multiple frequency domain input block vectors; S4: performing an inverse fast Fourier transform on the frequency domain output block vector and discarding a preset number of front elements to obtain a time domain output block vector; S5: According to the time domain output block vector, the filter tap weights are updated using a phase-related decision-directed least mean square algorithm and a gradient descent algorithm.

2. The frequency domain equalization method based on the PD-DD-LMS architecture according to claim 1, characterized in that: Step S1 specifically includes: S11: Separate the input sequence into odd and even parts, and get Polarization even sequence, Odd sequence, Polarization even sequence, Polarization odd sequence; the input sequence includes Polarization input sequence and Polarization input sequence; S12: Using a serial-to-parallel conversion method, according to a preset number, the Polarization even sequence, the Polarization odd sequence, the Polarization even sequence, the The polarization odd-number sequences are divided into a plurality of data blocks respectively.

3. The frequency domain equalization method based on the PD-DD-LMS architecture according to claim 1, characterized in that: Step S2 specifically includes: according to the multiple data blocks, using fast Fourier transform, obtaining multiple frequency domain input block vectors, such as formula: ， in, Indicates frequency domain input block vector, represents the fast Fourier transform, Indicates In the data block samples; Indicates transposing the matrix.

4. The frequency domain equalization method based on the PD-DD-LMS architecture according to claim 1, characterized in that: Step S3 specifically includes: according to the multiple frequency domain input block vectors, using a multi-input multi-output frequency domain equalizer, obtaining a frequency domain output block vector, such as formula: ， ， in, for Polarization time domain output block vector, for Polarization time domain output block vector, , , , , , , and Respectively represent the tap coefficients of eight sub-equalizer frequency domain filters in the multiple-input multiple-output frequency domain equalizer; Represents the dot product operation between frequency domain vectors; , , , Represents the even sequence and odd sequence respectively and Polarization frequency domain input block vector.

5. The frequency domain equalization method based on the PD-DD-LMS architecture according to claim 1, characterized in that: Step S5 specifically includes: S51: according to the time domain output block vector, using a phase-related decision-oriented least mean square algorithm to obtain an error vector; S52: After filling the error vector with a preset number of zeros, a frequency domain error vector is obtained by fast Fourier transform; S53: Obtaining a gradient vector according to the frequency domain error vector and the multiple frequency domain input block vectors; S54: Update the filter tap weights according to the gradient vector.

6. The frequency domain equalization method based on the PD-DD-LMS architecture according to claim 5, characterized in that: Step S51 specifically includes: according to the time domain output block vector, using the phase-related decision-oriented least mean square algorithm, to obtain an error vector, such as the formula: ， ， ， ， ， in, is the error vector, express polarization( represent and Polarization) desired signal in training mode or decoded signal in tracking mode; express The tap coefficient vector of the polarization first-stage phase estimator, express The tap coefficient vector of the polarization second-stage phase estimator, Indicates the equalizer Output block vector on polarization; is the step size parameter, symbol is to take its conjugate vector, is the tap coefficient vector controlling the first-stage phase estimator The error signal is the step size parameter, is the tap coefficient vector controlling the second-stage phase estimator The error signal.

7. The frequency domain equalization method based on PD-DD-LMS architecture according to claim 5, characterized in that: Step S54 specifically includes: updating the filter tap weights according to the gradient vector, such as the formula: ， in, is the updated filter tap weight applied to the next data block, is the filter tap weight applied to the current data block before updating, is the step size parameter of stochastic gradient descent, is the gradient vector, Indicates Fill with 0s.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the frequency domain equalization method based on the PD-DD-LMS architecture as described in any one of claims 1 to 7 are implemented.

9. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the frequency domain equalization method based on the PD-DD-LMS architecture as described in any one of claims 1-7 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the frequency domain equalization method based on the PD-DD-LMS architecture described in any one of claims 1 to 7 are implemented.

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