System-level verification convergence system, method and product

Abstract

The invention provides a system-level verification convergence system, method and product, and belongs to the technical field of chip verification. The system is a cocotb system verification platform based on a Python language, and the system comprises an application component app agent which is used for calling an application program based on a Python library to carry out network message testing on a DUT; the cocotblet-pcie TLP transmission layer adapter is used for receiving and transmitting a PCIe (Peripheral Component Interconnect Express) message at a TLP transmission layer interface; the network message transmitting and receiving component pktgen scapy agent is used for executing the processes of transmitting, receiving, analyzing and automatically responding different types of network messages based on the scapy application program of the Python library; the cocotbleth-th TLP transmission layer adapter is used for receiving and transmitting a network message at a TLP transmission layer interface; and the checker agent is used for generating a comparison result of the test expected result and an actual output result of the DUT. The invention aims to improve the convergence speed of intelligent network card chip system-level verification.

Description

Technical Field

[0001] Embodiments of the present application relate to the technical field of chip verification, and in particular, to a system-level verification convergence system, method, and product. Background Art

[0002] The Smart NIC chip integrates an Ethernet controller and interface, a PCIe controller and bus interface, a multi-core processor (CPU), and an optional field programmable gate array (FPGA). It is mainly used to assist the host server to achieve functions such as virtual switching acceleration, network offload acceleration, storage acceleration, and security acceleration, and is used in cloud computing network virtualization solutions.

[0003] In the EDA (Electronics Design Automation) functional simulation verification of the chip development cycle, including system-level verification, for the system-level verification of smart NIC chips, the verification IP (Verification Intellectual Property, VIP) used by PCIe and Ethernet simulation models mostly provides Serdes and PIPE interface modeling and simulation. Serdes is serial port modeling, and PIPE is parallel port modeling. Compared with Serdes interface, although the simulation speed of PIPE interface has been greatly improved, the overall simulation speed of system-level verification is still very slow. The more VIPs are integrated, the slower the simulation speed. Smart NIC chips generally integrate 2 PCIe controllers and at least 4 Ethernet controllers. Even if the verification VIPs are all modeled using the PIPE interface, the speed is still very slow in system-level simulation, which means that the verification convergence of the chip is affected.

[0004] Secondly, for the business testing and driver simulation of the system-level verification of the smart network card chip, which involves business functions and driver simulation such as network acceleration, storage acceleration and security acceleration, the traditional UVM verification platform architecture based on the SystemVerilog language cannot integrate application libraries and software drivers developed based on the Python language. Therefore, all application testing and driver simulation are developed from scratch. Developers need to invest a lot of time in the three processes of familiarizing themselves with the business, driver development and debugging. In addition, the processes of verification platform construction, integrated debugging, verification case development, verification implementation, problem location and solution, and regression convergence require more manpower and take longer project time, which greatly affects the verification convergence of the chip. Summary of the invention

[0005] The embodiments of the present application provide a system-level verification convergence system, method and product, which are intended to increase the speed of system-level verification convergence of smart network card chips.

[0006] In a first aspect, an embodiment of the present application provides a system-level verification convergence system, the system is a cocotb system verification platform based on Python language, and the system includes: The application component app agent is used to call the application based on the Python library to perform network message testing on the DUT; cocotbext-pcie TLP transport layer adapter, used to send and receive PCIe messages on the TLP transport layer interface; The network message sending and receiving component pkt_gen scapy agent is used for the scapy application based on the Python library to perform different types of network message sending, receiving, parsing and automatic response processes; cocotbext-eth TLP transport layer adapter, used to send and receive network messages on the TLP transport layer interface; The checker agent is used to generate comparison results between the expected test results and the actual output results of the DUT.

[0007] Optionally, the system further comprises: The configuration component config agent is used to perform tasks including BAR address space allocation, definition and allocation of address space for each business module, PCIe enumeration process, common task and function maintenance, system storage space allocation and recycling, queue allocation, and interrupt allocation.

[0008] Optionally, when verifying any DUT, after the simulator compiles the verification environment code of the DUT and the system, the application component app agent is used to call the configuration component config agent to initialize the configuration of the host system and the DUT; The initialization configuration includes allocating PCIe BAR address space, creating TX / RX queue, CQ queue, initializing descriptors and PCIe interrupts, and initializing the DUT through the cocotbext-pcie TLP transport layer adapter by calling any smart network card driver, wherein the smart network card driver includes VirtIO driver, OVS driver and RDMA driver.

[0009] Optionally, after initialization configuration, the application component app agent is used to call an iperf application based on a Python library to enable the DUT, and the iperf application sends the network message to be sent to the PCIe tlp interface of the DUT through the cocotbext-pcie TLP transport layer adapter; The network message transceiver component pkt_gen scapy agent is used to receive the network message sent by the DUT through the cocotbext-eth TLP transport layer adapter; The checking component checker agent is used to obtain the network message to be sent and the network message currently received by the network message sending and receiving component pkt_gen scapy agent, then compare them and output the comparison result.

[0010] Optionally, after the initialization configuration, the network message transceiver component pkt_gen scapy agent is used to call a scapy application based on a Python library, and send the network message to be received to the ETH tlp interface of the DUT through the cocotbext-eth TLP transport layer adapter; The application component app agent is used to obtain network messages in response to the interrupt processing program; The checker agent component is used to obtain the network message to be received and compare it with the network message currently received by the application component appagent, and output the comparison result.

[0011] Optionally, the DUT used for verification by the system includes a smart network card chip, a GPU and a smart AI chip.

[0012] In a second aspect, an embodiment of the present application provides a system-level verification convergence method, which is applied to the system-level verification convergence system described in the first aspect of the embodiment, and the method includes: After the initial configuration, the network message sending test process and the network message receiving test process are performed on the DUT; The network message sending test process includes: the application component app agent calls the iperf application based on the Python library to enable the DUT, and the iperf application sends the network message to be sent to the PCIe tlp interface of the DUT through the cocotbext-pcieTLP transport layer adapter; the network message transceiver component pkt_gen scapy agent receives the network message sent by the DUT through the cocotbext-eth TLP transport layer adapter; the checker agent component obtains the network message to be sent and the network message currently received by the network message transceiver component pkt_gen scapy agent, and then compares them and outputs the comparison result; The network message receiving test process includes: the network message sending and receiving component pkt_gen scapy agent calls the scapy application based on the Python library, and sends the network message to be received to the ETH tlp interface of the DUT through the cocotbext-eth TLP transport layer adapter; the application component app agent obtains the network message in response to the interrupt handler; the check component checker agent obtains the network message to be received and compares it with the network message currently received by the application component app agent, and outputs the comparison result.

[0013] In a third aspect, an embodiment of the present application provides a computer device, comprising: at least one processor, and a memory, wherein the memory stores a computer program that can be run on the processor, wherein when the processor executes the computer program, the system-level verification convergence method described in the second aspect of the embodiment is executed.

[0014] In a fourth aspect, an embodiment of the present application provides a non-volatile readable storage medium, wherein the non-volatile readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the system-level verification convergence method described in the second aspect of the embodiment is executed.

[0015] In a fifth aspect, an embodiment of the present application provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the system-level verification convergence method described in the second aspect of the embodiment.

[0016] Beneficial effects: The system-level verification convergence system of this embodiment is a cocotb system verification platform based on Python language, and the system includes: an application component app agent, which is used to call an application based on the Python library to perform network message testing on the DUT; a cocotbext-pcie TLP transport layer adapter, which is used to send and receive PCIe messages at the TLP transport layer interface; a network message sending and receiving component pkt_gen scapy agent, which is used for the scapy application based on the Python library to execute different types of network message sending, receiving, parsing and automatic response processes; a cocotbext-eth TLP transport layer adapter, which is used to send and receive network messages at the TLP transport layer interface; a checking component checker agent, which is used to generate a comparison result between the expected test result and the actual output result of the DUT.

[0017] This system models the PCIe and Ethernet TLP transport layer interface, which can significantly improve the system simulation verification speed compared to traditional Serdes, PIPE or MAC layer interface modeling; and the cocotb system verification platform based on Python language can reuse the iperf application, fio application and scapy application in the Python library to perform DUT simulation verification, reducing a lot of repeated development and debugging work, accelerating the verification progress and shortening the verification convergence time. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0019] Figure 1 It is a functional module diagram of a system-level verification convergence system proposed in an embodiment of the present application; Figure 2 It is a functional module diagram of a system-level verification convergence system proposed in an embodiment of the present application; Figure 3 It is a schematic diagram of a verification network message sending scenario provided by an embodiment of the present application; Figure 4 It is a schematic diagram of a verification network message reception scenario proposed in an embodiment of the present application; Figure 5 is a schematic diagram of a computer device proposed in one embodiment of the present application; Figure 6 is a schematic diagram of a non-volatile readable storage medium provided in an embodiment of the present application; Figure 7 It is a schematic diagram of a computer program product proposed in one embodiment of the present application. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0021] COCOTB: COroutine based COsimulation TestBench, a verification platform development framework based on Python class library, which can use Python to write VHDL / Verilog functional verification environment; UVM: Universal Verification Methodology, a verification platform development framework based on the SystemVerilog class library, which can use its reusable components to build a functional verification environment with standardized hierarchical structures and interfaces; PCIe: Peripheral Component Interconnect express, a high-speed serial computer expansion bus standard, belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission. The connected devices are allocated exclusive channel bandwidth and do not share bus bandwidth. It mainly supports active power management, error reporting, end-to-end reliable transmission, hot plugging and quality of service (QOS) and other functions; MAC: Media Access Control, media access control layer, defines how data frames are transmitted on the medium; in links sharing the same bandwidth, access to the connection medium is "first come, first served"; physical addressing is defined here, and the logical topology (the path that the signal takes through the physical topology) is also defined here; line control, error notification (uncorrected), frame delivery order, and optional flow control are also implemented in this sublayer; CPU: Central Processing Unit, central processing unit; GPU: Graphics Processing Unit, graphics processor; FPGA: Field Programmable Gate Array, thread programmable gate array; EDA: Electronics Design Automation, functional simulation verification; SoC: System on Chip, system-level chip; PIPE: Physical Interface for PCI Express, PCIe physical layer interface; DUT: Device Under Test, device under test; AI: Artificial Intelligence; TX / RX queue: send / receive queue; CQ Queue: Response Queue TCP: Transmission Control Protocol, transmission control protocol; UDP: User Datagram Protocol.

[0022] The Smart NIC chip integrates an Ethernet controller and interface, a PCIe controller and bus interface, a multi-core processor (CPU), and an optional field programmable gate array (FPGA). It is mainly used to assist the host server to achieve functions such as virtual switching acceleration, network offload acceleration, storage acceleration, and security acceleration. It is used in cloud computing network virtualization solutions. The chip development cycle includes multiple stages such as functional requirement specification formulation, architecture design, code design, EDA functional simulation verification, FPGA prototype verification, software development and testing, and chip post-silicon product application testing.

[0023] Among them, EDA functional simulation verification takes up most of the chip development cycle, so accelerating the convergence of chip EDA functional verification means shortening the chip development cycle and improving chip product quality.

[0024] Chip EDA functional verification is divided according to the verification level, generally into module level (module level / unit level), sub-system level (sub-system level) and system level (chip level / system level); among them, system-level verification simulates software transaction behavior, focusing on the interaction between subsystems, and has the characteristics of slow simulation speed, high positioning difficulty and long convergence time.

[0025] Specifically, the system-level verification of smart network card chips faces two challenges: (1) The simulation speed is slow. The smart NIC chip integrates at least 2 PCIe controllers (including 1 PCIe controller on the host side and 1 on the SoC side), at least 2 Ethernet controllers, and usually 4 or more Ethernet controllers. These IPs are simulated and modeled using the Serdes interface or the PIPE interface. Compared with the Serdes interface, the simulation speed of PIPE has been greatly improved. However, in system-level simulation, when multiple PCIe and Ethernet controllers are integrated, the simulation speed is also extremely slow, which greatly affects the system simulation convergence speed.

[0026] (2) Business testing and driver simulation are difficult. Smart NICs involve business functions such as network acceleration, storage acceleration, and security acceleration. Network acceleration mainly includes VirtIO acceleration, OVS (Open vSwitch) acceleration, TCP offload, Vxlan / GRE tunnel message offload, reliable UDP, NAT / PAT, and RDMA; storage acceleration includes NVMe-OF, support for local PCIe SSD disks, and support for remote NVMe arrays; security acceleration includes IPSec encryption and decryption offload, message filtering, firewalls, DPI, and DDoS; and the software drivers used by these services include OVS virtual switching, SDN / NFV virtualization standard software, TCP / UDP offload, SR-IOV (Single Root I / O Virtualzation), LinuxNet / DPDK (IntelData Plane Development Kit), Express Virtio (XVIO), and vPDA. Testing and simulating such complex functional services and software drivers requires a lot of manpower and time.

[0027] Therefore, how to construct PCIe and Ethernet simulation models to improve the simulation speed of system verification; how to build a system simulation platform to reuse various application libraries and software drivers as much as possible, simulate real business tests and software driver behaviors, and accelerate the convergence of smart network card chip system-level verification are the pain points that need to be solved in verifying the smart network card chip system.

[0028] Therefore, an embodiment of the present application provides a system-level verification convergence system, which can accelerate the speed of system-level verification convergence.

[0029] Reference Figure 1 , showing a functional module diagram of a system-level verification convergence system provided in an embodiment of the present application, wherein the system is a cocotb system verification platform based on the Python language. Cocotb is a verification platform development framework based on the Python class library, and the Python language can be used to write a VHDL / Verilog functional verification environment.

[0030] The system comprises an application component app agent, a cocotbext-pcie TLP transport layer adapter, a network message transceiver component pkt_gen scapy agent, a cocotbext-eth TLP transport layer adapter and a check component checkeragent.

[0031] The application component app agent is used to call an application based on a Python library to perform a network message test on the DUT.

[0032] The cocotbext-pcie TLP transport layer adapter is used to send and receive PCIe messages at the TLP transport layer interface.

[0033] The network message transceiver component pkt_gen scapy agent is used for the scapy application based on the Python library to execute different types of network message sending, receiving, parsing and automatic response processes.

[0034] The cocotbext-eth TLP transport layer adapter is used to send and receive network messages at the TLP transport layer interface.

[0035] The checker agent is used to generate a comparison result between the expected test result and the actual output result of the DUT.

[0036] This system models the PCIe and Ethernet slave TLP transport layer interface, which can significantly improve the system simulation verification speed compared with the traditional Serdes, PIPE or MAC layer interface modeling.

[0037] Moreover, the cocotb system verification platform based on Python language can reuse the iperf application, fio application, and scapy application in the Python library to perform simulation verification of the DUT, reducing a large amount of repetitive development and debugging work, accelerating the verification progress, and shortening the verification convergence time.

[0038] Reference Figure 2 , showing a functional module diagram of a system-level verification convergence system provided in an embodiment of the present application, the system is a cocotb system verification platform based on Python language, and the system includes an application component app agent, a cocotbext-pcie TLP transport layer adapter, a network message sending and receiving component pkt_gen scapy agent, a cocotbext-eth TLP transport layer adapter, a check component checker agent and a configuration component config agent.

[0039] Among them, the application component app agent can call the application based on the Python library to perform network message testing on the DUT, and can also perform host and soc application testing and host and soc driver simulation.

[0040] For example, in the host and soc application test, the application component app agent performs flow testing of network and storage services based on the iperf application and the fio application of the Python library.

[0041] The host and soc driver simulation includes Virtio-network, Virtio-block, OVS and RDMA service driver simulation, so as to realize the simulation of IO generation process on the host side and the simulation of Virtio driver, including various behaviors on the host side, the generation and issuance of various IO requests, the structure maintenance of queues under various devices, tx queue, rxqueue, control queue maintenance, avail ring, used ring maintenance and multi-function multi-queue maintenance.

[0042] The cocotbext-pcie TLP transport layer adapter mainly provides PCIe protocol support and interface driver adaptation, and is used to send and receive PCIe messages at the TLP transport layer interface.

[0043] The network message transceiver component pkt_gen scapy agent can execute different types of network message sending, receiving, parsing and automatic response processes based on the scapy application of the Python library.

[0044] The cocotbext-eth TLP transport layer adapter mainly provides network message protocol support and interface driver adaptation, and is used to send and receive network messages at the TLP transport layer interface.

[0045] The checking component checker agent is used to generate a comparison result between the expected test result and the actual output result of the DUT. Specifically, the checking component checker agent can automatically compare whether the test stimulus input is consistent with the DUT output by adopting a random comparison method, and give a comparison result.

[0046] The configuration component config agent is used to perform tasks including BAR address space allocation, definition and allocation of address spaces for each business module, PCIe enumeration process, public task and function maintenance, system storage space allocation and recycling, queue allocation, and interrupt allocation.

[0047] The system-level verification convergence system provided in this embodiment can model the interface between PCIe and Ethernet simulation models from the TLP transport layer by introducing application components app agent, cocotbext-pcie TLP transport layer adapter, network message sending and receiving components pkt_gen scapy agent, cocotbext-eth TLP transport layer adapter, configuration component config agent and checking component checker agent, thereby simulating the verification speed.

[0048] The system's cocotb system verification platform based on Python language can reuse Python class libraries to build test applications and software drivers, and then run them directly on the verification platform of this system, so as to quickly realize the application simulation of any simulated and verified smart network card network and storage services; the driver simulation of various smart network card services, including VirtIO / OVS / RDMA driver simulation, can also be reused after partial driver adaptation and modification, which will greatly reduce the workload of system verification application testing and driver simulation development, further accelerate system verification convergence, improve chip system verification efficiency, and shorten the verification cycle.

[0049] The DUTs for which this system can perform system-level verification convergence include smart network card chips, GPUs, and smart AI chips. In other words, in addition to being directly applied to the verification projects of smart network card chips, it can also be used in different chip verification projects, including the verification of GPUs and smart AI chips, etc., and has a wide range of applications.

[0050] In the actual implementation process, when verifying and converging based on this system, the testing principle can be simple first and then complex. For example, smoke testing of simple services can be performed first, such as enumeration, register reading and writing, single pf and single queue TX / RX service testing, etc., and then multi-pf, multi-queue TX / RX services, virtualized vf services, hot-swap services and reset services. Finally, performance services are tested, such as various flow stress tests and exception handling tests. System problem location also goes from simple to complex, improving verification efficiency, thereby achieving rapid convergence of system-level verification.

[0051] When verifying any DUT, obtain the system-level simulation mode from the command line or test script, including the number of MACs used, TX / RX / CQ queue depth, number of pf / vfs, and number of segs, etc., and then start the simulation test after compiling the DUT code and verification environment code.

[0052] In the actual application process, the verification platform first allocates system memory space, including PCIe BAR address space, TX / RX queue, CQ, and initialization interrupts and descriptors; then starts system enumeration and initialization configuration; after the configuration is completed, the network message sending and receiving test is started, and finally the sent and received network messages are compared to see if they are correct, and the simulation test ends.

[0053] In a feasible implementation, when verifying the reception and transmission of network messages of the DUT based on this system, after the simulator compiles the verification environment code of the DUT and the system, the application component app agent is used to call the configuration component config agent to initialize the configuration of the host system and the DUT.

[0054] The initialization configuration includes allocating PCIe BAR address space, creating TX / RX queue, CQ queue, initializing descriptors and PCIe interrupts, and initializing the DUT through the cocotbext-pcie TLP transport layer adapter by calling any smart network card driver, wherein the smart network card driver includes VirtIO driver, OVS driver and RDMA driver.

[0055] After the initial configuration, perform a network message sending test process to verify the network message sending scenario.

[0056] Specifically, the application component app agent is used to call the iperf application based on the Python library to enable the DUT to send the network message to be sent, and the network message to be sent includes a network TCP message or a UDP network message.

[0057] The iperf application sends the network message to be sent to the PCIe tlp interface of the DUT through the cocotbext-pcie TLP transport layer adapter.

[0058] The DUT performs corresponding operations according to the driver configuration and application issued by the iperf application, including: reading various initialized descriptors in the host side memory through the PCIe tlp interface, reading the network message to be sent according to the descriptor, updating the descriptor, writing back the relevant status to the host side, and reporting the interrupt, etc. Finally, the network message to be sent is sent to the network message sending and receiving component pkt_gen scapy agent through the ETH tlp interface.

[0059] The network message transceiver component pkt_gen scapy agent is used to receive the network message sent by the DUT through the cocotbext-eth TLP transport layer adapter, and perform a legitimacy check on the received network message, and perform corresponding processing, including message reception, discarding and replying.

[0060] The checking component checker agent is used to obtain the network message to be sent and the network message currently received by the network message sending and receiving component pkt_gen scapy agent, and then compare them, output the comparison result, and finally end the simulation process.

[0061] After the initial configuration, you can also perform a network message reception test process to verify the network message reception scenario.

[0062] Specifically, the network message transceiver component pkt_gen scapy agent is used to call the scapy application based on the Python library, and send the network message to be received to the ETH tlp interface of the DUT through the cocotbext-eth TLP transport layer adapter, where the network message to be received includes a network TCP message or a UDP network message.

[0063] The DUT writes the received network message to be received into the host side memory through its own PCIe tlp interface, updates the descriptor and reports an interrupt to notify the host to process the received message.

[0064] The application component app agent is used to respond to the interrupt handler, read the received network message from the host memory, and update the RX queue and CQ queue.

[0065] The checker agent component is used to obtain the network message to be received and the network message currently received by the application component appagent for comparison, and output the comparison result, and finally end the simulation process.

[0066] In the verification network message sending scenario and verification network message receiving scenario of any DUT, this system can realize the driver simulation of sending and receiving PCIe messages directly on the TLP transport layer interface through the system's cocotbext-pcie TLP adapter, and realize the driver simulation of sending and receiving network messages directly on the TLP transport layer interface through the system's cocotbext-eth TLP adapter, thereby significantly improving the system simulation speed.

[0067] The embodiment of the present application further provides a system-level verification convergence method, which is applied to the system-level verification convergence system described in the embodiment, and the method includes: After the initialization configuration, the network message sending test process and the network message receiving test process are executed on the DUT.

[0068] Among them, the network message sending test process includes: the application component app agent calls the iperf application based on the Python library to enable the DUT, and the iperf application sends the network message to be sent to the PCIe tlp interface of the DUT through the cocotbext-pcieTLP transport layer adapter; the network message transceiver component pkt_gen scapy agent receives the network message sent by the DUT through the cocotbext-eth TLP transport layer adapter; the checking component checker agent obtains the network message to be sent and the network message currently received by the network message transceiver component pkt_gen scapy agent, compares them, and outputs the comparison result.

[0069] The network message receiving test process includes: the network message sending and receiving component pkt_gen scapy agent calls the scapy application based on the Python library, and sends the network message to be received to the ETH tlp interface of the DUT through the cocotbext-eth TLP transport layer adapter; the application component app agent obtains the network message in response to the interrupt handler; the check component checker agent obtains the network message to be received and compares it with the network message currently received by the application component app agent, and outputs the comparison result.

[0070] Reference Figure 3 , which shows a schematic diagram of a verification network message sending scenario provided in an embodiment of the present application, Figure 3 The arrow in the middle represents the data flow of the network message sending process. In a feasible implementation manner, based on the system-level verification convergence system described in this embodiment, when performing network message sending verification for any DUT, the following process is included: A1: Get the simulation mode settings from the command line or test script.

[0071] Specifically, the system-level simulation mode is determined, including the number of MACs used, TX / RX / CQ queue depth, number of pf / vfs, and number of segs.

[0072] A2: The Makefile script starts the emulator according to the simulation mode settings.

[0073] In this implementation, the VCS simulator is taken as an example. The VCS simulator compiles the design code of the DUT and the cocotb verification environment code, and starts running the simulation after the compilation.

[0074] A3: The application component app agent calls the configuration component config agent to initialize the configuration of the host system and DUT.

[0075] app_agent calls the config_agent component to initialize the host system and DUT, including allocating PCIeBAR address space, creating TX / RX queues, CQ queues, initializing descriptors and PCIe interrupts, etc.; then it starts system enumeration and initialization configuration, and initializes the DUT through the cocotbext-pcie tlp adapter by calling any smart NIC driver, such as the VirtIO driver, OVS driver, and RDMA driver.

[0076] After the initial configuration, you can perform a network message sending test process.

[0077] A4: The application component app agent calls the iperf application based on the Python library to enable the DUT to send the network packets to be sent.

[0078] The iperf application sends the network message to be sent to the PCIe tlp interface of the DUT through the cocotbext-pcie TLP transport layer adapter, and the network message to be sent includes a network TCP message or a UDP network message.

[0079] A5: The DUT performs corresponding operations according to the driver configuration and application program sent by the iperf application program.

[0080] For example, the DUT performs corresponding operations according to the driver configuration and application sent by the iperf application, including reading various initialized descriptors in the host side memory through the PCIe tlp interface, reading the network message to be sent according to the descriptor, updating the descriptor, writing back the relevant status to the host side, and reporting the interrupt, etc. Finally, the network message to be sent is sent to the network message sending and receiving component pkt_gen scapy agent through the ETH tlp interface.

[0081] A6: The network message transceiver component pkt_gen scapy agent receives and processes the network message sent by the DUT through the cocotbext-ethTLP transport layer adapter.

[0082] For example, the network message receiving and sending component pkt_gen scapy agent performs a validity check on the received network message and performs corresponding processing including message receiving, discarding and replying.

[0083] A7: The checker agent obtains the network message to be sent and the network message currently received by the pkt_genscapy agent, and then compares them, outputs the comparison result, and finally ends the simulation process.

[0084] Reference Figure 4 , which shows a schematic diagram of a verification network message reception scenario provided in an embodiment of the present application, Figure 4 The dashed arrow in the middle represents the data flow of the network message receiving process. In a feasible implementation manner, based on the system-level verification convergence system described in this embodiment, when performing network message reception verification for any DUT, the following process is included: B1: Get simulation mode settings from the command line or test script.

[0085] If the system-level simulation mode is selected, the configuration includes the number of MACs used, TX / RX / CQ queue depth, number of pf / vfs, and number of segs.

[0086] B2: The Makefile script starts the simulator according to the simulation mode settings.

[0087] Taking the VCS simulator as an example, the VCS simulator compiles the design code of the DUT and the cocotb verification environment code, and starts running the simulation after compilation.

[0088] B3: The application component app agent calls the configuration component config agent to initialize the configuration of the host system and DUT.

[0089] app_agent calls the config_agent component to initialize the host system and DUT, which may include: allocating PCIe BAR address space, creating TX / RX queues, CQ queues, initializing descriptors and PCIe interrupts, etc.; then starts system enumeration and initialization configuration, and initializes the DUT through the cocotbext-pcie tlp adapter by calling any smart NIC driver, such as VirtIO driver, OVS driver and RDMA driver.

[0090] After the initial configuration, the network message reception test process can be performed.

[0091] B4: The network message transceiver component pkt_gen scapy agent calls the scapy application based on the Python library, and sends the network message to be received to the ETH tlp interface of the DUT through the cocotbext-eth TLP transport layer adapter.

[0092] The network message to be received includes a network TCP message or a network UDP message.

[0093] B5: The DUT writes the received network message to the host side memory through its own PCIe tlp interface, updates the descriptor and reports an interrupt to notify the host to process the received message.

[0094] B6: The application component app agent responds to the interrupt handler, reads the received network message from the host memory, and updates the RX queue and CQ queue.

[0095] B7: The checker agent component is used to obtain the network message to be received and the network message currently received by the application component appagent for comparison, and output the comparison result, and finally end the simulation process.

[0096] The system-level verification convergence system and system-level verification convergence method provided in this embodiment have at least the following beneficial effects: 1. The system-level verification convergence system is based on the cocotb verification platform architecture of the Python language. It can reuse Python application libraries such as the iperf application, fio application, and scapy application to quickly implement application simulation of the network and storage services of the smart network card; the simulation of each service driver of the smart network card, including the VirtIO / OVS / RDMA driver simulation, can also be reused after partial adaptation and transformation, reducing a large amount of repeated development and debugging work, accelerating the verification progress, shortening the verification convergence time, and thus accelerating the verification convergence of the chip; 2. By introducing the cocotbext-pcie TLP adapter, the driver simulation of sending and receiving PCIe messages directly on the TLP transport layer interface is realized, which significantly improves the system simulation speed.

[0097] 3. By introducing the cocotbext-eth TLP adapter, the driver simulation of sending and receiving network messages directly on the TLP transport layer interface is realized, which significantly improves the system simulation speed.

[0098] 4. The system-level verification convergence system and system-level verification convergence method provided in this embodiment can not only be directly applied to the smart network card chip verification project, but also can be used in different chip verification projects, including the verification of GPU and smart AI chip projects, which can significantly accelerate the convergence of chip system verification.

[0099] Reference Figure 5 , shows a schematic diagram of a computer device provided in an embodiment of the present application, comprising: at least one processor 501, and a memory 502, wherein the memory 502 stores a computer program that can be executed on the processor 501, wherein the processor 501 executes the system-level verification convergence method described in the embodiment when executing the computer program.

[0100] Specifically, when the processor 501 executes the computer program, the system-level verification convergence method described in the embodiment is executed, including: after the initialization configuration, performing a network message sending test process and a network message receiving test process on the DUT.

[0101] The network message sending test process includes: the application component app agent calls the iperf application based on the Python library to enable the DUT, and the iperf application sends the network message to be sent to the PCIe tlp interface of the DUT through the cocotbext-pcie TLP transport layer adapter; the network message transceiver component pkt_gen scapy agent receives the network message sent by the DUT through the cocotbext-eth TLP transport layer adapter; the checker agent obtains the network message to be sent and the network message currently received by the network message transceiver component pkt_gen scapy agent, and then compares them and outputs the comparison result; the network message receiving test process includes the network message transceiver component pkt_genscapy agent calling the scapy application based on the Python library, and sending the network message to be received to the ETH tlp interface of the DUT through the cocotbext-eth TLP transport layer adapter; the application component app agent obtains the network message in response to the interrupt handler; the checker agent The agent obtains the network message to be received and compares it with the network message currently received by the application component appagent, and outputs the comparison result.

[0102] Reference Figure 6, shows a schematic diagram of a non-volatile readable storage medium provided in an embodiment of the present application, wherein the non-volatile readable storage medium 600 stores a computer program 601, wherein the computer program 601, when executed by a processor, performs the system-level verification convergence method described in the embodiment.

[0103] Specifically, when the computer program 601 is executed by the processor, the system-level verification convergence method described in the embodiment is executed, including: after the initialization configuration, performing a network message sending test process and a network message receiving test process on the DUT.

[0104] The network message sending test process includes: the application component app agent calls the iperf application based on the Python library to enable the DUT, and the iperf application sends the network message to be sent to the PCIe tlp interface of the DUT through the cocotbext-pcie TLP transport layer adapter; the network message transceiver component pkt_gen scapy agent receives the network message sent by the DUT through the cocotbext-eth TLP transport layer adapter; the checker agent obtains the network message to be sent and the network message currently received by the network message transceiver component pkt_gen scapy agent, and then compares them and outputs the comparison result; the network message receiving test process includes: the network message transceiver component pkt_genscapy agent calls the scapy application based on the Python library, and sends the network message to be received to the ETH tlp interface of the DUT through the cocotbext-eth TLP transport layer adapter; the application component app agent obtains the network message in response to the interrupt handler; the checker agent obtains the network message The agent obtains the network message to be received and compares it with the network message currently received by the application component appagent, and outputs the comparison result.

[0105] Reference Figure 7 , showing a schematic diagram of a computer program product provided in an embodiment of the present application, the computer program product 700 includes a computer program / instruction 701, and when the computer program / instruction 701 is executed by a processor, the system-level verification convergence method described in the embodiment is implemented.

[0106] Specifically, when the computer program / instruction 701 is executed by the processor, the system-level verification convergence method described in the embodiment is implemented, including executing: after the initialization configuration, performing a network message sending test process and a network message receiving test process on the DUT.

[0107] The network message sending test process includes: the application component app agent calls the iperf application based on the Python library to enable the DUT, and the iperf application sends the network message to be sent to the PCIe tlp interface of the DUT through the cocotbext-pcie TLP transport layer adapter; the network message transceiver component pkt_gen scapy agent receives the network message sent by the DUT through the cocotbext-eth TLP transport layer adapter; the checker agent obtains the network message to be sent and the network message currently received by the network message transceiver component pkt_gen scapy agent, and then compares them and outputs the comparison result; the network message receiving test process includes: the network message transceiver component pkt_genscapy agent calls the scapy application based on the Python library, and sends the network message to be received to the ETH tlp interface of the DUT through the cocotbext-eth TLP transport layer adapter; the application component app agent obtains the network message in response to the interrupt handler; the checker agent The agent obtains the network message to be received and compares it with the network message currently received by the application component appagent, and outputs the comparison result.

[0108] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0109] It should be understood by those skilled in the art that the embodiments of the present application can be provided as methods, devices or computer program products. Therefore, the embodiments of the present application can be in the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, the embodiments of the present application can be in the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0110] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems) and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0111] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0112] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0113] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present application.

[0114] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0115] Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A system-level verification convergence system, characterized in that: The system is a cocotb system verification platform based on Python language, and the system includes: The application component app agent is used to call the application based on the Python library to perform network message testing on the DUT; cocotbext-pcie TLP transport layer adapter, used to send and receive PCIe messages on the TLP transport layer interface; The network message sending and receiving component pkt_gen scapy agent is used for the scapy application based on the Python library to perform different types of network message sending, receiving, parsing and automatic response processes; cocotbext-eth TLP transport layer adapter, used to send and receive network messages on the TLP transport layer interface; The checker agent is used to generate comparison results between the expected test results and the actual output results of the DUT.

2. The system according to claim 1, characterized in that The system further comprises: The configuration component config agent is used to perform tasks including BAR address space allocation, definition and allocation of address space for each business module, PCIe enumeration process, common task and function maintenance, system storage space allocation and recycling, queue allocation, and interrupt allocation.

3. The system according to claim 2, characterized in that When verifying any DUT, after the simulator compiles the verification environment code of the DUT and the system, the application component app agent is used to call the configuration component config agent to initialize the configuration of the host system and the DUT; The initialization configuration includes allocating PCIe BAR address space, creating TX / RX queue, CQ queue, initializing descriptors and PCIe interrupts, and initializing the DUT through the cocotbext-pcie TLP transport layer adapter by calling any smart network card driver, wherein the smart network card driver includes VirtIO driver, OVS driver and RDMA driver.

4. The system according to claim 3, characterized in that After the initialization configuration, the application component app agent is used to call the iperf application based on the Python library to enable the DUT, and the iperf application sends the network message to be sent to the PCIe tlp interface of the DUT through the cocotbext-pcie TLP transport layer adapter; The network message transceiver component pkt_gen scapy agent is used to receive the network message sent by the DUT through the cocotbext-eth TLP transport layer adapter; The checking component checker agent is used to obtain the network message to be sent and the network message currently received by the network message sending and receiving component pkt_gen scapy agent, then compare them and output the comparison result.

5. The system according to claim 3, characterized in that After the initialization configuration, the network message transceiver component pkt_gen scapy agent is used to call the scapy application based on the Python library, and send the network message to be received to the ETH tlp interface of the DUT through the cocotbext-eth TLP transport layer adapter; The application component app agent is used to obtain network messages in response to the interrupt processing program; The checker agent component is used to obtain the network message to be received and compare it with the network message currently received by the application component appagent, and output the comparison result.

6. The system according to claim 1, characterized in that The DUT that the system is used to verify includes a smart network card chip, a GPU and a smart AI chip.

7. A system-level verification convergence method, characterized in that: The method is applied to the system-level verification convergence system according to any one of claims 1 to 6, and the method comprises: After the initial configuration, the network message sending test process and the network message receiving test process are performed on the DUT; The network message sending test process includes: the application component app agent calls the iperf application based on the Python library to enable the DUT, and the iperf application sends the network message to be sent to the PCIe tlp interface of the DUT through the cocotbext-pcieTLP transport layer adapter; the network message transceiver component pkt_gen scapy agent receives the network message sent by the DUT through the cocotbext-eth TLP transport layer adapter; the checker agent component obtains the network message to be sent and the network message currently received by the network message transceiver component pkt_gen scapy agent, and then compares them and outputs the comparison result; The network message receiving test process includes: the network message sending and receiving component pkt_gen scapy agent calls the scapy application based on the Python library, and sends the network message to be received to the ETH tlp interface of the DUT through the cocotbext-eth TLP transport layer adapter; the application component app agent obtains the network message in response to the interrupt handler; the check component checker agent obtains the network message to be received and compares it with the network message currently received by the application component app agent, and outputs the comparison result.

8. A computer device, characterized in that: include: At least one processor, and a memory, wherein the memory stores a computer program executable on the processor, wherein the system-level verification closure method according to claim 7 is performed when the processor executes the computer program.

9. A non-volatile readable storage medium, characterized in that: The non-volatile readable storage medium stores a computer program, wherein the computer program, when executed by a processor, performs the system-level verification closure method of claim 7 .

10. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instruction is executed by a processor, the system-level verification closure method of claim 7 is implemented.

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