Method and device for displaying interface data and chip

By directly sending line data to the synthesis module by displaying the input module and combining the synchronization signal for synthesis output, the problems of unreliable synchronization and waste of bandwidth in the prior art are solved, and lower latency and higher synchronization reliability are achieved.

CN119814954APending Publication Date: 2025-04-11FUZHOU ROCKCHIP SEMICON
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Patent Information

Application Number
CN202411849541.1
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-12-16
Publication Date
2025-04-11

AI Technical Summary

Technical Problem

When displaying interface data in the prior art, unreliable synchronization results in large delays and wastes memory bandwidth resources and power consumption.

Method used

The display input module directly sends the row data to the synthesis module and sends a synchronization signal. The synthesis module synthesizes the synchronization signal and the row data with the user interface data and outputs it to the display output module.

Benefits of technology

Reduces system bandwidth occupancy, optimizes latency, from frame delay optimization to row delay, improves synchronization reliability, and saves memory bandwidth and power consumption.

✦ Generated by Eureka AI based on patent content.

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Abstract

The invention discloses a method and a device for displaying interface data and a chip. The method comprises the steps that a display input module obtains row data input through an input interface and sends the row data to a synthesis module, the display input module sends a synchronizing signal to the synthesis module, and the synthesis module obtains user interface data to be displayed in a memory; and the synthesis module synthesizes the line data and the user interface data to be displayed according to the synchronizing signal and then outputs the synthesized data to the display output module. In this way, the display input module can directly send the received row data to the synthesis module for synthesis output, frame delay in the prior art can be optimized to row delay while the system bandwidth occupancy rate is reduced, and the display delay time is effectively shortened.
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Description

Technical Field

[0001] The present invention relates to the field of image processing technology, and in particular to a method, device and chip for displaying interface data. Background Art

[0002] In the current interface data display method, data transmission is usually initiated by PC / BOX, and HDMI IN stores the received data in memory, wherein HDMI IN submits a new frame to the display frame after receiving a frame of data.

[0003] Figure 1 This is a framework diagram showing the interface data display method of the prior art. Taking the Android system as an example, the display input module (HDMI IN) is generally based on the V4L2 (Video for linux2) framework to drive the hardware module, which belongs to the data producer. When HDMI IN receives a frame of image, the software needs to notify the display framework (corresponding to the SurfaceFlinger module on Android) that the current producer has a frame of data that needs to be displayed on the screen. The SurfaceFlinger module will collect the data of all producers including HDMI IN, and send it to the VOP module through the HWC (HardwareComposer, hardware design component) module. After the VOP module receives a new frame configuration, it starts to fetch data from the memory for synthesis when the next frame start signal arrives. The VOP module synthesizes the data provided by several producers and sends it to the screen display end (TV / panel) line by line through the display output module (HDMIOUT) for display.

[0004] Therefore, the software controls and synchronizes the HDMI IN writing to the memory and the display reading data from the memory. Since the CPU (central processing unit) is subject to uncertain factors such as system load and interruption during operation, the synchronization between the two modules is not very reliable, so a frame of time is often reserved, that is, after the HDMI IN collects a complete frame of data, it is sent to the screen for display, so the delay is large and the reliability is low. In addition, the HDMI IN writing data to the memory and the VOP module reading data from the memory will also waste system memory bandwidth resources and power consumption. Summary of the invention

[0005] The present invention provides a method, a device and a chip for displaying interface data, which can reduce the system bandwidth occupancy rate and reduce the display delay time.

[0006] In one aspect of the present invention, a method for displaying interface data is provided. The method includes: obtaining row data inputted through an input interface by a display input module, and directly sending the obtained row data to a synthesis module; sending a synchronization signal to the synthesis module by the display input module; obtaining user interface data to be displayed from a memory by the synthesis module; and synthesizing the row data and the user interface data according to the synchronization signal by the synthesis module to generate synthesized display data, and outputting the synthesized display data to a display output module.

[0007] In another aspect of the present invention, a device for displaying interface data is provided. The device includes: a display input module, configured to obtain line data input through an input interface, directly send the obtained line data, and send a synchronization signal; a synthesis module, directly electrically coupled to the display input module, and configured to: receive the line data and the synchronization signal from the display input module; obtain user interface data to be displayed from a memory; synthesize based on the line data and the user interface data according to the synchronization signal to generate synthesized display data; and a display output module, configured to receive the synthesized display data from the synthesis module, and send the synthesized display data to a screen display terminal through an output interface.

[0008] In another aspect of the present invention, a chip is provided, comprising: the device for displaying interface data as described above; and a memory configured to store user interface data instead of storing line data of interface input for display.

[0009] According to the present invention, the display input module obtains the row data input through the input interface and sends it to the synthesis module, the display input module sends the synchronization signal to the synthesis module, the synthesis module obtains the user interface data to be displayed in the memory, and the synthesis module synthesizes the row data and the user interface data to be displayed according to the synchronization signal and outputs it to the display output module. Compared with the method in the prior art that requires the display input module to write data to the memory and the synthesis module needs to uniformly read data from the memory and synthesize, the display input module in the present invention can directly send the received row data to the synthesis module for synthesis output, while reducing the system bandwidth occupancy rate, it can be optimized from the frame delay in the prior art to the row delay, effectively reducing the display delay time. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A framework diagram of a method for displaying interface data in the prior art; Figure 2 is a flowchart of a method for displaying interface data according to an embodiment of the present invention; Figure 3 A framework diagram of a method for displaying interface data according to an embodiment of the present invention; Figure 4 It is a structural diagram of a device for displaying interface data according to an embodiment of the present invention. DETAILED DESCRIPTION

[0011] In order to explain the technical content, achieved objectives and effects of the present invention in detail, the following is an explanation in combination with the implementation modes and the accompanying drawings.

[0012] In the prior art, in the interface data display scheme, the display input module needs to write data to the memory, and the synthesis module needs to uniformly read and synthesize data from the memory, which wastes system memory bandwidth resources and power consumption and delays display.

[0013] In order to solve at least the above technical problems, the present disclosure provides a method for displaying interface data, wherein the display input module obtains the row data input through the input interface and sends it directly to the synthesis module, the display input module sends the synchronization signal to the synthesis module, the synthesis module obtains the user interface data to be displayed in the memory, and the synthesis module synthesizes the row data and the user interface data to be displayed according to the synchronization signal and outputs it to the display output module. In this way, according to an embodiment of the present disclosure, the display input module can directly send the received row data to the synthesis module for synthesis output, reducing the reading and writing of the memory, thereby reducing the system bandwidth occupancy rate, optimizing the delay to the row delay, and reducing the display delay.

[0014] Hereinafter, the technical solution according to the present disclosure will be described with reference to specific embodiments and in conjunction with the accompanying drawings.

[0015] Figure 2 2 is a flow chart showing a method 200 for displaying interface data according to an embodiment of the present disclosure. Figure 2 The method 200 includes the following steps 202 to 208.

[0016] In step 202, the display input module obtains the row data input through the input interface, and directly sends the obtained row data to the synthesis module.

[0017] In step 204, the display input module sends a synchronization signal to the synthesis module.

[0018] In some embodiments, the synchronization signal includes a frame start signal and a line start signal, and the synthesis module compares the frame signal and the line signal in the synthesis module according to the synchronization signal to adjust the timing of the synthesis module so that the synthesis module is synchronized with the display input module, wherein the timing includes at least one of the pixel clock, the line blanking period, and the field blanking period. In this way, the display input module and the synthesis module are synchronized through the transmission and comparison of the synchronization signal, so that the display input module receives a line of data, and the synthesis module outputs the synthesis result of a line of data, ensuring that the delay from the display input to the output is just the time of a line, and hard synchronization between modules can also improve the synchronization reliability.

[0019] In some embodiments, the display input module sends the synchronization signal at the beginning of each frame. After the synthesis module receives the synchronization signal, it calculates the time difference with the display input module and adjusts the frame scanning time of the synthesis module so that the synthesis module and the display input module maintain the same frequency.

[0020] In step 206, the synthesis module obtains the user interface data to be displayed from the memory.

[0021] In step 208 , a synthesis module performs synthesis based on the line data and the user interface data according to the synchronization signal to generate synthesized display data, and outputs the synthesized display data to a display output module.

[0022] In some embodiments, each target row data is obtained based on the row data according to the synchronization signal, and each target row data is synthesized with the user interface data row by row to generate the synthesized display data. Specifically, first target row data is obtained according to the received frame start signal and the row start signal, and the first target row data is synthesized with the corresponding user interface row data to generate first synthesized row display data.

[0023] In some embodiments, the target row data corresponding to the same row and the user interface row data are synthesized in the row buffer of the synthesis module according to the image resolution to generate synthesized row display data. In some embodiments, the time when a frame starts is determined according to the synchronization signal, the row data is received at the time, and the row data is synthesized with at least the user interface data. In this way, the image is synthesized line by line, and when there are multiple data input terminals for providing data in the same row, the row data of the multiple data input terminals can be placed in the buffer of the synthesis module and synthesized together. The synthesis module can start synthesizing the row data sent by the display input module when receiving the frame start signal, and there is no need to wait for the complete frame data to be transmitted before synthesizing, thereby reducing the transmission delay.

[0024] In some embodiments, the display output module sends the synthesized display data line by line to the screen display terminal through the output interface, thereby ensuring the integrity of the image synthesis.

[0025] Hereinafter, application scenarios of the method, device, and chip for displaying interface data according to the embodiments of the present invention will be described by way of examples.

[0026] Figure 3 is a framework diagram showing a method for displaying interface data according to an embodiment of the present invention. The chip implementing the method of this embodiment can be applied to a whiteboard, such as Figure 3 As shown, the display input module is HDMI IN, the synthesis module is the VOP module, the display output module is HDMI OUT, the data input terminal is PC / BOX, the screen display terminal is TV / panel, and the memory is DDR (double rate synchronous dynamic random access memory).

[0027] When an HDMI cable is plugged into the data input port, and the other end of the HDMI cable is plugged into the whiteboard, the module on the whiteboard connected to the HDMI cable is the display input module. After the whiteboard receives the data projected by the display input module from the data input port, there may also be a native user interface or mouse on the whiteboard. The synthesis module is responsible for getting these data and then synthesizing them. The display output module is responsible for outputting the synthesized data as a high-speed differential signal (TMDS) and sending it to the screen display end for display through the hardware circuit board routing. However, due to the chip cost, the internal cache is generally small, that is, the display input module and the synthesis module can usually have 4 to 8 lines of cache.

[0028] In this embodiment, the display input module and the synthesis module are synchronized from the chip design to ensure that both write and read data at a fixed frequency. Specifically, a synchronization signal Sync is set to synchronize the reading and writing of data between the two hardware modules. For the convenience of description, it is assumed that the resolution of the display input and display output is 4k60Hz, so the time of one frame is 16.67ms.

[0029] Specifically, the display input module receives the image data output by the previous data input terminal at a fixed frame rate. If the resolution is 4k60Hz, the time to receive one frame is 16.67ms. The synthesis module obtains the data received by the display input module at a fixed frequency, and after synthesizing it with other user interface data in the memory, it is sent to the screen display terminal at a fixed display frame rate through the display output module for display. If the frame rate given to the display input module by the previous data input terminal is exactly the same as the reading frequency of the synthesis module, then the display input module can receive a line of data, and the synthesis module can output the synthesis result corresponding to a line of data, so that the delay from display input to output is exactly the time of one line.

[0030] However, since the clock of the previous P data input terminal may not be completely accurate, the time of one frame may deviate from around 16.67ms. At this time, the data received by the display input module and the frame rate displayed by the synthesis module do not match, resulting in deviation. Therefore, the synchronization signal Sync is used in this embodiment to solve this deviation, which is further manifested in: the display input module inside the chip provides the frame start signal and the line start signal to the synthesis module; when the synthesis module receives the frame signal and the line signal, it compares it with its own frame signal and line signal, and adjusts the timing of the synthesis module, such as the pixel clock, the line blanking period, and the field blanking period, so that the synthesis module and the display input module are synchronized.

[0031] At this time, the interface line data written by the display input module and the interface line data read by the synthesis module no longer pass through the memory, but the display input module and the synthesis module are directly connected inside the chip, that is, the data received by the display input module is directly sent to the synthesis module through the internal connection of the chip. At this time, the sending and receiving are controlled by the synchronization signal sync. The display input module sends a signal, and the synthesis module makes adjustments based on the received signal.

[0032] The synthesis module starts to receive the data from the display input module for synthesis when a new frame start signal comes. When the frame start signal comes, it is the moment when a new frame starts to be transmitted.

[0033] The synthesis module receives the data provided by each producer during synthesis, such as the interface data of the display input module, the user interface data and mouse data stored in the memory and processed by the CPU (central processing unit) and GPU (graphics processing unit). The synthesis module synthesizes a complete frame of image after receiving these data. The synthesis module sends the synthesized data to the screen for display line by line. When synthesizing, it synthesizes line by line according to the resolution. If there are data provided by multiple producers on the same line, the synthesis module will put the data of multiple producers into the line cache of the synthesis module, and then send the current line to the screen through the display output module for display after synthesis.

[0034] In this way, the interface data can be transmitted and displayed in one line, reducing the delay from display input to display on the screen from milliseconds to microseconds, and hard synchronization between modules makes it more reliable. It can also reduce the reading and writing of memory, saving bandwidth and power consumption within the chip.

[0035] According to another aspect of the present invention, Figure 4 4 is a structural diagram showing an apparatus 400 for displaying interface data according to an embodiment of the present invention. The apparatus 400 includes a display input module 402, a synthesis module 404 and a display output module 406.

[0036] The display input module is configured to acquire line data input through an input interface, directly send the acquired line data, and send a synchronization signal.

[0037] The synthesis module is directly electrically coupled to the display input module. The synthesis module is configured to receive the line data and the synchronization signal from the display input module. The synthesis module is configured to obtain the user interface data to be displayed from the memory. In addition, the synthesis module is configured to synthesize based on the line data and the user interface data according to the synchronization signal to generate synthesized display data.

[0038] The display output module is configured to receive the synthesized display data from the synthesis module, and send the synthesized display data to the screen display terminal through an output interface.

[0039] According to another aspect of the present invention, a chip is provided, comprising the device for displaying interface data as described in the above embodiment and a memory, wherein the memory is configured to store user interface data instead of storing line data of interface input for display.

[0040] In summary, the method, device, and chip for displaying interface data provided by the present invention are that the display input module obtains the row data input through the input interface and sends it to the synthesis module, the display input module sends the synchronization signal to the synthesis module, the synthesis module obtains the user interface data to be displayed in the memory, and the synthesis module synthesizes the row data and the user interface data to be displayed according to the synchronization signal and outputs it to the display output module. In this way, according to the embodiment of the present disclosure, the display input module can directly send the received row data to the synthesis module for synthesis output, reduce the reading and writing of the memory, thereby reducing the system bandwidth occupancy while optimizing the delay to the row delay and reducing the display delay.

[0041] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent transformations made using the contents of the present invention's specification and drawings, or directly or indirectly applied in related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A method for displaying interface data, characterized in that: include: The display input module acquires the row data input through the input interface, and directly sends the acquired row data to the synthesis module; The display input module sends the synchronization signal to the synthesis module; The synthesis module obtains the user interface data to be displayed from the memory; as well as The synthesis module performs synthesis based on the line data and the user interface data according to the synchronization signal to generate synthesized display data, and outputs the synthesized display data to the display output module.

2. The method according to claim 1, characterized in that The synchronization signal includes a frame start signal and a line start signal, and the method further includes: The synthesis module compares the frame signal and the row signal in the synthesis module according to the synchronization signal to adjust the timing of the synthesis module so that the synthesis module is synchronized with the display input module. The timing sequence includes at least one of a pixel clock, a line blanking period, and a field blanking period.

3. The method according to claim 2, characterized in that The synthesizing module synthesizes the row data and the user interface data according to the synchronization signal to generate synthesized display data, including: acquiring each target row data based on the row data according to the synchronization signal; and Each of the target row data is synthesized row by row with the user interface data to generate the synthesized display data.

4. The method according to claim 3, characterized in that Acquiring each target row data based on the row data according to the synchronization signal includes: acquiring first target row data according to the received frame start signal and the row start signal, Combining each of the target row data with the user interface data row by row to generate the synthesized display data includes: combining the first target row data with the corresponding user interface row data to generate first synthesized row display data.

5. The method according to claim 3, characterized in that: Combining each of the target row data with the user interface data row by row to generate the composite display data comprises: In the row buffer of the synthesis module, the target row data and the user interface row data corresponding to the same row are synthesized according to the image resolution to generate synthesized row display data.

6. The method according to claim 2, characterized in that The display input module sends the synchronization signal to the synthesis module, comprising: the display input module sends the synchronization signal at the beginning of each frame, Synchronizing the synthesis module with the display input module includes: calculating the time difference between the synthesis module and the display input module after the synthesis module receives the synchronization signal, and adjusting the frame scanning time of the synthesis module so that the synthesis module and the display input module maintain the same frequency.

7. The method according to claim 1, characterized in that The synthesizing module synthesizes the row data and the user interface data according to the synchronization signal to generate synthesized display data, including: Determine the start time of a frame according to the synchronization signal; Start receiving the row data at the time; and The row data is synthesized with at least the user interface data.

8. The method according to claim 1, characterized in that Also includes: The display output module sends the synthesized display data line by line to the screen display terminal through the output interface.

9. A device for displaying interface data, characterized in that: include: A display input module, configured to obtain line data input through the input interface, directly send the obtained line data, and send a synchronization signal; A synthesis module is directly electrically coupled to the display input module and is configured to: receiving the row data and the synchronization signal from the display input module; Get the user interface data to be displayed from the memory; synthesizing based on the line data and the user interface data according to the synchronization signal to generate synthesized display data; as well as The display output module is configured to receive the synthesized display data from the synthesis module and send the synthesized display data to the screen display terminal through an output interface.

10. A chip, characterized in that: include: The device according to claim 9; as well as The memory is configured to store the user interface data but not to store the line data of the interface input for display.